1 /*
2 * Copyright (C) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c:
6 * Copyright (C) 2012 rockchips
7 * zyw <zyw@rock-chips.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <power/rk8xx_pmic.h>
16 #include <power/pmic.h>
17 #include <power/regulator.h>
18
19 #ifndef CONFIG_SPL_BUILD
20 #define ENABLE_DRIVER
21 #endif
22
23 /* Not used or exisit register and configure */
24 #define NA -1
25
26 /* Field Definitions */
27 #define RK808_BUCK_VSEL_MASK 0x3f
28 #define RK808_BUCK4_VSEL_MASK 0xf
29 #define RK808_LDO_VSEL_MASK 0x1f
30
31 #define RK818_BUCK_VSEL_MASK 0x3f
32 #define RK818_BUCK4_VSEL_MASK 0x1f
33 #define RK818_LDO_VSEL_MASK 0x1f
34 #define RK818_LDO3_ON_VSEL_MASK 0xf
35 #define RK818_BOOST_ON_VSEL_MASK 0xe0
36 #define RK818_USB_ILIM_SEL_MASK 0x0f
37 #define RK818_USB_CHG_SD_VSEL_MASK 0x70
38
39 /* RK809 BUCK5 */
40 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1)
41 #define RK809_BUCK5_VSEL_MASK 0x07
42
43 /* RK817 BUCK */
44 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1))
45 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1))
46 #define RK817_BUCK_VSEL_MASK 0x7f
47 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3)
48
49 /* RK817 LDO */
50 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1))
51 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1))
52 #define RK817_LDO_VSEL_MASK 0x7f
53
54 /* RK817 ENABLE */
55 #define RK817_POWER_EN(n) (0xb1 + (n))
56 #define RK817_POWER_SLP_EN(n) (0xb5 + (n))
57
58 /*
59 * Ramp delay
60 */
61 #define RK805_RAMP_RATE_OFFSET 3
62 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET)
63 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET)
64 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET)
65 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET)
66 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET)
67
68 #define RK808_RAMP_RATE_OFFSET 3
69 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
70 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
71 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET)
72 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET)
73 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET)
74
75 #define RK817_RAMP_RATE_OFFSET 6
76 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
77 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
78 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
79 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
80 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
81
82 struct rk8xx_reg_info {
83 uint min_uv;
84 uint step_uv;
85 u8 vsel_reg;
86 u8 vsel_sleep_reg;
87 u8 config_reg;
88 u8 vsel_mask;
89 u8 min_sel;
90 /* only for buck now */
91 u8 max_sel;
92 u8 range_num;
93 };
94
95 static const struct rk8xx_reg_info rk808_buck[] = {
96 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
97 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
98 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1},
99 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK,0x00, 0x0f, 1},
100 };
101
102 static const struct rk8xx_reg_info rk816_buck[] = {
103 /* buck 1 */
104 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3},
105 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3},
106 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3},
107 /* buck 2 */
108 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3},
109 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3},
110 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3},
111 /* buck 3 */
112 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1},
113 /* buck 4 */
114 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x1b, 1},
115 };
116
117 static const struct rk8xx_reg_info rk809_buck5[] = {
118 /* buck 5 */
119 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, 0x00, 4},
120 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, 0x03, 4},
121 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, 0x05, 4},
122 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, 0x07, 4},
123 };
124
125 static const struct rk8xx_reg_info rk817_buck[] = {
126 /* buck 1 */
127 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
128 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3},
129 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3},
130 /* buck 2 */
131 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
132 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3},
133 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3},
134 /* buck 3 */
135 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
136 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3},
137 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3},
138 /* buck 4 */
139 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
140 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, 0x62, 3},
141 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, 0x63, 3},
142 };
143
144 static const struct rk8xx_reg_info rk818_buck[] = {
145 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
146 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
147 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1},
148 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x10, 1},
149 };
150
151 #ifdef ENABLE_DRIVER
152 static const struct rk8xx_reg_info rk808_ldo[] = {
153 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
154 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
155 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, },
156 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
157 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
158 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
159 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
160 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
161 };
162
163 static const struct rk8xx_reg_info rk816_ldo[] = {
164 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
165 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
166 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
167 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
168 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
169 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
170 };
171
172 static const struct rk8xx_reg_info rk817_ldo[] = {
173 /* ldo1 */
174 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, },
175 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, },
176 /* ldo2 */
177 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, },
178 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, },
179 /* ldo3 */
180 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, },
181 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, },
182 /* ldo4 */
183 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, },
184 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, },
185 /* ldo5 */
186 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, },
187 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, },
188 /* ldo6 */
189 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, },
190 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, },
191 /* ldo7 */
192 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, },
193 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, },
194 /* ldo8 */
195 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, },
196 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, },
197 /* ldo9 */
198 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, },
199 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, },
200 };
201
202 static const struct rk8xx_reg_info rk818_ldo[] = {
203 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
204 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
205 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, },
206 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
207 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
208 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
209 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
210 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
211 };
212 #endif
213
214 static const u16 rk818_chrg_cur_input_array[] = {
215 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
216 };
217
218 static const uint rk818_chrg_shutdown_vsel_array[] = {
219 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
220 };
221
get_buck_reg(struct udevice * pmic,int num,int uvolt)222 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
223 int num, int uvolt)
224 {
225 struct rk8xx_priv *priv = dev_get_priv(pmic);
226
227 switch (priv->variant) {
228 case RK805_ID:
229 case RK816_ID:
230 switch (num) {
231 case 0:
232 case 1:
233 if (uvolt <= 1450000)
234 return &rk816_buck[num * 3 + 0];
235 else if (uvolt <= 2200000)
236 return &rk816_buck[num * 3 + 1];
237 else
238 return &rk816_buck[num * 3 + 2];
239 default:
240 return &rk816_buck[num + 4];
241 }
242
243 case RK809_ID:
244 case RK817_ID:
245 switch (num) {
246 case 0 ... 2:
247 if (uvolt < 1500000)
248 return &rk817_buck[num * 3 + 0];
249 else if (uvolt < 2400000)
250 return &rk817_buck[num * 3 + 1];
251 else
252 return &rk817_buck[num * 3 + 2];
253 case 3:
254 if (uvolt < 1500000)
255 return &rk817_buck[num * 3 + 0];
256 else if (uvolt < 3400000)
257 return &rk817_buck[num * 3 + 1];
258 else
259 return &rk817_buck[num * 3 + 2];
260 /* BUCK5 for RK809 */
261 default:
262 if (uvolt < 1800000)
263 return &rk809_buck5[0];
264 else if (uvolt < 2800000)
265 return &rk809_buck5[1];
266 else if (uvolt < 3300000)
267 return &rk809_buck5[2];
268 else
269 return &rk809_buck5[3];
270 }
271 case RK818_ID:
272 return &rk818_buck[num];
273 default:
274 return &rk808_buck[num];
275 }
276 }
277
_buck_set_value(struct udevice * pmic,int buck,int uvolt)278 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
279 {
280 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
281 struct rk8xx_priv *priv = dev_get_priv(pmic);
282 int mask = info->vsel_mask;
283 int val;
284
285 if (info->vsel_reg == NA)
286 return -ENOSYS;
287
288 if (info->step_uv == 0) /* Fixed voltage */
289 val = info->min_sel;
290 else
291 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
292
293 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
294 __func__, uvolt, buck+1, info->vsel_reg, mask, val);
295
296 if (priv->variant == RK816_ID) {
297 pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
298 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2, 1 << 7, 1 << 7);
299 } else {
300 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
301 }
302 }
303
_buck_set_enable(struct udevice * pmic,int buck,bool enable)304 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
305 {
306 uint mask, value, en_reg;
307 int ret;
308 struct rk8xx_priv *priv = dev_get_priv(pmic);
309
310 switch (priv->variant) {
311 case RK805_ID:
312 case RK816_ID:
313 if (buck >= 4) {
314 buck -= 4;
315 en_reg = RK816_REG_DCDC_EN2;
316 } else {
317 en_reg = RK816_REG_DCDC_EN1;
318 }
319 if (enable)
320 value = ((1 << buck) | (1 << (buck + 4)));
321 else
322 value = ((0 << buck) | (1 << (buck + 4)));
323 ret = pmic_reg_write(pmic, en_reg, value);
324 break;
325
326 case RK808_ID:
327 case RK818_ID:
328 mask = 1 << buck;
329 if (enable) {
330 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX,
331 0, 3 << (buck * 2));
332 if (ret)
333 return ret;
334 }
335 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask,
336 enable ? mask : 0);
337 break;
338 case RK809_ID:
339 case RK817_ID:
340 if (buck < 4) {
341 if (enable)
342 value = ((1 << buck) | (1 << (buck + 4)));
343 else
344 value = ((0 << buck) | (1 << (buck + 4)));
345 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value);
346 /* BUCK5 for RK809 */
347 } else {
348 if (enable)
349 value = ((1 << 1) | (1 << 5));
350 else
351 value = ((0 << 1) | (1 << 5));
352 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value);
353 }
354 break;
355 default:
356 ret = -EINVAL;
357 }
358
359 return ret;
360 }
361
362 #ifdef ENABLE_DRIVER
_buck_set_suspend_value(struct udevice * pmic,int buck,int uvolt)363 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
364 {
365 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
366 int mask = info->vsel_mask;
367 int val;
368
369 if (info->vsel_sleep_reg == NA)
370 return -ENOSYS;
371
372 if (info->step_uv == 0)
373 val = info->min_sel;
374 else
375 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
376
377 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
378 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val);
379
380 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
381 }
382
_buck_get_enable(struct udevice * pmic,int buck)383 static int _buck_get_enable(struct udevice *pmic, int buck)
384 {
385 struct rk8xx_priv *priv = dev_get_priv(pmic);
386 uint mask = 0;
387 int ret = 0;
388
389 switch (priv->variant) {
390 case RK805_ID:
391 case RK816_ID:
392 if (buck >= 4) {
393 mask = 1 << (buck - 4);
394 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2);
395 } else {
396 mask = 1 << buck;
397 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1);
398 }
399 break;
400 case RK808_ID:
401 case RK818_ID:
402 mask = 1 << buck;
403 ret = pmic_reg_read(pmic, REG_DCDC_EN);
404 if (ret < 0)
405 return ret;
406 break;
407 case RK809_ID:
408 case RK817_ID:
409 if (buck < 4) {
410 mask = 1 << buck;
411 ret = pmic_reg_read(pmic, RK817_POWER_EN(0));
412 /* BUCK5 for RK809 */
413 } else {
414 mask = 1 << 1;
415 ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
416 }
417 break;
418 }
419
420 if (ret < 0)
421 return ret;
422
423 return ret & mask ? true : false;
424 }
425
_buck_set_ramp_delay(struct udevice * pmic,int buck,u32 ramp_delay)426 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay)
427 {
428 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0);
429 struct rk8xx_priv *priv = dev_get_priv(pmic);
430 u32 ramp_value, ramp_mask;
431
432 if (info->config_reg == NA)
433 return -ENOSYS;
434
435 switch (priv->variant) {
436 case RK805_ID:
437 ramp_mask = RK805_RAMP_RATE_MASK;
438 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
439 switch (ramp_delay) {
440 case 0 ... 3000:
441 ramp_value = RK805_RAMP_RATE_3MV_PER_US;
442 break;
443 case 3001 ... 6000:
444 ramp_value = RK805_RAMP_RATE_6MV_PER_US;
445 break;
446 case 6001 ... 12500:
447 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
448 break;
449 case 12501 ... 25000:
450 ramp_value = RK805_RAMP_RATE_25MV_PER_US;
451 break;
452 default:
453 printf("buck%d ramp_delay: %d not supported\n",
454 buck, ramp_delay);
455 }
456 break;
457 case RK808_ID:
458 case RK816_ID:
459 case RK818_ID:
460 ramp_value = RK808_RAMP_RATE_6MV_PER_US;
461 ramp_mask = RK808_RAMP_RATE_MASK;
462 switch (ramp_delay) {
463 case 1 ... 2000:
464 ramp_value = RK808_RAMP_RATE_2MV_PER_US;
465 break;
466 case 2001 ... 4000:
467 ramp_value = RK808_RAMP_RATE_4MV_PER_US;
468 break;
469 case 4001 ... 6000:
470 ramp_value = RK808_RAMP_RATE_6MV_PER_US;
471 break;
472 case 6001 ... 10000:
473 ramp_value = RK808_RAMP_RATE_6MV_PER_US;
474 break;
475 default:
476 printf("buck%d ramp_delay: %d not supported\n",
477 buck, ramp_delay);
478 }
479 break;
480 case RK809_ID:
481 case RK817_ID:
482 ramp_mask = RK817_RAMP_RATE_MASK;
483 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
484 switch (ramp_delay) {
485 case 0 ... 3000:
486 ramp_value = RK817_RAMP_RATE_3MV_PER_US;
487 break;
488 case 3001 ... 6300:
489 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US;
490 break;
491 case 6301 ... 12500:
492 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
493 break;
494 case 12501 ... 25000:
495 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
496 break;
497 default:
498 printf("buck%d ramp_delay: %d not supported\n",
499 buck, ramp_delay);
500 }
501 break;
502 default:
503 return -EINVAL;
504 }
505
506 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value);
507 }
508
_buck_set_suspend_enable(struct udevice * pmic,int buck,bool enable)509 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
510 {
511 uint mask;
512 int ret;
513 struct rk8xx_priv *priv = dev_get_priv(pmic);
514
515 switch (priv->variant) {
516 case RK805_ID:
517 case RK816_ID:
518 mask = 1 << buck;
519 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask,
520 enable ? mask : 0);
521 break;
522 case RK808_ID:
523 case RK818_ID:
524 mask = 1 << buck;
525 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask,
526 enable ? 0 : mask);
527 break;
528 case RK809_ID:
529 case RK817_ID:
530 if (buck < 4)
531 mask = 1 << buck;
532 else
533 mask = 1 << 5; /* BUCK5 for RK809 */
534 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
535 enable ? mask : 0);
536 break;
537 default:
538 ret = -EINVAL;
539 }
540
541 return ret;
542 }
543
_buck_get_suspend_enable(struct udevice * pmic,int buck)544 static int _buck_get_suspend_enable(struct udevice *pmic, int buck)
545 {
546 struct rk8xx_priv *priv = dev_get_priv(pmic);
547 int ret, val;
548 uint mask;
549
550 switch (priv->variant) {
551 case RK805_ID:
552 case RK816_ID:
553 mask = 1 << buck;
554 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN);
555 if (val < 0)
556 return val;
557 ret = val & mask ? 1 : 0;
558 break;
559 case RK808_ID:
560 case RK818_ID:
561 mask = 1 << buck;
562 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1);
563 if (val < 0)
564 return val;
565 ret = val & mask ? 0 : 1;
566 break;
567 case RK809_ID:
568 case RK817_ID:
569 if (buck < 4)
570 mask = 1 << buck;
571 else
572 mask = 1 << 5; /* BUCK5 for RK809 */
573
574 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
575 if (val < 0)
576 return val;
577 ret = val & mask ? 1 : 0;
578 break;
579 default:
580 ret = -EINVAL;
581 }
582
583 return ret;
584 }
585
get_ldo_reg(struct udevice * pmic,int num,int uvolt)586 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
587 int num, int uvolt)
588 {
589 struct rk8xx_priv *priv = dev_get_priv(pmic);
590
591 switch (priv->variant) {
592 case RK805_ID:
593 case RK816_ID:
594 return &rk816_ldo[num];
595 case RK809_ID:
596 case RK817_ID:
597 if (uvolt < 3400000)
598 return &rk817_ldo[num * 2 + 0];
599 else
600 return &rk817_ldo[num * 2 + 1];
601 case RK818_ID:
602 return &rk818_ldo[num];
603 default:
604 return &rk808_ldo[num];
605 }
606 }
607
_ldo_get_enable(struct udevice * pmic,int ldo)608 static int _ldo_get_enable(struct udevice *pmic, int ldo)
609 {
610 struct rk8xx_priv *priv = dev_get_priv(pmic);
611 uint mask = 0;
612 int ret = 0;
613
614 switch (priv->variant) {
615 case RK805_ID:
616 case RK816_ID:
617 if (ldo >= 4) {
618 mask = 1 << (ldo - 4);
619 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2);
620 } else {
621 mask = 1 << ldo;
622 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1);
623 }
624 break;
625 case RK808_ID:
626 case RK818_ID:
627 mask = 1 << ldo;
628 ret = pmic_reg_read(pmic, REG_LDO_EN);
629 if (ret < 0)
630 return ret;
631 break;
632 case RK809_ID:
633 case RK817_ID:
634 if (ldo < 4) {
635 mask = 1 << ldo;
636 ret = pmic_reg_read(pmic, RK817_POWER_EN(1));
637 } else if (ldo < 8) {
638 mask = 1 << (ldo - 4);
639 ret = pmic_reg_read(pmic, RK817_POWER_EN(2));
640 } else if (ldo == 8) {
641 mask = 1 << 0;
642 ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
643 } else {
644 return false;
645 }
646 break;
647 }
648
649 if (ret < 0)
650 return ret;
651
652 return ret & mask ? true : false;
653 }
654
_ldo_set_enable(struct udevice * pmic,int ldo,bool enable)655 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
656 {
657 struct rk8xx_priv *priv = dev_get_priv(pmic);
658 uint mask, value, en_reg;
659 int ret = 0;
660
661 switch (priv->variant) {
662 case RK805_ID:
663 case RK816_ID:
664 if (ldo >= 4) {
665 ldo -= 4;
666 en_reg = RK816_REG_LDO_EN2;
667 } else {
668 en_reg = RK816_REG_LDO_EN1;
669 }
670 if (enable)
671 value = ((1 << ldo) | (1 << (ldo + 4)));
672 else
673 value = ((0 << ldo) | (1 << (ldo + 4)));
674
675 ret = pmic_reg_write(pmic, en_reg, value);
676 break;
677 case RK808_ID:
678 case RK818_ID:
679 mask = 1 << ldo;
680 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask,
681 enable ? mask : 0);
682 break;
683 case RK809_ID:
684 case RK817_ID:
685 if (ldo < 4) {
686 en_reg = RK817_POWER_EN(1);
687 } else if (ldo < 8) {
688 ldo -= 4;
689 en_reg = RK817_POWER_EN(2);
690 } else if (ldo == 8) {
691 ldo = 0; /* BIT 0 */
692 en_reg = RK817_POWER_EN(3);
693 } else {
694 return -EINVAL;
695 }
696 if (enable)
697 value = ((1 << ldo) | (1 << (ldo + 4)));
698 else
699 value = ((0 << ldo) | (1 << (ldo + 4)));
700 ret = pmic_reg_write(pmic, en_reg, value);
701 break;
702 }
703
704 return ret;
705 }
706
_ldo_set_suspend_enable(struct udevice * pmic,int ldo,bool enable)707 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
708 {
709 struct rk8xx_priv *priv = dev_get_priv(pmic);
710 uint mask;
711 int ret = 0;
712
713 switch (priv->variant) {
714 case RK805_ID:
715 case RK816_ID:
716 mask = 1 << ldo;
717 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask,
718 enable ? mask : 0);
719 break;
720 case RK808_ID:
721 case RK818_ID:
722 mask = 1 << ldo;
723 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask,
724 enable ? 0 : mask);
725 break;
726 case RK809_ID:
727 case RK817_ID:
728 if (ldo == 8) {
729 mask = 1 << 4; /* LDO9 */
730 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
731 enable ? mask : 0);
732 } else {
733 mask = 1 << ldo;
734 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask,
735 enable ? mask : 0);
736 }
737 break;
738 }
739
740 return ret;
741 }
742
_ldo_get_suspend_enable(struct udevice * pmic,int ldo)743 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
744 {
745 struct rk8xx_priv *priv = dev_get_priv(pmic);
746 int val, ret = 0;
747 uint mask;
748
749 switch (priv->variant) {
750 case RK805_ID:
751 case RK816_ID:
752 mask = 1 << ldo;
753 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN);
754 if (val < 0)
755 return val;
756 ret = val & mask ? 1 : 0;
757 break;
758 case RK808_ID:
759 case RK818_ID:
760 mask = 1 << ldo;
761 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2);
762 if (val < 0)
763 return val;
764 ret = val & mask ? 0 : 1;
765 break;
766 case RK809_ID:
767 case RK817_ID:
768 if (ldo == 8) {
769 mask = 1 << 4; /* LDO9 */
770 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
771 if (val < 0)
772 return val;
773 ret = val & mask ? 1 : 0;
774 } else {
775 mask = 1 << ldo;
776 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1));
777 if (val < 0)
778 return val;
779 ret = val & mask ? 1 : 0;
780 }
781 break;
782 }
783
784 return ret;
785 }
786
buck_get_value(struct udevice * dev)787 static int buck_get_value(struct udevice *dev)
788 {
789 int buck = dev->driver_data - 1;
790 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
791 int mask = info->vsel_mask;
792 int i, ret, val;
793
794 if (info->vsel_reg == NA)
795 return -ENOSYS;
796
797 ret = pmic_reg_read(dev->parent, info->vsel_reg);
798 if (ret < 0)
799 return ret;
800
801 val = ret & mask;
802 if (val >= info->min_sel && val <= info->max_sel)
803 goto finish;
804
805 /* unlucky to try */
806 for (i = 1; i < info->range_num; i++) {
807 info++;
808 if (val <= info->max_sel && val >= info->min_sel)
809 break;
810 }
811
812 finish:
813 return info->min_uv + (val - info->min_sel) * info->step_uv;
814 }
815
buck_set_value(struct udevice * dev,int uvolt)816 static int buck_set_value(struct udevice *dev, int uvolt)
817 {
818 int buck = dev->driver_data - 1;
819
820 return _buck_set_value(dev->parent, buck, uvolt);
821 }
822
buck_get_suspend_value(struct udevice * dev)823 static int buck_get_suspend_value(struct udevice *dev)
824 {
825 int buck = dev->driver_data - 1;
826 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
827 int mask = info->vsel_mask;
828 int i, ret, val;
829
830 if (info->vsel_sleep_reg == NA)
831 return -ENOSYS;
832
833 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
834 if (ret < 0)
835 return ret;
836
837 val = ret & mask;
838 if (val <= info->max_sel && val >= info->min_sel)
839 goto finish;
840
841 /* unlucky to try */
842 for (i = 1; i < info->range_num; i++) {
843 info++;
844 if (val <= info->max_sel && val >= info->min_sel)
845 break;
846 }
847
848 finish:
849 return info->min_uv + (val - info->min_sel) * info->step_uv;
850 }
851
buck_set_suspend_value(struct udevice * dev,int uvolt)852 static int buck_set_suspend_value(struct udevice *dev, int uvolt)
853 {
854 int buck = dev->driver_data - 1;
855
856 return _buck_set_suspend_value(dev->parent, buck, uvolt);
857 }
858
buck_set_enable(struct udevice * dev,bool enable)859 static int buck_set_enable(struct udevice *dev, bool enable)
860 {
861 int buck = dev->driver_data - 1;
862
863 return _buck_set_enable(dev->parent, buck, enable);
864 }
865
buck_set_suspend_enable(struct udevice * dev,bool enable)866 static int buck_set_suspend_enable(struct udevice *dev, bool enable)
867 {
868 int buck = dev->driver_data - 1;
869
870 return _buck_set_suspend_enable(dev->parent, buck, enable);
871 }
872
buck_get_suspend_enable(struct udevice * dev)873 static int buck_get_suspend_enable(struct udevice *dev)
874 {
875 int buck = dev->driver_data - 1;
876
877 return _buck_get_suspend_enable(dev->parent, buck);
878 }
879
buck_set_ramp_delay(struct udevice * dev,u32 ramp_delay)880 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay)
881 {
882 int buck = dev->driver_data - 1;
883
884 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay);
885 }
886
buck_get_enable(struct udevice * dev)887 static int buck_get_enable(struct udevice *dev)
888 {
889 int buck = dev->driver_data - 1;
890
891 return _buck_get_enable(dev->parent, buck);
892 }
893
ldo_get_value(struct udevice * dev)894 static int ldo_get_value(struct udevice *dev)
895 {
896 int ldo = dev->driver_data - 1;
897 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
898 int mask = info->vsel_mask;
899 int ret, val;
900
901 if (info->vsel_reg == NA)
902 return -ENOSYS;
903 ret = pmic_reg_read(dev->parent, info->vsel_reg);
904 if (ret < 0)
905 return ret;
906 val = ret & mask;
907
908 return info->min_uv + val * info->step_uv;
909 }
910
ldo_set_value(struct udevice * dev,int uvolt)911 static int ldo_set_value(struct udevice *dev, int uvolt)
912 {
913 int ldo = dev->driver_data - 1;
914 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
915 int mask = info->vsel_mask;
916 int val;
917
918 if (info->vsel_reg == NA)
919 return -ENOSYS;
920
921 if (info->step_uv == 0)
922 val = info->min_sel;
923 else
924 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
925
926 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
927 __func__, uvolt, ldo+1, info->vsel_reg, mask, val);
928
929 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
930 }
931
ldo_set_suspend_value(struct udevice * dev,int uvolt)932 static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
933 {
934 int ldo = dev->driver_data - 1;
935 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
936 int mask = info->vsel_mask;
937 int val;
938
939 if (info->vsel_sleep_reg == NA)
940 return -ENOSYS;
941
942 if (info->step_uv == 0)
943 val = info->min_sel;
944 else
945 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
946
947 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
948 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val);
949
950 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
951 }
952
ldo_get_suspend_value(struct udevice * dev)953 static int ldo_get_suspend_value(struct udevice *dev)
954 {
955 int ldo = dev->driver_data - 1;
956 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
957 int mask = info->vsel_mask;
958 int val, ret;
959
960 if (info->vsel_sleep_reg == NA)
961 return -ENOSYS;
962
963 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
964 if (ret < 0)
965 return ret;
966
967 val = ret & mask;
968
969 return info->min_uv + val * info->step_uv;
970 }
971
ldo_set_enable(struct udevice * dev,bool enable)972 static int ldo_set_enable(struct udevice *dev, bool enable)
973 {
974 int ldo = dev->driver_data - 1;
975
976 return _ldo_set_enable(dev->parent, ldo, enable);
977 }
978
ldo_set_suspend_enable(struct udevice * dev,bool enable)979 static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
980 {
981 int ldo = dev->driver_data - 1;
982
983 return _ldo_set_suspend_enable(dev->parent, ldo, enable);
984 }
985
ldo_get_suspend_enable(struct udevice * dev)986 static int ldo_get_suspend_enable(struct udevice *dev)
987 {
988 int ldo = dev->driver_data - 1;
989
990 return _ldo_get_suspend_enable(dev->parent, ldo);
991 }
992
ldo_get_enable(struct udevice * dev)993 static int ldo_get_enable(struct udevice *dev)
994 {
995 int ldo = dev->driver_data - 1;
996
997 return _ldo_get_enable(dev->parent, ldo);
998 }
999
switch_set_enable(struct udevice * dev,bool enable)1000 static int switch_set_enable(struct udevice *dev, bool enable)
1001 {
1002 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1003 int ret = 0, sw = dev->driver_data - 1;
1004 uint mask = 0;
1005
1006 switch (priv->variant) {
1007 case RK808_ID:
1008 mask = 1 << (sw + 5);
1009 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
1010 enable ? mask : 0);
1011 break;
1012 case RK809_ID:
1013 mask = (1 << (sw + 2)) | (1 << (sw + 6));
1014 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
1015 enable ? mask : (1 << (sw + 6)));
1016 break;
1017 case RK818_ID:
1018 mask = 1 << 6;
1019 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
1020 enable ? mask : 0);
1021 break;
1022 }
1023
1024 debug("%s: switch%d, enable=%d, mask=0x%x\n",
1025 __func__, sw + 1, enable, mask);
1026
1027 return ret;
1028 }
1029
switch_get_enable(struct udevice * dev)1030 static int switch_get_enable(struct udevice *dev)
1031 {
1032 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1033 int ret = 0, sw = dev->driver_data - 1;
1034 uint mask = 0;
1035
1036 switch (priv->variant) {
1037 case RK808_ID:
1038 mask = 1 << (sw + 5);
1039 ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
1040 break;
1041 case RK809_ID:
1042 mask = 1 << (sw + 2);
1043 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
1044 break;
1045 case RK818_ID:
1046 mask = 1 << 6;
1047 ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
1048 break;
1049 }
1050
1051 if (ret < 0)
1052 return ret;
1053
1054 return ret & mask ? true : false;
1055 }
1056
switch_set_suspend_value(struct udevice * dev,int uvolt)1057 static int switch_set_suspend_value(struct udevice *dev, int uvolt)
1058 {
1059 return 0;
1060 }
1061
switch_get_suspend_value(struct udevice * dev)1062 static int switch_get_suspend_value(struct udevice *dev)
1063 {
1064 return 0;
1065 }
1066
switch_set_suspend_enable(struct udevice * dev,bool enable)1067 static int switch_set_suspend_enable(struct udevice *dev, bool enable)
1068 {
1069 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1070 int ret = 0, sw = dev->driver_data - 1;
1071 uint mask = 0;
1072
1073 switch (priv->variant) {
1074 case RK808_ID:
1075 mask = 1 << (sw + 5);
1076 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
1077 enable ? 0 : mask);
1078 break;
1079 case RK809_ID:
1080 mask = 1 << (sw + 6);
1081 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
1082 enable ? mask : 0);
1083 break;
1084 case RK818_ID:
1085 mask = 1 << 6;
1086 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
1087 enable ? 0 : mask);
1088 break;
1089 }
1090
1091 debug("%s: switch%d, enable=%d, mask=0x%x\n",
1092 __func__, sw + 1, enable, mask);
1093
1094 return ret;
1095 }
1096
switch_get_suspend_enable(struct udevice * dev)1097 static int switch_get_suspend_enable(struct udevice *dev)
1098 {
1099 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1100 int val, ret = 0, sw = dev->driver_data - 1;
1101 uint mask = 0;
1102
1103 switch (priv->variant) {
1104 case RK808_ID:
1105 mask = 1 << (sw + 5);
1106 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
1107 if (val < 0)
1108 return val;
1109 ret = val & mask ? 0 : 1;
1110 break;
1111 case RK809_ID:
1112 mask = 1 << (sw + 6);
1113 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
1114 if (val < 0)
1115 return val;
1116 ret = val & mask ? 1 : 0;
1117 break;
1118 case RK818_ID:
1119 mask = 1 << 6;
1120 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
1121 if (val < 0)
1122 return val;
1123 ret = val & mask ? 0 : 1;
1124 break;
1125 }
1126
1127 return ret;
1128 }
1129
1130 /*
1131 * RK8xx switch does not need to set the voltage,
1132 * but if dts set regulator-min-microvolt/regulator-max-microvolt,
1133 * will cause regulator set value fail and not to enable this switch.
1134 * So add an empty function to return success.
1135 */
switch_get_value(struct udevice * dev)1136 static int switch_get_value(struct udevice *dev)
1137 {
1138 const char *supply_name[] = { "vcc9-supply", "vcc8-supply", };
1139 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1140 struct udevice *supply;
1141 int id = dev->driver_data - 1;
1142
1143 if (!switch_get_enable(dev))
1144 return 0;
1145
1146 /* note: rk817 only contains switch0 */
1147 if ((priv->variant == RK809_ID) || (priv->variant == RK817_ID)) {
1148 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
1149 dev_get_parent(dev),
1150 supply_name[id],
1151 &supply))
1152 return regulator_get_value(supply);
1153 }
1154
1155 return 0;
1156 }
1157
switch_set_value(struct udevice * dev,int uvolt)1158 static int switch_set_value(struct udevice *dev, int uvolt)
1159 {
1160 return 0;
1161 }
1162
rk8xx_buck_probe(struct udevice * dev)1163 static int rk8xx_buck_probe(struct udevice *dev)
1164 {
1165 struct dm_regulator_uclass_platdata *uc_pdata;
1166
1167 uc_pdata = dev_get_uclass_platdata(dev);
1168
1169 uc_pdata->type = REGULATOR_TYPE_BUCK;
1170 uc_pdata->mode_count = 0;
1171
1172 return 0;
1173 }
1174
rk8xx_ldo_probe(struct udevice * dev)1175 static int rk8xx_ldo_probe(struct udevice *dev)
1176 {
1177 struct dm_regulator_uclass_platdata *uc_pdata;
1178
1179 uc_pdata = dev_get_uclass_platdata(dev);
1180
1181 uc_pdata->type = REGULATOR_TYPE_LDO;
1182 uc_pdata->mode_count = 0;
1183
1184 return 0;
1185 }
1186
rk8xx_switch_probe(struct udevice * dev)1187 static int rk8xx_switch_probe(struct udevice *dev)
1188 {
1189 struct dm_regulator_uclass_platdata *uc_pdata;
1190
1191 uc_pdata = dev_get_uclass_platdata(dev);
1192
1193 uc_pdata->type = REGULATOR_TYPE_FIXED;
1194 uc_pdata->mode_count = 0;
1195
1196 return 0;
1197 }
1198
1199 static const struct dm_regulator_ops rk8xx_buck_ops = {
1200 .get_value = buck_get_value,
1201 .set_value = buck_set_value,
1202 .set_suspend_value = buck_set_suspend_value,
1203 .get_suspend_value = buck_get_suspend_value,
1204 .get_enable = buck_get_enable,
1205 .set_enable = buck_set_enable,
1206 .set_suspend_enable = buck_set_suspend_enable,
1207 .get_suspend_enable = buck_get_suspend_enable,
1208 .set_ramp_delay = buck_set_ramp_delay,
1209 };
1210
1211 static const struct dm_regulator_ops rk8xx_ldo_ops = {
1212 .get_value = ldo_get_value,
1213 .set_value = ldo_set_value,
1214 .set_suspend_value = ldo_set_suspend_value,
1215 .get_suspend_value = ldo_get_suspend_value,
1216 .get_enable = ldo_get_enable,
1217 .set_enable = ldo_set_enable,
1218 .set_suspend_enable = ldo_set_suspend_enable,
1219 .get_suspend_enable = ldo_get_suspend_enable,
1220 };
1221
1222 static const struct dm_regulator_ops rk8xx_switch_ops = {
1223 .get_value = switch_get_value,
1224 .set_value = switch_set_value,
1225 .get_enable = switch_get_enable,
1226 .set_enable = switch_set_enable,
1227 .set_suspend_enable = switch_set_suspend_enable,
1228 .get_suspend_enable = switch_get_suspend_enable,
1229 .set_suspend_value = switch_set_suspend_value,
1230 .get_suspend_value = switch_get_suspend_value,
1231 };
1232
1233 U_BOOT_DRIVER(rk8xx_buck) = {
1234 .name = "rk8xx_buck",
1235 .id = UCLASS_REGULATOR,
1236 .ops = &rk8xx_buck_ops,
1237 .probe = rk8xx_buck_probe,
1238 };
1239
1240 U_BOOT_DRIVER(rk8xx_ldo) = {
1241 .name = "rk8xx_ldo",
1242 .id = UCLASS_REGULATOR,
1243 .ops = &rk8xx_ldo_ops,
1244 .probe = rk8xx_ldo_probe,
1245 };
1246
1247 U_BOOT_DRIVER(rk8xx_switch) = {
1248 .name = "rk8xx_switch",
1249 .id = UCLASS_REGULATOR,
1250 .ops = &rk8xx_switch_ops,
1251 .probe = rk8xx_switch_probe,
1252 };
1253 #endif
1254
rk8xx_spl_configure_buck(struct udevice * pmic,int buck,int uvolt)1255 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
1256 {
1257 int ret;
1258
1259 ret = _buck_set_value(pmic, buck, uvolt);
1260 if (ret)
1261 return ret;
1262
1263 return _buck_set_enable(pmic, buck, true);
1264 }
1265
rk818_spl_configure_usb_input_current(struct udevice * pmic,int current_ma)1266 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
1267 {
1268 uint i;
1269
1270 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
1271 if (current_ma <= rk818_chrg_cur_input_array[i])
1272 break;
1273
1274 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
1275 }
1276
rk818_spl_configure_usb_chrg_shutdown(struct udevice * pmic,int uvolt)1277 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
1278 {
1279 uint i;
1280
1281 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
1282 if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
1283 break;
1284
1285 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
1286 i);
1287 }
1288