1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Shunqing Chen <csq@rock-chips.com>
6 */
7
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13
14 #include "rk628.h"
15 #include "rk628_combrxphy.h"
16 #include "rk628_combtxphy.h"
17 #include "rk628_cru.h"
18 #include "rk628_csi.h"
19 #include "rk628_dsi.h"
20 #include "rk628_hdmirx.h"
21
22 static const struct regmap_range rk628_cru_readable_ranges[] = {
23 regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
24 regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4),
25 regmap_reg_range(CRU_MODE_CON00, CRU_MODE_CON00),
26 regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21),
27 regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05),
28 regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04),
29 };
30
31 static const struct regmap_access_table rk628_cru_readable_table = {
32 .yes_ranges = rk628_cru_readable_ranges,
33 .n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges),
34 };
35
36 static const struct regmap_range rk628_combrxphy_readable_ranges[] = {
37 regmap_reg_range(COMBRX_REG(0x6600), COMBRX_REG(0x665b)),
38 regmap_reg_range(COMBRX_REG(0x66a0), COMBRX_REG(0x66db)),
39 regmap_reg_range(COMBRX_REG(0x66f0), COMBRX_REG(0x66ff)),
40 regmap_reg_range(COMBRX_REG(0x6700), COMBRX_REG(0x6790)),
41 };
42
43 static const struct regmap_access_table rk628_combrxphy_readable_table = {
44 .yes_ranges = rk628_combrxphy_readable_ranges,
45 .n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges),
46 };
47
48 static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
49 regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_SETUP_CTRL),
50 regmap_reg_range(HDMI_RX_HDMI_PCB_CTRL, HDMI_RX_HDMI_PCB_CTRL),
51 regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERROR_PROTECT),
52 regmap_reg_range(HDMI_RX_HDMI_SYNC_CTRL, HDMI_RX_HDMI_CKM_RESULT),
53 regmap_reg_range(HDMI_RX_HDMI_RESMPL_CTRL, HDMI_RX_HDMI_RESMPL_CTRL),
54 regmap_reg_range(HDMI_VM_CFG_CH2, HDMI_VM_CFG_CH2),
55 regmap_reg_range(HDMI_RX_HDCP_CTRL, HDMI_RX_HDCP_SETTINGS),
56 regmap_reg_range(HDMI_RX_HDCP_KIDX, HDMI_RX_HDCP_KIDX),
57 regmap_reg_range(HDMI_RX_HDCP_DBG, HDMI_RX_HDCP_AN0),
58 regmap_reg_range(HDMI_RX_HDCP_STS, HDMI_RX_HDCP_STS),
59 regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_HACT_PX),
60 regmap_reg_range(HDMI_RX_MD_VCTRL, HDMI_RX_MD_VSC),
61 regmap_reg_range(HDMI_RX_MD_VOL, HDMI_RX_MD_VTL),
62 regmap_reg_range(HDMI_RX_MD_IL_POL, HDMI_RX_MD_STS),
63 regmap_reg_range(HDMI_RX_AUD_CTRL, HDMI_RX_AUD_CTRL),
64 regmap_reg_range(HDMI_RX_AUD_PLL_CTRL, HDMI_RX_AUD_PLL_CTRL),
65 regmap_reg_range(HDMI_RX_AUD_CLK_CTRL, HDMI_RX_AUD_CLK_CTRL),
66 regmap_reg_range(HDMI_RX_AUD_FIFO_CTRL, HDMI_RX_AUD_FIFO_TH),
67 regmap_reg_range(HDMI_RX_AUD_CHEXTR_CTRL, HDMI_RX_AUD_PAO_CTRL),
68 regmap_reg_range(HDMI_RX_AUD_FIFO_STS, HDMI_RX_AUD_FIFO_STS),
69 regmap_reg_range(HDMI_RX_AUDPLL_GEN_CTS, HDMI_RX_AUDPLL_GEN_N),
70 regmap_reg_range(HDMI_RX_PDEC_CTRL, HDMI_RX_PDEC_CTRL),
71 regmap_reg_range(HDMI_RX_PDEC_AUDIODET_CTRL, HDMI_RX_PDEC_AUDIODET_CTRL),
72 regmap_reg_range(HDMI_RX_PDEC_ERR_FILTER, HDMI_RX_PDEC_ASP_CTRL),
73 regmap_reg_range(HDMI_RX_PDEC_STS, HDMI_RX_PDEC_STS),
74 regmap_reg_range(HDMI_RX_PDEC_GCP_AVMUTE, HDMI_RX_PDEC_GCP_AVMUTE),
75 regmap_reg_range(HDMI_RX_PDEC_ACR_CTS, HDMI_RX_PDEC_ACR_N),
76 regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_AIF_PB0),
77 regmap_reg_range(HDMI_RX_PDEC_AVI_PB, HDMI_RX_PDEC_AVI_PB),
78 regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
79 regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS2),
80 regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA0),
81 regmap_reg_range(HDMI_RX_PDEC_ISTS, HDMI_RX_PDEC_IEN),
82 regmap_reg_range(HDMI_RX_AUD_FIFO_ISTS, HDMI_RX_AUD_FIFO_IEN),
83 regmap_reg_range(HDMI_RX_MD_ISTS, HDMI_RX_MD_IEN),
84 regmap_reg_range(HDMI_RX_HDMI_ISTS, HDMI_RX_HDMI_IEN),
85 regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
86 };
87
88 static const struct regmap_access_table rk628_hdmirx_readable_table = {
89 .yes_ranges = rk628_hdmirx_readable_ranges,
90 .n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
91 };
92
93 static const struct regmap_range rk628_key_readable_ranges[] = {
94 regmap_reg_range(EDID_BASE, EDID_BASE + 0x400),
95 };
96
97 static const struct regmap_access_table rk628_key_readable_table = {
98 .yes_ranges = rk628_key_readable_ranges,
99 .n_yes_ranges = ARRAY_SIZE(rk628_key_readable_ranges),
100 };
101
102 static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
103 regmap_reg_range(COMBTXPHY_BASE, COMBTXPHY_CON10),
104 };
105
106 static const struct regmap_access_table rk628_combtxphy_readable_table = {
107 .yes_ranges = rk628_combtxphy_readable_ranges,
108 .n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
109 };
110
111 static const struct regmap_range rk628_csi_readable_ranges[] = {
112 regmap_reg_range(CSITX_CONFIG_DONE, CSITX_CSITX_VERSION),
113 regmap_reg_range(CSITX_SYS_CTRL0_IMD, CSITX_TIMING_HPW_PADDING_NUM),
114 regmap_reg_range(CSITX_VOP_PATH_CTRL, CSITX_VOP_PATH_CTRL),
115 regmap_reg_range(CSITX_VOP_PATH_PKT_CTRL, CSITX_VOP_PATH_PKT_CTRL),
116 regmap_reg_range(CSITX_CSITX_STATUS0, CSITX_LPDT_DATA_IMD),
117 regmap_reg_range(CSITX_DPHY_CTRL, CSITX_DPHY_CTRL),
118 };
119
120 static const struct regmap_access_table rk628_csi_readable_table = {
121 .yes_ranges = rk628_csi_readable_ranges,
122 .n_yes_ranges = ARRAY_SIZE(rk628_csi_readable_ranges),
123 };
124
125 static const struct regmap_range rk628_dsi0_readable_ranges[] = {
126 regmap_reg_range(DSI0_BASE, DSI0_BASE + DSI_MAX_REGISTER),
127 };
128
129 static const struct regmap_access_table rk628_dsi0_readable_table = {
130 .yes_ranges = rk628_dsi0_readable_ranges,
131 .n_yes_ranges = ARRAY_SIZE(rk628_dsi0_readable_ranges),
132 };
133
134 static const struct regmap_range rk628_dsi1_readable_ranges[] = {
135 regmap_reg_range(DSI1_BASE, DSI1_BASE + DSI_MAX_REGISTER),
136 };
137
138 static const struct regmap_access_table rk628_dsi1_readable_table = {
139 .yes_ranges = rk628_dsi1_readable_ranges,
140 .n_yes_ranges = ARRAY_SIZE(rk628_dsi1_readable_ranges),
141 };
142
143
144 static const struct regmap_config rk628_regmap_config[RK628_DEV_MAX] = {
145 [RK628_DEV_GRF] = {
146 .name = "grf",
147 .reg_bits = 32,
148 .val_bits = 32,
149 .reg_stride = 4,
150 .max_register = GRF_MAX_REGISTER,
151 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
152 .val_format_endian = REGMAP_ENDIAN_LITTLE,
153 },
154 [RK628_DEV_CRU] = {
155 .name = "cru",
156 .reg_bits = 32,
157 .val_bits = 32,
158 .reg_stride = 4,
159 .max_register = CRU_MAX_REGISTER,
160 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
161 .val_format_endian = REGMAP_ENDIAN_LITTLE,
162 .rd_table = &rk628_cru_readable_table,
163 },
164 [RK628_DEV_COMBRXPHY] = {
165 .name = "combrxphy",
166 .reg_bits = 32,
167 .val_bits = 32,
168 .reg_stride = 4,
169 .max_register = COMBRX_REG(0x6790),
170 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
171 .val_format_endian = REGMAP_ENDIAN_LITTLE,
172 .rd_table = &rk628_combrxphy_readable_table,
173 },
174 [RK628_DEV_DSI0] = {
175 .name = "dsi0",
176 .reg_bits = 32,
177 .val_bits = 32,
178 .reg_stride = 4,
179 .max_register = DSI0_BASE + DSI_MAX_REGISTER,
180 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
181 .val_format_endian = REGMAP_ENDIAN_LITTLE,
182 .rd_table = &rk628_dsi0_readable_table,
183 },
184 [RK628_DEV_DSI1] = {
185 .name = "dsi1",
186 .reg_bits = 32,
187 .val_bits = 32,
188 .reg_stride = 4,
189 .max_register = DSI1_BASE + DSI_MAX_REGISTER,
190 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
191 .val_format_endian = REGMAP_ENDIAN_LITTLE,
192 .rd_table = &rk628_dsi1_readable_table,
193 },
194 [RK628_DEV_HDMIRX] = {
195 .name = "hdmirx",
196 .reg_bits = 32,
197 .val_bits = 32,
198 .reg_stride = 4,
199 .max_register = HDMI_RX_MAX_REGISTER,
200 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
201 .val_format_endian = REGMAP_ENDIAN_LITTLE,
202 .rd_table = &rk628_hdmirx_readable_table,
203 },
204 [RK628_DEV_ADAPTER] = {
205 .name = "adapter",
206 .reg_bits = 32,
207 .val_bits = 32,
208 .reg_stride = 4,
209 .max_register = KEY_MAX_REGISTER,
210 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
211 .val_format_endian = REGMAP_ENDIAN_LITTLE,
212 .rd_table = &rk628_key_readable_table,
213 },
214 [RK628_DEV_COMBTXPHY] = {
215 .name = "combtxphy",
216 .reg_bits = 32,
217 .val_bits = 32,
218 .reg_stride = 4,
219 .max_register = COMBTXPHY_CON10,
220 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
221 .val_format_endian = REGMAP_ENDIAN_LITTLE,
222 .rd_table = &rk628_combtxphy_readable_table,
223 },
224 [RK628_DEV_CSI] = {
225 .name = "csi",
226 .reg_bits = 32,
227 .val_bits = 32,
228 .reg_stride = 4,
229 .max_register = CSI_MAX_REGISTER,
230 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
231 .val_format_endian = REGMAP_ENDIAN_LITTLE,
232 .rd_table = &rk628_csi_readable_table,
233 },
234 };
235
rk628_i2c_register(struct i2c_client * client)236 struct rk628 *rk628_i2c_register(struct i2c_client *client)
237 {
238 struct rk628 *rk628;
239 int i, ret;
240 struct device *dev = &client->dev;
241
242 rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
243 if (!rk628)
244 return NULL;
245
246 rk628->client = client;
247 rk628->dev = dev;
248 for (i = 0; i < RK628_DEV_MAX; i++) {
249 const struct regmap_config *config = &rk628_regmap_config[i];
250
251 if (!config->name)
252 continue;
253
254 rk628->regmap[i] = devm_regmap_init_i2c(client, config);
255 if (IS_ERR(rk628->regmap[i])) {
256 ret = PTR_ERR(rk628->regmap[i]);
257 dev_err(dev, "failed to allocate register map %d: %d\n",
258 i, ret);
259 return NULL;
260 }
261 }
262
263 return rk628;
264 }
265 EXPORT_SYMBOL(rk628_i2c_register);
266
calc_dsp_frm_hst_vst(const struct videomode * src,const struct videomode * dst,u32 * dsp_frame_hst,u32 * dsp_frame_vst)267 static void calc_dsp_frm_hst_vst(const struct videomode *src,
268 const struct videomode *dst,
269 u32 *dsp_frame_hst, u32 *dsp_frame_vst)
270 {
271 u32 bp_in, bp_out;
272 u32 v_scale_ratio;
273 u64 t_frm_st;
274 u64 t_bp_in, t_bp_out, t_delta, tin;
275 u32 src_pixclock, dst_pixclock;
276 u32 dsp_htotal, src_htotal, src_vtotal;
277
278 src_pixclock = div_u64(1000000000000llu, src->pixelclock);
279 dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
280
281 src_htotal = src->hsync_len + src->hback_porch + src->hactive +
282 src->hfront_porch;
283 src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
284 src->vfront_porch;
285 dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
286 dst->hfront_porch;
287
288 bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
289 src->hsync_len + src->hback_porch;
290 bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
291 dst->hsync_len + dst->hback_porch;
292
293 t_bp_in = bp_in * src_pixclock;
294 t_bp_out = bp_out * dst_pixclock;
295 tin = src_vtotal * src_htotal * src_pixclock;
296
297 v_scale_ratio = src->vactive / dst->vactive;
298 if (v_scale_ratio <= 2)
299 t_delta = 5 * src_htotal * src_pixclock;
300 else
301 t_delta = 12 * src_htotal * src_pixclock;
302
303 if (t_bp_in + t_delta > t_bp_out)
304 t_frm_st = (t_bp_in + t_delta - t_bp_out);
305 else
306 t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
307
308 do_div(t_frm_st, src_pixclock);
309 *dsp_frame_hst = do_div(t_frm_st, src_htotal);
310 *dsp_frame_vst = t_frm_st;
311 }
312
rk628_post_process_scaler_init(struct rk628 * rk628,const struct videomode * src,const struct videomode * dst)313 static void rk628_post_process_scaler_init(struct rk628 *rk628,
314 const struct videomode *src,
315 const struct videomode *dst)
316 {
317 u32 dsp_frame_hst, dsp_frame_vst;
318 u32 scl_hor_mode, scl_ver_mode;
319 u32 scl_v_factor, scl_h_factor;
320 u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
321 u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
322 u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
323 u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
324 u8 hor_down_mode = 0, ver_down_mode = 0;
325
326 dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
327 dst->hfront_porch;
328 dsp_vtotal = dst->vsync_len + dst->vback_porch + dst->vactive +
329 dst->vfront_porch;
330 dsp_hs_end = dst->hsync_len;
331 dsp_vs_end = dst->vsync_len;
332 dsp_hbor_end = dst->hsync_len + dst->hback_porch + dst->hactive;
333 dsp_hbor_st = dst->hsync_len + dst->hback_porch;
334 dsp_vbor_end = dst->vsync_len + dst->vback_porch + dst->vactive;
335 dsp_vbor_st = dst->vsync_len + dst->vback_porch;
336 dsp_hact_st = dsp_hbor_st + bor_left;
337 dsp_hact_end = dsp_hbor_end - bor_right;
338 dsp_vact_st = dsp_vbor_st + bor_up;
339 dsp_vact_end = dsp_vbor_end - bor_down;
340
341 calc_dsp_frm_hst_vst(src, dst, &dsp_frame_hst, &dsp_frame_vst);
342 dev_dbg(rk628->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
343 dsp_frame_vst, dsp_frame_hst);
344
345 if (src->hactive > dst->hactive) {
346 scl_hor_mode = 2;
347
348 if (hor_down_mode == 0) {
349 if ((src->hactive - 1) / (dst->hactive - 1) > 2)
350 scl_h_factor = ((src->hactive - 1) << 14) /
351 (dst->hactive - 1);
352 else
353 scl_h_factor = ((src->hactive - 2) << 14) /
354 (dst->hactive - 1);
355 } else {
356 scl_h_factor = (dst->hactive << 16) /
357 (src->hactive - 1);
358 }
359
360 dev_dbg(rk628->dev, "horizontal scale down\n");
361 } else if (src->hactive == dst->hactive) {
362 scl_hor_mode = 0;
363 scl_h_factor = 0;
364
365 dev_dbg(rk628->dev, "horizontal no scale\n");
366 } else {
367 scl_hor_mode = 1;
368 scl_h_factor = ((src->hactive - 1) << 16) / (dst->hactive - 1);
369
370 dev_dbg(rk628->dev, "horizontal scale up\n");
371 }
372
373 if (src->vactive > dst->vactive) {
374 scl_ver_mode = 2;
375
376 if (ver_down_mode == 0) {
377 if ((src->vactive - 1) / (dst->vactive - 1) > 2)
378 scl_v_factor = ((src->vactive - 1) << 14) /
379 (dst->vactive - 1);
380 else
381 scl_v_factor = ((src->vactive - 2) << 14) /
382 (dst->vactive - 1);
383 } else {
384 scl_v_factor = (dst->vactive << 16) /
385 (src->vactive - 1);
386 }
387
388 dev_dbg(rk628->dev, "vertical scale down\n");
389 } else if (src->vactive == dst->vactive) {
390 scl_ver_mode = 0;
391 scl_v_factor = 0;
392
393 dev_dbg(rk628->dev, "vertical no scale\n");
394 } else {
395 scl_ver_mode = 1;
396 scl_v_factor = ((src->vactive - 1) << 16) / (dst->vactive - 1);
397
398 dev_dbg(rk628->dev, "vertical scale up\n");
399 }
400
401 rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0,
402 SW_HRES_MASK, SW_HRES(src->hactive));
403 rk628_i2c_write(rk628, GRF_SCALER_CON0,
404 SCL_VER_DOWN_MODE(ver_down_mode) |
405 SCL_HOR_DOWN_MODE(hor_down_mode) |
406 SCL_VER_MODE(scl_ver_mode) |
407 SCL_HOR_MODE(scl_hor_mode) |
408 SCL_EN(1));
409 rk628_i2c_write(rk628, GRF_SCALER_CON1,
410 SCL_V_FACTOR(scl_v_factor) |
411 SCL_H_FACTOR(scl_h_factor));
412 rk628_i2c_write(rk628, GRF_SCALER_CON2,
413 DSP_FRAME_VST(dsp_frame_vst) |
414 DSP_FRAME_HST(dsp_frame_hst));
415 rk628_i2c_write(rk628, GRF_SCALER_CON3,
416 DSP_HS_END(dsp_hs_end) |
417 DSP_HTOTAL(dsp_htotal));
418 rk628_i2c_write(rk628, GRF_SCALER_CON4,
419 DSP_HACT_END(dsp_hact_end) |
420 DSP_HACT_ST(dsp_hact_st));
421 rk628_i2c_write(rk628, GRF_SCALER_CON5,
422 DSP_VS_END(dsp_vs_end) |
423 DSP_VTOTAL(dsp_vtotal));
424 rk628_i2c_write(rk628, GRF_SCALER_CON6,
425 DSP_VACT_END(dsp_vact_end) |
426 DSP_VACT_ST(dsp_vact_st));
427 rk628_i2c_write(rk628, GRF_SCALER_CON7,
428 DSP_HBOR_END(dsp_hbor_end) |
429 DSP_HBOR_ST(dsp_hbor_st));
430 rk628_i2c_write(rk628, GRF_SCALER_CON8,
431 DSP_VBOR_END(dsp_vbor_end) |
432 DSP_VBOR_ST(dsp_vbor_st));
433 }
434
rk628_post_process_en(struct rk628 * rk628,struct videomode * src,struct videomode * dst,u64 * dst_pclk)435 void rk628_post_process_en(struct rk628 *rk628,
436 struct videomode *src,
437 struct videomode *dst,
438 u64 *dst_pclk)
439 {
440 u64 dst_rate, src_rate;
441 u64 dst_htotal, src_htotal;
442
443 src_rate = src->pixelclock;
444 dst_htotal = dst->hactive + dst->hfront_porch + dst->hsync_len + dst->hback_porch;
445 dst_rate = src_rate * dst->vactive * dst_htotal;
446 src_htotal = src->hactive + src->hfront_porch + src->hsync_len + src->hback_porch;
447 do_div(dst_rate, (src->vactive * src_htotal));
448 dst->pixelclock = dst_rate;
449 *dst_pclk = dst->pixelclock;
450
451 dev_info(rk628->dev, "src %dx%d clock:%lu\n",
452 src->hactive, src->vactive, src->pixelclock);
453 dev_info(rk628->dev, "dst %dx%d clock:%lu\n",
454 dst->hactive, dst->vactive, dst->pixelclock);
455 dst->flags = 0;
456
457 rk628_control_assert(rk628, RGU_DECODER);
458 udelay(10);
459 rk628_control_deassert(rk628, RGU_DECODER);
460 udelay(10);
461
462 rk628_clk_set_rate(rk628, CGU_CLK_RX_READ, src->pixelclock);
463 rk628_control_assert(rk628, RGU_CLK_RX);
464 udelay(10);
465 rk628_control_deassert(rk628, RGU_CLK_RX);
466 udelay(10);
467
468 rk628_clk_set_rate(rk628, CGU_SCLK_VOP, dst->pixelclock);
469 rk628_control_assert(rk628, RGU_VOP);
470 udelay(10);
471 rk628_control_deassert(rk628, RGU_VOP);
472 udelay(10);
473
474 rk628_post_process_scaler_init(rk628, src, dst);
475 }
476 EXPORT_SYMBOL(rk628_post_process_en);
477
478 MODULE_AUTHOR("Shunqing Chen <csq@rock-chips.com>");
479 MODULE_DESCRIPTION("Rockchip RK628 driver");
480 MODULE_LICENSE("GPL");
481