1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <spl_display.h> 21 #include <clk.h> 22 23 /* 24 * major: IP major version, used for IP structure 25 * minor: big feature change under same structure 26 * build: RTL current SVN number 27 */ 28 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 29 #define VOP_MAJOR(version) ((version) >> 8) 30 #define VOP_MINOR(version) ((version) & 0xff) 31 32 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 33 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 34 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 35 #define VOP2_BUILD(version) ((version) & 0xffff) 36 37 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 38 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 39 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 40 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 41 42 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 43 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 44 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 45 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 46 47 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 48 49 enum data_format { 50 ROCKCHIP_FMT_ARGB8888 = 0, 51 ROCKCHIP_FMT_RGB888, 52 ROCKCHIP_FMT_RGB565, 53 ROCKCHIP_FMT_YUV420SP = 4, 54 ROCKCHIP_FMT_YUV422SP, 55 ROCKCHIP_FMT_YUV444SP, 56 }; 57 58 enum display_mode { 59 ROCKCHIP_DISPLAY_FULLSCREEN, 60 ROCKCHIP_DISPLAY_CENTER, 61 }; 62 63 enum rockchip_cmd_type { 64 CMD_TYPE_DEFAULT, 65 CMD_TYPE_SPI, 66 CMD_TYPE_MCU 67 }; 68 69 enum rockchip_mcu_cmd { 70 MCU_WRCMD = 0, 71 MCU_WRDATA, 72 MCU_SETBYPASS, 73 }; 74 75 /* 76 * display output interface supported by rockchip lcdc 77 */ 78 #define ROCKCHIP_OUT_MODE_P888 0 79 #define ROCKCHIP_OUT_MODE_BT1120 0 80 #define ROCKCHIP_OUT_MODE_P666 1 81 #define ROCKCHIP_OUT_MODE_P565 2 82 #define ROCKCHIP_OUT_MODE_BT656 5 83 #define ROCKCHIP_OUT_MODE_S888 8 84 #define ROCKCHIP_OUT_MODE_YUV422 9 85 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 86 #define ROCKCHIP_OUT_MODE_YUV420 14 87 /* for use special outface */ 88 #define ROCKCHIP_OUT_MODE_AAAA 15 89 90 #define VOP_OUTPUT_IF_RGB BIT(0) 91 #define VOP_OUTPUT_IF_BT1120 BIT(1) 92 #define VOP_OUTPUT_IF_BT656 BIT(2) 93 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 94 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 95 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 96 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 97 #define VOP_OUTPUT_IF_eDP0 BIT(7) 98 #define VOP_OUTPUT_IF_eDP1 BIT(8) 99 #define VOP_OUTPUT_IF_DP0 BIT(9) 100 #define VOP_OUTPUT_IF_DP1 BIT(10) 101 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 102 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 103 104 struct rockchip_mcu_timing { 105 int mcu_pix_total; 106 int mcu_cs_pst; 107 int mcu_cs_pend; 108 int mcu_rw_pst; 109 int mcu_rw_pend; 110 int mcu_hold_mode; 111 }; 112 113 struct vop_rect { 114 int width; 115 int height; 116 }; 117 118 struct rockchip_dsc_sink_cap { 119 /** 120 * @slice_width: the number of pixel columns that comprise the slice width 121 * @slice_height: the number of pixel rows that comprise the slice height 122 * @block_pred: Does block prediction 123 * @native_420: Does sink support DSC with 4:2:0 compression 124 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 125 * @version_major: DSC major version 126 * @version_minor: DSC minor version 127 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 128 */ 129 u16 slice_width; 130 u16 slice_height; 131 bool block_pred; 132 bool native_420; 133 u8 bpc_supported; 134 u8 version_major; 135 u8 version_minor; 136 u16 target_bits_per_pixel_x16; 137 }; 138 139 struct display_rect { 140 int x; 141 int y; 142 int w; 143 int h; 144 }; 145 146 struct bcsh_state { 147 int brightness; 148 int contrast; 149 int saturation; 150 int sin_hue; 151 int cos_hue; 152 }; 153 154 struct crtc_state { 155 struct udevice *dev; 156 struct rockchip_crtc *crtc; 157 void *private; 158 ofnode node; 159 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 160 struct clk dclk; 161 int crtc_id; 162 163 int format; 164 u32 dma_addr; 165 int ymirror; 166 int rb_swap; 167 int xvir; 168 int post_csc_mode; 169 int dclk_core_div; 170 int dclk_out_div; 171 struct display_rect src_rect; 172 struct display_rect crtc_rect; 173 struct display_rect right_src_rect; 174 struct display_rect right_crtc_rect; 175 bool yuv_overlay; 176 bool post_r2y_en; 177 bool post_y2r_en; 178 bool bcsh_en; 179 bool splice_mode; 180 bool soft_te; 181 u8 splice_crtc_id; 182 u8 dsc_id; 183 u8 dsc_enable; 184 u8 dsc_slice_num; 185 u8 dsc_pixel_num; 186 struct rockchip_mcu_timing mcu_timing; 187 u32 dual_channel_swap; 188 u32 feature; 189 struct vop_rect max_output; 190 191 u64 dsc_txp_clk_rate; 192 u64 dsc_pxl_clk_rate; 193 u64 dsc_cds_clk_rate; 194 struct drm_dsc_picture_parameter_set pps; 195 struct rockchip_dsc_sink_cap dsc_sink_cap; 196 }; 197 198 struct panel_state { 199 struct rockchip_panel *panel; 200 201 ofnode dsp_lut_node; 202 }; 203 204 struct overscan { 205 int left_margin; 206 int right_margin; 207 int top_margin; 208 int bottom_margin; 209 }; 210 211 struct connector_state { 212 struct rockchip_connector *connector; 213 struct rockchip_connector *secondary; 214 215 struct drm_display_mode mode; 216 struct overscan overscan; 217 u8 edid[EDID_SIZE * 4]; 218 int bus_format; 219 u32 bus_flags; 220 int output_mode; 221 int type; 222 int output_if; 223 int output_flags; 224 int color_space; 225 unsigned int bpc; 226 227 /** 228 * @hold_mode: enabled when it's: 229 * (1) mcu hold mode 230 * (2) mipi dsi cmd mode 231 * (3) edp psr mode 232 */ 233 bool hold_mode; 234 235 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 236 237 u8 dsc_id; 238 u8 dsc_slice_num; 239 u8 dsc_pixel_num; 240 u64 dsc_txp_clk; 241 u64 dsc_pxl_clk; 242 u64 dsc_cds_clk; 243 struct rockchip_dsc_sink_cap dsc_sink_cap; 244 struct drm_dsc_picture_parameter_set pps; 245 246 struct gpio_desc *te_gpio; 247 248 struct { 249 u32 *lut; 250 int size; 251 } gamma; 252 }; 253 254 struct logo_info { 255 int mode; 256 char *mem; 257 bool ymirror; 258 u32 offset; 259 u32 width; 260 int height; 261 u32 bpp; 262 }; 263 264 struct rockchip_logo_cache { 265 struct list_head head; 266 char name[20]; 267 struct logo_info logo; 268 }; 269 270 struct display_state { 271 struct list_head head; 272 273 const void *blob; 274 ofnode node; 275 276 struct crtc_state crtc_state; 277 struct connector_state conn_state; 278 struct panel_state panel_state; 279 280 char ulogo_name[30]; 281 char klogo_name[30]; 282 283 struct logo_info logo; 284 int logo_mode; 285 int charge_logo_mode; 286 void *mem_base; 287 int mem_size; 288 289 int enable; 290 int is_init; 291 int is_enable; 292 bool is_klogo_valid; 293 bool force_output; 294 bool enabled_at_spl; 295 struct drm_display_mode force_mode; 296 u32 force_bus_format; 297 }; 298 299 int drm_mode_vrefresh(const struct drm_display_mode *mode); 300 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 301 bool drm_mode_is_420(const struct drm_display_info *display, 302 struct drm_display_mode *mode); 303 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 304 305 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 306 struct vop_rect *max_output); 307 unsigned long get_cubic_lut_buffer(int crtc_id); 308 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 309 u32 *bus_flags); 310 void rockchip_display_make_crc32_table(void); 311 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 312 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 313 314 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 315 int min_hscale, int max_hscale); 316 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 317 int min_vscale, int max_vscale); 318 const struct device_node * 319 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 320 321 #ifdef CONFIG_SPL_BUILD 322 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 323 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 324 int inno_spl_hdmi_phy_probe(struct display_state *state); 325 #endif 326 #endif 327