1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Rockchip Electronics Co., Ltd.
4 *
5 * Author: Huang Lee <Putin.li@rock-chips.com>
6 */
7
8 #define pr_fmt(fmt) "rga2_reg: " fmt
9
10 #include "rga2_reg_info.h"
11 #include "rga_dma_buf.h"
12 #include "rga_iommu.h"
13 #include "rga_common.h"
14 #include "rga_hw_config.h"
15 #include "rga_debugger.h"
16
17 unsigned int rga2_rop_code[256] = {
18 0x00000007, 0x00000451, 0x00006051, 0x00800051,
19 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
20 0x00800765, 0x000004b0, 0x00000065, 0x000004f4,
21 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
22
23 0x00006850, 0x00800050, 0x00805028, 0x00000568,
24 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
25 0x008007aa, 0x00036071, 0x00002c6a, 0x00803631,
26 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
27
28 0x0080066e, 0x00000528, 0x00000066, 0x0000056c,
29 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
30 0x00800631, 0x0002b471, 0x00006071, 0x008037aa,
31 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
32
33 0x0000006e, 0x00000565, 0x00003451, 0x00800006,
34 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
35 0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c,
36 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
37
38 0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870,
39 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
40 0x00800728, 0x0002a561, 0x000026c2, 0x008002c6,
41 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
42
43 0x0000006c, 0x00000475, 0x000024e2, 0x008036b0,
44 0x00804051, 0x00800004, 0x00800251, 0x00000651,
45 0x00002e4a, 0x0080024e, 0x00000028, 0x00824842,
46 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
47
48 0x008006b0, 0x000234f0, 0x00002741, 0x00800345,
49 0x00003651, 0x00800255, 0x00000030, 0x00834051,
50 0x00a34842, 0x000002b0, 0x00800271, 0x0002b651,
51 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
52
53 0x00006870, 0x008037a2, 0x00003431, 0x00000745,
54 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
55 0x008002f0, 0x000236d0, 0x000026d4, 0x00807028,
56 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
57
58 0x00800671, 0x000005aa, 0x00006031, 0x008036c6,
59 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
60 0x00000070, 0x0080346e, 0x00800655, 0x00802521,
61 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
62
63 0x00006830, 0x0080364e, 0x00822f48, 0x00000361,
64 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
65 0x00034051, 0x00800030, 0x0080026e, 0x00803651,
66 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
67
68 0x00000068, 0x00802c75, 0x0080064e, 0x008024a2,
69 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
70 0x00800651, 0x00000251, 0x00800000, 0x00004051,
71 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
72
73 0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068,
74 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
75 0x00002f28, 0x00802561, 0x0080046e, 0x00000046,
76 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
77
78 0x00000071, 0x008034e6, 0x00034850, 0x00800031,
79 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
80 0x00800748, 0x00000341, 0x000026a2, 0x008034f0,
81 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
82
83 0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0,
84 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
85 0x00002e2a, 0x00803471, 0x00826862, 0x010007aa,
86 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
87
88 0x008006d0, 0x000002d0, 0x00002721, 0x00802d68,
89 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
90 0x010037aa, 0x00a36870, 0x00800471, 0x00004031,
91 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
92
93 0x00800001, 0x00004850, 0x008004e6, 0x0000004e,
94 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
95 0x008004f0, 0x00004830, 0x00000048, 0x0080044e,
96 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
97 };
98
RGA2_reg_get_param(unsigned char * base,struct rga2_req * msg)99 static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
100 {
101 u32 *bRGA_SRC_X_FACTOR;
102 u32 *bRGA_SRC_Y_FACTOR;
103 u32 sw, sh;
104 u32 dw, dh;
105 u32 param_x, param_y;
106
107 bRGA_SRC_X_FACTOR = (u32 *) (base + RGA2_SRC_X_FACTOR_OFFSET);
108 bRGA_SRC_Y_FACTOR = (u32 *) (base + RGA2_SRC_Y_FACTOR_OFFSET);
109
110 if (((msg->rotate_mode & 0x3) == 1) ||
111 ((msg->rotate_mode & 0x3) == 3)) {
112 dw = msg->dst.act_h;
113 dh = msg->dst.act_w;
114 } else {
115 dw = msg->dst.act_w;
116 dh = msg->dst.act_h;
117 }
118
119 sw = msg->src.act_w;
120 sh = msg->src.act_h;
121
122 if (sw > dw) {
123 #if SCALE_DOWN_LARGE
124 param_x = ((dw) << 16) / (sw) + 1;
125 #else
126 param_x = ((dw) << 16) / (sw);
127 #endif
128 *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 0);
129 } else if (sw < dw) {
130 #if SCALE_UP_LARGE
131 param_x = ((sw - 1) << 16) / (dw - 1);
132 #else
133 param_x = ((sw) << 16) / (dw);
134 #endif
135 *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 16);
136 } else {
137 *bRGA_SRC_X_FACTOR = 0; //((1 << 14) << 16) | (1 << 14);
138 }
139
140 if (sh > dh) {
141 #if SCALE_DOWN_LARGE
142 param_y = ((dh) << 16) / (sh) + 1;
143 #else
144 param_y = ((dh) << 16) / (sh);
145 #endif
146 *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 0);
147 } else if (sh < dh) {
148 #if SCALE_UP_LARGE
149 param_y = ((sh - 1) << 16) / (dh - 1);
150 #else
151 param_y = ((sh) << 16) / (dh);
152 #endif
153 *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 16);
154 } else {
155 *bRGA_SRC_Y_FACTOR = 0; //((1 << 14) << 16) | (1 << 14);
156 }
157 }
158
RGA2_set_mode_ctrl(u8 * base,struct rga2_req * msg)159 static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
160 {
161 u32 *bRGA_MODE_CTL;
162 u32 reg = 0;
163 u32 render_mode = msg->render_mode;
164
165 bRGA_MODE_CTL = (u32 *) (base + RGA2_MODE_CTRL_OFFSET);
166
167 if (msg->render_mode == UPDATE_PALETTE_TABLE_MODE)
168 render_mode = 0x3;
169
170 reg =
171 ((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) |
172 (s_RGA2_MODE_CTRL_SW_RENDER_MODE(render_mode)));
173 reg =
174 ((reg & (~m_RGA2_MODE_CTRL_SW_BITBLT_MODE)) |
175 (s_RGA2_MODE_CTRL_SW_BITBLT_MODE(msg->bitblt_mode)));
176 reg =
177 ((reg & (~m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT)) |
178 (s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(msg->color_fill_mode)));
179 reg =
180 ((reg & (~m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET)) |
181 (s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(msg->alpha_zero_key)));
182 reg =
183 ((reg & (~m_RGA2_MODE_CTRL_SW_GRADIENT_SAT)) |
184 (s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(msg->alpha_rop_flag >> 7)));
185 reg =
186 ((reg & (~m_RGA2_MODE_CTRL_SW_INTR_CF_E)) |
187 (s_RGA2_MODE_CTRL_SW_INTR_CF_E(msg->CMD_fin_int_enable)));
188
189 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_MOSAIC_EN)) |
190 (s_RGA2_MODE_CTRL_SW_MOSAIC_EN(msg->mosaic_info.enable)));
191
192 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_YIN_YOUT_EN)) |
193 (s_RGA2_MODE_CTRL_SW_YIN_YOUT_EN(msg->yin_yout_en)));
194
195 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_OSD_E)) |
196 (s_RGA2_MODE_CTRL_SW_OSD_E(msg->osd_info.enable)));
197
198 *bRGA_MODE_CTL = reg;
199 }
200
RGA2_set_reg_src_info(u8 * base,struct rga2_req * msg)201 static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
202 {
203 u32 *bRGA_SRC_INFO;
204 u32 *bRGA_SRC_BASE0, *bRGA_SRC_BASE1, *bRGA_SRC_BASE2;
205 u32 *bRGA_SRC_VIR_INFO;
206 u32 *bRGA_SRC_ACT_INFO;
207 u32 *bRGA_MASK_ADDR;
208 u32 *bRGA_SRC_TR_COLOR0, *bRGA_SRC_TR_COLOR1;
209
210 u8 disable_uv_channel_en = 0;
211
212 u32 reg = 0;
213 u8 src0_format = 0;
214
215 u8 src0_rb_swp = 0;
216 u8 src0_alpha_swp = 0;
217
218 u8 src0_cbcr_swp = 0;
219 u8 pixel_width = 1;
220 u32 stride = 0;
221 u32 uv_stride = 0;
222 u32 mask_stride = 0;
223 u32 ydiv = 1, xdiv = 2;
224 u8 yuv10 = 0;
225
226 u32 sw, sh;
227 u32 dw, dh;
228 u8 rotate_mode;
229 u8 vsp_scale_mode = 0;
230 u8 scale_w_flag, scale_h_flag;
231
232 bRGA_SRC_INFO = (u32 *) (base + RGA2_SRC_INFO_OFFSET);
233
234 bRGA_SRC_BASE0 = (u32 *) (base + RGA2_SRC_BASE0_OFFSET);
235 bRGA_SRC_BASE1 = (u32 *) (base + RGA2_SRC_BASE1_OFFSET);
236 bRGA_SRC_BASE2 = (u32 *) (base + RGA2_SRC_BASE2_OFFSET);
237
238 bRGA_SRC_VIR_INFO = (u32 *) (base + RGA2_SRC_VIR_INFO_OFFSET);
239 bRGA_SRC_ACT_INFO = (u32 *) (base + RGA2_SRC_ACT_INFO_OFFSET);
240
241 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
242
243 bRGA_SRC_TR_COLOR0 = (u32 *) (base + RGA2_SRC_TR_COLOR0_OFFSET);
244 bRGA_SRC_TR_COLOR1 = (u32 *) (base + RGA2_SRC_TR_COLOR1_OFFSET);
245
246 if (msg->src.format == RGA_FORMAT_YCbCr_420_SP_10B ||
247 msg->src.format == RGA_FORMAT_YCrCb_420_SP_10B) {
248 if ((msg->src.act_w == msg->dst.act_w) &&
249 (msg->src.act_h == msg->dst.act_h) &&
250 (msg->rotate_mode == 0))
251 msg->rotate_mode = 1 << 6;
252 }
253
254 {
255 rotate_mode = msg->rotate_mode & 0x3;
256
257 sw = msg->src.act_w;
258 sh = msg->src.act_h;
259
260 if ((rotate_mode == 1) | (rotate_mode == 3)) {
261 dw = msg->dst.act_h;
262 dh = msg->dst.act_w;
263 } else {
264 dw = msg->dst.act_w;
265 dh = msg->dst.act_h;
266 }
267
268 if (sw > dw)
269 scale_w_flag = 1;
270 else if (sw < dw)
271 scale_w_flag = 2;
272 else {
273 scale_w_flag = 0;
274 if (msg->rotate_mode >> 6)
275 scale_w_flag = 3;
276 }
277
278 if (sh > dh)
279 scale_h_flag = 1;
280 else if (sh < dh)
281 scale_h_flag = 2;
282 else {
283 scale_h_flag = 0;
284 if (msg->rotate_mode >> 6)
285 scale_h_flag = 3;
286 }
287
288 /* uvvds need to force tile mode. */
289 if (msg->uvvds_mode && scale_w_flag == 0)
290 scale_w_flag = 3;
291 }
292
293 /* VSP scale mode select, HSD > VSD > VSP > HSP */
294 if (scale_h_flag == 0x2) {
295 /* After HSD, VSP needs to check dst_width */
296 if ((scale_w_flag == 0x1) && (dw < RGA2_VSP_BICUBIC_LIMIT))
297 vsp_scale_mode = 0x0;
298 else if (sw < RGA2_VSP_BICUBIC_LIMIT)
299 vsp_scale_mode = 0x0;
300 else
301 /* default select bilinear */
302 vsp_scale_mode = 0x1;
303 }
304
305 switch (msg->src.format) {
306 case RGA_FORMAT_RGBA_8888:
307 src0_format = 0x0;
308 pixel_width = 4;
309 break;
310 case RGA_FORMAT_BGRA_8888:
311 src0_format = 0x0;
312 src0_rb_swp = 0x1;
313 pixel_width = 4;
314 break;
315 case RGA_FORMAT_RGBX_8888:
316 src0_format = 0x1;
317 pixel_width = 4;
318 msg->src_trans_mode &= 0x07;
319 break;
320 case RGA_FORMAT_BGRX_8888:
321 src0_format = 0x1;
322 src0_rb_swp = 0x1;
323 pixel_width = 4;
324 msg->src_trans_mode &= 0x07;
325 break;
326 case RGA_FORMAT_RGB_888:
327 src0_format = 0x2;
328 pixel_width = 3;
329 msg->src_trans_mode &= 0x07;
330 break;
331 case RGA_FORMAT_BGR_888:
332 src0_format = 0x2;
333 src0_rb_swp = 1;
334 pixel_width = 3;
335 msg->src_trans_mode &= 0x07;
336 break;
337 case RGA_FORMAT_RGB_565:
338 src0_format = 0x4;
339 pixel_width = 2;
340 msg->src_trans_mode &= 0x07;
341 break;
342 case RGA_FORMAT_RGBA_5551:
343 src0_format = 0x5;
344 pixel_width = 2;
345 break;
346 case RGA_FORMAT_RGBA_4444:
347 src0_format = 0x6;
348 pixel_width = 2;
349 break;
350 case RGA_FORMAT_BGR_565:
351 src0_format = 0x4;
352 pixel_width = 2;
353 msg->src_trans_mode &= 0x07;
354 src0_rb_swp = 0x1;
355 break;
356 case RGA_FORMAT_BGRA_5551:
357 src0_format = 0x5;
358 pixel_width = 2;
359 src0_rb_swp = 0x1;
360 break;
361 case RGA_FORMAT_BGRA_4444:
362 src0_format = 0x6;
363 pixel_width = 2;
364 src0_rb_swp = 0x1;
365 break;
366
367 /* ARGB */
368 /*
369 * In colorkey mode, xrgb/xbgr does not
370 * need to enable the alpha channel
371 */
372 case RGA_FORMAT_ARGB_8888:
373 src0_format = 0x0;
374 pixel_width = 4;
375 src0_alpha_swp = 1;
376 break;
377 case RGA_FORMAT_ABGR_8888:
378 src0_format = 0x0;
379 pixel_width = 4;
380 src0_alpha_swp = 1;
381 src0_rb_swp = 0x1;
382 break;
383 case RGA_FORMAT_XRGB_8888:
384 src0_format = 0x1;
385 pixel_width = 4;
386 src0_alpha_swp = 1;
387 msg->src_trans_mode &= 0x07;
388 break;
389 case RGA_FORMAT_XBGR_8888:
390 src0_format = 0x1;
391 pixel_width = 4;
392 src0_alpha_swp = 1;
393 src0_rb_swp = 0x1;
394 msg->src_trans_mode &= 0x07;
395 break;
396 case RGA_FORMAT_ARGB_5551:
397 src0_format = 0x5;
398 pixel_width = 2;
399 src0_alpha_swp = 1;
400 break;
401 case RGA_FORMAT_ABGR_5551:
402 src0_format = 0x5;
403 pixel_width = 2;
404 src0_alpha_swp = 1;
405 src0_rb_swp = 0x1;
406 break;
407 case RGA_FORMAT_ARGB_4444:
408 src0_format = 0x6;
409 pixel_width = 2;
410 src0_alpha_swp = 1;
411 break;
412 case RGA_FORMAT_ABGR_4444:
413 src0_format = 0x6;
414 pixel_width = 2;
415 src0_alpha_swp = 1;
416 src0_rb_swp = 0x1;
417 break;
418
419 case RGA_FORMAT_YVYU_422:
420 src0_format = 0x7;
421 pixel_width = 2;
422 src0_cbcr_swp = 1;
423 src0_rb_swp = 0x1;
424 break; //rbswap=ycswap
425 case RGA_FORMAT_VYUY_422:
426 src0_format = 0x7;
427 pixel_width = 2;
428 src0_cbcr_swp = 1;
429 src0_rb_swp = 0x0;
430 break;
431 case RGA_FORMAT_YUYV_422:
432 src0_format = 0x7;
433 pixel_width = 2;
434 src0_cbcr_swp = 0;
435 src0_rb_swp = 0x1;
436 break;
437 case RGA_FORMAT_UYVY_422:
438 src0_format = 0x7;
439 pixel_width = 2;
440 src0_cbcr_swp = 0;
441 src0_rb_swp = 0x0;
442 break;
443
444 case RGA_FORMAT_YCbCr_422_SP:
445 src0_format = 0x8;
446 xdiv = 1;
447 ydiv = 1;
448 break;
449 case RGA_FORMAT_YCbCr_422_P:
450 src0_format = 0x9;
451 xdiv = 2;
452 ydiv = 1;
453 break;
454 case RGA_FORMAT_YCbCr_420_SP:
455 src0_format = 0xa;
456 xdiv = 1;
457 ydiv = 2;
458 break;
459 case RGA_FORMAT_YCbCr_420_P:
460 src0_format = 0xb;
461 xdiv = 2;
462 ydiv = 2;
463 break;
464 case RGA_FORMAT_YCrCb_422_SP:
465 src0_format = 0x8;
466 xdiv = 1;
467 ydiv = 1;
468 src0_cbcr_swp = 1;
469 break;
470 case RGA_FORMAT_YCrCb_422_P:
471 src0_format = 0x9;
472 xdiv = 2;
473 ydiv = 1;
474 src0_cbcr_swp = 1;
475 break;
476 case RGA_FORMAT_YCrCb_420_SP:
477 src0_format = 0xa;
478 xdiv = 1;
479 ydiv = 2;
480 src0_cbcr_swp = 1;
481 break;
482 case RGA_FORMAT_YCrCb_420_P:
483 src0_format = 0xb;
484 xdiv = 2;
485 ydiv = 2;
486 src0_cbcr_swp = 1;
487 break;
488
489 case RGA_FORMAT_YCbCr_420_SP_10B:
490 src0_format = 0xa;
491 xdiv = 1;
492 ydiv = 2;
493 yuv10 = 1;
494 break;
495 case RGA_FORMAT_YCrCb_420_SP_10B:
496 src0_format = 0xa;
497 xdiv = 1;
498 ydiv = 2;
499 src0_cbcr_swp = 1;
500 yuv10 = 1;
501 break;
502 case RGA_FORMAT_YCbCr_422_SP_10B:
503 src0_format = 0x8;
504 xdiv = 1;
505 ydiv = 1;
506 yuv10 = 1;
507 break;
508 case RGA_FORMAT_YCrCb_422_SP_10B:
509 src0_format = 0x8;
510 xdiv = 1;
511 ydiv = 1;
512 src0_cbcr_swp = 1;
513 yuv10 = 1;
514 break;
515
516 case RGA_FORMAT_YCbCr_400:
517 src0_format = 0x8;
518 /* When Yin_Yout is enabled, no need to go through the software. */
519 disable_uv_channel_en = msg->yin_yout_en ? false : true;
520 xdiv = 1;
521 ydiv = 1;
522 break;
523 };
524
525 reg =
526 ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) |
527 (s_RGA2_SRC_INFO_SW_SRC_FMT(src0_format)));
528 reg =
529 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP)) |
530 (s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(src0_rb_swp)));
531 reg =
532 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP)) |
533 (s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(src0_alpha_swp)));
534 reg =
535 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP)) |
536 (s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(src0_cbcr_swp)));
537
538 if (msg->src1.format == RGA_FORMAT_RGBA_2BPP)
539 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_CP_ENDIAN)) |
540 (s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(msg->osd_info.bpp2_info.endian_swap & 1)));
541
542 reg =
543 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) |
544 (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(msg->yuv2rgb_mode)));
545
546 reg =
547 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE)) |
548 (s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(msg->rotate_mode & 0x3)));
549 reg =
550 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE)) |
551 (s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE
552 ((msg->rotate_mode >> 4) & 0x3)));
553 reg =
554 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE)) |
555 (s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE((scale_w_flag))));
556 reg =
557 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) |
558 (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE((scale_h_flag))));
559 reg =
560 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER)) |
561 (s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER((
562 msg->scale_bicu_mode))));
563 reg =
564 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE)) |
565 (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(msg->src_trans_mode)));
566 reg =
567 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E)) |
568 (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(msg->src_trans_mode >> 1)));
569 reg =
570 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E)) |
571 (s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E
572 ((msg->alpha_rop_flag >> 4) & 0x1)));
573 reg =
574 ((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) |
575 (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((vsp_scale_mode))));
576 reg =
577 ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_E)) |
578 (s_RGA2_SRC_INFO_SW_SW_YUV10_E((yuv10))));
579
580 reg =
581 ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E)) |
582 (s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E((yuv10))));
583
584 RGA2_reg_get_param(base, msg);
585
586 stride = (((msg->src.vir_w * pixel_width) + 3) & ~3) >> 2;
587 uv_stride = ((msg->src.vir_w / xdiv + 3) & ~3);
588
589 if (disable_uv_channel_en == 1) {
590 /*
591 * When Y400 as the input format, because the current
592 * RGA does not support closing
593 * the access of the UV channel, the address of the UV
594 * channel access is equal to
595 * the address of the Y channel access to ensure that
596 * the UV channel can access,
597 * preventing the RGA hardware from reporting errors.
598 */
599 *bRGA_SRC_BASE0 =
600 (u32) (msg->src.yrgb_addr +
601 msg->src.y_offset * (stride << 2) +
602 msg->src.x_offset * pixel_width);
603 *bRGA_SRC_BASE1 = *bRGA_SRC_BASE0;
604 *bRGA_SRC_BASE2 = *bRGA_SRC_BASE0;
605 } else {
606 *bRGA_SRC_BASE0 =
607 (u32) (msg->src.yrgb_addr +
608 msg->src.y_offset * (stride << 2) +
609 msg->src.x_offset * pixel_width);
610 *bRGA_SRC_BASE1 =
611 (u32) (msg->src.uv_addr +
612 (msg->src.y_offset / ydiv) * uv_stride +
613 (msg->src.x_offset / xdiv));
614 *bRGA_SRC_BASE2 =
615 (u32) (msg->src.v_addr +
616 (msg->src.y_offset / ydiv) * uv_stride +
617 (msg->src.x_offset / xdiv));
618 }
619
620 //mask_stride = ((msg->src0_act.width + 31) & ~31) >> 5;
621 mask_stride = msg->rop_mask_stride;
622
623 *bRGA_SRC_VIR_INFO = stride | (mask_stride << 16);
624
625 *bRGA_SRC_ACT_INFO =
626 (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);
627
628 *bRGA_MASK_ADDR = (u32) msg->rop_mask_addr;
629
630 *bRGA_SRC_INFO = reg;
631
632 *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
633 *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
634 }
635
RGA2_set_reg_dst_info(u8 * base,struct rga2_req * msg)636 static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
637 {
638 u32 *bRGA_DST_INFO;
639 u32 *bRGA_DST_BASE0, *bRGA_DST_BASE1, *bRGA_DST_BASE2,
640 *bRGA_SRC_BASE3;
641 u32 *bRGA_DST_VIR_INFO;
642 u32 *bRGA_DST_ACT_INFO;
643
644 u32 *RGA_DST_Y4MAP_LUT0; //Y4 LUT0
645 u32 *RGA_DST_Y4MAP_LUT1; //Y4 LUT1
646 u32 *RGA_DST_NN_QUANTIZE_SCALE;
647 u32 *RGA_DST_NN_QUANTIZE_OFFSET;
648
649 u32 line_width_real;
650
651 u8 ydither_en = 0;
652
653 u8 src1_format = 0;
654 u8 src1_rb_swp = 0;
655 u8 src1_alpha_swp = 0;
656
657 u8 dst_format = 0;
658 u8 dst_rb_swp = 0;
659 u8 dst_cbcr_swp = 0;
660 u8 dst_alpha_swp = 0;
661
662 u8 dst_fmt_yuv400_en = 0;
663 u8 dst_fmt_y4_en = 0;
664 u8 dst_nn_quantize_en = 0;
665
666 u32 reg = 0;
667 u8 spw, dpw;
668 u8 bbp_shift = 0;
669 u32 s_stride, d_stride;
670 u32 x_mirr, y_mirr, rot_90_flag;
671 u32 yrgb_addr, u_addr, v_addr, s_yrgb_addr;
672 u32 d_uv_stride, x_div, y_div;
673 u32 y_lt_addr, y_ld_addr, y_rt_addr, y_rd_addr;
674 u32 u_lt_addr, u_ld_addr, u_rt_addr, u_rd_addr;
675 u32 v_lt_addr, v_ld_addr, v_rt_addr, v_rd_addr;
676
677 dpw = 1;
678 x_div = y_div = 1;
679
680 dst_nn_quantize_en = (msg->alpha_rop_flag >> 8) & 0x1;
681
682 bRGA_DST_INFO = (u32 *) (base + RGA2_DST_INFO_OFFSET);
683 bRGA_DST_BASE0 = (u32 *) (base + RGA2_DST_BASE0_OFFSET);
684 bRGA_DST_BASE1 = (u32 *) (base + RGA2_DST_BASE1_OFFSET);
685 bRGA_DST_BASE2 = (u32 *) (base + RGA2_DST_BASE2_OFFSET);
686
687 bRGA_SRC_BASE3 = (u32 *) (base + RGA2_SRC_BASE3_OFFSET);
688
689 bRGA_DST_VIR_INFO = (u32 *) (base + RGA2_DST_VIR_INFO_OFFSET);
690 bRGA_DST_ACT_INFO = (u32 *) (base + RGA2_DST_ACT_INFO_OFFSET);
691
692 RGA_DST_Y4MAP_LUT0 = (u32 *) (base + RGA2_DST_Y4MAP_LUT0_OFFSET);
693 RGA_DST_Y4MAP_LUT1 = (u32 *) (base + RGA2_DST_Y4MAP_LUT1_OFFSET);
694 RGA_DST_NN_QUANTIZE_SCALE =
695 (u32 *) (base + RGA2_DST_QUANTIZE_SCALE_OFFSET);
696 RGA_DST_NN_QUANTIZE_OFFSET =
697 (u32 *) (base + RGA2_DST_QUANTIZE_OFFSET_OFFSET);
698
699 switch (msg->src1.format) {
700 case RGA_FORMAT_RGBA_8888:
701 src1_format = 0x0;
702 spw = 4;
703 break;
704 case RGA_FORMAT_BGRA_8888:
705 src1_format = 0x0;
706 src1_rb_swp = 0x1;
707 spw = 4;
708 break;
709 case RGA_FORMAT_RGBX_8888:
710 src1_format = 0x1;
711 spw = 4;
712 break;
713 case RGA_FORMAT_BGRX_8888:
714 src1_format = 0x1;
715 src1_rb_swp = 0x1;
716 spw = 4;
717 break;
718 case RGA_FORMAT_RGB_888:
719 src1_format = 0x2;
720 spw = 3;
721 break;
722 case RGA_FORMAT_BGR_888:
723 src1_format = 0x2;
724 src1_rb_swp = 1;
725 spw = 3;
726 break;
727 case RGA_FORMAT_RGB_565:
728 src1_format = 0x4;
729 spw = 2;
730 break;
731 case RGA_FORMAT_RGBA_5551:
732 src1_format = 0x5;
733 spw = 2;
734 break;
735 case RGA_FORMAT_RGBA_4444:
736 src1_format = 0x6;
737 spw = 2;
738 break;
739 case RGA_FORMAT_BGR_565:
740 src1_format = 0x4;
741 spw = 2;
742 src1_rb_swp = 0x1;
743 break;
744 case RGA_FORMAT_BGRA_5551:
745 src1_format = 0x5;
746 spw = 2;
747 src1_rb_swp = 0x1;
748 break;
749 case RGA_FORMAT_BGRA_4444:
750 src1_format = 0x6;
751 spw = 2;
752 src1_rb_swp = 0x1;
753 break;
754
755 /* ARGB */
756 case RGA_FORMAT_ARGB_8888:
757 src1_format = 0x0;
758 spw = 4;
759 src1_alpha_swp = 1;
760 break;
761 case RGA_FORMAT_ABGR_8888:
762 src1_format = 0x0;
763 spw = 4;
764 src1_alpha_swp = 1;
765 src1_rb_swp = 0x1;
766 break;
767 case RGA_FORMAT_XRGB_8888:
768 src1_format = 0x1;
769 spw = 4;
770 src1_alpha_swp = 1;
771 break;
772 case RGA_FORMAT_XBGR_8888:
773 src1_format = 0x1;
774 spw = 4;
775 src1_alpha_swp = 1;
776 src1_rb_swp = 0x1;
777 break;
778 case RGA_FORMAT_ARGB_5551:
779 src1_format = 0x5;
780 spw = 2;
781 src1_alpha_swp = 1;
782 break;
783 case RGA_FORMAT_ABGR_5551:
784 src1_format = 0x5;
785 spw = 2;
786 src1_alpha_swp = 1;
787 src1_rb_swp = 0x1;
788 break;
789 case RGA_FORMAT_ARGB_4444:
790 src1_format = 0x6;
791 spw = 2;
792 src1_alpha_swp = 1;
793 break;
794 case RGA_FORMAT_ABGR_4444:
795 src1_format = 0x6;
796 spw = 2;
797 src1_alpha_swp = 1;
798 src1_rb_swp = 0x1;
799 break;
800 case RGA_FORMAT_RGBA_2BPP:
801 src1_format = 0x0;
802 spw = 1;
803 /* 2BPP = 8 >> 2 = 2bit */
804 bbp_shift = 2;
805 src1_alpha_swp = msg->osd_info.bpp2_info.ac_swap;
806 break;
807 default:
808 spw = 4;
809 break;
810 };
811
812 reg =
813 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_FMT)) |
814 (s_RGA2_DST_INFO_SW_SRC1_FMT(src1_format)));
815 reg =
816 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_RB_SWP)) |
817 (s_RGA2_DST_INFO_SW_SRC1_RB_SWP(src1_rb_swp)));
818 reg =
819 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP)) |
820 (s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(src1_alpha_swp)));
821
822 switch (msg->dst.format) {
823 case RGA_FORMAT_RGBA_8888:
824 dst_format = 0x0;
825 dpw = 4;
826 break;
827 case RGA_FORMAT_BGRA_8888:
828 dst_format = 0x0;
829 dst_rb_swp = 0x1;
830 dpw = 4;
831 break;
832 case RGA_FORMAT_RGBX_8888:
833 dst_format = 0x1;
834 dpw = 4;
835 break;
836 case RGA_FORMAT_BGRX_8888:
837 dst_format = 0x1;
838 dst_rb_swp = 0x1;
839 dpw = 4;
840 break;
841 case RGA_FORMAT_RGB_888:
842 dst_format = 0x2;
843 dpw = 3;
844 break;
845 case RGA_FORMAT_BGR_888:
846 dst_format = 0x2;
847 dst_rb_swp = 1;
848 dpw = 3;
849 break;
850 case RGA_FORMAT_RGB_565:
851 dst_format = 0x4;
852 dpw = 2;
853 break;
854 case RGA_FORMAT_RGBA_5551:
855 dst_format = 0x5;
856 dpw = 2;
857 break;
858 case RGA_FORMAT_RGBA_4444:
859 dst_format = 0x6;
860 dpw = 2;
861 break;
862 case RGA_FORMAT_BGR_565:
863 dst_format = 0x4;
864 dpw = 2;
865 dst_rb_swp = 0x1;
866 break;
867 case RGA_FORMAT_BGRA_5551:
868 dst_format = 0x5;
869 dpw = 2;
870 dst_rb_swp = 0x1;
871 break;
872 case RGA_FORMAT_BGRA_4444:
873 dst_format = 0x6;
874 dpw = 2;
875 dst_rb_swp = 0x1;
876 break;
877
878 /* ARGB */
879 case RGA_FORMAT_ARGB_8888:
880 dst_format = 0x0;
881 dpw = 4;
882 dst_alpha_swp = 1;
883 break;
884 case RGA_FORMAT_ABGR_8888:
885 dst_format = 0x0;
886 dpw = 4;
887 dst_alpha_swp = 1;
888 dst_rb_swp = 0x1;
889 break;
890 case RGA_FORMAT_XRGB_8888:
891 dst_format = 0x1;
892 dpw = 4;
893 dst_alpha_swp = 1;
894 break;
895 case RGA_FORMAT_XBGR_8888:
896 dst_format = 0x1;
897 dpw = 4;
898 dst_alpha_swp = 1;
899 dst_rb_swp = 0x1;
900 break;
901 case RGA_FORMAT_ARGB_5551:
902 dst_format = 0x5;
903 dpw = 2;
904 dst_alpha_swp = 1;
905 break;
906 case RGA_FORMAT_ABGR_5551:
907 dst_format = 0x5;
908 dpw = 2;
909 dst_alpha_swp = 1;
910 dst_rb_swp = 0x1;
911 break;
912 case RGA_FORMAT_ARGB_4444:
913 dst_format = 0x6;
914 dpw = 2;
915 dst_alpha_swp = 1;
916 break;
917 case RGA_FORMAT_ABGR_4444:
918 dst_format = 0x6;
919 dpw = 2;
920 dst_alpha_swp = 1;
921 dst_rb_swp = 0x1;
922 break;
923
924 case RGA_FORMAT_YCbCr_422_SP:
925 dst_format = 0x8;
926 x_div = 1;
927 y_div = 1;
928 break;
929 case RGA_FORMAT_YCbCr_422_P:
930 dst_format = 0x9;
931 x_div = 2;
932 y_div = 1;
933 break;
934 case RGA_FORMAT_YCbCr_420_SP:
935 dst_format = 0xa;
936 x_div = 1;
937 y_div = 2;
938 break;
939 case RGA_FORMAT_YCbCr_420_P:
940 dst_format = 0xb;
941 dst_cbcr_swp = 1;
942 x_div = 2;
943 y_div = 2;
944 break;
945 case RGA_FORMAT_YCrCb_422_SP:
946 dst_format = 0x8;
947 dst_cbcr_swp = 1;
948 x_div = 1;
949 y_div = 1;
950 break;
951 case RGA_FORMAT_YCrCb_422_P:
952 dst_format = 0x9;
953 dst_cbcr_swp = 1;
954 x_div = 2;
955 y_div = 1;
956 break;
957 case RGA_FORMAT_YCrCb_420_SP:
958 dst_format = 0xa;
959 dst_cbcr_swp = 1;
960 x_div = 1;
961 y_div = 2;
962 break;
963 case RGA_FORMAT_YCrCb_420_P:
964 dst_format = 0xb;
965 x_div = 2;
966 y_div = 2;
967 break;
968
969 case RGA_FORMAT_YCbCr_400:
970 dst_format = 0x8;
971 dst_fmt_yuv400_en = 1;
972 x_div = 1;
973 y_div = 1;
974 break;
975 case RGA_FORMAT_Y4:
976 dst_format = 0x8;
977 dst_fmt_y4_en = 1;
978 dst_fmt_yuv400_en = 1;
979 x_div = 1;
980 y_div = 1;
981 break;
982
983 case RGA_FORMAT_YUYV_422:
984 dst_format = 0xe;
985 dpw = 2;
986 dst_cbcr_swp = 1;
987 break;
988 case RGA_FORMAT_YVYU_422:
989 dst_format = 0xe;
990 dpw = 2;
991 break;
992 case RGA_FORMAT_YUYV_420:
993 dst_format = 0xf;
994 dpw = 2;
995 dst_cbcr_swp = 1;
996 break;
997 case RGA_FORMAT_YVYU_420:
998 dst_format = 0xf;
999 dpw = 2;
1000 break;
1001 case RGA_FORMAT_UYVY_422:
1002 dst_format = 0xc;
1003 dpw = 2;
1004 dst_cbcr_swp = 1;
1005 break;
1006 case RGA_FORMAT_VYUY_422:
1007 dst_format = 0xc;
1008 dpw = 2;
1009 break;
1010 case RGA_FORMAT_UYVY_420:
1011 dst_format = 0xd;
1012 dpw = 2;
1013 dst_cbcr_swp = 1;
1014 break;
1015 case RGA_FORMAT_VYUY_420:
1016 dst_format = 0xd;
1017 dpw = 2;
1018 break;
1019 };
1020
1021 reg =
1022 ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT)) |
1023 (s_RGA2_DST_INFO_SW_DST_FMT(dst_format)));
1024 reg =
1025 ((reg & (~m_RGA2_DST_INFO_SW_DST_RB_SWAP)) |
1026 (s_RGA2_DST_INFO_SW_DST_RB_SWAP(dst_rb_swp)));
1027 reg =
1028 ((reg & (~m_RGA2_DST_INFO_SW_ALPHA_SWAP)) |
1029 (s_RGA2_DST_INFO_SW_ALPHA_SWAP(dst_alpha_swp)));
1030 reg =
1031 ((reg & (~m_RGA2_DST_INFO_SW_DST_UV_SWAP)) |
1032 (s_RGA2_DST_INFO_SW_DST_UV_SWAP(dst_cbcr_swp)));
1033
1034 reg =
1035 ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN)) |
1036 (s_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN(dst_fmt_yuv400_en)));
1037 reg =
1038 ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT_Y4_EN)) |
1039 (s_RGA2_DST_INFO_SW_DST_FMT_Y4_EN(dst_fmt_y4_en)));
1040 reg =
1041 ((reg & (~m_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN)) |
1042 (s_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN(dst_nn_quantize_en)));
1043 reg =
1044 ((reg & (~m_RGA2_DST_INFO_SW_DITHER_UP_E)) |
1045 (s_RGA2_DST_INFO_SW_DITHER_UP_E(msg->alpha_rop_flag >> 5)));
1046 reg =
1047 ((reg & (~m_RGA2_DST_INFO_SW_DITHER_DOWN_E)) |
1048 (s_RGA2_DST_INFO_SW_DITHER_DOWN_E(msg->alpha_rop_flag >> 6)));
1049 reg =
1050 ((reg & (~m_RGA2_DST_INFO_SW_DITHER_MODE)) |
1051 (s_RGA2_DST_INFO_SW_DITHER_MODE(msg->dither_mode)));
1052 reg =
1053 ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE)) |
1054 (s_RGA2_DST_INFO_SW_DST_CSC_MODE(msg->yuv2rgb_mode >> 2)));
1055 reg =
1056 ((reg & (~m_RGA2_DST_INFO_SW_CSC_CLIP_MODE)) |
1057 (s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 4)));
1058 /* full csc enable */
1059 reg =
1060 ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE_2)) |
1061 (s_RGA2_DST_INFO_SW_DST_CSC_MODE_2(msg->full_csc_en)));
1062 /*
1063 * Some older chips do not support src1 csc mode,
1064 * they do not have these two registers.
1065 */
1066 reg =
1067 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_MODE)) |
1068 (s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(msg->yuv2rgb_mode >> 5)));
1069 reg =
1070 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE)) |
1071 (s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(
1072 msg->yuv2rgb_mode >> 7)));
1073
1074 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_UVHDS_MODE)) |
1075 (s_RGA2_DST_INFO_SW_DST_UVHDS_MODE(msg->uvhds_mode)));
1076 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_UVVDS_MODE)) |
1077 (s_RGA2_DST_INFO_SW_DST_UVVDS_MODE(msg->uvvds_mode)));
1078
1079 ydither_en = (msg->dst.format == RGA_FORMAT_Y4)
1080 && ((msg->alpha_rop_flag >> 6) & 0x1);
1081
1082 *bRGA_DST_INFO = reg;
1083
1084 s_stride = (((msg->src1.vir_w * spw >> bbp_shift) + 3) & ~3) >> 2;
1085 d_stride = ((msg->dst.vir_w * dpw + 3) & ~3) >> 2;
1086
1087 if (dst_fmt_y4_en) {
1088 /* Y4 output will HALF */
1089 d_stride = ((d_stride + 1) & ~1) >> 1;
1090 }
1091
1092 d_uv_stride = (d_stride << 2) / x_div;
1093
1094 *bRGA_DST_VIR_INFO = d_stride | (s_stride << 16);
1095 if ((msg->dst.vir_w % 2 != 0) &&
1096 (msg->dst.act_w == msg->src.act_w)
1097 && (msg->dst.act_h == msg->src.act_h)
1098 && (msg->dst.format == RGA_FORMAT_BGR_888
1099 || msg->dst.format == RGA_FORMAT_RGB_888))
1100 *bRGA_DST_ACT_INFO =
1101 (msg->dst.act_w) | ((msg->dst.act_h - 1) << 16);
1102 else
1103 *bRGA_DST_ACT_INFO =
1104 (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
1105 s_stride <<= 2;
1106 d_stride <<= 2;
1107
1108 if (((msg->rotate_mode & 0xf) == 0) ||
1109 ((msg->rotate_mode & 0xf) == 1)) {
1110 x_mirr = 0;
1111 y_mirr = 0;
1112 } else {
1113 x_mirr = 1;
1114 y_mirr = 1;
1115 }
1116
1117 rot_90_flag = msg->rotate_mode & 1;
1118 x_mirr = (x_mirr + ((msg->rotate_mode >> 4) & 1)) & 1;
1119 y_mirr = (y_mirr + ((msg->rotate_mode >> 5) & 1)) & 1;
1120
1121 if (ydither_en) {
1122 if (x_mirr && y_mirr) {
1123 pr_err("ydither mode do not support rotate x_mirr=%d,y_mirr=%d\n",
1124 x_mirr, y_mirr);
1125 }
1126
1127 if (msg->dst.act_w != msg->src.act_w)
1128 pr_err("ydither mode do not support x dir scale\n");
1129
1130 if (msg->dst.act_h != msg->src.act_h)
1131 pr_err("ydither mode do not support y dir scale\n");
1132 }
1133
1134 if (dst_fmt_y4_en) {
1135 *RGA_DST_Y4MAP_LUT0 = (msg->gr_color.gr_x_r & 0xffff) |
1136 (msg->gr_color.gr_x_g << 16);
1137 *RGA_DST_Y4MAP_LUT1 = (msg->gr_color.gr_y_r & 0xffff) |
1138 (msg->gr_color.gr_y_g << 16);
1139 }
1140
1141 if (dst_nn_quantize_en) {
1142 *RGA_DST_NN_QUANTIZE_SCALE = (msg->gr_color.gr_x_r & 0xffff) |
1143 (msg->gr_color.gr_x_g << 10) |
1144 (msg->gr_color.gr_x_b << 20);
1145 *RGA_DST_NN_QUANTIZE_OFFSET = (msg->gr_color.gr_y_r & 0xffff) |
1146 (msg->gr_color.gr_y_g << 10) |
1147 (msg->gr_color.gr_y_b << 20);
1148 }
1149
1150 s_yrgb_addr =
1151 (u32) msg->src1.yrgb_addr + (msg->src1.y_offset * s_stride) +
1152 (msg->src1.x_offset * spw >> bbp_shift);
1153
1154 *bRGA_SRC_BASE3 = s_yrgb_addr;
1155
1156 if (dst_fmt_y4_en) {
1157 yrgb_addr = (u32) msg->dst.yrgb_addr +
1158 (msg->dst.y_offset * d_stride) +
1159 ((msg->dst.x_offset * dpw) >> 1);
1160 } else {
1161 yrgb_addr = (u32) msg->dst.yrgb_addr +
1162 (msg->dst.y_offset * d_stride) +
1163 (msg->dst.x_offset * dpw);
1164 }
1165 u_addr = (u32) msg->dst.uv_addr +
1166 (msg->dst.y_offset / y_div) * d_uv_stride +
1167 msg->dst.x_offset / x_div;
1168 v_addr = (u32) msg->dst.v_addr +
1169 (msg->dst.y_offset / y_div) * d_uv_stride +
1170 msg->dst.x_offset / x_div;
1171
1172 y_lt_addr = yrgb_addr;
1173 u_lt_addr = u_addr;
1174 v_lt_addr = v_addr;
1175
1176 /* Warning */
1177 line_width_real =
1178 dst_fmt_y4_en ? ((msg->dst.act_w) >> 1) : msg->dst.act_w;
1179
1180 /*
1181 * YUV packet mode is a new format, and the write behavior during
1182 * rotation is different from the old format.
1183 */
1184 if (rga_is_yuv422_packed_format(msg->dst.format)) {
1185 y_ld_addr = yrgb_addr + (msg->dst.act_h - 1) * (d_stride);
1186 y_rt_addr = yrgb_addr + (msg->dst.act_w * 2 - 1);
1187 y_rd_addr = y_ld_addr + (msg->dst.act_w * 2 - 1);
1188 } else if (rga_is_yuv420_packed_format(msg->dst.format)) {
1189 y_ld_addr = (u32)msg->dst.yrgb_addr +
1190 ((msg->dst.y_offset + (msg->dst.act_h - 1)) * d_stride) +
1191 msg->dst.x_offset;
1192 y_rt_addr = yrgb_addr + (msg->dst.act_w * 2 - 1);
1193 y_rd_addr = y_ld_addr + (msg->dst.act_w - 1);
1194 } else {
1195 /* 270 degree & Mirror V */
1196 y_ld_addr = yrgb_addr + (msg->dst.act_h - 1) * (d_stride);
1197 /* 90 degree & Mirror H */
1198 y_rt_addr = yrgb_addr + (line_width_real - 1) * dpw;
1199 /* 180 degree */
1200 y_rd_addr = y_ld_addr + (line_width_real - 1) * dpw;
1201 }
1202
1203 u_ld_addr = u_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);
1204 v_ld_addr = v_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);
1205
1206 u_rt_addr = u_addr + (msg->dst.act_w / x_div) - 1;
1207 v_rt_addr = v_addr + (msg->dst.act_w / x_div) - 1;
1208
1209 u_rd_addr = u_ld_addr + (msg->dst.act_w / x_div) - 1;
1210 v_rd_addr = v_ld_addr + (msg->dst.act_w / x_div) - 1;
1211
1212 if (rot_90_flag == 0) {
1213 if (y_mirr == 1) {
1214 if (x_mirr == 1) {
1215 yrgb_addr = y_rd_addr;
1216 u_addr = u_rd_addr;
1217 v_addr = v_rd_addr;
1218 } else {
1219 yrgb_addr = y_ld_addr;
1220 u_addr = u_ld_addr;
1221 v_addr = v_ld_addr;
1222 }
1223 } else {
1224 if (x_mirr == 1) {
1225 yrgb_addr = y_rt_addr;
1226 u_addr = u_rt_addr;
1227 v_addr = v_rt_addr;
1228 } else {
1229 yrgb_addr = y_lt_addr;
1230 u_addr = u_lt_addr;
1231 v_addr = v_lt_addr;
1232 }
1233 }
1234 } else {
1235 if (y_mirr == 1) {
1236 if (x_mirr == 1) {
1237 yrgb_addr = y_ld_addr;
1238 u_addr = u_ld_addr;
1239 v_addr = v_ld_addr;
1240 } else {
1241 yrgb_addr = y_rd_addr;
1242 u_addr = u_rd_addr;
1243 v_addr = v_rd_addr;
1244 }
1245 } else {
1246 if (x_mirr == 1) {
1247 yrgb_addr = y_lt_addr;
1248 u_addr = u_lt_addr;
1249 v_addr = v_lt_addr;
1250 } else {
1251 yrgb_addr = y_rt_addr;
1252 u_addr = u_rt_addr;
1253 v_addr = v_rt_addr;
1254 }
1255 }
1256 }
1257
1258 *bRGA_DST_BASE0 = (u32) yrgb_addr;
1259
1260 if ((msg->dst.format == RGA_FORMAT_YCbCr_420_P)
1261 || (msg->dst.format == RGA_FORMAT_YCrCb_420_P)) {
1262 if (dst_cbcr_swp == 0) {
1263 *bRGA_DST_BASE1 = (u32) v_addr;
1264 *bRGA_DST_BASE2 = (u32) u_addr;
1265 } else {
1266 *bRGA_DST_BASE1 = (u32) u_addr;
1267 *bRGA_DST_BASE2 = (u32) v_addr;
1268 }
1269 } else {
1270 *bRGA_DST_BASE1 = (u32) u_addr;
1271 *bRGA_DST_BASE2 = (u32) v_addr;
1272 }
1273 }
1274
RGA2_set_reg_alpha_info(u8 * base,struct rga2_req * msg)1275 static void RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)
1276 {
1277 u32 *bRGA_ALPHA_CTRL0;
1278 u32 *bRGA_ALPHA_CTRL1;
1279 u32 *bRGA_FADING_CTRL;
1280 u32 reg = 0;
1281 union rga2_color_ctrl color_ctrl;
1282 union rga2_alpha_ctrl alpha_ctrl;
1283 struct rga_alpha_config *config;
1284
1285 bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET);
1286 bRGA_ALPHA_CTRL1 = (u32 *) (base + RGA2_ALPHA_CTRL1_OFFSET);
1287 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1288
1289 color_ctrl.value = 0;
1290 alpha_ctrl.value = 0;
1291 config = &msg->alpha_config;
1292
1293 color_ctrl.bits.src_color_mode =
1294 config->fg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1295 color_ctrl.bits.dst_color_mode =
1296 config->bg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1297
1298 if (config->fg_pixel_alpha_en)
1299 color_ctrl.bits.src_blend_mode =
1300 config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1301 RGA_ALPHA_PER_PIXEL;
1302 else
1303 color_ctrl.bits.src_blend_mode = RGA_ALPHA_GLOBAL;
1304
1305 if (config->bg_pixel_alpha_en)
1306 color_ctrl.bits.dst_blend_mode =
1307 config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1308 RGA_ALPHA_PER_PIXEL;
1309 else
1310 color_ctrl.bits.dst_blend_mode = RGA_ALPHA_GLOBAL;
1311
1312 /*
1313 * Since the hardware uses 256 as 1, the original alpha value needs to
1314 * be + (alpha >> 7).
1315 */
1316 color_ctrl.bits.src_alpha_cal_mode = RGA_ALPHA_SATURATION;
1317 color_ctrl.bits.dst_alpha_cal_mode = RGA_ALPHA_SATURATION;
1318
1319 /* porter duff alpha enable */
1320 switch (config->mode) {
1321 case RGA_ALPHA_BLEND_SRC:
1322 /*
1323 * SRC mode:
1324 * Sf = 1, Df = 0；
1325 * [Rc,Ra] = [Sc,Sa]；
1326 */
1327 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1328 color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE;
1329
1330 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1331 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1332
1333 break;
1334
1335 case RGA_ALPHA_BLEND_DST:
1336 /*
1337 * SRC mode:
1338 * Sf = 0, Df = 1；
1339 * [Rc,Ra] = [Dc,Da]；
1340 */
1341 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1342 color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1343
1344 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1345 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE;
1346
1347 break;
1348
1349 case RGA_ALPHA_BLEND_SRC_OVER:
1350 /*
1351 * SRC-OVER mode:
1352 * Sf = 1, Df = (1 - Sa)
1353 * [Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ]
1354 */
1355 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1356 color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE;
1357
1358 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1359 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1360
1361 break;
1362
1363 case RGA_ALPHA_BLEND_DST_OVER:
1364 /*
1365 * DST-OVER mode:
1366 * Sf = (1 - Da) , Df = 1
1367 * [Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ]
1368 */
1369 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1370 color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1371
1372 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1373 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE;
1374
1375 break;
1376
1377 case RGA_ALPHA_BLEND_SRC_IN:
1378 /*
1379 * SRC-IN mode:
1380 * Sf = Da , Df = 0
1381 * [Rc,Ra] = [ Sc * Da, Sa * Da ]
1382 */
1383 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1384 color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE;
1385
1386 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1387 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1388
1389 break;
1390
1391 case RGA_ALPHA_BLEND_DST_IN:
1392 /*
1393 * DST-IN mode:
1394 * Sf = 0 , Df = Sa
1395 * [Rc,Ra] = [ Dc * Sa, Da * Sa ]
1396 */
1397 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1398 color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1399
1400 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1401 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE;
1402
1403 break;
1404
1405 case RGA_ALPHA_BLEND_SRC_OUT:
1406 /*
1407 * SRC-OUT mode:
1408 * Sf = (1 - Da) , Df = 0
1409 * [Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ]
1410 */
1411 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1412 color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1413
1414 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1415 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1416
1417 break;
1418
1419 case RGA_ALPHA_BLEND_DST_OUT:
1420 /*
1421 * DST-OUT mode:
1422 * Sf = 0 , Df = (1 - Sa)
1423 * [Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ]
1424 */
1425 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1426 color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1427
1428 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1429 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1430
1431 break;
1432
1433 case RGA_ALPHA_BLEND_SRC_ATOP:
1434 /*
1435 * SRC-ATOP mode:
1436 * Sf = Da , Df = (1 - Sa)
1437 * [Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ]
1438 */
1439 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1440 color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE;
1441
1442 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1443 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1444
1445 break;
1446
1447 case RGA_ALPHA_BLEND_DST_ATOP:
1448 /*
1449 * DST-ATOP mode:
1450 * Sf = (1 - Da) , Df = Sa
1451 * [Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ]
1452 */
1453 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1454 color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1455
1456 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1457 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE;
1458
1459 break;
1460
1461 case RGA_ALPHA_BLEND_XOR:
1462 /*
1463 * DST-XOR mode:
1464 * Sf = (1 - Da) , Df = (1 - Sa)
1465 * [Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ]
1466 */
1467 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1468 color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1469
1470 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1471 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1472
1473 break;
1474
1475 case RGA_ALPHA_BLEND_CLEAR:
1476 /*
1477 * DST-CLEAR mode:
1478 * Sf = 0 , Df = 0
1479 * [Rc,Ra] = [ 0, 0 ]
1480 */
1481 color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1482 color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1483
1484 color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1485 color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1486
1487 break;
1488
1489 default:
1490 break;
1491 }
1492
1493 alpha_ctrl.bits.src_blend_mode = color_ctrl.bits.src_blend_mode;
1494 alpha_ctrl.bits.dst_blend_mode = color_ctrl.bits.dst_blend_mode;
1495
1496 alpha_ctrl.bits.src_alpha_cal_mode = color_ctrl.bits.src_alpha_cal_mode;
1497 alpha_ctrl.bits.dst_alpha_cal_mode = color_ctrl.bits.dst_alpha_cal_mode;
1498
1499 alpha_ctrl.bits.src_alpha_mode = color_ctrl.bits.src_alpha_mode;
1500 alpha_ctrl.bits.src_factor_mode = color_ctrl.bits.src_factor_mode;
1501
1502 alpha_ctrl.bits.dst_alpha_mode = color_ctrl.bits.dst_alpha_mode;
1503 alpha_ctrl.bits.dst_factor_mode = color_ctrl.bits.dst_factor_mode;
1504
1505 reg =
1506 ((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) |
1507 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag)));
1508 reg =
1509 ((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) |
1510 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL
1511 (msg->alpha_rop_flag >> 1)));
1512 reg =
1513 ((reg & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) |
1514 (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode)));
1515 reg =
1516 ((reg & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) |
1517 (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA
1518 ((uint8_t)config->fg_global_alpha_value)));
1519 reg =
1520 ((reg & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) |
1521 (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA
1522 ((uint8_t)config->bg_global_alpha_value)));
1523
1524 *bRGA_ALPHA_CTRL0 = reg;
1525 *bRGA_ALPHA_CTRL1 = color_ctrl.value | (alpha_ctrl.value << 16);
1526
1527
1528 if ((msg->alpha_rop_flag >> 2) & 1) {
1529 *bRGA_FADING_CTRL = (1 << 24) | (msg->fading_b_value << 16) |
1530 (msg->fading_g_value << 8) | (msg->fading_r_value);
1531 }
1532 }
1533
RGA2_set_reg_rop_info(u8 * base,struct rga2_req * msg)1534 static void RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
1535 {
1536 u32 *bRGA_ALPHA_CTRL0;
1537 u32 *bRGA_ROP_CTRL0;
1538 u32 *bRGA_ROP_CTRL1;
1539 u32 *bRGA_MASK_ADDR;
1540 u32 *bRGA_FG_COLOR;
1541 u32 *bRGA_PAT_CON;
1542
1543 u32 rop_code0 = 0;
1544 u32 rop_code1 = 0;
1545
1546 bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET);
1547 bRGA_ROP_CTRL0 = (u32 *) (base + RGA2_ROP_CTRL0_OFFSET);
1548 bRGA_ROP_CTRL1 = (u32 *) (base + RGA2_ROP_CTRL1_OFFSET);
1549 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1550 bRGA_FG_COLOR = (u32 *) (base + RGA2_SRC_FG_COLOR_OFFSET);
1551 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1552
1553 if (msg->rop_mode == 0) {
1554 rop_code0 = rga2_rop_code[(msg->rop_code & 0xff)];
1555 } else if (msg->rop_mode == 1) {
1556 rop_code0 = rga2_rop_code[(msg->rop_code & 0xff)];
1557 } else if (msg->rop_mode == 2) {
1558 rop_code0 = rga2_rop_code[(msg->rop_code & 0xff)];
1559 rop_code1 = rga2_rop_code[(msg->rop_code & 0xff00) >> 8];
1560 }
1561
1562 *bRGA_ROP_CTRL0 = rop_code0;
1563 *bRGA_ROP_CTRL1 = rop_code1;
1564 *bRGA_FG_COLOR = msg->fg_color;
1565 *bRGA_MASK_ADDR = (u32) msg->rop_mask_addr;
1566 *bRGA_PAT_CON = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8)
1567 | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
1568 *bRGA_ALPHA_CTRL0 =
1569 *bRGA_ALPHA_CTRL0 | (((msg->endian_mode >> 1) & 1) << 20);
1570
1571 }
1572
RGA_set_reg_mosaic(u8 * base,struct rga2_req * msg)1573 static void RGA_set_reg_mosaic(u8 *base, struct rga2_req *msg)
1574 {
1575 u32 *bRGA_MOSAIC_MODE;
1576
1577 bRGA_MOSAIC_MODE = (u32 *)(base + RGA2_MOSAIC_MODE_OFFSET);
1578
1579 *bRGA_MOSAIC_MODE = (u32)(msg->mosaic_info.mode & 0x7);
1580 }
1581
RGA2_set_reg_osd(u8 * base,struct rga2_req * msg)1582 static void RGA2_set_reg_osd(u8 *base, struct rga2_req *msg)
1583 {
1584 u32 *bRGA_OSD_CTRL0;
1585 u32 *bRGA_OSD_CTRL1;
1586 u32 *bRGA_OSD_INVERTSION_CAL0;
1587 u32 *bRGA_OSD_INVERTSION_CAL1;
1588 u32 *bRGA_OSD_COLOR0;
1589 u32 *bRGA_OSD_COLOR1;
1590 u32 *bRGA_OSD_LAST_FLAGS0;
1591 u32 *bRGA_OSD_LAST_FLAGS1;
1592 u32 reg;
1593 u8 rgba2bpp_en = 0;
1594 u8 block_num;
1595 u16 fix_width;
1596
1597
1598 bRGA_OSD_CTRL0 = (u32 *)(base + RGA2_OSD_CTRL0_OFFSET);
1599 bRGA_OSD_CTRL1 = (u32 *)(base + RGA2_OSD_CTRL1_OFFSET);
1600 bRGA_OSD_INVERTSION_CAL0 = (u32 *)(base + RGA2_OSD_INVERTSION_CAL0_OFFSET);
1601 bRGA_OSD_INVERTSION_CAL1 = (u32 *)(base + RGA2_OSD_INVERTSION_CAL1_OFFSET);
1602 bRGA_OSD_COLOR0 = (u32 *)(base + RGA2_OSD_COLOR0_OFFSET);
1603 bRGA_OSD_COLOR1 = (u32 *)(base + RGA2_OSD_COLOR1_OFFSET);
1604 bRGA_OSD_LAST_FLAGS0 = (u32 *)(base + RGA2_OSD_LAST_FLAGS0_OFFSET);
1605 bRGA_OSD_LAST_FLAGS1 = (u32 *)(base + RGA2_OSD_LAST_FLAGS1_OFFSET);
1606
1607 /* To save the number of register bits. */
1608 fix_width = msg->osd_info.mode_ctrl.block_fix_width / 2 - 1;
1609
1610 /* The register is '0' as the first. */
1611 block_num = msg->osd_info.mode_ctrl.block_num - 1;
1612
1613 if (msg->src1.format == RGA_FORMAT_RGBA_2BPP)
1614 rgba2bpp_en = 1;
1615
1616 reg = 0;
1617 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_MODE)) |
1618 (s_RGA2_OSD_CTRL0_SW_OSD_MODE(msg->osd_info.mode_ctrl.mode)));
1619 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_VER_MODE)) |
1620 (s_RGA2_OSD_CTRL0_SW_OSD_VER_MODE(msg->osd_info.mode_ctrl.direction_mode)));
1621 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_WIDTH_MODE)) |
1622 (s_RGA2_OSD_CTRL0_SW_OSD_WIDTH_MODE(msg->osd_info.mode_ctrl.width_mode)));
1623 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_BLK_NUM)) |
1624 (s_RGA2_OSD_CTRL0_SW_OSD_BLK_NUM(block_num)));
1625 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_FLAGS_INDEX)) |
1626 (s_RGA2_OSD_CTRL0_SW_OSD_FLAGS_INDEX(msg->osd_info.mode_ctrl.flags_index)));
1627 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_FIX_WIDTH)) |
1628 (s_RGA2_OSD_CTRL0_SW_OSD_FIX_WIDTH(fix_width)));
1629 reg = ((reg & (~m_RGA2_OSD_CTRL0_SW_OSD_2BPP_MODE)) |
1630 (s_RGA2_OSD_CTRL0_SW_OSD_2BPP_MODE(rgba2bpp_en)));
1631 *bRGA_OSD_CTRL0 = reg;
1632
1633 reg = 0;
1634 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_COLOR_SEL)) |
1635 (s_RGA2_OSD_CTRL1_SW_OSD_COLOR_SEL(msg->osd_info.mode_ctrl.color_mode)));
1636 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_FLAG_SEL)) |
1637 (s_RGA2_OSD_CTRL1_SW_OSD_FLAG_SEL(msg->osd_info.mode_ctrl.invert_flags_mode)));
1638 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_DEFAULT_COLOR)) |
1639 (s_RGA2_OSD_CTRL1_SW_OSD_DEFAULT_COLOR(msg->osd_info.mode_ctrl.default_color_sel)));
1640 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_AUTO_INVERST_MODE)) |
1641 (s_RGA2_OSD_CTRL1_SW_OSD_AUTO_INVERST_MODE(msg->osd_info.mode_ctrl.invert_mode)));
1642 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_THRESH)) |
1643 (s_RGA2_OSD_CTRL1_SW_OSD_THRESH(msg->osd_info.mode_ctrl.invert_thresh)));
1644 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_INVERT_A_EN)) |
1645 (s_RGA2_OSD_CTRL1_SW_OSD_INVERT_A_EN(msg->osd_info.mode_ctrl.invert_enable)));
1646 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_INVERT_Y_DIS)) |
1647 (s_RGA2_OSD_CTRL1_SW_OSD_INVERT_Y_DIS(msg->osd_info.mode_ctrl.invert_enable >> 1)));
1648 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_INVERT_C_DIS)) |
1649 (s_RGA2_OSD_CTRL1_SW_OSD_INVERT_C_DIS(msg->osd_info.mode_ctrl.invert_enable >> 2)));
1650 reg = ((reg & (~m_RGA2_OSD_CTRL1_SW_OSD_UNFIX_INDEX)) |
1651 (s_RGA2_OSD_CTRL1_SW_OSD_UNFIX_INDEX(msg->osd_info.mode_ctrl.unfix_index)));
1652 *bRGA_OSD_CTRL1 = reg;
1653
1654 *bRGA_OSD_INVERTSION_CAL0 = ((msg->osd_info.cal_factor.crb_max) << 24) |
1655 ((msg->osd_info.cal_factor.crb_min) << 16) |
1656 ((msg->osd_info.cal_factor.yg_max) << 8) |
1657 ((msg->osd_info.cal_factor.yg_min) << 0);
1658 *bRGA_OSD_INVERTSION_CAL1 = ((msg->osd_info.cal_factor.alpha_max) << 8) |
1659 ((msg->osd_info.cal_factor.alpha_min) << 0);
1660
1661 *bRGA_OSD_LAST_FLAGS0 = (msg->osd_info.last_flags0);
1662 *bRGA_OSD_LAST_FLAGS1 = (msg->osd_info.last_flags1);
1663
1664 if (msg->osd_info.mode_ctrl.color_mode == 1) {
1665 *bRGA_OSD_COLOR0 = (msg->osd_info.bpp2_info.color0.value & 0xffffff);
1666 *bRGA_OSD_COLOR1 = (msg->osd_info.bpp2_info.color1.value & 0xffffff);
1667 }
1668
1669 if (rgba2bpp_en) {
1670 *bRGA_OSD_COLOR0 = msg->osd_info.bpp2_info.color0.value;
1671 *bRGA_OSD_COLOR1 = msg->osd_info.bpp2_info.color1.value;
1672 }
1673 }
1674
RGA2_set_reg_color_palette(u8 * base,struct rga2_req * msg)1675 static void RGA2_set_reg_color_palette(u8 *base, struct rga2_req *msg)
1676 {
1677 u32 *bRGA_SRC_BASE0, *bRGA_SRC_INFO, *bRGA_SRC_VIR_INFO,
1678 *bRGA_SRC_ACT_INFO, *bRGA_SRC_FG_COLOR, *bRGA_SRC_BG_COLOR;
1679 u32 *p;
1680 short x_off, y_off;
1681 u16 src_stride;
1682 u8 shift;
1683 u32 sw;
1684 u32 byte_num;
1685 u32 reg;
1686
1687 bRGA_SRC_BASE0 = (u32 *) (base + RGA2_SRC_BASE0_OFFSET);
1688 bRGA_SRC_INFO = (u32 *) (base + RGA2_SRC_INFO_OFFSET);
1689 bRGA_SRC_VIR_INFO = (u32 *) (base + RGA2_SRC_VIR_INFO_OFFSET);
1690 bRGA_SRC_ACT_INFO = (u32 *) (base + RGA2_SRC_ACT_INFO_OFFSET);
1691 bRGA_SRC_FG_COLOR = (u32 *) (base + RGA2_SRC_FG_COLOR_OFFSET);
1692 bRGA_SRC_BG_COLOR = (u32 *) (base + RGA2_SRC_BG_COLOR_OFFSET);
1693
1694 reg = 0;
1695
1696 shift = 3 - msg->palette_mode;
1697
1698 x_off = msg->src.x_offset;
1699 y_off = msg->src.y_offset;
1700
1701 sw = msg->src.vir_w;
1702 byte_num = sw >> shift;
1703
1704 src_stride = (byte_num + 3) & (~3);
1705
1706 p = (u32 *) ((unsigned long)msg->src.yrgb_addr);
1707
1708 p = p + (x_off >> shift) + y_off * src_stride;
1709
1710 *bRGA_SRC_BASE0 = (unsigned long)p;
1711
1712 reg =
1713 ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) |
1714 (s_RGA2_SRC_INFO_SW_SRC_FMT((msg->palette_mode | 0xc))));
1715 reg =
1716 ((reg & (~m_RGA2_SRC_INFO_SW_SW_CP_ENDIAN)) |
1717 (s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(msg->endian_mode & 1)));
1718 *bRGA_SRC_VIR_INFO = src_stride >> 2;
1719 *bRGA_SRC_ACT_INFO =
1720 (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);
1721 *bRGA_SRC_INFO = reg;
1722
1723 *bRGA_SRC_FG_COLOR = msg->fg_color;
1724 *bRGA_SRC_BG_COLOR = msg->bg_color;
1725
1726 }
1727
RGA2_set_reg_color_fill(u8 * base,struct rga2_req * msg)1728 static void RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)
1729 {
1730 u32 *bRGA_CF_GR_A;
1731 u32 *bRGA_CF_GR_B;
1732 u32 *bRGA_CF_GR_G;
1733 u32 *bRGA_CF_GR_R;
1734 u32 *bRGA_SRC_FG_COLOR;
1735 u32 *bRGA_MASK_ADDR;
1736 u32 *bRGA_PAT_CON;
1737
1738 u32 mask_stride;
1739 u32 *bRGA_SRC_VIR_INFO;
1740
1741 bRGA_SRC_FG_COLOR = (u32 *) (base + RGA2_SRC_FG_COLOR_OFFSET);
1742
1743 bRGA_CF_GR_A = (u32 *) (base + RGA2_CF_GR_A_OFFSET);
1744 bRGA_CF_GR_B = (u32 *) (base + RGA2_CF_GR_B_OFFSET);
1745 bRGA_CF_GR_G = (u32 *) (base + RGA2_CF_GR_G_OFFSET);
1746 bRGA_CF_GR_R = (u32 *) (base + RGA2_CF_GR_R_OFFSET);
1747
1748 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1749 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1750
1751 bRGA_SRC_VIR_INFO = (u32 *) (base + RGA2_SRC_VIR_INFO_OFFSET);
1752
1753 mask_stride = msg->rop_mask_stride;
1754
1755 if (msg->color_fill_mode == 0) {
1756 /* solid color */
1757 *bRGA_CF_GR_A = (msg->gr_color.gr_x_a & 0xffff) |
1758 (msg->gr_color.gr_y_a << 16);
1759 *bRGA_CF_GR_B = (msg->gr_color.gr_x_b & 0xffff) |
1760 (msg->gr_color.gr_y_b << 16);
1761 *bRGA_CF_GR_G = (msg->gr_color.gr_x_g & 0xffff) |
1762 (msg->gr_color.gr_y_g << 16);
1763 *bRGA_CF_GR_R = (msg->gr_color.gr_x_r & 0xffff) |
1764 (msg->gr_color.gr_y_r << 16);
1765
1766 *bRGA_SRC_FG_COLOR = msg->fg_color;
1767 } else {
1768 /* pattern color */
1769 *bRGA_MASK_ADDR = (u32) msg->pat.yrgb_addr;
1770 *bRGA_PAT_CON =
1771 (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8)
1772 | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
1773 }
1774 *bRGA_SRC_VIR_INFO = mask_stride << 16;
1775 }
1776
RGA2_set_reg_update_palette_table(u8 * base,struct rga2_req * msg)1777 static void RGA2_set_reg_update_palette_table(u8 *base,
1778 struct rga2_req *msg)
1779 {
1780 u32 *bRGA_MASK_BASE;
1781 u32 *bRGA_FADING_CTRL;
1782
1783 bRGA_MASK_BASE = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1784 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1785
1786 *bRGA_FADING_CTRL = msg->fading_g_value << 8;
1787 *bRGA_MASK_BASE = (u32) msg->pat.yrgb_addr;
1788 }
1789
RGA2_set_reg_update_patten_buff(u8 * base,struct rga2_req * msg)1790 static void RGA2_set_reg_update_patten_buff(u8 *base, struct rga2_req *msg)
1791 {
1792 u32 *bRGA_PAT_MST;
1793 u32 *bRGA_PAT_CON;
1794 u32 *bRGA_PAT_START_POINT;
1795 u32 *bRGA_FADING_CTRL;
1796 u32 reg = 0;
1797 struct rga_img_info_t *pat;
1798
1799 u32 num, offset;
1800
1801 pat = &msg->pat;
1802
1803 num = (pat->act_w * pat->act_h) - 1;
1804
1805 offset = pat->act_w * pat->y_offset + pat->x_offset;
1806
1807 bRGA_PAT_START_POINT = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1808 bRGA_PAT_MST = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1809 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1810 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1811
1812 *bRGA_PAT_MST = (u32) msg->pat.yrgb_addr;
1813 *bRGA_PAT_START_POINT = (pat->act_w * pat->y_offset) + pat->x_offset;
1814
1815 reg = (pat->act_w - 1) | ((pat->act_h - 1) << 8) |
1816 (pat->x_offset << 16) | (pat->y_offset << 24);
1817 *bRGA_PAT_CON = reg;
1818
1819 *bRGA_FADING_CTRL = (num << 8) | offset;
1820 }
1821
RGA2_set_pat_info(u8 * base,struct rga2_req * msg)1822 static void RGA2_set_pat_info(u8 *base, struct rga2_req *msg)
1823 {
1824 u32 *bRGA_PAT_CON;
1825 u32 *bRGA_FADING_CTRL;
1826 u32 reg = 0;
1827 struct rga_img_info_t *pat;
1828
1829 u32 num, offset;
1830
1831 pat = &msg->pat;
1832
1833 num = ((pat->act_w * pat->act_h) - 1) & 0xff;
1834
1835 offset = (pat->act_w * pat->y_offset) + pat->x_offset;
1836
1837 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1838 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1839
1840 reg = (pat->act_w - 1) | ((pat->act_h - 1) << 8) |
1841 (pat->x_offset << 16) | (pat->y_offset << 24);
1842 *bRGA_PAT_CON = reg;
1843 *bRGA_FADING_CTRL = (num << 8) | offset;
1844 }
1845
RGA2_set_mmu_reg_info(u8 * base,struct rga2_req * msg)1846 static void RGA2_set_mmu_reg_info(u8 *base, struct rga2_req *msg)
1847 {
1848 u32 *bRGA_MMU_CTRL1;
1849 u32 *bRGA_MMU_SRC_BASE;
1850 u32 *bRGA_MMU_SRC1_BASE;
1851 u32 *bRGA_MMU_DST_BASE;
1852 u32 *bRGA_MMU_ELS_BASE;
1853
1854 u32 reg;
1855
1856 bRGA_MMU_CTRL1 = (u32 *) (base + RGA2_MMU_CTRL1_OFFSET);
1857 bRGA_MMU_SRC_BASE = (u32 *) (base + RGA2_MMU_SRC_BASE_OFFSET);
1858 bRGA_MMU_SRC1_BASE = (u32 *) (base + RGA2_MMU_SRC1_BASE_OFFSET);
1859 bRGA_MMU_DST_BASE = (u32 *) (base + RGA2_MMU_DST_BASE_OFFSET);
1860 bRGA_MMU_ELS_BASE = (u32 *) (base + RGA2_MMU_ELS_BASE_OFFSET);
1861
1862 reg = (msg->mmu_info.src0_mmu_flag & 0xf) |
1863 ((msg->mmu_info.src1_mmu_flag & 0xf) << 4) |
1864 ((msg->mmu_info.dst_mmu_flag & 0xf) << 8) |
1865 ((msg->mmu_info.els_mmu_flag & 0x3) << 12);
1866
1867 *bRGA_MMU_CTRL1 = reg;
1868 *bRGA_MMU_SRC_BASE = (u32) (msg->mmu_info.src0_base_addr) >> 4;
1869 *bRGA_MMU_SRC1_BASE = (u32) (msg->mmu_info.src1_base_addr) >> 4;
1870 *bRGA_MMU_DST_BASE = (u32) (msg->mmu_info.dst_base_addr) >> 4;
1871 *bRGA_MMU_ELS_BASE = (u32) (msg->mmu_info.els_base_addr) >> 4;
1872 }
1873
rga2_gen_reg_info(u8 * base,struct rga2_req * msg)1874 static int rga2_gen_reg_info(u8 *base, struct rga2_req *msg)
1875 {
1876 u8 dst_nn_quantize_en = 0;
1877
1878 RGA2_set_mode_ctrl(base, msg);
1879
1880 RGA2_set_pat_info(base, msg);
1881
1882 switch (msg->render_mode) {
1883 case BITBLT_MODE:
1884 RGA2_set_reg_src_info(base, msg);
1885 RGA2_set_reg_dst_info(base, msg);
1886 dst_nn_quantize_en = (msg->alpha_rop_flag >> 8) & 0x1;
1887 if (dst_nn_quantize_en != 1) {
1888 if ((msg->dst.format !=
1889 RGA_FORMAT_Y4)) {
1890 RGA2_set_reg_alpha_info(base, msg);
1891 RGA2_set_reg_rop_info(base, msg);
1892 }
1893 }
1894 if (msg->mosaic_info.enable)
1895 RGA_set_reg_mosaic(base, msg);
1896 if (msg->osd_info.enable)
1897 RGA2_set_reg_osd(base, msg);
1898
1899 break;
1900 case COLOR_FILL_MODE:
1901 RGA2_set_reg_color_fill(base, msg);
1902 RGA2_set_reg_dst_info(base, msg);
1903 RGA2_set_reg_alpha_info(base, msg);
1904 break;
1905 case COLOR_PALETTE_MODE:
1906 RGA2_set_reg_color_palette(base, msg);
1907 RGA2_set_reg_dst_info(base, msg);
1908 break;
1909 case UPDATE_PALETTE_TABLE_MODE:
1910 RGA2_set_reg_update_palette_table(base, msg);
1911 break;
1912 case UPDATE_PATTEN_BUF_MODE:
1913 RGA2_set_reg_update_patten_buff(base, msg);
1914 break;
1915 default:
1916 pr_err("ERROR msg render mode %d\n", msg->render_mode);
1917 break;
1918 }
1919
1920 RGA2_set_mmu_reg_info(base, msg);
1921
1922 return 0;
1923 }
1924
rga_cmd_to_rga2_cmd(struct rga_scheduler_t * scheduler,struct rga_req * req_rga,struct rga2_req * req)1925 static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler,
1926 struct rga_req *req_rga, struct rga2_req *req)
1927 {
1928 if (req_rga->render_mode == 6)
1929 req->render_mode = UPDATE_PALETTE_TABLE_MODE;
1930 else if (req_rga->render_mode == 7)
1931 req->render_mode = UPDATE_PATTEN_BUF_MODE;
1932 else if (req_rga->render_mode == 5)
1933 req->render_mode = BITBLT_MODE;
1934 else
1935 req->render_mode = req_rga->render_mode;
1936
1937 memcpy(&req->src, &req_rga->src, sizeof(req_rga->src));
1938 memcpy(&req->dst, &req_rga->dst, sizeof(req_rga->dst));
1939 /* The application will only import pat or src1. */
1940 if (req->render_mode == UPDATE_PALETTE_TABLE_MODE)
1941 memcpy(&req->pat, &req_rga->pat, sizeof(req_rga->pat));
1942 else
1943 memcpy(&req->src1, &req_rga->pat, sizeof(req_rga->pat));
1944
1945 req->src.format = req_rga->src.format;
1946 req->dst.format = req_rga->dst.format;
1947 req->src1.format = req_rga->pat.format;
1948
1949 switch (req_rga->rotate_mode & 0x0F) {
1950 case 1:
1951 if (req_rga->sina == 0 && req_rga->cosa == 65536) {
1952 /* rotate 0 */
1953 req->rotate_mode = 0;
1954 } else if (req_rga->sina == 65536 && req_rga->cosa == 0) {
1955 /* rotate 90 */
1956 req->rotate_mode = 1;
1957 req->dst.x_offset = req_rga->dst.x_offset;
1958 req->dst.act_w = req_rga->dst.act_h;
1959 req->dst.act_h = req_rga->dst.act_w;
1960 } else if (req_rga->sina == 0 && req_rga->cosa == -65536) {
1961 /* rotate 180 */
1962 req->rotate_mode = 2;
1963 req->dst.x_offset = req_rga->dst.x_offset;
1964 req->dst.y_offset = req_rga->dst.y_offset;
1965 } else if (req_rga->sina == -65536 && req_rga->cosa == 0) {
1966 /* totate 270 */
1967 req->rotate_mode = 3;
1968 req->dst.y_offset = req_rga->dst.y_offset;
1969 req->dst.act_w = req_rga->dst.act_h;
1970 req->dst.act_h = req_rga->dst.act_w;
1971 }
1972 break;
1973 case 2:
1974 //x_mirror
1975 req->rotate_mode |= (1 << 4);
1976 break;
1977 case 3:
1978 //y_mirror
1979 req->rotate_mode |= (2 << 4);
1980 break;
1981 case 4:
1982 //x_mirror+y_mirror
1983 req->rotate_mode |= (3 << 4);
1984 break;
1985 default:
1986 req->rotate_mode = 0;
1987 break;
1988 }
1989
1990 switch ((req_rga->rotate_mode & 0xF0) >> 4) {
1991 case 2:
1992 //x_mirror
1993 req->rotate_mode |= (1 << 4);
1994 break;
1995 case 3:
1996 //y_mirror
1997 req->rotate_mode |= (2 << 4);
1998 break;
1999 case 4:
2000 //x_mirror+y_mirror
2001 req->rotate_mode |= (3 << 4);
2002 break;
2003 }
2004
2005 req->LUT_addr = req_rga->LUT_addr;
2006 req->rop_mask_addr = req_rga->rop_mask_addr;
2007
2008 req->bitblt_mode = req_rga->bsfilter_flag;
2009
2010 req->src_a_global_val = req_rga->alpha_global_value;
2011 req->dst_a_global_val = req_rga->alpha_global_value;
2012 req->rop_code = req_rga->rop_code;
2013 req->rop_mode = req_rga->alpha_rop_mode;
2014
2015 req->color_fill_mode = req_rga->color_fill_mode;
2016 req->alpha_zero_key = req_rga->alpha_rop_mode >> 4;
2017 req->src_trans_mode = req_rga->src_trans_mode;
2018 req->color_key_min = req_rga->color_key_min;
2019 req->color_key_max = req_rga->color_key_max;
2020
2021 req->fg_color = req_rga->fg_color;
2022 req->bg_color = req_rga->bg_color;
2023 memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color));
2024
2025 req->palette_mode = req_rga->palette_mode;
2026 req->yuv2rgb_mode = req_rga->yuv2rgb_mode;
2027 req->endian_mode = req_rga->endian_mode;
2028 req->rgb2yuv_mode = 0;
2029
2030 req->fading_alpha_value = 0;
2031 req->fading_r_value = req_rga->fading.r;
2032 req->fading_g_value = req_rga->fading.g;
2033 req->fading_b_value = req_rga->fading.b;
2034
2035 /* alpha mode set */
2036 req->alpha_rop_flag = 0;
2037 /* alpha_rop_enable */
2038 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1)));
2039 /* rop_enable */
2040 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1);
2041 /* fading_enable */
2042 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2);
2043 /* alpha_cal_mode_sel */
2044 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3);
2045 /* dst_dither_down */
2046 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6);
2047 /* gradient fill mode sel */
2048 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7);
2049 /* RGA_NN_QUANTIZE */
2050 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 8) & 1) << 8);
2051 req->dither_mode = req_rga->dither_mode;
2052
2053 /* RGA2 1106 add */
2054 memcpy(&req->mosaic_info, &req_rga->mosaic_info, sizeof(req_rga->mosaic_info));
2055
2056 if ((scheduler->data->feature & RGA_YIN_YOUT) &&
2057 rga_is_only_y_format(req->src.format) &&
2058 rga_is_only_y_format(req->dst.format))
2059 req->yin_yout_en = true;
2060
2061 req->uvhds_mode = req_rga->uvhds_mode;
2062 req->uvvds_mode = req_rga->uvvds_mode;
2063
2064 memcpy(&req->osd_info, &req_rga->osd_info, sizeof(req_rga->osd_info));
2065
2066 if (((req_rga->alpha_rop_flag) & 1)) {
2067 if ((req_rga->alpha_rop_flag >> 3) & 1) {
2068 req->alpha_config.enable = true;
2069
2070 if ((req_rga->alpha_rop_flag >> 9) & 1) {
2071 req->alpha_config.fg_pre_multiplied = false;
2072 req->alpha_config.bg_pre_multiplied = false;
2073 } else if (req->osd_info.enable) {
2074 req->alpha_config.fg_pre_multiplied = true;
2075 /* set dst(osd_block) real color mode */
2076 req->alpha_config.bg_pre_multiplied = false;
2077 } else {
2078 req->alpha_config.fg_pre_multiplied = true;
2079 req->alpha_config.bg_pre_multiplied = true;
2080 }
2081
2082 req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->src.format);
2083 if (req->bitblt_mode)
2084 req->alpha_config.bg_pixel_alpha_en =
2085 rga_is_alpha_format(req->src1.format);
2086 else
2087 req->alpha_config.bg_pixel_alpha_en =
2088 rga_is_alpha_format(req->dst.format);
2089
2090 req->alpha_config.fg_global_alpha_en = false;
2091 req->alpha_config.bg_global_alpha_en = false;
2092
2093 req->alpha_config.fg_global_alpha_value = req_rga->alpha_global_value;
2094 req->alpha_config.bg_global_alpha_value = req_rga->alpha_global_value;
2095
2096 /* porter duff alpha enable */
2097 switch (req_rga->PD_mode) {
2098 /* dst = 0 */
2099 case 0:
2100 break;
2101 case 1:
2102 req->alpha_config.mode = RGA_ALPHA_BLEND_SRC;
2103 break;
2104 case 2:
2105 req->alpha_config.mode = RGA_ALPHA_BLEND_DST;
2106 break;
2107 case 3:
2108 if ((req_rga->alpha_rop_mode & 3) == 0) {
2109 /* both use globalAlpha. */
2110 req->alpha_config.fg_global_alpha_en = true;
2111 req->alpha_config.bg_global_alpha_en = true;
2112 } else if ((req_rga->alpha_rop_mode & 3) == 1) {
2113 /* Do not use globalAlpha. */
2114 req->alpha_config.fg_global_alpha_en = false;
2115 req->alpha_config.bg_global_alpha_en = false;
2116 } else {
2117 /* dst use globalAlpha */
2118 req->alpha_config.fg_global_alpha_en = false;
2119 req->alpha_config.bg_global_alpha_en = true;
2120 }
2121
2122 req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_OVER;
2123 break;
2124 case 4:
2125 req->alpha_config.mode = RGA_ALPHA_BLEND_DST_OVER;
2126 break;
2127 case 5:
2128 req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_IN;
2129 break;
2130 case 6:
2131 req->alpha_config.mode = RGA_ALPHA_BLEND_DST_IN;
2132 break;
2133 case 7:
2134 req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_OUT;
2135 break;
2136 case 8:
2137 req->alpha_config.mode = RGA_ALPHA_BLEND_DST_OUT;
2138 break;
2139 case 9:
2140 req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_ATOP;
2141 break;
2142 case 10:
2143 req->alpha_config.mode = RGA_ALPHA_BLEND_DST_ATOP;
2144 break;
2145 case 11:
2146 req->alpha_config.mode = RGA_ALPHA_BLEND_XOR;
2147 break;
2148 case 12:
2149 req->alpha_config.mode = RGA_ALPHA_BLEND_CLEAR;
2150 break;
2151 default:
2152 break;
2153 }
2154 }
2155 }
2156
2157 if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) {
2158 req->mmu_info.src0_mmu_flag = 1;
2159 req->mmu_info.dst_mmu_flag = 1;
2160
2161 if (req_rga->mmu_info.mmu_flag >> 31) {
2162 req->mmu_info.src0_mmu_flag =
2163 ((req_rga->mmu_info.mmu_flag >> 8) & 1);
2164 req->mmu_info.src1_mmu_flag =
2165 ((req_rga->mmu_info.mmu_flag >> 9) & 1);
2166 req->mmu_info.dst_mmu_flag =
2167 ((req_rga->mmu_info.mmu_flag >> 10) & 1);
2168 req->mmu_info.els_mmu_flag =
2169 ((req_rga->mmu_info.mmu_flag >> 11) & 1);
2170 } else {
2171 if (req_rga->src.yrgb_addr >= 0xa0000000) {
2172 req->mmu_info.src0_mmu_flag = 0;
2173 req->src.yrgb_addr =
2174 req_rga->src.yrgb_addr - 0x60000000;
2175 req->src.uv_addr =
2176 req_rga->src.uv_addr - 0x60000000;
2177 req->src.v_addr =
2178 req_rga->src.v_addr - 0x60000000;
2179 }
2180
2181 if (req_rga->dst.yrgb_addr >= 0xa0000000) {
2182 req->mmu_info.dst_mmu_flag = 0;
2183 req->dst.yrgb_addr =
2184 req_rga->dst.yrgb_addr - 0x60000000;
2185 }
2186
2187 if (req_rga->pat.yrgb_addr >= 0xa0000000) {
2188 req->mmu_info.src1_mmu_flag = 0;
2189 req->src1.yrgb_addr =
2190 req_rga->pat.yrgb_addr - 0x60000000;
2191 }
2192 }
2193 }
2194 }
2195
rga2_soft_reset(struct rga_scheduler_t * scheduler)2196 static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
2197 {
2198 u32 i;
2199 u32 reg;
2200 u32 iommu_dte_addr = 0;
2201
2202 if (scheduler->data->mmu == RGA_IOMMU)
2203 iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
2204
2205 rga_write(m_RGA2_SYS_CTRL_ACLK_SRESET_P | m_RGA2_SYS_CTRL_CCLK_SRESET_P |
2206 m_RGA2_SYS_CTRL_RST_PROTECT_P,
2207 RGA2_SYS_CTRL, scheduler);
2208
2209 for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
2210 /* RGA_SYS_CTRL */
2211 reg = rga_read(RGA2_SYS_CTRL, scheduler) & 1;
2212
2213 if (reg == 0)
2214 break;
2215
2216 udelay(1);
2217 }
2218
2219 if (scheduler->data->mmu == RGA_IOMMU) {
2220 rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
2221 /* enable iommu */
2222 rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
2223 }
2224
2225 if (i == RGA_RESET_TIMEOUT)
2226 pr_err("RAG2 core[%d] soft reset timeout.\n", scheduler->core);
2227 else
2228 pr_info("RGA2 core[%d] soft reset complete.\n", scheduler->core);
2229
2230 }
2231
rga2_check_param(const struct rga_hw_data * data,const struct rga2_req * req)2232 static int rga2_check_param(const struct rga_hw_data *data, const struct rga2_req *req)
2233 {
2234 if (!((req->render_mode == COLOR_FILL_MODE))) {
2235 if (unlikely(rga_hw_out_of_range(&data->input_range,
2236 req->src.act_w, req->src.act_h))) {
2237 pr_err("invalid src resolution act_w = %d, act_h = %d\n",
2238 req->src.act_w, req->src.act_h);
2239 return -EINVAL;
2240 }
2241
2242 if (unlikely(req->src.vir_w * rga_get_pixel_stride_from_format(req->src.format) >
2243 data->max_byte_stride * 8)) {
2244 pr_err("invalid src stride, stride = %d, max_byte_stride = %d\n",
2245 req->src.vir_w, data->max_byte_stride);
2246 return -EINVAL;
2247 }
2248
2249 if (unlikely(req->src.vir_w < req->src.act_w)) {
2250 pr_err("invalid src_vir_w act_w = %d, vir_w = %d\n",
2251 req->src.act_w, req->src.vir_w);
2252 return -EINVAL;
2253 }
2254 }
2255
2256 if (unlikely(rga_hw_out_of_range(&data->output_range, req->dst.act_w, req->dst.act_h))) {
2257 pr_err("invalid dst resolution act_w = %d, act_h = %d\n",
2258 req->dst.act_w, req->dst.act_h);
2259 return -EINVAL;
2260 }
2261
2262 if (unlikely(req->dst.vir_w * rga_get_pixel_stride_from_format(req->dst.format) >
2263 data->max_byte_stride * 8)) {
2264 pr_err("invalid dst stride, stride = %d, max_byte_stride = %d\n",
2265 req->dst.vir_w, data->max_byte_stride);
2266 return -EINVAL;
2267 }
2268
2269 if (unlikely(req->dst.vir_w < req->dst.act_w)) {
2270 if (req->rotate_mode != 1) {
2271 pr_err("invalid dst_vir_w act_h = %d, vir_h = %d\n",
2272 req->dst.act_w, req->dst.vir_w);
2273 return -EINVAL;
2274 }
2275 }
2276
2277 return 0;
2278 }
2279
rga2_align_check(struct rga2_req * req)2280 static int rga2_align_check(struct rga2_req *req)
2281 {
2282 if (rga_is_yuv10bit_format(req->src.format))
2283 if ((req->src.vir_w % 16) || (req->src.x_offset % 2) ||
2284 (req->src.act_w % 2) || (req->src.y_offset % 2) ||
2285 (req->src.act_h % 2) || (req->src.vir_h % 2))
2286 pr_info("err src wstride, 10bit yuv\n");
2287 if (rga_is_yuv10bit_format(req->dst.format))
2288 if ((req->dst.vir_w % 16) || (req->dst.x_offset % 2) ||
2289 (req->dst.act_w % 2) || (req->dst.y_offset % 2) ||
2290 (req->dst.act_h % 2) || (req->dst.vir_h % 2))
2291 pr_info("err dst wstride, 10bit yuv\n");
2292 if (rga_is_yuv8bit_format(req->src.format))
2293 if ((req->src.vir_w % 4) || (req->src.x_offset % 2) ||
2294 (req->src.act_w % 2) || (req->src.y_offset % 2) ||
2295 (req->src.act_h % 2) || (req->src.vir_h % 2))
2296 pr_info("err src wstride, 8bit yuv\n");
2297 if (rga_is_yuv8bit_format(req->dst.format))
2298 if ((req->dst.vir_w % 4) || (req->dst.x_offset % 2) ||
2299 (req->dst.act_w % 2) || (req->dst.y_offset % 2) ||
2300 (req->dst.act_h % 2) || (req->dst.vir_h % 2))
2301 pr_info("err dst wstride, 8bit yuv\n");
2302
2303 return 0;
2304 }
2305
print_debug_info(struct rga2_req * req)2306 static void print_debug_info(struct rga2_req *req)
2307 {
2308 pr_info("render_mode:%s,bitblit_mode=%d,rotate_mode:%s\n",
2309 rga_get_render_mode_str(req->render_mode), req->bitblt_mode,
2310 rga_get_rotate_mode_str(req->rotate_mode));
2311
2312 pr_info("src: y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d\n",
2313 (unsigned long)req->src.yrgb_addr,
2314 (unsigned long)req->src.uv_addr,
2315 (unsigned long)req->src.v_addr,
2316 req->src.act_w, req->src.act_h,
2317 req->src.vir_w, req->src.vir_h);
2318 pr_info("src: xoff=%d yoff=%d format=%s\n",
2319 req->src.x_offset, req->src.y_offset,
2320 rga_get_format_name(req->src.format));
2321
2322 if (req->src1.yrgb_addr != 0 || req->src1.uv_addr != 0
2323 || req->src1.v_addr != 0) {
2324 pr_info("src1: y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d\n",
2325 (unsigned long)req->src1.yrgb_addr,
2326 (unsigned long)req->src1.uv_addr,
2327 (unsigned long)req->src1.v_addr,
2328 req->src1.act_w, req->src1.act_h,
2329 req->src1.vir_w, req->src1.vir_h);
2330 pr_info("src1: xoff=%d yoff=%d format=%s\n",
2331 req->src1.x_offset, req->src1.y_offset,
2332 rga_get_format_name(req->src1.format));
2333 }
2334
2335 pr_info("dst: y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d\n",
2336 (unsigned long)req->dst.yrgb_addr,
2337 (unsigned long)req->dst.uv_addr,
2338 (unsigned long)req->dst.v_addr,
2339 req->dst.act_w, req->dst.act_h,
2340 req->dst.vir_w, req->dst.vir_h);
2341 pr_info("dst: xoff=%d yoff=%d format=%s\n",
2342 req->dst.x_offset, req->dst.y_offset,
2343 rga_get_format_name(req->dst.format));
2344
2345 pr_info("mmu: src=%.2x src1=%.2x dst=%.2x els=%.2x\n",
2346 req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
2347 req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag);
2348 pr_info("alpha: flag %x mode=%s\n",
2349 req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode));
2350 pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n",
2351 req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied,
2352 req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en,
2353 req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en);
2354 pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n",
2355 req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value);
2356 pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
2357 }
2358
rga2_init_reg(struct rga_job * job)2359 static int rga2_init_reg(struct rga_job *job)
2360 {
2361 struct rga2_req req;
2362 int ret = 0;
2363 struct rga_scheduler_t *scheduler = NULL;
2364
2365 scheduler = job->scheduler;
2366 if (unlikely(scheduler == NULL)) {
2367 pr_err("failed to get scheduler, %s(%d)\n", __func__, __LINE__);
2368 return -EINVAL;
2369 }
2370
2371 memset(&req, 0x0, sizeof(req));
2372
2373 rga_cmd_to_rga2_cmd(scheduler, &job->rga_command_base, &req);
2374 memcpy(&job->full_csc, &job->rga_command_base.full_csc, sizeof(job->full_csc));
2375 memcpy(&job->pre_intr_info, &job->rga_command_base.pre_intr_info,
2376 sizeof(job->pre_intr_info));
2377
2378 /* check value if legal */
2379 ret = rga2_check_param(scheduler->data, &req);
2380 if (ret == -EINVAL) {
2381 pr_err("req argument is inval\n");
2382 return ret;
2383 }
2384
2385 rga2_align_check(&req);
2386
2387 /* for debug */
2388 if (DEBUGGER_EN(MSG))
2389 print_debug_info(&req);
2390
2391 /* RGA2 mmu set */
2392 if ((req.mmu_info.src0_mmu_flag & 1) || (req.mmu_info.src1_mmu_flag & 1) ||
2393 (req.mmu_info.dst_mmu_flag & 1) || (req.mmu_info.els_mmu_flag & 1)) {
2394 if (scheduler->data->mmu != RGA_MMU) {
2395 pr_err("core[%d] has no MMU, please use physically contiguous memory.\n",
2396 scheduler->core);
2397 pr_err("mmu_flag[src, src1, dst, els] = [0x%x, 0x%x, 0x%x, 0x%x]\n",
2398 req.mmu_info.src0_mmu_flag, req.mmu_info.src1_mmu_flag,
2399 req.mmu_info.dst_mmu_flag, req.mmu_info.els_mmu_flag);
2400 return -EINVAL;
2401 }
2402
2403 ret = rga_set_mmu_base(job, &req);
2404 if (ret < 0) {
2405 pr_err("%s, [%d] set mmu info error\n", __func__,
2406 __LINE__);
2407 return -EFAULT;
2408 }
2409 }
2410
2411 /* In slave mode, the current frame completion interrupt must be enabled. */
2412 if (scheduler->data->mmu == RGA_IOMMU)
2413 req.CMD_fin_int_enable = 1;
2414
2415 if (rga2_gen_reg_info((uint8_t *)job->cmd_reg, &req) == -1) {
2416 pr_err("gen reg info error\n");
2417 return -EINVAL;
2418 }
2419
2420 return ret;
2421 }
2422
rga2_dump_read_back_sys_reg(struct rga_scheduler_t * scheduler)2423 static void rga2_dump_read_back_sys_reg(struct rga_scheduler_t *scheduler)
2424 {
2425 int i;
2426 unsigned long flags;
2427 uint32_t sys_reg[24] = {0};
2428
2429 spin_lock_irqsave(&scheduler->irq_lock, flags);
2430
2431 for (i = 0; i < 24; i++)
2432 sys_reg[i] = rga_read(RGA2_SYS_REG_BASE + i * 4, scheduler);
2433
2434 spin_unlock_irqrestore(&scheduler->irq_lock, flags);
2435
2436 pr_info("SYS_READ_BACK_REG\n");
2437 for (i = 0; i < 6; i++)
2438 pr_info("0x%04x : %.8x %.8x %.8x %.8x\n",
2439 RGA2_SYS_REG_BASE + i * 0x10,
2440 sys_reg[0 + i * 4], sys_reg[1 + i * 4],
2441 sys_reg[2 + i * 4], sys_reg[3 + i * 4]);
2442 }
2443
rga2_dump_read_back_csc_reg(struct rga_scheduler_t * scheduler)2444 static void rga2_dump_read_back_csc_reg(struct rga_scheduler_t *scheduler)
2445 {
2446 int i;
2447 unsigned long flags;
2448 uint32_t csc_reg[12] = {0};
2449
2450 spin_lock_irqsave(&scheduler->irq_lock, flags);
2451
2452 for (i = 0; i < 12; i++)
2453 csc_reg[i] = rga_read(RGA2_CSC_REG_BASE + i * 4, scheduler);
2454
2455 spin_unlock_irqrestore(&scheduler->irq_lock, flags);
2456
2457 pr_info("CSC_READ_BACK_REG\n");
2458 for (i = 0; i < 3; i++)
2459 pr_info("0x%04x : %.8x %.8x %.8x %.8x\n",
2460 RGA2_CSC_REG_BASE + i * 0x10,
2461 csc_reg[0 + i * 4], csc_reg[1 + i * 4],
2462 csc_reg[2 + i * 4], csc_reg[3 + i * 4]);
2463 }
2464
rga2_dump_read_back_cmd_reg(struct rga_scheduler_t * scheduler)2465 static void rga2_dump_read_back_cmd_reg(struct rga_scheduler_t *scheduler)
2466 {
2467 int i;
2468 unsigned long flags;
2469 uint32_t cmd_reg[32] = {0};
2470
2471 spin_lock_irqsave(&scheduler->irq_lock, flags);
2472
2473 for (i = 0; i < 32; i++)
2474 cmd_reg[i] = rga_read(RGA2_CMD_REG_BASE + i * 4, scheduler);
2475
2476 spin_unlock_irqrestore(&scheduler->irq_lock, flags);
2477
2478 pr_info("CMD_READ_BACK_REG\n");
2479 for (i = 0; i < 8; i++)
2480 pr_info("0x%04x : %.8x %.8x %.8x %.8x\n",
2481 RGA2_CMD_REG_BASE + i * 0x10,
2482 cmd_reg[0 + i * 4], cmd_reg[1 + i * 4],
2483 cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
2484 }
2485
rga2_dump_read_back_reg(struct rga_scheduler_t * scheduler)2486 static void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler)
2487 {
2488 rga2_dump_read_back_sys_reg(scheduler);
2489 rga2_dump_read_back_csc_reg(scheduler);
2490 rga2_dump_read_back_cmd_reg(scheduler);
2491 }
2492
rga2_set_pre_intr_reg(struct rga_job * job,struct rga_scheduler_t * scheduler)2493 static void rga2_set_pre_intr_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
2494 {
2495 uint32_t reg;
2496
2497 if (job->pre_intr_info.read_intr_en) {
2498 reg = s_RGA2_READ_LINE_SW_INTR_LINE_RD_TH(job->pre_intr_info.read_threshold);
2499 rga_write(reg, RGA2_READ_LINE_CNT, scheduler);
2500 }
2501
2502 if (job->pre_intr_info.write_intr_en) {
2503 reg = s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_START(job->pre_intr_info.write_start);
2504 reg = ((reg & (~m_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP)) |
2505 (s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP(job->pre_intr_info.write_step)));
2506 rga_write(reg, RGA2_WRITE_LINE_CNT, scheduler);
2507 }
2508
2509 reg = rga_read(RGA2_SYS_CTRL, scheduler);
2510 reg = ((reg & (~m_RGA2_SYS_CTRL_HOLD_MODE_EN)) |
2511 (s_RGA2_SYS_CTRL_HOLD_MODE_EN(job->pre_intr_info.read_hold_en)));
2512 rga_write(reg, RGA2_SYS_CTRL, scheduler);
2513
2514 reg = rga_read(RGA2_INT, scheduler);
2515 reg = (reg | s_RGA2_INT_LINE_RD_CLEAR(0x1) | s_RGA2_INT_LINE_WR_CLEAR(0x1));
2516 reg = ((reg & (~m_RGA2_INT_LINE_RD_EN)) |
2517 (s_RGA2_INT_LINE_RD_EN(job->pre_intr_info.read_intr_en)));
2518 reg = ((reg & (~m_RGA2_INT_LINE_WR_EN)) |
2519 (s_RGA2_INT_LINE_WR_EN(job->pre_intr_info.write_intr_en)));
2520 rga_write(reg, RGA2_INT, scheduler);
2521 }
2522
rga2_set_reg_full_csc(struct rga_job * job,struct rga_scheduler_t * scheduler)2523 static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *scheduler)
2524 {
2525 uint8_t clip_y_max, clip_y_min;
2526 uint8_t clip_uv_max, clip_uv_min;
2527
2528 clip_y_max = 0xff;
2529 clip_y_min = 0x0;
2530 clip_uv_max = 0xff;
2531 clip_uv_min = 0;
2532
2533 /* full csc coefficient */
2534 /* Y coefficient */
2535 rga_write(job->full_csc.coe_y.r_v | (clip_y_max << 16) | (clip_y_min << 24),
2536 RGA2_DST_CSC_00, scheduler);
2537 rga_write(job->full_csc.coe_y.g_y | (clip_uv_max << 16) | (clip_uv_min << 24),
2538 RGA2_DST_CSC_01, scheduler);
2539 rga_write(job->full_csc.coe_y.b_u, RGA2_DST_CSC_02, scheduler);
2540 rga_write(job->full_csc.coe_y.off, RGA2_DST_CSC_OFF0, scheduler);
2541
2542 /* U coefficient */
2543 rga_write(job->full_csc.coe_u.r_v, RGA2_DST_CSC_10, scheduler);
2544 rga_write(job->full_csc.coe_u.g_y, RGA2_DST_CSC_11, scheduler);
2545 rga_write(job->full_csc.coe_u.b_u, RGA2_DST_CSC_12, scheduler);
2546 rga_write(job->full_csc.coe_u.off, RGA2_DST_CSC_OFF1, scheduler);
2547
2548 /* V coefficient */
2549 rga_write(job->full_csc.coe_v.r_v, RGA2_DST_CSC_20, scheduler);
2550 rga_write(job->full_csc.coe_v.g_y, RGA2_DST_CSC_21, scheduler);
2551 rga_write(job->full_csc.coe_v.b_u, RGA2_DST_CSC_22, scheduler);
2552 rga_write(job->full_csc.coe_v.off, RGA2_DST_CSC_OFF2, scheduler);
2553 }
2554
rga2_set_reg(struct rga_job * job,struct rga_scheduler_t * scheduler)2555 static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
2556 {
2557 int i;
2558 bool master_mode_en;
2559 uint32_t sys_ctrl;
2560 ktime_t now = ktime_get();
2561
2562 /*
2563 * Currently there is no iova allocated for storing cmd for the IOMMU device,
2564 * so the iommu device needs to use the slave mode.
2565 */
2566 if (scheduler->data->mmu != RGA_IOMMU)
2567 master_mode_en = true;
2568 else
2569 master_mode_en = false;
2570
2571 if (job->pre_intr_info.enable)
2572 rga2_set_pre_intr_reg(job, scheduler);
2573
2574 if (job->full_csc.flag)
2575 rga2_set_reg_full_csc(job, scheduler);
2576
2577 if (DEBUGGER_EN(REG)) {
2578 uint32_t *p;
2579
2580 rga2_dump_read_back_sys_reg(scheduler);
2581 rga2_dump_read_back_csc_reg(scheduler);
2582
2583 p = job->cmd_reg;
2584 pr_info("CMD_REG\n");
2585 for (i = 0; i < 8; i++)
2586 pr_info("i = %x : %.8x %.8x %.8x %.8x\n", i,
2587 p[0 + i * 4], p[1 + i * 4],
2588 p[2 + i * 4], p[3 + i * 4]);
2589 }
2590
2591 /* All CMD finish int */
2592 rga_write(rga_read(RGA2_INT, scheduler) |
2593 m_RGA2_INT_ERROR_ENABLE_MASK | m_RGA2_INT_ALL_CMD_DONE_INT_EN,
2594 RGA2_INT, scheduler);
2595
2596 /* sys_reg init */
2597 sys_ctrl = m_RGA2_SYS_CTRL_AUTO_CKG | m_RGA2_SYS_CTRL_AUTO_RST |
2598 m_RGA2_SYS_CTRL_RST_PROTECT_P | m_RGA2_SYS_CTRL_DST_WR_OPT_DIS |
2599 m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS;
2600
2601 if (master_mode_en) {
2602 /* master mode */
2603 sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(1);
2604
2605 /* cmd buffer flush cache to ddr */
2606 rga_dma_sync_flush_range(&job->cmd_reg[0], &job->cmd_reg[32], scheduler);
2607
2608 /* set cmd_addr */
2609 rga_write(virt_to_phys(job->cmd_reg), RGA2_CMD_BASE, scheduler);
2610 rga_write(sys_ctrl, RGA2_SYS_CTRL, scheduler);
2611 rga_write(m_RGA2_CMD_CTRL_CMD_LINE_ST_P, RGA2_CMD_CTRL, scheduler);
2612 } else {
2613 /* slave mode */
2614 sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(0) | m_RGA2_SYS_CTRL_CMD_OP_ST_P;
2615
2616 /* set cmd_reg */
2617 for (i = 0; i <= 32; i++)
2618 rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
2619
2620 rga_write(sys_ctrl, RGA2_SYS_CTRL, scheduler);
2621 }
2622
2623 if (DEBUGGER_EN(REG))
2624 pr_info("sys_ctrl = %x, int = %x\n",
2625 rga_read(RGA2_SYS_CTRL, scheduler),
2626 rga_read(RGA2_INT, scheduler));
2627
2628 if (DEBUGGER_EN(TIME))
2629 pr_info("set cmd use time = %lld\n",
2630 ktime_us_delta(now, job->timestamp));
2631
2632 job->hw_running_time = now;
2633 job->hw_recoder_time = now;
2634
2635 if (DEBUGGER_EN(REG))
2636 rga2_dump_read_back_reg(scheduler);
2637
2638 return 0;
2639 }
2640
rga2_get_version(struct rga_scheduler_t * scheduler)2641 static int rga2_get_version(struct rga_scheduler_t *scheduler)
2642 {
2643 u32 major_version, minor_version, svn_version;
2644 u32 reg_version;
2645
2646 if (!scheduler) {
2647 pr_err("scheduler is null\n");
2648 return -EINVAL;
2649 }
2650
2651 reg_version = rga_read(RGA2_VERSION_NUM, scheduler);
2652
2653 major_version = (reg_version & RGA2_MAJOR_VERSION_MASK) >> 24;
2654 minor_version = (reg_version & RGA2_MINOR_VERSION_MASK) >> 20;
2655 svn_version = (reg_version & RGA2_SVN_VERSION_MASK);
2656
2657 /*
2658 * some old rga ip has no rga version register, so force set to 2.00
2659 */
2660 if (!major_version && !minor_version)
2661 major_version = 2;
2662
2663 snprintf(scheduler->version.str, 10, "%x.%01x.%05x", major_version,
2664 minor_version, svn_version);
2665
2666 scheduler->version.major = major_version;
2667 scheduler->version.minor = minor_version;
2668 scheduler->version.revision = svn_version;
2669
2670 return 0;
2671 }
2672
rga2_read_back_reg(struct rga_job * job,struct rga_scheduler_t * scheduler)2673 static int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
2674 {
2675 if (job->rga_command_base.osd_info.enable) {
2676 job->rga_command_base.osd_info.cur_flags0 = rga_read(RGA2_OSD_CUR_FLAGS0,
2677 scheduler);
2678 job->rga_command_base.osd_info.cur_flags1 = rga_read(RGA2_OSD_CUR_FLAGS1,
2679 scheduler);
2680 }
2681
2682 return 0;
2683 }
2684
rga2_irq(struct rga_scheduler_t * scheduler)2685 static int rga2_irq(struct rga_scheduler_t *scheduler)
2686 {
2687 struct rga_job *job = scheduler->running_job;
2688
2689 /* The hardware interrupt top-half don't need to lock the scheduler. */
2690 if (job == NULL)
2691 return IRQ_HANDLED;
2692
2693 if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state))
2694 return IRQ_WAKE_THREAD;
2695
2696 job->intr_status = rga_read(RGA2_INT, scheduler);
2697 job->hw_status = rga_read(RGA2_STATUS2, scheduler);
2698 job->cmd_status = rga_read(RGA2_STATUS1, scheduler);
2699
2700 if (DEBUGGER_EN(INT_FLAG))
2701 pr_info("irq handler, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2702 job->intr_status, job->hw_status, job->cmd_status);
2703
2704 if (job->intr_status &
2705 (m_RGA2_INT_CUR_CMD_DONE_INT_FLAG | m_RGA2_INT_ALL_CMD_DONE_INT_FLAG)) {
2706 set_bit(RGA_JOB_STATE_FINISH, &job->state);
2707 } else if (job->intr_status & m_RGA2_INT_ERROR_FLAG_MASK) {
2708 set_bit(RGA_JOB_STATE_INTR_ERR, &job->state);
2709
2710 pr_err("irq handler err! INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2711 job->intr_status, job->hw_status, job->cmd_status);
2712 scheduler->ops->soft_reset(scheduler);
2713 }
2714
2715 /*clear INTR */
2716 rga_write(rga_read(RGA2_INT, scheduler) |
2717 (m_RGA2_INT_ERROR_CLEAR_MASK |
2718 m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR | m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR |
2719 m_RGA2_INT_LINE_RD_CLEAR | m_RGA2_INT_LINE_WR_CLEAR),
2720 RGA2_INT, scheduler);
2721
2722 return IRQ_WAKE_THREAD;
2723 }
2724
rga2_isr_thread(struct rga_job * job,struct rga_scheduler_t * scheduler)2725 static int rga2_isr_thread(struct rga_job *job, struct rga_scheduler_t *scheduler)
2726 {
2727 if (DEBUGGER_EN(INT_FLAG))
2728 pr_info("isr thread, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2729 rga_read(RGA2_INT, scheduler),
2730 rga_read(RGA2_STATUS2, scheduler),
2731 rga_read(RGA2_STATUS1, scheduler));
2732
2733 if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
2734 if (job->hw_status & m_RGA2_STATUS2_RPP_ERROR)
2735 pr_err("RGA current status: rpp error!\n");
2736 if (job->hw_status & m_RGA2_STATUS2_BUS_ERROR)
2737 pr_err("RGA current status: bus error!\n");
2738
2739 if (job->intr_status & m_RGA2_INT_ERROR_INT_FLAG) {
2740 pr_err("RGA bus error intr, please check your configuration and buffer.\n");
2741 job->ret = -EFAULT;
2742 } else if (job->intr_status & m_RGA2_INT_MMU_INT_FLAG) {
2743 pr_err("mmu failed, please check size of the buffer or whether the buffer has been freed.\n");
2744 job->ret = -EACCES;
2745 }
2746
2747 if (job->ret == 0) {
2748 pr_err("rga intr error[0x%x]!\n", job->intr_status);
2749 job->ret = -EFAULT;
2750 }
2751 }
2752
2753 return IRQ_HANDLED;
2754 }
2755
2756 const struct rga_backend_ops rga2_ops = {
2757 .get_version = rga2_get_version,
2758 .set_reg = rga2_set_reg,
2759 .init_reg = rga2_init_reg,
2760 .soft_reset = rga2_soft_reset,
2761 .read_back_reg = rga2_read_back_reg,
2762 .irq = rga2_irq,
2763 .isr_thread = rga2_isr_thread,
2764 };
2765