1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef __KIRIN_DRM_DSI_H__ 3 #define __KIRIN_DRM_DSI_H__ 4 5 #include <linux/clk.h> 6 #include <linux/component.h> 7 #include <linux/of_graph.h> 8 #include <linux/iopoll.h> 9 #include <video/mipi_display.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/of_address.h> 12 #include <linux/of_platform.h> 13 14 #include <drm/drm_of.h> 15 #include <drm/drm_crtc_helper.h> 16 #include <drm/drm_mipi_dsi.h> 17 #include <drm/drm_encoder_slave.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_panel.h> 20 21 #define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0)) 22 #define PHY_REF_CLK_RATE 19200000 23 #define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000)) 24 25 #define encoder_to_dsi(encoder) container_of(encoder, struct dw_dsi, encoder) 26 #define host_to_dsi(host) container_of(host, struct dw_dsi, host) 27 #define connector_to_dsi(connector) \ 28 container_of(connector, struct dw_dsi, connector) 29 30 enum dsi_output_client { OUT_HDMI = 0, OUT_PANEL, OUT_MAX }; 31 32 struct dsi_phy_range { 33 u32 min_range_kHz; 34 u32 max_range_kHz; 35 u32 pll_vco_750M; 36 u32 hstx_ckg_sel; 37 }; 38 39 static const struct dsi_phy_range dphy_range_info[] = { 40 { 46875, 62500, 1, 7 }, 41 { 62500, 93750, 0, 7 }, 42 { 93750, 125000, 1, 6 }, 43 { 125000, 187500, 0, 6 }, 44 { 187500, 250000, 1, 5 }, 45 { 250000, 375000, 0, 5 }, 46 { 375000, 500000, 1, 4 }, 47 { 500000, 750000, 0, 4 }, 48 { 750000, 1000000, 1, 0 }, 49 { 1000000, 1500000, 0, 0 } 50 }; 51 52 struct dsi_hw_ctx { 53 void __iomem *base; 54 char __iomem *peri_crg_base; 55 56 struct clk *pclk; 57 struct clk *dss_dphy0_ref_clk; 58 struct clk *dss_dphy1_ref_clk; 59 struct clk *dss_dphy0_cfg_clk; 60 struct clk *dss_dphy1_cfg_clk; 61 struct clk *dss_pclk_dsi0_clk; 62 struct clk *dss_pclk_dsi1_clk; 63 }; 64 65 struct mipi_panel_info { 66 u8 dsi_version; 67 u8 vc; 68 u8 lane_nums; 69 u8 lane_nums_select_support; 70 u8 color_mode; 71 u32 dsi_bit_clk; /* clock lane(p/n) */ 72 u32 burst_mode; 73 u32 max_tx_esc_clk; 74 u8 non_continue_en; 75 76 u32 dsi_bit_clk_val1; 77 u32 dsi_bit_clk_val2; 78 u32 dsi_bit_clk_val3; 79 u32 dsi_bit_clk_val4; 80 u32 dsi_bit_clk_val5; 81 u32 dsi_bit_clk_upt; 82 /*uint32_t dsi_pclk_rate;*/ 83 84 u32 hs_wr_to_time; 85 86 /* dphy config parameter adjust*/ 87 u32 clk_post_adjust; 88 u32 clk_pre_adjust; 89 u32 clk_pre_delay_adjust; 90 u32 clk_t_hs_exit_adjust; 91 u32 clk_t_hs_trial_adjust; 92 u32 clk_t_hs_prepare_adjust; 93 int clk_t_lpx_adjust; 94 u32 clk_t_hs_zero_adjust; 95 u32 data_post_delay_adjust; 96 int data_t_lpx_adjust; 97 u32 data_t_hs_prepare_adjust; 98 u32 data_t_hs_zero_adjust; 99 u32 data_t_hs_trial_adjust; 100 u32 rg_vrefsel_vcm_adjust; 101 102 /*only for Chicago<3660> use*/ 103 u32 rg_vrefsel_vcm_clk_adjust; 104 u32 rg_vrefsel_vcm_data_adjust; 105 }; 106 107 struct mipi_phy_params { 108 u32 clk_t_lpx; 109 u32 clk_t_hs_prepare; 110 u32 clk_t_hs_zero; 111 u32 clk_t_hs_trial; 112 u32 clk_t_wakeup; 113 u32 data_t_lpx; 114 u32 data_t_hs_prepare; 115 u32 data_t_hs_zero; 116 u32 data_t_hs_trial; 117 u32 data_t_ta_go; 118 u32 data_t_ta_get; 119 u32 data_t_wakeup; 120 u32 hstx_ckg_sel; 121 u32 pll_fbd_div5f; 122 u32 pll_fbd_div1f; 123 u32 pll_fbd_2p; 124 u32 pll_enbwt; 125 u32 pll_fbd_p; 126 u32 pll_fbd_s; 127 u32 pll_pre_div1p; 128 u32 pll_pre_p; 129 u32 pll_vco_750M; 130 u32 pll_lpf_rs; 131 u32 pll_lpf_cs; 132 u32 clk_division; 133 /********for hikey620************/ 134 u32 clklp2hs_time; 135 u32 clkhs2lp_time; 136 u32 lp2hs_time; 137 u32 hs2lp_time; 138 u32 clk_to_data_delay; 139 u32 data_to_clk_delay; 140 u32 lane_byte_clk_kHz; 141 /*****************/ 142 143 /****for hikey960*****/ 144 u64 lane_byte_clk; 145 146 u32 clk_lane_lp2hs_time; 147 u32 clk_lane_hs2lp_time; 148 u32 data_lane_lp2hs_time; 149 u32 data_lane_hs2lp_time; 150 u32 clk2data_delay; 151 u32 data2clk_delay; 152 153 u32 clk_pre_delay; 154 u32 clk_post_delay; 155 u32 data_pre_delay; 156 u32 data_post_delay; 157 u32 phy_stop_wait_time; 158 u32 rg_vrefsel_vcm; 159 160 u32 rg_pll_enswc; 161 u32 rg_pll_chp; 162 163 u32 pll_register_override; /*0x1E[0]*/ 164 u32 pll_power_down; /*0x1E[1]*/ 165 u32 rg_band_sel; /*0x1E[2]*/ 166 u32 rg_phase_gen_en; /*0x1E[3]*/ 167 u32 reload_sel; /*0x1E[4]*/ 168 u32 rg_pll_cp_p; /*0x1E[7:5]*/ 169 u32 rg_pll_refsel; /*0x16[1:0]*/ 170 u32 rg_pll_cp; /*0x16[7:5]*/ 171 u32 load_command; 172 /*********/ 173 }; 174 175 struct ldi_panel_info { 176 u32 h_back_porch; 177 u32 h_front_porch; 178 u32 h_pulse_width; 179 180 /* 181 * note: vbp > 8 if used overlay compose, 182 * also lcd vbp > 8 in lcd power on sequence 183 */ 184 u32 v_back_porch; 185 u32 v_front_porch; 186 u32 v_pulse_width; 187 188 u8 hsync_plr; 189 u8 vsync_plr; 190 u8 pixelclk_plr; 191 u8 data_en_plr; 192 193 /* for cabc */ 194 u8 dpi0_overlap_size; 195 u8 dpi1_overlap_size; 196 }; 197 198 struct dw_dsi_client { 199 u32 lanes; 200 u32 phy_clock; /* in kHz */ 201 enum mipi_dsi_pixel_format format; 202 unsigned long mode_flags; 203 }; 204 205 struct dw_dsi { 206 struct drm_encoder encoder; 207 struct drm_bridge *bridge; 208 struct drm_panel *panel; 209 struct mipi_dsi_host host; 210 struct drm_connector connector; /* connector for panel */ 211 struct drm_display_mode cur_mode; 212 struct dsi_hw_ctx *ctx; 213 struct mipi_phy_params phy; 214 struct mipi_panel_info mipi; 215 struct ldi_panel_info ldi; 216 u32 lanes; 217 enum mipi_dsi_pixel_format format; 218 unsigned long mode_flags; 219 struct gpio_desc *gpio_mux; 220 struct dw_dsi_client client[OUT_MAX]; 221 enum dsi_output_client cur_client; 222 bool enable; 223 }; 224 225 struct dsi_data { 226 struct dw_dsi dsi; 227 struct dsi_hw_ctx ctx; 228 }; 229 230 enum kirin_dsi_version { 231 KIRIN620_DSI = 0, 232 KIRIN960_DSI 233 }; 234 235 /* display controller init/cleanup ops */ 236 struct kirin_dsi_ops { 237 enum kirin_dsi_version version; 238 int (*parse_dt)(struct platform_device *pdev, struct dw_dsi *dsi); 239 int (*host_init)(struct device *dev, struct dw_dsi *dsi); 240 void (*encoder_enable)(struct drm_encoder *encoder); 241 enum drm_mode_status (*encoder_valid)( 242 struct drm_encoder *encoder, 243 const struct drm_display_mode *mode); 244 }; 245 246 #ifdef CONFIG_DRM_HISI_KIRIN960 247 extern const struct kirin_dsi_ops kirin_dsi_960; 248 #endif 249 #ifdef CONFIG_DRM_HISI_KIRIN620 250 extern const struct kirin_dsi_ops kirin_dsi_620; 251 #endif 252 253 #endif /* __KIRIN_DRM_DSI_H__ */ 254