1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright (c) 2025 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VEPU580_COMMON_H__ 7 #define __VEPU580_COMMON_H__ 8 9 #include "vepu5xx_common.h" 10 11 #define VEPU580_SLICE_FIFO_LEN 32 12 #define VEPU580_OSD_ADDR_IDX_BASE 3092 13 14 typedef struct Vepu580OsdPltColor_t { 15 /* V component */ 16 RK_U32 v : 8; 17 /* U component */ 18 RK_U32 u : 8; 19 /* Y component */ 20 RK_U32 y : 8; 21 /* Alpha */ 22 RK_U32 alpha : 8; 23 } Vepu580OsdPltColor; 24 25 typedef struct Vepu580OsdPos_t { 26 /* X coordinate/16 of OSD region's left-top point. */ 27 RK_U32 osd_lt_x : 10; 28 RK_U32 reserved0 : 6; 29 /* Y coordinate/16 of OSD region's left-top point. */ 30 RK_U32 osd_lt_y : 10; 31 RK_U32 reserved1 : 6; 32 /* X coordinate/16 of OSD region's right-bottom point. */ 33 RK_U32 osd_rb_x : 10; 34 RK_U32 reserved2 : 6; 35 /* Y coordinate/16 of OSD region's right-bottom point. */ 36 RK_U32 osd_rb_y : 10; 37 RK_U32 reserved3 : 6; 38 } Vepu580OsdPos; 39 40 typedef struct Vepu580OsdReg_t { 41 /* 42 * OSD_INV_CFG 43 * Address offset: 0x00003000 Access type: read and write 44 * OSD color inverse configuration 45 */ 46 struct { 47 /* 48 * OSD color inverse enable of luma component, 49 * each bit controls corresponding region. 50 */ 51 RK_U32 osd_lu_inv_en : 8; 52 53 /* OSD color inverse enable of chroma component, 54 * each bit controls corresponding region. 55 */ 56 RK_U32 osd_ch_inv_en : 8; 57 /* 58 * OSD color inverse expression switch for luma component 59 * each bit controls corresponding region. 60 * 1'h0: Expression need to determine the condition; 61 * 1'h1: Expression don't need to determine the condition; 62 */ 63 RK_U32 osd_lu_inv_msk : 8; 64 /* 65 * OSD color inverse expression switch for chroma component 66 * each bit controls corresponding region. 67 * 1'h0: Expression need to determine the condition; 68 * 1'h1: Expression don't need to determine the condition; 69 */ 70 RK_U32 osd_ch_inv_msk : 8; 71 } reg3072; 72 73 /* 74 * OSD_INV 75 * Address offset: 0x3004 Access type: read and write 76 * OSD color inverse configuration 77 */ 78 struct { 79 /* Color inverse theshold for OSD region0. */ 80 RK_U32 osd_ithd_r0 : 4; 81 /* Color inverse theshold for OSD region1. */ 82 RK_U32 osd_ithd_r1 : 4; 83 /* Color inverse theshold for OSD region2. */ 84 RK_U32 osd_ithd_r2 : 4; 85 /* Color inverse theshold for OSD region3. */ 86 RK_U32 osd_ithd_r3 : 4; 87 /* Color inverse theshold for OSD region4. */ 88 RK_U32 osd_ithd_r4 : 4; 89 /* Color inverse theshold for OSD region5. */ 90 RK_U32 osd_ithd_r5 : 4; 91 /* Color inverse theshold for OSD region6. */ 92 RK_U32 osd_ithd_r6 : 4; 93 /* Color inverse theshold for OSD region7. */ 94 RK_U32 osd_ithd_r7 : 4; 95 } reg3073; 96 97 /* 98 * OSD_CFG 99 * Address offset: 0x3008 Access type: read and write 100 * OSD configuration 101 */ 102 struct { 103 /* OSD region enable, each bit controls corresponding OSD region. */ 104 RK_U32 osd_e : 8; 105 /* 106 * OSD color inverse expression type 107 * each bit controls corresponding region. 108 * 1'h0: AND; 109 * 1'h1: OR 110 */ 111 RK_U32 osd_itype : 8; 112 /* 113 * OSD palette clock selection. 114 * 1'h0: Configure bus clock domain. 115 * 1'h1: Core clock domain. 116 */ 117 RK_U32 osd_plt_cks : 1; 118 /* 119 * OSD palette type. 120 * 1'h1: Default type. 121 * 1'h0: User defined type. 122 */ 123 RK_U32 osd_plt_typ : 1; 124 RK_U32 reserved : 14; 125 } reg3074; 126 127 RK_U32 reserved_3075; 128 /* 129 * OSD_POS reg3076_reg3091 130 * Address offset: 0x3010~0x304c Access type: read and write 131 * OSD region position 132 */ 133 Vepu580OsdPos osd_pos[8]; 134 135 /* 136 * ADR_OSD reg3092_reg3099 137 * Address offset: 0x00003050~reg306c Access type: read and write 138 * Base address for OSD region, 16B aligned 139 */ 140 RK_U32 osd_addr[8]; 141 142 RK_U32 reserved3100_3103[4]; 143 Vepu580OsdPltColor plt_data[256]; 144 } Vepu580OsdReg; 145 146 MPP_RET vepu580_set_osd(Vepu5xxOsdCfg *cfg); 147 148 #endif /* __VEPU580_COMMON_H__ */ 149