1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __HAL_VDPU383_VP9D_H__ 7 #define __HAL_VDPU383_VP9D_H__ 8 9 #include "rk_type.h" 10 #include "vdpu383_com.h" 11 12 typedef struct Vdpu383RegVp9dParas_t { 13 /* SWREG64_H26X_PARA */ 14 RK_U32 reg64_unused_bits; 15 16 /* SWREG65_STREAM_PARAM_SET */ 17 RK_U32 reg65_strm_start_bit; 18 19 /* SWREG66_STREAM_LEN */ 20 RK_U32 reg66_stream_len; 21 22 /* SWREG67_GLOBAL_LEN */ 23 RK_U32 reg67_global_len; 24 25 /* SWREG68_HOR_STRIDE */ 26 RK_U32 reg68_hor_virstride; 27 28 /* SWREG69_RASTER_UV_HOR_STRIDE */ 29 RK_U32 reg69_raster_uv_hor_virstride; 30 31 /* SWREG70_Y_STRIDE */ 32 RK_U32 reg70_y_virstride; 33 34 /* SWREG71_SCL_Y_HOR_VIRSTRIDE */ 35 RK_U32 reg71_scl_ref_hor_virstride; 36 37 /* SWREG72_SCL_UV_HOR_VIRSTRIDE */ 38 RK_U32 reg72_scl_ref_raster_uv_hor_virstride; 39 40 /* SWREG73_SCL_Y_VIRSTRIDE */ 41 RK_U32 reg73_scl_ref_virstride; 42 43 /* SWREG74_FGS_Y_HOR_VIRSTRIDE */ 44 RK_U32 reg74_fgs_ref_hor_virstride; 45 46 RK_U32 reserve_reg75_79[5]; 47 48 /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */ 49 RK_U32 reg80_error_ref_hor_virstride; 50 51 /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */ 52 RK_U32 reg81_error_ref_raster_uv_hor_virstride; 53 54 /* SWREG82_ERROR_REF_Y_VIRSTRIDE */ 55 RK_U32 reg82_error_ref_virstride; 56 57 /* SWREG83_REF0_Y_HOR_VIRSTRIDE */ 58 RK_U32 reg83_ref0_hor_virstride; 59 60 /* SWREG84_REF0_UV_HOR_VIRSTRIDE */ 61 RK_U32 reg84_ref0_raster_uv_hor_virstride; 62 63 /* SWREG85_REF0_Y_VIRSTRIDE */ 64 RK_U32 reg85_ref0_virstride; 65 66 /* SWREG86_REF1_Y_HOR_VIRSTRIDE */ 67 RK_U32 reg86_ref1_hor_virstride; 68 69 /* SWREG87_REF1_UV_HOR_VIRSTRIDE */ 70 RK_U32 reg87_ref1_raster_uv_hor_virstride; 71 72 /* SWREG88_REF1_Y_VIRSTRIDE */ 73 RK_U32 reg88_ref1_virstride; 74 75 /* SWREG89_REF2_Y_HOR_VIRSTRIDE */ 76 RK_U32 reg89_ref2_hor_virstride; 77 78 /* SWREG90_REF2_UV_HOR_VIRSTRIDE */ 79 RK_U32 reg90_ref2_raster_uv_hor_virstride; 80 81 /* SWREG91_REF2_Y_VIRSTRIDE */ 82 RK_U32 reg91_ref2_virstride; 83 84 /* SWREG92_REF3_Y_HOR_VIRSTRIDE */ 85 RK_U32 reg92_ref3_hor_virstride; 86 87 /* SWREG93_REF3_UV_HOR_VIRSTRIDE */ 88 RK_U32 reg93_ref3_raster_uv_hor_virstride; 89 90 /* SWREG94_REF3_Y_VIRSTRIDE */ 91 RK_U32 reg94_ref3_virstride; 92 93 /* SWREG95_REF4_Y_HOR_VIRSTRIDE */ 94 RK_U32 reg95_ref4_hor_virstride; 95 96 /* SWREG96_REF4_UV_HOR_VIRSTRIDE */ 97 RK_U32 reg96_ref4_raster_uv_hor_virstride; 98 99 /* SWREG97_REF4_Y_VIRSTRIDE */ 100 RK_U32 reg97_ref4_virstride; 101 102 /* SWREG98_REF5_Y_HOR_VIRSTRIDE */ 103 RK_U32 reg98_ref5_hor_virstride; 104 105 /* SWREG99_REF5_UV_HOR_VIRSTRIDE */ 106 RK_U32 reg99_ref5_raster_uv_hor_virstride; 107 108 /* SWREG100_REF5_Y_VIRSTRIDE */ 109 RK_U32 reg100_ref5_virstride; 110 111 /* SWREG101_REF6_Y_HOR_VIRSTRIDE */ 112 RK_U32 reg101_ref6_hor_virstride; 113 114 /* SWREG102_REF6_UV_HOR_VIRSTRIDE */ 115 RK_U32 reg102_ref6_raster_uv_hor_virstride; 116 117 /* SWREG103_REF6_Y_VIRSTRIDE */ 118 RK_U32 reg103_ref6_virstride; 119 120 /* SWREG104_REF7_Y_HOR_VIRSTRIDE */ 121 RK_U32 reg104_ref7_hor_virstride; 122 123 /* SWREG105_REF7_UV_HOR_VIRSTRIDE */ 124 RK_U32 reg105_ref7_raster_uv_hor_virstride; 125 126 /* SWREG106_REF7_Y_VIRSTRIDE */ 127 RK_U32 reg106_ref7_virstride; 128 129 } Vdpu383RegVp9dParas; 130 131 132 typedef struct Vdpu383RegVp9dAddr_t { 133 /* SWREG168_DECOUT_BASE */ 134 RK_U32 reg168_decout_base; 135 136 /* SWREG169_ERROR_REF_BASE */ 137 RK_U32 reg169_error_ref_base; 138 139 /* SWREG170_185_REF0_BASE */ 140 union { 141 RK_U32 reg170_185_ref_base[16]; 142 struct { 143 RK_U32 reg170_180[11]; 144 RK_U32 reg181_segidlast_base; 145 RK_U32 reg182_segidcur_base; 146 RK_U32 reg183_kfprob_base; 147 RK_U32 reg184_lastprob_base; 148 RK_U32 reg185_updateprob_base; 149 }; 150 }; 151 152 RK_U32 reserve_reg186_191[6]; 153 154 /* SWREG192_PAYLOAD_ST_CUR_BASE */ 155 RK_U32 reg192_payload_st_cur_base; 156 157 /* SWREG193_FBC_PAYLOAD_OFFSET */ 158 RK_U32 reg193_fbc_payload_offset; 159 160 /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */ 161 RK_U32 reg194_payload_st_error_ref_base; 162 163 /* SWREG195_210_PAYLOAD_ST_REF0_BASE */ 164 RK_U32 reg195_210_payload_st_ref_base[16]; 165 166 RK_U32 reserve_reg211_215[5]; 167 168 /* SWREG216_COLMV_CUR_BASE */ 169 RK_U32 reg216_colmv_cur_base; 170 171 /* SWREG217_232_COLMV_REF0_BASE */ 172 RK_U32 reg217_232_colmv_ref_base[16]; 173 174 } Vdpu383RegVp9dAddr; 175 176 typedef struct Vdpu383Vp9dRegSet_t { 177 Vdpu383RegVersion reg_version; /* 0 */ 178 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ 179 Vdpu383RegCommonAddr common_addr; /* 128-134, 140-161 */ 180 Vdpu383RegVp9dParas vp9d_paras; /* 64-74, 80-106 */ 181 Vdpu383RegVp9dAddr vp9d_addrs; /* 168-185, 192-210, 216-232 */ 182 } Vdpu383Vp9dRegSet; 183 184 #endif /* __HAL_VDPU383_VP9D_H__ */