1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VDPU383_AV1D_H__ 7 #define __VDPU383_AV1D_H__ 8 9 #include "rk_type.h" 10 #include "vdpu383_com.h" 11 12 13 typedef struct Vdpu383RegAv1dParas_t { 14 /* SWREG64_AV1_PARA */ 15 RK_U32 reg64_unused_bits; 16 17 /* SWREG65_STREAM_PARAM_SET */ 18 RK_U32 reg65_strm_start_bit; 19 20 /* SWREG66_STREAM_LEN */ 21 RK_U32 reg66_stream_len; 22 23 /* SWREG67_GLOBAL_LEN */ 24 RK_U32 reg67_global_len; 25 26 /* SWREG68_HOR_STRIDE */ 27 RK_U32 reg68_hor_virstride; 28 29 /* SWREG69_RASTER_UV_HOR_STRIDE */ 30 RK_U32 reg69_raster_uv_hor_virstride; 31 32 /* SWREG70_Y_STRIDE */ 33 RK_U32 reg70_y_virstride; 34 35 /* SWREG71_SCL_Y_HOR_VIRSTRIDE */ 36 RK_U32 reg71_scl_ref_hor_virstride; 37 38 /* SWREG72_SCL_UV_HOR_VIRSTRIDE */ 39 RK_U32 reg72_scl_ref_raster_uv_hor_virstride; 40 41 /* SWREG73_SCL_Y_VIRSTRIDE */ 42 RK_U32 reg73_scl_ref_virstride; 43 44 /* SWREG74_FGS_Y_HOR_VIRSTRIDE */ 45 RK_U32 reg74_fgs_ref_hor_virstride; 46 47 RK_U32 reserve_reg75_79[5]; 48 49 /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */ 50 RK_U32 reg80_error_ref_hor_virstride; 51 52 /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */ 53 RK_U32 reg81_error_ref_raster_uv_hor_virstride; 54 55 /* SWREG82_ERROR_REF_Y_VIRSTRIDE */ 56 RK_U32 reg82_error_ref_virstride; 57 58 /* SWREG83_REF0_Y_HOR_VIRSTRIDE */ 59 RK_U32 reg83_ref0_hor_virstride; 60 61 /* SWREG84_REF0_UV_HOR_VIRSTRIDE */ 62 RK_U32 reg84_ref0_raster_uv_hor_virstride; 63 64 /* SWREG85_REF0_Y_VIRSTRIDE */ 65 RK_U32 reg85_ref0_virstride; 66 67 /* SWREG86_REF1_Y_HOR_VIRSTRIDE */ 68 RK_U32 reg86_ref1_hor_virstride; 69 70 /* SWREG87_REF1_UV_HOR_VIRSTRIDE */ 71 RK_U32 reg87_ref1_raster_uv_hor_virstride; 72 73 /* SWREG88_REF1_Y_VIRSTRIDE */ 74 RK_U32 reg88_ref1_virstride; 75 76 /* SWREG89_REF2_Y_HOR_VIRSTRIDE */ 77 RK_U32 reg89_ref2_hor_virstride; 78 79 /* SWREG90_REF2_UV_HOR_VIRSTRIDE */ 80 RK_U32 reg90_ref2_raster_uv_hor_virstride; 81 82 /* SWREG91_REF2_Y_VIRSTRIDE */ 83 RK_U32 reg91_ref2_virstride; 84 85 /* SWREG92_REF3_Y_HOR_VIRSTRIDE */ 86 RK_U32 reg92_ref3_hor_virstride; 87 88 /* SWREG93_REF3_UV_HOR_VIRSTRIDE */ 89 RK_U32 reg93_ref3_raster_uv_hor_virstride; 90 91 /* SWREG94_REF3_Y_VIRSTRIDE */ 92 RK_U32 reg94_ref3_virstride; 93 94 /* SWREG95_REF4_Y_HOR_VIRSTRIDE */ 95 RK_U32 reg95_ref4_hor_virstride; 96 97 /* SWREG96_REF4_UV_HOR_VIRSTRIDE */ 98 RK_U32 reg96_ref4_raster_uv_hor_virstride; 99 100 /* SWREG97_REF4_Y_VIRSTRIDE */ 101 RK_U32 reg97_ref4_virstride; 102 103 /* SWREG98_REF5_Y_HOR_VIRSTRIDE */ 104 RK_U32 reg98_ref5_hor_virstride; 105 106 /* SWREG99_REF5_UV_HOR_VIRSTRIDE */ 107 RK_U32 reg99_ref5_raster_uv_hor_virstride; 108 109 /* SWREG100_REF5_Y_VIRSTRIDE */ 110 RK_U32 reg100_ref5_virstride; 111 112 /* SWREG101_REF6_Y_HOR_VIRSTRIDE */ 113 RK_U32 reg101_ref6_hor_virstride; 114 115 /* SWREG102_REF6_UV_HOR_VIRSTRIDE */ 116 RK_U32 reg102_ref6_raster_uv_hor_virstride; 117 118 /* SWREG103_REF6_Y_VIRSTRIDE */ 119 RK_U32 reg103_ref6_virstride; 120 121 /* SWREG104_REF7_Y_HOR_VIRSTRIDE */ 122 RK_U32 reg104_ref7_hor_virstride; 123 124 /* SWREG105_REF7_UV_HOR_VIRSTRIDE */ 125 RK_U32 reg105_ref7_raster_uv_hor_virstride; 126 127 /* SWREG106_REF7_Y_VIRSTRIDE */ 128 RK_U32 reg106_ref7_virstride; 129 130 } Vdpu383RegAv1dParas; 131 132 typedef struct Vdpu383RegAv1dAddr_t { 133 /* SWREG168_DECOUT_BASE */ 134 RK_U32 reg168_decout_base; 135 136 /* SWREG169_ERROR_REF_BASE */ 137 RK_U32 reg169_error_ref_base; 138 139 /* SWREG170_REF0_BASE */ 140 // RK_U32 reg170_refer0_base; 141 RK_U32 reg170_av1_last_base; 142 143 /* SWREG171_REF1_BASE */ 144 // RK_U32 reg171_refer1_base; 145 RK_U32 reg171_av1golden_base; 146 147 /* SWREG172_REF2_BASE */ 148 // RK_U32 reg172_refer2_base; 149 RK_U32 reg172_av1alfter_base; 150 151 /* SWREG173_REF3_BASE */ 152 RK_U32 reg173_refer3_base; 153 154 /* SWREG174_REF4_BASE */ 155 RK_U32 reg174_refer4_base; 156 157 /* SWREG175_REF5_BASE */ 158 RK_U32 reg175_refer5_base; 159 160 /* SWREG176_REF6_BASE */ 161 RK_U32 reg176_refer6_base; 162 163 /* SWREG177_REF7_BASE */ 164 RK_U32 reg177_refer7_base; 165 166 /* SWREG178_H26X_REF8_BASE */ 167 // RK_U32 reg178_refer8_base; 168 RK_U32 reg178_av1_coef_rd_base; 169 170 /* SWREG179_H26X_REF9_BASE */ 171 // RK_U32 reg179_refer9_base; 172 RK_U32 reg179_av1_coef_wr_base; 173 174 /* SWREG180_H26X_REF10_BASE */ 175 RK_U32 reg180_refer10_base; 176 177 /* SWREG181_H26X_REF11_BASE */ 178 RK_U32 reg181_av1_rd_segid_base; 179 180 /* SWREG182_H26X_REF12_BASE */ 181 RK_U32 reg182_av1_wr_segid_base; 182 183 /* SWREG183_H26X_REF13_BASE */ 184 RK_U32 reg183_kf_prob_base; 185 186 /* SWREG184_H26X_REF14_BASE */ 187 RK_U32 reg184_av1_noncoef_rd_base; 188 189 /* SWREG185_H26X_REF15_BASE */ 190 RK_U32 reg185_av1_noncoef_wr_base; 191 192 RK_U32 reserve_reg186_191[6]; 193 194 /* SWREG192_PAYLOAD_ST_CUR_BASE */ 195 RK_U32 reg192_payload_st_cur_base; 196 197 /* SWREG193_FBC_PAYLOAD_OFFSET */ 198 RK_U32 reg193_fbc_payload_offset; 199 200 /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */ 201 RK_U32 reg194_payload_st_error_ref_base; 202 203 /* SWREG195_PAYLOAD_ST_REF0_BASE */ 204 RK_U32 reg195_payload_st_ref0_base; 205 206 /* SWREG196_PAYLOAD_ST_REF1_BASE */ 207 RK_U32 reg196_payload_st_ref1_base; 208 209 /* SWREG197_PAYLOAD_ST_REF2_BASE */ 210 RK_U32 reg197_payload_st_ref2_base; 211 212 /* SWREG198_PAYLOAD_ST_REF3_BASE */ 213 RK_U32 reg198_payload_st_ref3_base; 214 215 /* SWREG199_PAYLOAD_ST_REF4_BASE */ 216 RK_U32 reg199_payload_st_ref4_base; 217 218 /* SWREG200_PAYLOAD_ST_REF5_BASE */ 219 RK_U32 reg200_payload_st_ref5_base; 220 221 /* SWREG201_PAYLOAD_ST_REF6_BASE */ 222 RK_U32 reg201_payload_st_ref6_base; 223 224 /* SWREG202_PAYLOAD_ST_REF7_BASE */ 225 RK_U32 reg202_payload_st_ref7_base; 226 227 /* SWREG203_PAYLOAD_ST_REF8_BASE */ 228 RK_U32 reg203_payload_st_ref8_base; 229 230 /* SWREG204_PAYLOAD_ST_REF9_BASE */ 231 RK_U32 reg204_payload_st_ref9_base; 232 233 /* SWREG205_PAYLOAD_ST_REF10_BASE */ 234 RK_U32 reg205_payload_st_ref10_base; 235 236 /* SWREG206_PAYLOAD_ST_REF11_BASE */ 237 RK_U32 reg206_payload_st_ref11_base; 238 239 /* SWREG207_PAYLOAD_ST_REF12_BASE */ 240 RK_U32 reg207_payload_st_ref12_base; 241 242 /* SWREG208_PAYLOAD_ST_REF13_BASE */ 243 RK_U32 reg208_payload_st_ref13_base; 244 245 /* SWREG209_PAYLOAD_ST_REF14_BASE */ 246 RK_U32 reg209_payload_st_ref14_base; 247 248 /* SWREG210_PAYLOAD_ST_REF15_BASE */ 249 RK_U32 reg210_payload_st_ref15_base; 250 251 RK_U32 reserve_reg211_215[5]; 252 253 /* SWREG216_COLMV_CUR_BASE */ 254 RK_U32 reg216_colmv_cur_base; 255 256 /* SWREG217_232_COLMV_REF0_BASE */ 257 RK_U32 reg217_232_colmv_ref_base[16]; 258 } Vdpu383RegAv1dAddr; 259 260 typedef struct Vdpu383Av1dRegSet_t { 261 Vdpu383RegVersion reg_version; 262 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ 263 Vdpu383RegCommonAddr common_addr; /* 128-134, 140-161 */ 264 Vdpu383RegAv1dParas av1d_paras; /* 64-106 */ 265 Vdpu383RegAv1dAddr av1d_addrs; /* 168-185(ref) */ 266 /* 192-210(fbc) */ 267 /* 216-232(col mv) */ 268 } Vdpu383Av1dRegSet; 269 270 #endif /* __VDPU383_AV1D_H__ */ 271