1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H264E_VEPU541_REG_H__ 18 #define __HAL_H264E_VEPU541_REG_H__ 19 20 #include "vepu541_common.h" 21 22 typedef struct Vepu541H264eRegSet_t { 23 /* 24 * VERSION 25 * Address: 0x0000 Access type: read only 26 * VEPU version. It contains IP function summary and sub-version informations. 27 */ 28 struct { 29 /* Sub-version(version 1.1) */ 30 RK_U32 sub_ver : 8; 31 /* Support H.264 encoding */ 32 RK_U32 h264_enc : 1; 33 /* Support HEVC encoding */ 34 RK_U32 h265_enc : 1; 35 RK_U32 reserved0 : 2; 36 /* 37 * The maximum resolution supported 38 * 4'd0: 4096x2304 pixels; 39 * 4'd1: 1920x1088 pixels; 40 * others: reserved 41 */ 42 RK_U32 pic_size : 4; 43 /* 44 * OSD capability. 45 * 2'd0: 8-area OSD, with 256-color palette 46 * 2'd3: no OSD 47 * others: reserved 48 */ 49 RK_U32 osd_cap : 2; 50 /* 51 * pre-process filter capability 52 * 2'd0: basic pre-process filter 53 * 2'd3: no pre-process filter 54 * others: reserved 55 */ 56 RK_U32 filtr_cap : 2; 57 /* B frame encoding capability */ 58 RK_U32 bfrm_cap : 1; 59 /* frame buffer compress capability */ 60 RK_U32 fbc_cap : 1; 61 RK_U32 reserved1 : 2; 62 /* IP indentifier for RKVENC default: 0x50 */ 63 RK_U32 rkvenc_ver : 8; 64 } reg000; 65 66 /* 67 * ENC_STRT 68 * Address: 0x0004 Access type: read and write/write only 69 * Start cmd register.(auto clock gating enable, auto reset enable and 70 * tmvp adjust enable when frame done are also allocated here.) 71 */ 72 struct { 73 /* 74 * Number of new nodes in link table. 75 * It's valid only when rkvenc_cmd is 2 or 3. 76 */ 77 RK_U32 lkt_num : 8; 78 /* 79 * Rockchip video encoder command: 80 * 2'd0: N/A 81 * 2'd1: one frame encode by register configuration 82 * 2'd2: multi-frame encode start with link table 83 * 2'd3: multi_frame_encode link table update 84 */ 85 RK_U32 rkvenc_cmd : 2; 86 RK_U32 reserved0 : 6; 87 /* RKVENC encoder clock gating enable */ 88 RK_U32 clk_gate_en : 1; 89 /* auto reset core clock domain when frame finished */ 90 RK_U32 resetn_hw_en : 1; 91 /* wait tmvp write done by dma */ 92 RK_U32 enc_done_tmvp_en : 1; 93 RK_U32 reserved1 : 13; 94 } reg001; 95 96 /* 97 * ENC_CLR 98 * Address offset: 0x0008 Access type: read and write 99 * ENC_CLR.safe_clr only clears RKVENC DMA and confirms the integrity of 100 * AXI transactions. To execute the global reset of RKVENC, user needs to 101 * configure SOC CRU register which controls RKVENC's asynchronous reset 102 */ 103 struct { 104 /* 105 * Safe clear. This filed only clears DMA module to confirm the 106 * integrity of AXI transactions 107 */ 108 RK_U32 safe_clr : 1; 109 /* 110 * Force clear. Clear all the sub modules besides regfile and AHB data 111 * path. 112 */ 113 RK_U32 force_clr : 1; 114 RK_U32 reserved : 30; 115 } reg002; 116 117 /* 118 * LKT_ADDR 119 * Address offset: 0x000c Access type: read and write 120 * Link table 121 */ 122 struct { 123 /* 124 * High 28 bits of the address for the first node in current link table 125 * (16bytes aligned) 126 */ 127 RK_U32 lkt_addr : 32; 128 } reg003; 129 130 /* 131 * INT_EN 132 * Address offset: 0x0010 Access type: read and write 133 * VEPU interrupt enable 134 */ 135 struct { 136 /* One frame encode finish interrupt enable */ 137 RK_U32 enc_done_en : 1; 138 /* Link table finish interrupt enable */ 139 RK_U32 lkt_done_en : 1; 140 /* Safe clear finish interrupt enable */ 141 RK_U32 sclr_done_en : 1; 142 /* Safe clear finish interrupt enable */ 143 RK_U32 enc_slice_done_en : 1; 144 /* Bit stream overflow interrupt enable */ 145 RK_U32 oflw_done_en : 1; 146 /* AXI write response fifo full interrupt enable */ 147 RK_U32 brsp_done_en : 1; 148 /* AXI write response channel error interrupt enable */ 149 RK_U32 berr_done_en : 1; 150 /* AXI read channel error interrupt enable */ 151 RK_U32 rerr_done_en : 1; 152 /* timeout error interrupt enable */ 153 RK_U32 wdg_done_en : 1; 154 RK_U32 reserved : 23; 155 } reg004; 156 157 /* 158 * INT_MSK 159 * Address offset: 0x0014 Access type: read and write 160 * VEPU interrupt mask 161 */ 162 struct { 163 /* One frame encode finish interrupt mask */ 164 RK_U32 enc_done_msk : 1; 165 /* Link table finish interrupt mask */ 166 RK_U32 lkt_done_msk : 1; 167 /* Safe clear finish interrupt mask */ 168 RK_U32 sclr_done_msk : 1; 169 /* Safe clear finish interrupt mask */ 170 RK_U32 enc_slice_done_msk : 1; 171 /* Bit stream overflow interrupt mask */ 172 RK_U32 oflw_done_msk : 1; 173 /* AXI write response fifo full interrupt mask */ 174 RK_U32 brsp_done_msk : 1; 175 /* AXI write response channel error interrupt mask */ 176 RK_U32 berr_done_msk : 1; 177 /* AXI read channel error interrupt mask */ 178 RK_U32 rerr_done_msk : 1; 179 /* timeout error interrupt mask */ 180 RK_U32 wdg_done_msk : 1; 181 RK_U32 reserved : 23; 182 } reg005; 183 184 /* 185 * INT_CLR 186 * Address offset: 0x0018 Access type: read and write, write one to clear 187 * VEPU interrupt clear 188 */ 189 struct { 190 /* One frame encode finish interrupt clear */ 191 RK_U32 enc_done_clr : 1; 192 /* Link table finish interrupt clear */ 193 RK_U32 lkt_done_clr : 1; 194 /* Safe clear finish interrupt clear */ 195 RK_U32 sclr_done_clr : 1; 196 /* One slice encode finish interrupt clear */ 197 RK_U32 enc_slice_done_clr : 1; 198 /* Bit stream overflow interrupt clear */ 199 RK_U32 oflw_done_clr : 1; 200 /* AXI write response fifo full interrupt clear */ 201 RK_U32 brsp_done_clr : 1; 202 /* AXI write response channel error interrupt clear */ 203 RK_U32 berr_done_clr : 1; 204 /* AXI read channel error interrupt clear */ 205 RK_U32 rerr_done_clr : 1; 206 /* timeout error interrupt clear */ 207 RK_U32 wdg_done_clr : 1; 208 RK_U32 reserved : 23; 209 } reg006; 210 211 /* 212 * INT_STA 213 * Address offset: 0x001c Access type: read and write, write one to clear 214 * VEPU interrupt status 215 */ 216 struct { 217 /* One frame encode finish interrupt status */ 218 RK_U32 enc_done_sta : 1; 219 /* Link table finish interrupt status */ 220 RK_U32 lkt_done_sta : 1; 221 /* Safe clear finish interrupt status */ 222 RK_U32 sclr_done_sta : 1; 223 /* One slice encode finish interrupt status */ 224 RK_U32 enc_slice_done_sta : 1; 225 /* Bit stream overflow interrupt status */ 226 RK_U32 oflw_done_sta : 1; 227 /* AXI write response fifo full interrupt status */ 228 RK_U32 brsp_done_sta : 1; 229 /* AXI write response channel error interrupt status */ 230 RK_U32 berr_done_sta : 1; 231 /* AXI read channel error interrupt status */ 232 RK_U32 rerr_done_sta : 1; 233 /* timeout error interrupt status */ 234 RK_U32 wdg_done_sta : 1; 235 RK_U32 reserved : 23; 236 } reg007; 237 238 /* reg gap 008~011 */ 239 RK_U32 reg_008_011[4]; 240 241 /* 242 * ENC_RSL 243 * Address offset: 0x0030 Access type: read and write 244 * Resolution 245 */ 246 struct { 247 /* ceil(picture width/8) - 1 */ 248 RK_U32 pic_wd8_m1 : 9; 249 RK_U32 reserved0 : 1; 250 /* filling pixels to maintain picture width 8 pixels aligned */ 251 RK_U32 pic_wfill : 6; 252 /* Ceil(picture_height/8)-1 */ 253 RK_U32 pic_hd8_m1 : 9; 254 RK_U32 reserved1 : 1; 255 /* Filling pixels to maintain picture height 8 pixels aligned */ 256 RK_U32 pic_hfill : 6; 257 } reg012; 258 259 /* 260 * ENC_PIC 261 * Address offset: 0x0034 Access type: read and write 262 * VEPU common configuration 263 */ 264 struct { 265 /* Video standard: 0->H.264; 1->HEVC */ 266 RK_U32 enc_stnd : 1; 267 /* ROI encode enable */ 268 RK_U32 roi_enc : 1; 269 /* Current frame should be refered in future */ 270 RK_U32 cur_frm_ref : 1; 271 /* Output ME information */ 272 RK_U32 mei_stor : 1; 273 /* Output start code prefix */ 274 RK_U32 bs_scp : 1; 275 /* 0: select table A, 1: select table B */ 276 RK_U32 lamb_mod_sel : 1; 277 RK_U32 reserved0 : 2; 278 /* QP value for current frame encoding */ 279 RK_U32 pic_qp : 6; 280 /* sum of reference pictures (indexed by difference POCs), HEVC only */ 281 RK_U32 tot_poc_num : 5; 282 /* bit width to express the maximum ctu number in current picure, HEVC only */ 283 RK_U32 log2_ctu_num : 4; 284 /* 1'h0: Select atr_thd group 1'h1: Select atr_thd group1 */ 285 RK_U32 atr_thd_sel : 1; 286 /* Dual-core handshake Rx ID. */ 287 RK_U32 dchs_rxid : 2; 288 /* Dual-core handshake tx ID. */ 289 RK_U32 dchs_txid : 2; 290 /* Dual-core handshake rx enable. */ 291 RK_U32 dchs_rxe : 1; 292 /* RDO intra-prediction satd path bypass enable. */ 293 RK_U32 satd_byps_en : 1; 294 /* Slice length fifo enable. */ 295 RK_U32 slen_fifo : 1; 296 /* Node interrupt enable (only for link table node configuration). */ 297 RK_U32 node_int : 1; 298 } reg013; 299 300 /* 301 * ENC_WDG 302 * Address offset: 0x0038 Access type: read and write 303 * VEPU watch dog configure register 304 */ 305 struct { 306 /* 307 * Video source loading timeout threshold. 308 * 24'h0: No time limit 309 * 24'hx: x*256 core clock cycles 310 */ 311 RK_U32 vs_load_thd : 24; 312 /* 313 * Reference picture loading timeout threshold. 314 * 8'h0: No time limit 315 * 8'hx: x*256 core clock cycles 316 */ 317 RK_U32 rfp_load_thrd : 8; 318 } reg014; 319 320 /* 321 * DTRNS_MAP 322 * Address offset: 0x003c Access type: read and write 323 * Data transaction mapping (endian and order) 324 */ 325 struct { 326 /* swap the position of 64bits in 128bits for lpf write data between tiles */ 327 RK_U32 lpfw_bus_ordr : 1; 328 /* Swap the position of 64 bits in 128 bits for co-located Mv(HEVC only). */ 329 RK_U32 cmvw_bus_ordr : 1; 330 /* Swap the position of 64 bits in 128 bits for down-sampled picture. */ 331 RK_U32 dspw_bus_ordr : 1; 332 /* Swap the position of 64 bits in 128 bits for reference picture. */ 333 RK_U32 rfpw_bus_ordr : 1; 334 /* 335 * Data swap for video source loading channel. 336 * [3]: Swap 64 bits in 128 bits 337 * [2]: Swap 32 bits in 64 bits 338 * [1]: Swap 16 bits in 32 bits 339 * [0]: Swap 8 bits in 16 bits 340 */ 341 RK_U32 src_bus_edin : 4; 342 /* 343 * Data swap for ME information write channel. 344 * [3]: Swap 64 bits in 128 bits 345 * [2]: Swap 32 bits in 64 bits 346 * [1]: Swap 16 bits in 32 bits 347 * [0]: Swap 8 bits in 16 bits 348 */ 349 RK_U32 meiw_bus_edin : 4; 350 /* 351 * Data swap for bis stream write channel. 352 * [2]: Swap 32 bits in 64 bits 353 * [1]: Swap 16 bits in 32 bits 354 * [0]: Swap 8 bits in 16 bits 355 */ 356 RK_U32 bsw_bus_edin : 3; 357 /* 358 * Data swap for link table read channel. 359 * [3]: Swap 64 bits in 128 bits 360 * [2]: Swap 32 bits in 64 bits 361 * [1]: Swap 16 bits in 32 bits 362 * [0]: Swap 8 bits in 16 bits 363 */ 364 RK_U32 lktr_bus_edin : 4; 365 /* 366 * Data swap for ROI configuration read channel. 367 * [3]: Swap 64 bits in 128 bits 368 * [2]: Swap 32 bits in 64 bits 369 * [1]: Swap 16 bits in 32 bits 370 * [0]: Swap 8 bits in 16 bits 371 */ 372 RK_U32 roir_bus_edin : 4; 373 /* 374 * Data swap for link table write channel. 375 * [3]: Swap 64 bits in 128 bits 376 * [2]: Swap 32 bits in 64 bits 377 * [1]: Swap 16 bits in 32 bits 378 * [0]: Swap 8 bits in 16 bits 379 */ 380 RK_U32 lktw_bus_edin : 4; 381 /* 382 * AFBC video source loading burst size. 383 * 1'h0: 32 bytes 384 * 1'h1: 64 bytes 385 */ 386 RK_U32 afbc_bsize : 1; 387 RK_U32 reserved1 : 4; 388 } reg015; 389 390 /* 391 * DTRNS_CFG 392 * Address offset: 0x0040 Access type: read and write 393 * (AXI bus) Data transaction configuration 394 */ 395 union { 396 struct vepu541_t { 397 /* 398 * AXI write response channel check enable. 399 * [6]: Reconstructed picture write response check enable. 400 * [5]: ME information write response check enable. 401 * [4]: CTU information write response check enable. 402 * [3]: Down-sampled picture write response check enable. 403 * [2]: Bit stream write response check enable. 404 * [1]: Link table mode write reponse check enable. 405 * [0]: Reserved for video preprocess. 406 */ 407 RK_U32 axi_brsp_cke : 7; 408 /* 409 * Down sampled reference picture read outstanding enable. 410 * 1'h0: No outstanding 411 * 1'h1: Outstanding read, which improves data transaction efficiency, 412 * but core clock frequency should not lower than bus clock frequency. 413 */ 414 RK_U32 dspr_otsd : 1; 415 RK_U32 reserved : 24; 416 } vepu541; 417 418 struct vepu540_t { 419 RK_U32 reserved0 : 7; 420 /* 421 * Down sampled reference picture read outstanding enable. 422 * 1'h0: No outstanding 423 * 1'h1: Outstanding read, which improves data transaction efficiency, 424 * but core clock frequency should not lower than bus clock frequency. 425 */ 426 RK_U32 dspr_otsd : 1; 427 RK_U32 reserved1 : 8; 428 /* 429 * AXI write response channel check enable. 430 * [7]: lpf write response check enable 431 * [6]: Reconstructed picture write response check enable. 432 * [5]: ME information write response check enable. 433 * [4]: CTU information write response check enable. 434 * [3]: Down-sampled picture write response check enable. 435 * [2]: Bit stream write response check enable. 436 * [1]: Link table mode write reponse check enable. 437 * [0]: Reserved for video preprocess. 438 */ 439 RK_U32 axi_brsp_cke : 8; 440 RK_U32 reserved2 : 8; 441 } vepu540; 442 } reg016; 443 444 /* 445 * SRC_FMT 446 * Address offset: 0x0044 Access type: read and write 447 * Video source format 448 */ 449 struct { 450 /* 451 * Swap the position of alpha and RGB for ARBG8888. 452 * 1'h0: BGRA8888 or RGBA8888. 453 * 1'h1: ABGR8888 or ARGB8888. 454 */ 455 RK_U32 alpha_swap : 1; 456 /* 457 * Swap the position of R and B for BGRA8888, RGB888, RGB 656 format; 458 * Swap the position of U and V for YUV422-SP, YUV420-SP, YUYV422 and UYUV422 format. 459 * 1'h0: RGB or YUYV or UYVY. 460 * 1'h1: BGR or YVYU or VYUY. 461 */ 462 RK_U32 rbuv_swap : 1; 463 /* 464 * Video source color format. 465 * 4'h0: BGRA8888 466 * 4'h1: RGB888 467 * 4'h2: RGB565 468 * 4'h4: YUV422 SP 469 * 4'h5: YUV422 P 470 * 4'h6: YUV420 SP 471 * 4'h7: YUV420 P 472 * 4'h8: YUYV422 473 * 4'h9: UYVY422 474 * Others: Reserved 475 */ 476 RK_U32 src_cfmt : 4; 477 /* 478 * Video source clip (low active). 479 * 1'h0: [16:235] for luma and [16:240] for chroma. 480 * 1'h1: [0:255] for both luma and chroma. 481 */ 482 RK_U32 src_range : 1; 483 /* 484 * Ourput reconstructed frame format 485 * 1'h0: yuv420 486 * 1'h1: yuv400 487 */ 488 RK_U32 out_fmt_cfg : 1; 489 RK_U32 reserved : 24; 490 } reg017; 491 492 /* 493 * SRC_UDFY 494 * Address offset: 0x0048 Access type: read and write 495 * Weight of user defined formula for RBG to Y conversion 496 */ 497 struct { 498 /* Weight of BLUE in RBG to Y conversion formula. */ 499 RK_U32 csc_wgt_b2y : 9; 500 /* Weight of GREEN in RBG to Y conversion formula. */ 501 RK_U32 csc_wgt_g2y : 9; 502 /* Weight of RED in RBG to Y conversion formula. */ 503 RK_U32 csc_wgt_r2y : 9; 504 RK_U32 reserved : 5; 505 } reg018; 506 507 /* 508 * SRC_UDFU 509 * Address offset: 0x004c Access type: read and write 510 * Weight of user defined formula for RBG to U conversion 511 */ 512 struct { 513 /* Weight of BLUE in RBG to U conversion formula. */ 514 RK_U32 csc_wgt_b2u : 9; 515 /* Weight of GREEN in RBG to U conversion formula. */ 516 RK_U32 csc_wgt_g2u : 9; 517 /* Weight of RED in RBG to U conversion formula. */ 518 RK_U32 csc_wgt_r2u : 9; 519 RK_U32 reserved : 5; 520 } reg019; 521 522 /* 523 * SRC_UDFV 524 * Address offset: 0x0050 Access type: read and write 525 * Weight of user defined formula for RBG to V conversion 526 */ 527 struct { 528 /* Weight of BLUE in RBG to V conversion formula. */ 529 RK_U32 csc_wgt_b2v : 9; 530 /* Weight of GREEN in RBG to V conversion formula. */ 531 RK_U32 csc_wgt_g2v : 9; 532 /* Weight of RED in RBG to V conversion formula. */ 533 RK_U32 csc_wgt_r2v : 9; 534 RK_U32 reserved : 5; 535 } reg020; 536 537 /* 538 * SRC_UDFO 539 * Address offset: 0x0054 Access type: read and write 540 * Offset of user defined formula for RBG to YUV conversion 541 */ 542 struct { 543 /* Offset of RBG to V conversion formula. */ 544 RK_U32 csc_ofst_v : 8; 545 /* Offset of RBG to U conversion formula. */ 546 RK_U32 csc_ofst_u : 8; 547 /* Offset of RBG to Y conversion formula. */ 548 RK_U32 csc_ofst_y : 5; 549 RK_U32 reserved : 11; 550 } reg021; 551 552 /* 553 * SRC_PROC 554 * Address offset: 0x0058 Access type: read and write 555 * Video source process 556 */ 557 struct { 558 RK_U32 reserved0 : 26; 559 /* Video source mirror mode enable. */ 560 RK_U32 src_mirr : 1; 561 /* 562 * Video source rotation mode. 563 * 2'h0: 0 degree 564 * 2'h1: Clockwise 90 degree 565 * 2'h2: Clockwise 180 degree 566 * 2'h3: Clockwise 280 degree 567 */ 568 RK_U32 src_rot : 2; 569 /* Video source texture analysis enable. */ 570 RK_U32 txa_en : 1; 571 /* AFBC decompress enable (for AFBC format video source). */ 572 RK_U32 afbcd_en : 1; 573 RK_U32 reserved1 : 1; 574 } reg022; 575 576 /* 577 * SLI_CFG_H264 578 * Address offset: 0x005C Access type: read and write 579 * Slice cross lines configuration, h264 only. 580 */ 581 struct { 582 RK_U32 reserved0 : 31; 583 /* 584 * Slice cut cross lines enable, 585 * using for breaking the resolution limit, h264 only. 586 */ 587 RK_U32 sli_crs_en : 1; 588 } reg023; 589 590 /* reg gap 024 */ 591 RK_U32 reg_024; 592 593 /* 594 * KLUT_OFST 595 * Address offset: 0x0064 Access type: read and write 596 * Offset of (RDO) chroma cost weight table 597 */ 598 struct { 599 /* Offset of (RDO) chroma cost weight table, values from 0 to 6. */ 600 RK_U32 chrm_klut_ofst : 3; 601 RK_U32 reserved : 1; 602 } reg025; 603 604 /* 605 * KLUT_WGT0 606 * Address offset: 0x0068 Access type: read and write 607 * (RDO) Chroma weight table configure register0 608 */ 609 struct { 610 /* Data0 in chroma cost weight table. */ 611 RK_U32 chrm_klut_wgt0 : 18; 612 RK_U32 reserved : 5; 613 /* Low 9 bits of data1 in chroma cost weight table. */ 614 RK_U32 chrm_klut_wgt1_l9 : 9; 615 } reg026; 616 617 /* 618 * KLUT_WGT1 619 * Address offset: 0x006C Access type: read and write 620 * (RDO) Chroma weight table configure register1 621 */ 622 struct { 623 /* High 9 bits of data1 in chroma cost weight table. */ 624 RK_U32 chrm_klut_wgt1_h9 : 9; 625 RK_U32 reserved : 5; 626 /* Data2 in chroma cost weight table. */ 627 RK_U32 chrm_klut_wgt2 : 18; 628 } reg027; 629 630 /* 631 * KLUT_WGT2 632 * Address offset: 0x0070 Access type: read and write 633 * (RDO) Chroma weight table configure register2 634 */ 635 struct { 636 /* Data3 in chroma cost weight table. */ 637 RK_U32 chrm_klut_wgt3 : 18; 638 RK_U32 reserved : 5; 639 /* Low 9 bits of data4 in chroma cost weight table. */ 640 RK_U32 chrm_klut_wgt4_l9 : 9; 641 } reg028; 642 643 /* 644 * KLUT_WGT3 645 * Address offset: 0x0074 Access type: read and write 646 * (RDO) Chroma weight table configure register3 647 */ 648 struct { 649 /* High 9 bits of data4 in chroma cost weight table. */ 650 RK_U32 chrm_klut_wgt4_h9 : 9; 651 RK_U32 reserved : 5; 652 /* Data5 in chroma cost weight table. */ 653 RK_U32 chrm_klut_wgt5 : 18; 654 } reg029; 655 656 /* 657 * KLUT_WGT4 658 * Address offset: 0x0078 Access type: read and write 659 * (RDO) Chroma weight table configure register4 660 */ 661 struct { 662 /* Data6 in chroma cost weight table. */ 663 RK_U32 chrm_klut_wgt6 : 18; 664 RK_U32 reserved : 5; 665 /* Low 9 bits of data7 in chroma cost weight table. */ 666 RK_U32 chrm_klut_wgt7_l9 : 9; 667 } reg030; 668 669 /* 670 * KLUT_WGT5 671 * Address offset: 0x007C Access type: read and write 672 * (RDO) Chroma weight table configure register5 673 */ 674 struct { 675 /* High 9 bits of data7 in chroma cost weight table. */ 676 RK_U32 chrm_klut_wgt7_h9 : 9; 677 RK_U32 reserved : 5; 678 /* Data8 in chroma cost weight table. */ 679 RK_U32 chrm_klut_wgt8 : 18; 680 } reg031; 681 682 /* 683 * KLUT_WGT6 684 * Address offset: 0x0080 Access type: read and write 685 * (RDO) Chroma weight table configure register6 686 */ 687 struct { 688 /* Data9 in chroma cost weight table. */ 689 RK_U32 chrm_klut_wgt9 : 18; 690 RK_U32 reserved : 5; 691 /* Low 9 bits of data10 in chroma cost weight table. */ 692 RK_U32 chrm_klut_wgt10_l9 : 9; 693 } reg032; 694 695 /* 696 * KLUT_WGT7 697 * Address offset: 0x0084 Access type: read and write 698 * (RDO) Chroma weight table configure register7 699 */ 700 struct { 701 /* High 9 bits of data10 in chroma cost weight table. */ 702 RK_U32 chrm_klut_wgt10_h9 : 9; 703 RK_U32 reserved : 5; 704 /* Data11 in chroma cost weight table. */ 705 RK_U32 chrm_klut_wgt11 : 18; 706 } reg033; 707 708 /* 709 * KLUT_WGT8 710 * Address offset: 0x0088 Access type: read and write 711 * (RDO) Chroma weight table configure register8 712 */ 713 struct { 714 /* Data12 in chroma cost weight table. */ 715 RK_U32 chrm_klut_wgt12 : 18; 716 RK_U32 reserved : 5; 717 /* Low 9 bits of data13 in chroma cost weight table. */ 718 RK_U32 chrm_klut_wgt13_l9 : 9; 719 } reg034; 720 721 /* 722 * KLUT_WGT9 723 * Address offset: 0x008C Access type: read and write 724 * (RDO) Chroma weight table configure register9 725 */ 726 struct { 727 /* High 9 bits of data13 in chroma cost weight table. */ 728 RK_U32 chrm_klut_wgt13_h9 : 9; 729 RK_U32 reserved : 5; 730 /* Data14 in chroma cost weight table. */ 731 RK_U32 chrm_klut_wgt14 : 18; 732 } reg035; 733 734 /* 735 * KLUT_WGT10 736 * Address offset: 0x0090 Access type: read and write 737 * (RDO) Chroma weight table configure register10 738 */ 739 struct { 740 /* Data15 in chroma cost weight table. */ 741 RK_U32 chrm_klut_wgt15 : 18; 742 RK_U32 reserved : 5; 743 /* Low 9 bits of data16 in chroma cost weight table. */ 744 RK_U32 chrm_klut_wgt16_l9 : 9; 745 } reg036; 746 747 /* 748 * KLUT_WGT11 749 * Address offset: 0x0094 Access type: read and write 750 * (RDO) Chroma weight table configure register11 751 */ 752 struct { 753 /* High 9 bits of data16 in chroma cost weight table. */ 754 RK_U32 chrm_klut_wgt16_h9 : 9; 755 RK_U32 reserved : 5; 756 /* Data17 in chroma cost weight table. */ 757 RK_U32 chrm_klut_wgt17 : 18; 758 } reg037; 759 760 /* 761 * KLUT_WGT12 762 * Address offset: 0x0098 Access type: read and write 763 * (RDO) Chroma weight table configure register12 764 */ 765 struct { 766 /* Data18 in chroma cost weight table. */ 767 RK_U32 chrm_klut_wgt18 : 18; 768 RK_U32 reserved : 5; 769 /* Low 9 bits of data19 in chroma cost weight table. */ 770 RK_U32 chrm_klut_wgt19_l9 : 9; 771 } reg038; 772 773 /* 774 * KLUT_WGT13 775 * Address offset: 0x009C Access type: read and write 776 * (RDO) Chroma weight table configure register13 777 */ 778 struct { 779 /* High 9 bits of data19 in chroma cost weight table. */ 780 RK_U32 chrm_klut_wgt19_h9 : 9; 781 RK_U32 reserved : 5; 782 /* Data14 in chroma cost weight table. */ 783 RK_U32 chrm_klut_wgt20 : 18; 784 } reg039; 785 786 /* 787 * KLUT_WGT14 788 * Address offset: 0x00A0 Access type: read and write 789 * (RDO) Chroma weight table configure register14 790 */ 791 struct { 792 /* Data21 in chroma cost weight table. */ 793 RK_U32 chrm_klut_wgt21 : 18; 794 RK_U32 reserved : 5; 795 /* Low 9 bits of data22 in chroma cost weight table. */ 796 RK_U32 chrm_klut_wgt22_l9 : 9; 797 } reg040; 798 799 /* 800 * KLUT_WGT15 801 * Address offset: 0x00A4 Access type: read and write 802 * (RDO) Chroma weight table configure register15 803 */ 804 struct { 805 /* High 9 bits of data22 in chroma cost weight table. */ 806 RK_U32 chrm_klut_wgt22_h9 : 9; 807 RK_U32 reserved : 5; 808 /* Data23 in chroma cost weight table. */ 809 RK_U32 chrm_klut_wgt23 : 18; 810 } reg041; 811 812 /* 813 * KLUT_WGT16 814 * Address offset: 0x00A8 Access type: read and write 815 * (RDO) Chroma weight table configure register16 816 */ 817 struct { 818 /* Data24 in chroma cost weight table. */ 819 RK_U32 chrm_klut_wgt24 : 18; 820 RK_U32 reserved : 5; 821 /* Low 9 bits of data25 in chroma cost weight table. */ 822 RK_U32 chrm_klut_wgt25_l9 : 9; 823 } reg042; 824 825 /* 826 * KLUT_WGT17 827 * Address offset: 0x00AC Access type: read and write 828 * (RDO) Chroma weight table configure register17 829 */ 830 struct { 831 /* High 9 bits of data25 in chroma cost weight table. */ 832 RK_U32 chrm_klut_wgt25_h9 : 9; 833 RK_U32 reserved : 5; 834 /* Data26 in chroma cost weight table. */ 835 RK_U32 chrm_klut_wgt26 : 18; 836 } reg043; 837 838 /* 839 * KLUT_WGT18 840 * Address offset: 0x00B0 Access type: read and write 841 * (RDO) Chroma weight table configure register18 842 */ 843 struct { 844 /* Data27 in chroma cost weight table. */ 845 RK_U32 chrm_klut_wgt27 : 18; 846 RK_U32 reserved : 5; 847 /* Low 9 bits of data28 in chroma cost weight table. */ 848 RK_U32 chrm_klut_wgt28_l9 : 9; 849 } reg044; 850 851 /* 852 * KLUT_WGT19 853 * Address offset: 0x00B4 Access type: read and write 854 * (RDO) Chroma weight table configure register19 855 */ 856 struct { 857 /* High 9 bits of data28 in chroma cost weight table. */ 858 RK_U32 chrm_klut_wgt28_h9 : 9; 859 RK_U32 reserved : 5; 860 /* Data29 in chroma cost weight table. */ 861 RK_U32 chrm_klut_wgt29 : 18; 862 } reg045; 863 864 /* 865 * KLUT_WGT20 866 * Address offset: 0x00B8 Access type: read and write 867 * (RDO) Chroma weight table configure register20 868 */ 869 struct { 870 /* Data30 in chroma cost weight table. */ 871 RK_U32 chrm_klut_wgt30 : 18; 872 RK_U32 reserved : 5; 873 /* Low 9 bits of data31 in chroma cost weight table. */ 874 RK_U32 chrm_klut_wgt31_l9 : 9; 875 } reg046; 876 877 /* 878 * KLUT_WGT21 879 * Address offset: 0x00BC Access type: read and write 880 * (RDO) Chroma weight table configure register21 881 */ 882 struct { 883 /* High 9 bits of data31 in chroma cost weight table. */ 884 RK_U32 chrm_klut_wgt31_h9 : 9; 885 RK_U32 reserved : 5; 886 /* Data32 in chroma cost weight table. */ 887 RK_U32 chrm_klut_wgt32 : 18; 888 } reg047; 889 890 /* 891 * KLUT_WGT22 892 * Address offset: 0x00C0 Access type: read and write 893 * (RDO) Chroma weight table configure register22 894 */ 895 struct { 896 /* Data33 in chroma cost weight table. */ 897 RK_U32 chrm_klut_wgt33 : 18; 898 RK_U32 reserved : 5; 899 /* Low 9 bits of data34 in chroma cost weight table. */ 900 RK_U32 chrm_klut_wgt34_l9 : 9; 901 } reg048; 902 903 /* 904 * KLUT_WGT23 905 * Address offset: 0x00C4 Access type: read and write 906 * (RDO) Chroma weight table configure register23 907 */ 908 struct { 909 /* High 9 bits of data34 in chroma cost weight table. */ 910 RK_U32 chrm_klut_wgt34_h9 : 9; 911 RK_U32 reserved : 23; 912 } reg049; 913 914 /* 915 * RC_CFG 916 * Address offset: 0x00C8 Access type: read and write 917 * Rate control configuration 918 */ 919 struct { 920 /* Rate control enable. */ 921 RK_U32 rc_en : 1; 922 /* Adaptive quantization enable. */ 923 RK_U32 aq_en : 1; 924 /* 925 * Mode of aq_delta calculation for CU32 and CU64. 926 * 1'b0: aq_delta of CU32/CU64 is calculated by corresponding MADI32/64; 927 * 1'b1: aq_delta of CU32/CU64 is calculated by corresponding 4/16 CU16 qp_deltas. 928 */ 929 RK_U32 aq_mode : 1; 930 RK_U32 reserved : 13; 931 /* RC adjustment intervals, base on CTU number. */ 932 RK_U32 rc_ctu_num : 16; 933 } reg050; 934 935 /* 936 * RC_QP 937 * Address offset: 0x00CC Access type: read and write 938 * QP configuration for rate control 939 */ 940 struct { 941 RK_U32 reserved : 16; 942 /* 943 * QP adjust range(delta_qp) in rate control. 944 * Delta_qp is constrained between -rc_qp_range to rc_qp_range. 945 */ 946 RK_S32 rc_qp_range : 4; 947 /* Max QP for rate control and AQ mode. */ 948 RK_U32 rc_max_qp : 6; 949 /* Min QP for rate control and AQ mode. */ 950 RK_U32 rc_min_qp : 6; 951 } reg051; 952 953 /* 954 * RC_TGT 955 * Address offset: 0x00D0 Access type: read and write 956 * The target bit rate for rate control 957 */ 958 struct { 959 /* 960 * Target bit num for one 64x64 CTU(for HEVC) 961 * or one 16x16 MB(for H.264), with 1/16 precision. 962 */ 963 RK_U32 ctu_ebit : 20; 964 RK_U32 reserved : 12; 965 } reg052; 966 967 /* 968 * RC_ADJ0 969 * Address offset: 0x00D4 Access type: read and write 970 * QP adjust configuration for rate control 971 */ 972 struct { 973 /* QP adjust step0 for rate control. */ 974 RK_S32 qp_adj0 : 5; 975 /* QP adjust step1 for rate control. */ 976 RK_S32 qp_adj1 : 5; 977 /* QP adjust step2 for rate control. */ 978 RK_S32 qp_adj2 : 5; 979 /* QP adjust step3 for rate control. */ 980 RK_S32 qp_adj3 : 5; 981 /* QP adjust step4 for rate control. */ 982 RK_S32 qp_adj4 : 5; 983 RK_U32 reserved : 7; 984 } reg053; 985 986 /* 987 * RC_ADJ1 988 * Address offset: 0x00D8 Access type: read and write 989 * QP adjust configuration for rate control 990 */ 991 struct { 992 /* QP adjust step5 for rate control. */ 993 RK_S32 qp_adj5 : 5; 994 /* QP adjust step6 for rate control. */ 995 RK_S32 qp_adj6 : 5; 996 /* QP adjust step7 for rate control. */ 997 RK_S32 qp_adj7 : 5; 998 /* QP adjust step8 for rate control. */ 999 RK_S32 qp_adj8 : 5; 1000 RK_U32 reserved : 12; 1001 } reg054; 1002 1003 /* 1004 * RC_DTHD0~8 1005 * Address offset: 0x00DC~0x00FC Access type: read and write 1006 * Bits rate deviation threshold0~8 1007 */ 1008 struct { 1009 /* Bits rate deviation threshold0~8. */ 1010 RK_U32 rc_dthd[9]; 1011 } reg055_063; 1012 1013 /* 1014 * ROI_QTHD0 1015 * Address offset: 0x0100 Access type: read and write 1016 * ROI QP threshold configuration0 1017 */ 1018 struct { 1019 /* Min QP for 16x16 CU inside ROI area0. */ 1020 RK_U32 qpmin_area0 : 6; 1021 /* Max QP for 16x16 CU inside ROI area0. */ 1022 RK_U32 qpmax_area0 : 6; 1023 /* Min QP for 16x16 CU inside ROI area1. */ 1024 RK_U32 qpmin_area1 : 6; 1025 /* Max QP for 16x16 CU inside ROI area1. */ 1026 RK_U32 qpmax_area1 : 6; 1027 /* Min QP for 16x16 CU inside ROI area2. */ 1028 RK_U32 qpmin_area2 : 6; 1029 RK_U32 reserved : 2; 1030 } reg064; 1031 1032 /* 1033 * ROI_QTHD1 1034 * Address offset: 0x0104 Access type: read and write 1035 * ROI QP threshold configuration1 1036 */ 1037 struct { 1038 /* Max QP for 16x16 CU inside ROI area2. */ 1039 RK_U32 qpmax_area2 : 6; 1040 /* Min QP for 16x16 CU inside ROI area3. */ 1041 RK_U32 qpmin_area3 : 6; 1042 /* Max QP for 16x16 CU inside ROI area3. */ 1043 RK_U32 qpmax_area3 : 6; 1044 /* Min QP for 16x16 CU inside ROI area4. */ 1045 RK_U32 qpmin_area4 : 6; 1046 /* Min QP for 16x16 CU inside ROI area4. */ 1047 RK_U32 qpmax_area4 : 6; 1048 RK_U32 reserved : 2; 1049 } reg065; 1050 1051 /* 1052 * ROI_QTHD2 1053 * Address offset: 0x0108 Access type: read and write 1054 * ROI QP threshold configuration2 1055 */ 1056 struct { 1057 /* Min QP for 16x16 CU inside ROI area5. */ 1058 RK_U32 qpmin_area5 : 6; 1059 /* Max QP for 16x16 CU inside ROI area5. */ 1060 RK_U32 qpmax_area5 : 6; 1061 /* Min QP for 16x16 CU inside ROI area6. */ 1062 RK_U32 qpmin_area6 : 6; 1063 /* Max QP for 16x16 CU inside ROI area6. */ 1064 RK_U32 qpmax_area6 : 6; 1065 /* Min QP for 16x16 CU inside ROI area7. */ 1066 RK_U32 qpmin_area7 : 6; 1067 RK_U32 reserved : 2; 1068 } reg066; 1069 1070 /* 1071 * ROI_QTHD3 1072 * Address offset: 0x010C Access type: read and write 1073 * ROI QP threshold configuration3 1074 */ 1075 struct { 1076 /* Max QP for 16x16 CU inside ROI area7. */ 1077 RK_U32 qpmax_area7 : 6; 1078 RK_U32 reserved : 24; 1079 /* 1080 * QP theshold generation for the CUs whose size is bigger than 16x16. 1081 * 2'h0: Mean value of 16x16 CU QP thesholds 1082 * 2'h1: Max value of 16x16 CU QP thesholds 1083 * 2'h2: Min value of 16x16 CU QP thesholds 1084 * 2'h3: Reserved 1085 */ 1086 RK_U32 qpmap_mode : 2; 1087 } reg067; 1088 1089 /* 1090 * PIC_OFST 1091 * Address offset: 0x0110 Access type: read and write 1092 * Encoding picture offset 1093 */ 1094 struct { 1095 /* Vertical offset for encoding picture. */ 1096 RK_U32 pic_ofst_y : 13; 1097 RK_U32 reserved0 : 3; 1098 /* Horizontal offset for encoding picture. */ 1099 RK_U32 pic_ofst_x : 13; 1100 RK_U32 reserved1 : 3; 1101 } reg068; 1102 1103 /* 1104 * SRC_STRID 1105 * Address offset: 0x0114 Access type: read and write 1106 * Video source stride 1107 */ 1108 struct { 1109 /* 1110 * Video source stride0, based on pixel (byte). 1111 * Note that if the video format is YUV, src_strd is the LUMA component 1112 * stride while src_strid1 is the CHROMA component stride. 1113 */ 1114 RK_U32 src_strd0 : 16; 1115 /* 1116 * CHROMA stride of video source, only for YUV format. 1117 * Note that U and V stride must be the same when color format is YUV 1118 * planar. 1119 */ 1120 RK_U32 src_strd1 : 16; 1121 } reg069; 1122 1123 /* 1124 * ADR_SRC0 1125 * Address offset: 0x0118 Access type: read and write 1126 * Base address of the 1st storage area for video source 1127 */ 1128 struct { 1129 /* 1130 * Base address of the 1st storage area for video source. 1131 * ARGB8888, BGR888, RGB565, YUYV422 and UYUV422 have only one storage 1132 * area, while adr_src0 is configured as the base address of video 1133 * source frame buffer. 1134 * YUV422/420 semi-planar have 2 storage area, while adr_src0 is 1135 * configured as the base address of Y frame buffer. 1136 * YUV422/420 planar have 3 storage area, while adr_src0 is configured 1137 * as the base address of Y frame buffer. 1138 * Note that if the video source is compressed by AFBC, adr_src0 is 1139 * configured as the base address of compressed frame buffer. 1140 */ 1141 RK_U32 adr_src0; 1142 } reg070; 1143 1144 /* 1145 * ADR_SRC1 1146 * Address offset: 0x011C Access type: read and write 1147 * Base address of the 2nd storage area for video source 1148 */ 1149 struct { 1150 /* 1151 * Base address of V frame buffer when video source is uncompress and 1152 * color format is YUV422/420 planar. 1153 */ 1154 RK_U32 adr_src1; 1155 } reg071; 1156 1157 /* 1158 * ADR_SRC2 1159 * Address offset: 0x0120 Access type: read and write 1160 * Base address of the 3rd storage area for video source 1161 */ 1162 struct { 1163 /* 1164 * Base address of V frame buffer when video source is uncompress and 1165 * color format is YUV422/420 planar. 1166 */ 1167 RK_U32 adr_src2; 1168 } reg072; 1169 1170 /* 1171 * ADR_ROI 1172 * Address offset: 0x0124 Access type: read and write 1173 * Base address for ROI configuration, 16 bytes aligned 1174 */ 1175 struct { 1176 /* High 28 bits of base address for ROI configuration. */ 1177 RK_U32 roi_addr; 1178 } reg073; 1179 1180 /* 1181 * ADR_RFPW_H 1182 * Address offset: 0x0128 Access type: read and write 1183 * Base address of header_block for compressed reference frame write, 1184 * 4K bytes aligned 1185 */ 1186 struct { 1187 /* 1188 * High 20 bits of the header_block base address for compressed 1189 * reference frame write. 1190 */ 1191 RK_U32 rfpw_h_addr; 1192 } reg074; 1193 1194 /* 1195 * ADR_RFPW_B 1196 * Address offset: 0x012C Access type: read and write 1197 * Base address of body_block for compressed reference frame write, 1198 * 4K bytes aligned 1199 */ 1200 struct { 1201 /* 1202 * High 20 bits of the body_block base address for compressed 1203 * reference frame write. 1204 */ 1205 RK_U32 rfpw_b_addr; 1206 } reg075; 1207 1208 /* 1209 * ADR_RFPR_H 1210 * Address offset: 0x0130 Access type: read and write 1211 * Base address of header_block for compressed reference frame read, 1212 * 4K bytes aligned 1213 */ 1214 struct { 1215 /* 1216 * High 20 bits of the header_block base address for compressed 1217 * reference frame read. 1218 */ 1219 RK_U32 rfpr_h_addr; 1220 } reg076; 1221 1222 /* 1223 * ADR_RFPR_B 1224 * Address offset: 0x0134 Access type: read and write 1225 * Base address of body_block for compressed reference frame read, 1226 * 4K bytes aligned 1227 */ 1228 struct { 1229 /* 1230 * High 20 bits of the body_block base address for compressed 1231 * reference frame read. 1232 */ 1233 RK_U32 rfpr_b_addr; 1234 } reg077; 1235 1236 /* 1237 * ADR_CMVW 1238 * Address offset: 0x0138 Access type: read and write 1239 * Base address for col-located Mv write, 1KB aligned, HEVC only 1240 */ 1241 struct { 1242 /* High 22 bits of base address for col-located Mv write, HEVC only. */ 1243 RK_U32 cmvw_addr; 1244 } reg078; 1245 1246 /* 1247 * ADR_CMVR 1248 * Address offset: 0x013C Access type: read and write 1249 * Base address for col-located Mv read, 1KB aligned, HEVC only 1250 */ 1251 struct { 1252 /* High 22 bits of base address for col-located Mv read, HEVC only. */ 1253 RK_U32 cmvr_addr; 1254 } reg079; 1255 1256 /* 1257 * ADR_DSPW 1258 * Address offset: 0x0140 Access type: read and write 1259 * Base address for down-sampled reference frame write, 1KB aligned 1260 */ 1261 struct { 1262 /* High 22 bits of base address for down-sampled reference frame write. */ 1263 RK_U32 dspw_addr; 1264 } reg080; 1265 1266 /* 1267 * ADR_DSPR 1268 * Address offset: 0x0144 Access type: read and write 1269 * Base address for down-sampled reference frame read, 1KB aligned 1270 */ 1271 struct { 1272 /* High 22 bits of base address for down-sampled reference frame read. */ 1273 RK_U32 dspr_addr; 1274 } reg081; 1275 1276 /* 1277 * ADR_MEIW 1278 * Address offset: 0x0148 Access type: read and write 1279 * Base address for ME information write, 1KB aligned 1280 */ 1281 struct { 1282 /* High 22 bits of base address for ME information write. */ 1283 RK_U32 meiw_addr; 1284 } reg082; 1285 1286 /* 1287 * ADR_BSBT 1288 * Address offset: 0x014C Access type: read and write 1289 * Top address of bit stream buffer, 128B aligned 1290 */ 1291 struct { 1292 /* High 25 bits of the top address of bit stream buffer. */ 1293 RK_U32 bsbt_addr; 1294 } reg083; 1295 1296 /* 1297 * ADR_BSBB 1298 * Address offset: 0x0150 Access type: read and write 1299 * Bottom address of bit stream buffer, 128B aligned 1300 */ 1301 struct { 1302 /* High 25 bits of the bottom address of bit stream buffer. */ 1303 RK_U32 bsbb_addr; 1304 } reg084; 1305 1306 /* 1307 * ADR_BSBR 1308 * Address offset: 0x0154 Access type: read and write 1309 * Read address of bit stream buffer, 128B aligned 1310 */ 1311 struct { 1312 /* 1313 * Read address of bit stream buffer, 128B aligned. 1314 * VEPU will pause when write address meets read address and then send 1315 * an interrupt. SW should move some data out from bit stream buffer 1316 * and change this register accordingly. 1317 * After that VEPU will continue processing automatically. 1318 */ 1319 RK_U32 bsbr_addr; 1320 } reg085; 1321 1322 /* 1323 * ADR_BSBS 1324 * Address offset: 0x0158 Access type: read and write 1325 * Start address of bit stream buffer 1326 */ 1327 struct { 1328 /* 1329 * Start address of bit stream buffer. 1330 * VEPU begins to write bit stream from this address and increase 1331 * address automatically. 1332 * Note that the VEPU's real-time write address is marked in BSB_STUS. 1333 */ 1334 RK_U32 adr_bsbs; 1335 } reg086; 1336 1337 /* 1338 * SLI_SPLT 1339 * Address offset: 0x015C Access type: read and write 1340 * Slice split configuration 1341 */ 1342 struct { 1343 /* Slice split enable. */ 1344 RK_U32 sli_splt : 1; 1345 /* 1346 * Slice split mode. 1347 * 1'h0: Slice splited by byte. 1348 * 1'h1: Slice splited by number of MB(H.264)/CTU(HEVC). 1349 */ 1350 RK_U32 sli_splt_mode : 1; 1351 /* 1352 * Slice split compensation when slice is splited by byte. 1353 * Byte distortion of current slice will be compensated in the next slice. 1354 */ 1355 RK_U32 sli_splt_cpst : 1; 1356 /* Max slice num in one frame. */ 1357 RK_U32 sli_max_num_m1 : 10; 1358 /* Slice flush. Flush all the bit stream after each slice finished. */ 1359 RK_U32 sli_flsh : 1; 1360 RK_U32 reserved : 2; 1361 /* Number of CTU/MB for slice split. Valid when slice is splited by CTU/MB. */ 1362 RK_U32 sli_splt_cnum_m1 : 16; 1363 } reg087; 1364 1365 /* 1366 * SLI_BYTE 1367 * Address offset: 0x0160 Access type: read and write 1368 * Number of bytes for slice split 1369 */ 1370 struct { 1371 /* Byte number for each slice when slice is splited by byte. */ 1372 RK_U32 sli_splt_byte : 18; 1373 RK_U32 reserved : 14; 1374 } reg088; 1375 1376 /* 1377 * ME_RNGE 1378 * Address offset: 0x0164 Access type: read and write 1379 * Motion estimation range 1380 */ 1381 struct { 1382 /* CME horizontal search range, base on 16 pixels. */ 1383 RK_U32 cme_srch_h : 4; 1384 /* CME vertical search range, base on 16 pixel. */ 1385 RK_U32 cme_srch_v : 4; 1386 /* RME horizontal search range, values from 3 to 7. */ 1387 RK_U32 rme_srch_h : 3; 1388 /* RME vertical search range, values from 4 to 5. */ 1389 RK_U32 rme_srch_v : 3; 1390 RK_U32 reserved : 2; 1391 /* Frame number difference value between current and reference frame, HEVC only. */ 1392 RK_U32 dlt_frm_num : 16; 1393 } reg089; 1394 1395 /* 1396 * ME_CNST 1397 * Address offset: 0x0168 Access type: read and write 1398 * Motion estimation configuration 1399 */ 1400 struct { 1401 /* Min horizontal distance for PMV selection. */ 1402 RK_U32 pmv_mdst_h : 8; 1403 /* Min vertical distance for PMV selection. */ 1404 RK_U32 pmv_mdst_v : 8; 1405 /* 1406 * Motion vector limit ( by level), H.264 only. 1407 * 2'h0: Mvy is limited to [-64,63]. 1408 * Others: Mvy is limited to [-128,127]. 1409 */ 1410 RK_U32 mv_limit : 2; 1411 /* PMV number (should be constant2). */ 1412 RK_U32 pmv_num : 2; 1413 /* Store col-Mv information to external memory, HEVC only. */ 1414 RK_U32 colmv_stor : 1; 1415 /* Load co-located Mvs as predicated Mv candidates, HEVC only. */ 1416 RK_U32 colmv_load : 1; 1417 /* 1418 * [4]: Disable 64x64 block RME. 1419 * [3]: Disable 32x32 block RME. 1420 * [2]: Disable 16x16 block RME. 1421 * [1]: Disable 8x8 block RME. 1422 * [0]: Disable 4x4 block RME. 1423 */ 1424 RK_U32 rme_dis : 5; 1425 /* 1426 * [4]: Disable 64x64 block FME. 1427 * [3]: Disable 32x32 block FME. 1428 * [2]: Disable 16x16 block FME. 1429 * [1]: Disable 8x8 block FME. 1430 * [0]: Disable 4x4 block FME. 1431 */ 1432 RK_U32 fme_dis : 5; 1433 } reg090; 1434 1435 /* 1436 * ME_RAM 1437 * Address offset: 0x016C Access type: read and write 1438 * ME cache configuration 1439 */ 1440 struct { 1441 /* CME's max RAM address. */ 1442 RK_U32 cme_rama_max : 11; 1443 /* Height of CME RAMA district, base on 4 pixels. */ 1444 RK_U32 cme_rama_h : 5; 1445 /* 1446 * L2 cach mapping, base on pixels. 1447 * 2'h0: 32x512 1448 * 2'h1: 16x1024 1449 * 2'h2: 8x2048 1450 * 2'h3: 4x4096 1451 */ 1452 RK_U32 cach_l2_map : 2; 1453 /* The width of CIME down-sample recon data linebuf, based on 64 pixel. */ 1454 RK_U32 cme_linebuf_w : 8; 1455 RK_U32 reserved : 6; 1456 } reg091; 1457 1458 /* 1459 * SYNT_LONG_REFM0 1460 * Address offset: 0x0170 Access type: read and write 1461 * Long term reference frame mark0 for HEVC 1462 */ 1463 struct { 1464 /* Poc_lsb_lt[1] */ 1465 RK_U32 poc_lsb_lt1 : 16; 1466 /* Poc_lsb_lt[2] */ 1467 RK_U32 poc_lsb_lt2 : 16; 1468 } reg092; 1469 1470 /* 1471 * SYNT_LONG_REFM1 1472 * Address offset: 0x0174 Access type: read and write 1473 * Long term reference frame mark1 for HEVC 1474 */ 1475 struct { 1476 /* Delta_poc_msb_cycle_lt[1] */ 1477 RK_U32 dlt_poc_msb_cycl1 : 16; 1478 /* Delta_poc_msb_cycle_lt[2] */ 1479 RK_U32 dlt_poc_msb_cycl2 : 16; 1480 } reg093; 1481 1482 /* 1483 * OSD_INV_CFG 1484 * Address offset: 0x0178 Access type: read and write 1485 * OSD color inverse configuration 1486 * 1487 * Added in vepu540 1488 */ 1489 struct { 1490 /* 1491 * OSD color inverse enable of chroma component, 1492 * each bit controls corresponding region. 1493 */ 1494 RK_U32 osd_ch_inv_en : 8; 1495 /* 1496 * OSD color inverse expression type 1497 * each bit controls corresponding region. 1498 * 1'h0: AND; 1499 * 1'h1: OR 1500 */ 1501 RK_U32 osd_itype : 8; 1502 /* 1503 * OSD color inverse expression switch for luma component 1504 * each bit controls corresponding region. 1505 * 1'h0: Expression need to determine the condition; 1506 * 1'h1: Expression don't need to determine the condition; 1507 */ 1508 RK_U32 osd_lu_inv_msk : 8; 1509 /* 1510 * OSD color inverse expression switch for chroma component 1511 * each bit controls corresponding region. 1512 * 1'h0: Expression need to determine the condition; 1513 * 1'h1: Expression don't need to determine the condition; 1514 */ 1515 RK_U32 osd_ch_inv_msk : 8; 1516 } reg094; 1517 1518 /* reg gap 095~100 */ 1519 RK_U32 reg_095_100[6]; 1520 1521 /* 1522 * IPRD_CSTS 1523 * Address offset: 0x0194 Access type: read and write 1524 * Cost function configuration for intra prediction 1525 */ 1526 struct { 1527 /* LUMA variance threshold to select intra prediction cost function. */ 1528 RK_U32 vthd_y : 12; 1529 RK_U32 reserved0 : 4; 1530 /* CHROMA variance threshold to select intra prediction cost function. */ 1531 RK_U32 vthd_c : 12; 1532 RK_U32 reserved1 : 4; 1533 } reg101; 1534 1535 /* 1536 * RDO_CFG_H264 1537 * Address offset: 0x0198 Access type: read and write 1538 * H.264 RDO configuration 1539 */ 1540 struct { 1541 /* Limit sub_mb_rect_size for low level. */ 1542 RK_U32 rect_size : 1; 1543 /* 4x4 sub MB enable. */ 1544 RK_U32 inter_4x4 : 1; 1545 /* Reserved */ 1546 RK_U32 arb_sel : 1; 1547 /* CAVLC syntax limit. */ 1548 RK_U32 vlc_lmt : 1; 1549 /* Chroma special candidates enable. */ 1550 RK_U32 chrm_spcl : 1; 1551 /* 1552 * [7]: Disable intra4x4. 1553 * [6]: Disable intra8x8. 1554 * [5]: Disable intra16x16. 1555 * [4]: Disable inter8x8 with T4. 1556 * [3]: Disable inter8x8 with T8. 1557 * [2]: Disable inter16x16 with T4. 1558 * [1]: Disable inter16x16 with T8. 1559 * [0]: Disable skip mode. 1560 */ 1561 RK_U32 rdo_mask : 8; 1562 /* Chroma cost weight adjustment(KLUT) enable. */ 1563 RK_U32 ccwa_e : 1; 1564 /* 1565 * Scale list selection. 1566 * 1'h0: Flat scale list. 1567 * 1'h1: Default scale list. 1568 */ 1569 RK_U32 scl_lst_sel : 1; 1570 /* Anti-ring enable. */ 1571 RK_U32 atr_e : 1; 1572 /* Edge of anti-flicker, base on MB. the MBs inside edge should not influenced. */ 1573 RK_U32 atf_edg : 2; 1574 /* Block level anti-flicker enable. */ 1575 RK_U32 atf_lvl_e : 1; 1576 /* Intra mode anti-flicker enable. */ 1577 RK_U32 atf_intra_e : 1; 1578 /* 1579 * Scale list selection. (for vepu540) 1580 * 2'h0: Flat scale list. 1581 * 2'h1: Default scale list. 1582 * 2'h2: User defined. 1583 * 2'h3: Reserved. 1584 */ 1585 RK_U32 scl_lst_sel_ : 2; 1586 RK_U32 reserved : 9; 1587 /* 1588 * Rdo cost caculation expression for intra by using sad or satd. 1589 * 1'h0: SATD; 1590 * 1'h1: SAD; 1591 */ 1592 RK_U32 satd_byps_flg : 1; 1593 } reg102; 1594 1595 /* 1596 * SYNT_NAL_H264 1597 * Address offset: 0x019C Access type: read and write 1598 * NAL configuration for H.264 1599 */ 1600 struct { 1601 /* nal_ref_idc */ 1602 RK_U32 nal_ref_idc : 2; 1603 RK_U32 nal_unit_type : 5; 1604 /* nal_unit_type */ 1605 RK_U32 reserved : 25; 1606 } reg103; 1607 1608 /* 1609 * SYNT_SPS_H264 1610 * Address offset: 0x01A0 Access type: read and write 1611 * Sequence parameter set syntax configuration for H.264 1612 */ 1613 struct { 1614 /* log2_max_frame_num_minus4 */ 1615 RK_U32 max_fnum : 4; 1616 /* direct_8x8_inference_flag */ 1617 RK_U32 drct_8x8 : 1; 1618 /* log2_max_pic_order_cnt_lsb_minus4 */ 1619 RK_U32 mpoc_lm4 : 4; 1620 RK_U32 reserved : 23; 1621 } reg104; 1622 1623 /* 1624 * SYNT_PPS_H264 1625 * Address offset: 0x01A4 Access type: read and write 1626 * Picture parameter set configuration for H.264 1627 */ 1628 struct { 1629 /* entropy_coding_mode_flag */ 1630 RK_U32 etpy_mode : 1; 1631 /* transform_8x8_mode_flag */ 1632 RK_U32 trns_8x8 : 1; 1633 /* constrained_intra_pred_flag */ 1634 RK_U32 csip_flag : 1; 1635 /* num_ref_idx_l0_active_minus1 */ 1636 RK_U32 num_ref0_idx : 2; 1637 /* num_ref_idx_l1_active_minus1 */ 1638 RK_U32 num_ref1_idx : 2; 1639 /* pic_init_qp_minus26 + 26 */ 1640 RK_U32 pic_init_qp : 6; 1641 /* chroma_qp_index_offset */ 1642 RK_U32 cb_ofst : 5; 1643 /* second_chroma_qp_index_offset */ 1644 RK_U32 cr_ofst : 5; 1645 /* weight_pred_flag */ 1646 RK_U32 wght_pred : 1; 1647 /* deblocking_filter_control_present_flag */ 1648 RK_U32 dbf_cp_flg : 1; 1649 RK_U32 reserved : 7; 1650 } reg105; 1651 1652 /* 1653 * SYNT_SLI0_H264 1654 * Address offset: 0x01A8 Access type: read and write 1655 * Slice header configuration0 for H.264 1656 */ 1657 struct { 1658 /* slice_type: 0->P, 1->B, 2->I. */ 1659 RK_U32 sli_type : 2; 1660 /* pic_parameter_set_id */ 1661 RK_U32 pps_id : 8; 1662 /* direct_spatial_mv_pred_flag */ 1663 RK_U32 drct_smvp : 1; 1664 /* num_ref_idx_active_override_flag */ 1665 RK_U32 num_ref_ovrd : 1; 1666 /* cabac_init_idc */ 1667 RK_U32 cbc_init_idc : 2; 1668 RK_U32 reserved : 2; 1669 /* frame_num */ 1670 RK_U32 frm_num : 16; 1671 } reg106; 1672 1673 /* 1674 * SYNT_SLI1_H264 1675 * Address offset: 0x01AC Access type: read and write 1676 * Slice header configuration1 for H.264 1677 */ 1678 struct { 1679 /* idr_pid */ 1680 RK_U32 idr_pic_id : 16; 1681 /* pic_order_cnt_lsb */ 1682 RK_U32 poc_lsb : 16; 1683 } reg107; 1684 1685 /* 1686 * SYNT_SLI2_H264 1687 * Address offset: 0x01B0 Access type: read and write 1688 * Slice header configuration2 for H.264 1689 */ 1690 struct { 1691 /* reordering_of_pic_nums_idc */ 1692 RK_U32 rodr_pic_idx : 2; 1693 /* ref_pic_list_reordering_flag_l0 */ 1694 RK_U32 ref_list0_rodr : 1; 1695 /* slice_beta_offset_div2 */ 1696 RK_U32 sli_beta_ofst : 4; 1697 /* slice_alpha_c0_offset_div2 */ 1698 RK_U32 sli_alph_ofst : 4; 1699 /* disable_deblocking_filter_idc */ 1700 RK_U32 dis_dblk_idc : 2; 1701 RK_U32 reserved : 3; 1702 /* abs_diff_pic_num_minus1/long_term_pic_num */ 1703 RK_U32 rodr_pic_num : 16; 1704 } reg108; 1705 1706 /* 1707 * SYNT_REFM0_H264 1708 * Address offset: 0x01B4 Access type: read and write 1709 * Reference frame mark0 for H.264 1710 */ 1711 struct { 1712 /* no_output_of_prior_pics_flag */ 1713 RK_U32 nopp_flg : 1; 1714 /* long_term_reference_flag */ 1715 RK_U32 ltrf_flg : 1; 1716 /* adaptive_ref_pic_marking_mode_flag */ 1717 RK_U32 arpm_flg : 1; 1718 /* A No.4 MMCO should be executed firstly if mmo4_pre is 1 */ 1719 RK_U32 mmco4_pre : 1; 1720 /* memory_management_control_operation */ 1721 RK_U32 mmco_type0 : 3; 1722 /* 1723 * MMCO parameters which have different meanings according to different mmco_parm0 valus. 1724 * difference_of_pic_nums_minus1 for mmco_parm0 equals 0 or 3. 1725 * long_term_pic_num for mmco_parm0 equals 2. 1726 * long_term_frame_idx for mmco_parm0 equals 6. 1727 * max_long_term_frame_idx_plus1 for mmco_parm0 equals 4. 1728 */ 1729 RK_U32 mmco_parm0 : 16; 1730 /* memory_management_control_operation[1] */ 1731 RK_U32 mmco_type1 : 3; 1732 /* memory_management_control_operation[2] */ 1733 RK_U32 mmco_type2 : 3; 1734 RK_U32 reserved : 3; 1735 } reg109; 1736 1737 /* 1738 * SYNT_REFM1_H264 1739 * Address offset: 0x01B8 Access type: read and write 1740 * Reference frame mark1 for H.264 1741 */ 1742 struct { 1743 /* 1744 * MMCO parameters which have different meanings according to different mmco_parm1 valus. 1745 * difference_of_pic_nums_minus1 for mmco_parm1 equals 0 or 3. 1746 * long_term_pic_num for mmco_parm1 equals 2. 1747 * long_term_frame_idx for mmco_parm1 equals 6. 1748 * max_long_term_frame_idx_plus1 for mmco_parm1 equals 4. 1749 */ 1750 RK_U32 mmco_parm1 : 16; 1751 /* 1752 * MMCO parameters which have different meanings according to different mmco_parm2 valus. 1753 * difference_of_pic_nums_minus1 for mmco_parm2 equals 0 or 3. 1754 * long_term_pic_num for mmco_parm2 equals 2. 1755 * long_term_frame_idx for mmco_parm2 equals 6. 1756 * max_long_term_frame_idx_plus1 for mmco_parm2 equals 4. 1757 */ 1758 RK_U32 mmco_parm2 : 16; 1759 } reg110; 1760 1761 /* reg gap 111 */ 1762 RK_U32 reg_111; 1763 1764 /* 1765 * OSD_CFG 1766 * Address offset: 0x01C0 Access type: read and write 1767 * OSD configuration 1768 */ 1769 struct { 1770 /* OSD region enable, each bit controls corresponding OSD region. */ 1771 RK_U32 osd_e : 8; 1772 /* OSD inverse color enable, each bit controls corresponding region. */ 1773 RK_U32 osd_inv_e : 8; 1774 /* 1775 * OSD palette clock selection. 1776 * 1'h0: Configure bus clock domain. 1777 * 1'h1: Core clock domain. 1778 */ 1779 RK_U32 osd_plt_cks : 1; 1780 /* 1781 * OSD palette type. 1782 * 1'h1: Default type. 1783 * 1'h0: User defined type. 1784 */ 1785 RK_U32 osd_plt_typ : 1; 1786 RK_U32 reserved : 14; 1787 } reg112; 1788 1789 /* 1790 * OSD_INV 1791 * Address offset: 0x01C4 Access type: read and write 1792 * OSD color inverse configuration 1793 */ 1794 struct { 1795 /* Color inverse theshold for OSD region0. */ 1796 RK_U32 osd_ithd_r0 : 4; 1797 /* Color inverse theshold for OSD region1. */ 1798 RK_U32 osd_ithd_r1 : 4; 1799 /* Color inverse theshold for OSD region2. */ 1800 RK_U32 osd_ithd_r2 : 4; 1801 /* Color inverse theshold for OSD region3. */ 1802 RK_U32 osd_ithd_r3 : 4; 1803 /* Color inverse theshold for OSD region4. */ 1804 RK_U32 osd_ithd_r4 : 4; 1805 /* Color inverse theshold for OSD region5. */ 1806 RK_U32 osd_ithd_r5 : 4; 1807 /* Color inverse theshold for OSD region6. */ 1808 RK_U32 osd_ithd_r6 : 4; 1809 /* Color inverse theshold for OSD region7. */ 1810 RK_U32 osd_ithd_r7 : 4; 1811 } reg113; 1812 1813 /* 1814 * SYNT_REFM2_H264 1815 * Address offset: 0x01C8 Access type: read and write 1816 * Reference frame mark2 for H.264 1817 */ 1818 struct { 1819 /* long_term_frame_idx[0] (when mmco equal 3) */ 1820 RK_U32 long_term_frame_idx0 : 4; 1821 /* long_term_frame_idx[1] (when mmco equal 3) */ 1822 RK_U32 long_term_frame_idx1 : 4; 1823 /* long_term_frame_idx[2] (when mmco equal 3) */ 1824 RK_U32 long_term_frame_idx2 : 4; 1825 RK_U32 reserved : 20; 1826 } reg114; 1827 1828 /* 1829 * SYNT_REFM3 1830 * Address offset: 0x01CC Access type: read and write 1831 * Reference frame mark3 for HEVC 1832 */ 1833 RK_U32 reg115; 1834 1835 /* 1836 * OSD_POS 1837 * Address offset: 0x01D0~0x01EC Access type: read and write 1838 * OSD region position 1839 */ 1840 struct { 1841 Vepu541OsdPos osd_pos[8]; 1842 } reg116_123; 1843 1844 /* 1845 * ADR_OSD 1846 * Address offset: 0x01F0~0x20C Access type: read and write 1847 * Base address for OSD region, 16B aligned 1848 */ 1849 struct { 1850 RK_U32 osd_addr[8]; 1851 } reg124_131; 1852 1853 /* 1854 * ST_BSL 1855 * Address offset: 0x210 Access type: read only 1856 * Bit stream length for current frame 1857 */ 1858 struct { 1859 /* Bit stream length for current frame. */ 1860 RK_U32 bs_lgth : 27; 1861 RK_U32 reserved : 5; 1862 } reg132; 1863 1864 /* 1865 * ST_SSE_L32 1866 * Address offset: 0x214 Access type: read only 1867 * Low 32 bits of encoding distortion (SSE) 1868 */ 1869 struct { 1870 RK_U32 sse_l32; 1871 } reg133; 1872 1873 /* 1874 * ST_SSE_QP 1875 * Address offset: 0x218 Access type: read only 1876 * High 8 bits of encoding distortion (SSE) and sum of QP for the encoded frame 1877 */ 1878 struct { 1879 /* Sum of QP for the encoded frame. */ 1880 RK_U32 qp_sum : 22; 1881 RK_U32 reserved : 2; 1882 /* High bits of encoding distortion(SSE). */ 1883 RK_U32 sse_h8 : 8; 1884 } reg134; 1885 1886 /* 1887 * ST_SAO 1888 * Address offset: 0x21C Access type: read only 1889 * Number of CTUs which adjusted by SAO 1890 */ 1891 struct { 1892 /* Number of CTUs whose CHROMA component are adjusted by SAO. */ 1893 RK_U32 sao_cnum : 12; 1894 /* Number of CTUs whose LUMA component are adjusted by SAO. */ 1895 RK_U32 sao_ynum : 12; 1896 RK_U32 reserved : 8; 1897 } reg135; 1898 1899 /* reg gap 136~137 */ 1900 RK_U32 reg_136_137[2]; 1901 1902 /* 1903 * ST_ENC 1904 * Address offset: 0x228 Access type: read only 1905 * VEPU working status 1906 */ 1907 struct { 1908 /* 1909 * VEPU working status. 1910 * 2'h0: Idle. 1911 * 2'h1: Working in register conifguration mode. 1912 * 2'h2: Working in link table configuration mode. 1913 */ 1914 RK_U32 st_enc : 2; 1915 /* 1916 * Status of safe clear. 1917 * 1'h0: Safe clear is finished or not started. 1918 * 1'h1: VEPU is performing safe clear. 1919 */ 1920 RK_U32 st_sclr : 1; 1921 RK_U32 reserved : 29; 1922 } reg138; 1923 1924 /* 1925 * ST_LKT 1926 * Address offset: 0x22C Access type: read only 1927 * Status of link table mode encoding 1928 */ 1929 struct { 1930 /* Number of frames has been encoded since link table mode started. */ 1931 RK_U32 fnum_enc : 8; 1932 /* Number of frames has been configured since link table mode started. */ 1933 RK_U32 fnum_cfg : 8; 1934 /* 1935 * Number of frames has been encoded since link table mode started, 1936 * updated only when corresponding link table node send interrupt 1937 * (VEPU_ENC_PIC_node_int==1). 1938 */ 1939 RK_U32 fnum_int : 8; 1940 RK_U32 reserved : 8; 1941 } reg139; 1942 1943 /* 1944 * ST_NADR 1945 * Address offset: 0x230 Access type: read only 1946 * Address of the processing link table node 1947 */ 1948 struct { 1949 /* High 28 bits of the address for the processing linke table node. */ 1950 RK_U32 node_addr; 1951 } reg140; 1952 1953 /* 1954 * ST_BSB 1955 * Address offset: 0x234 Access type: read only 1956 * Status of bit stream buffer 1957 */ 1958 struct { 1959 /* High 28 bits of bit stream buffer write address. */ 1960 RK_U32 bsbw_addr; 1961 } reg141; 1962 1963 /* 1964 * ST_BUS 1965 * Address offset: 0x238 Access type: read only 1966 * VEPU bus status 1967 */ 1968 struct { 1969 /* 1970 * AXI write response idle. 1971 * [6]: Reconstructed picture channel (AXI0_WID==5) 1972 * [5]: ME information channel (AXI0_WID==4) 1973 * [4]: Co-located Mv channel (AXI0_WID==3) 1974 * [3]: Down-sampled picture channel (AXI0_WID==2) 1975 * [2]: Bit stream channel (AXI0_WID==1) 1976 * [1]: Link table node channel (AXI0_WID==0) 1977 * [0]: Reserved 1978 */ 1979 RK_U32 axib_idl : 7; 1980 /* 1981 * AXI write response outstanding overflow. 1982 * [6]: Reconstructed picture channel (AXI0_WID==5) 1983 * [5]: ME information channel (AXI0_WID==4) 1984 * [4]: Co-located Mv channel (AXI0_WID==3) 1985 * [3]: Down-sampled picture channel (AXI0_WID==2) 1986 * [2]: Bit stream channel (AXI0_WID==1) 1987 * [1]: Link table node channel (AXI0_WID==0) 1988 * [0]: Reserved. 1989 */ 1990 RK_U32 axib_ovfl : 7; 1991 /* 1992 * AXI write response error. 1993 * [6]: Reconstructed picture channel (AXI0_WID==5) 1994 * [5]: ME information channel (AXI0_WID==4) 1995 * [4]: Co-located Mv channel (AXI0_WID==3) 1996 * [3]: Down-sampled picture channel (AXI0_WID==2) 1997 * [2]: Bit stream channel (AXI0_WID==1) 1998 * [1]: Link table node channel (AXI0_WID==0) 1999 * [0]: Reserved. 2000 */ 2001 RK_U32 axib_err : 7; 2002 /* 2003 * AXI read error. 2004 * [5]: ROI configuration (AXI0_ARID==7) 2005 * [4]: Down-sampled picture (AXI0_ARID==6) 2006 * [3]: Co-located Mv (AXI0_ARID==5) 2007 * [2]: Link table (AXI0_ARID==4) 2008 * [1]: Reference picture (AXI0_ARID==1,2,3,8) 2009 * [0]: Video source load (AXI1) 2010 */ 2011 RK_U32 axir_err : 6; 2012 RK_U32 reserved : 5; 2013 } reg142; 2014 2015 /* 2016 * ST_SNUM 2017 * Address offset: 0x23C Access type: read only 2018 * Slice number status 2019 */ 2020 struct { 2021 /* Number for slices has been encoded and not read out (by reading ST_SLEN). */ 2022 RK_U32 sli_num : 6; 2023 RK_U32 reserved : 30; 2024 } reg143; 2025 2026 /* 2027 * ST_SLEN 2028 * Address offset: 0x240 Access type: read only 2029 * Status of slice length 2030 */ 2031 struct { 2032 /* Byte length for the earlist encoded slice which has not been read out( by reading VEPU_ST_SLEN). */ 2033 RK_U32 sli_len : 25; 2034 RK_U32 reserved : 7; 2035 } reg144; 2036 2037 /* 2038 * ST_PNUM_P64 2039 * Address offset: 0x244 Access type: read only 2040 * Number of 64x64 inter predicted blocks 2041 */ 2042 struct { 2043 /* Number of 64x64 inter predicted blocks. */ 2044 RK_U32 pnum_p64 : 12; 2045 RK_U32 reserved : 20; 2046 } reg145; 2047 2048 /* 2049 * ST_PNUM_P32 2050 * Address offset: 0x248 Access type: read only 2051 * Number of 32x32 inter predicted blocks 2052 */ 2053 struct { 2054 /* Number of 32x32 inter predicted blocks. */ 2055 RK_U32 pnum_p32 : 14; 2056 RK_U32 reserved : 18; 2057 } reg146; 2058 2059 /* 2060 * ST_PNUM_P16 2061 * Address offset: 0x24C Access type: read only 2062 * Number of 16x16 inter predicted blocks 2063 */ 2064 struct { 2065 /* Number of 16x16 inter predicted blocks. */ 2066 RK_U32 pnum_p16 : 16; 2067 RK_U32 reserved : 16; 2068 } reg147; 2069 2070 /* 2071 * ST_PNUM_P8 2072 * Address offset: 0x250 Access type: read only 2073 * Number of 8x8 inter predicted blocks 2074 */ 2075 struct { 2076 /* Number of 8x8 inter predicted blocks. */ 2077 RK_U32 pnum_p8 : 18; 2078 RK_U32 reserved : 14; 2079 } reg148; 2080 2081 /* 2082 * ST_PNUM_I32 2083 * Address offset: 0x254 Access type: read only 2084 * Number of 32x32 intra predicted blocks 2085 */ 2086 struct { 2087 /* Number of 32x32 intra predicted blocks. */ 2088 RK_U32 pnum_i32 : 14; 2089 RK_U32 reserved : 18; 2090 } reg149; 2091 2092 /* 2093 * ST_PNUM_I16 2094 * Address offset: 0x258 Access type: read only 2095 * Number of 16x16 intra predicted blocks 2096 */ 2097 struct { 2098 /* Number of 16x16 intra predicted blocks. */ 2099 RK_U32 pnum_i16 : 16; 2100 RK_U32 reserved : 16; 2101 } reg150; 2102 2103 /* 2104 * ST_PNUM_I8 2105 * Address offset: 0x25C Access type: read only 2106 * Number of 8x8 intra predicted blocks 2107 */ 2108 struct { 2109 /* Number of 8x8 intra predicted blocks. */ 2110 RK_U32 pnum_i8 : 18; 2111 RK_U32 reserved : 14; 2112 } reg151; 2113 2114 /* 2115 * ST_PNUM_I4 2116 * Address offset: 0x260 Access type: read only 2117 * Number of 4x4 intra predicted blocks 2118 */ 2119 struct { 2120 /* Number of 4x4 intra predicted blocks. */ 2121 RK_U32 pnum_i4 : 20; 2122 RK_U32 reserved : 12; 2123 } reg152; 2124 2125 /* 2126 * ST_B8_QP0~51 2127 * Address offset: 0x264~0x330 Access type: read only 2128 * Number of block8x8s with QP=0~51 2129 */ 2130 struct { 2131 /* 2132 * Number of block8x8s with QP value. 2133 * HEVC CUs of which size are bigger that 8x8 are considered as 2134 * (CU_size/8)*(CU_size/8) clock8x8s; 2135 * while H.264 MB is considered as 4 block8x8s. 2136 */ 2137 Vepu541B8NumQp num_qp[52]; 2138 } reg153_204; 2139 2140 /* 2141 * ST_CPLX_TMP 2142 * Address offset: 0x334 Access type: read only 2143 * Temporal complexity(MADP) for current encoding and reference frame 2144 */ 2145 struct { 2146 /* Mean absolute differences between current encoding and reference frame. */ 2147 RK_U32 madp; 2148 } reg205; 2149 2150 /* 2151 * ST_BNUM_CME 2152 * Address offset: 0x338 Access type: read only 2153 * Number of CME blocks in frame. 2154 * H.264: number CME blocks (4 MBs) in 16x64 aligned extended frame, 2155 * except for the CME blocks configured as force intra. 2156 * HEVC : number CME blocks (CTU) in 64x64 aligned extended frame, 2157 * except for the CME blocks configured as force intra. 2158 */ 2159 struct { 2160 /* Number of CTU (HEVC: 64x64; H.264: 64x16) for CME inter-frame prediction. */ 2161 RK_U32 num_ctu : 16; 2162 RK_U32 reserved : 16; 2163 } reg206; 2164 2165 /* 2166 * ST_CPLX_SPT 2167 * Address offset: 0x33C Access type: read only 2168 * Spatial complexity(MADI) for current encoding frame 2169 */ 2170 struct { 2171 /* Mean absolute differences for current encoding frame. */ 2172 RK_U32 madi; 2173 } reg207; 2174 2175 /* 2176 * ST_BNUM_B16 2177 * Address offset: 0x340 Access type: read only 2178 * Number of valid 16x16 blocks for one frame. 2179 */ 2180 struct { 2181 /* Number of valid 16x16 blocks for one frame. */ 2182 RK_U32 num_b16; 2183 } reg208; 2184 } Vepu541H264eRegSet; 2185 2186 /* return register is a subset of the whole register. */ 2187 typedef struct Vepu541H264eRegRet_t { 2188 /* 2189 * INT_STA 2190 * Address offset: 0x001c Access type: read and write, write one to clear 2191 * VEPU interrupt status 2192 */ 2193 struct { 2194 /* One frame encode finish interrupt status */ 2195 RK_U32 enc_done_sta : 1; 2196 /* Link table finish interrupt status */ 2197 RK_U32 lkt_done_sta : 1; 2198 /* Safe clear finish interrupt status */ 2199 RK_U32 sclr_done_sta : 1; 2200 /* One slice encode finish interrupt status */ 2201 RK_U32 enc_slice_done_sta : 1; 2202 /* Bit stream overflow interrupt status */ 2203 RK_U32 oflw_done_sta : 1; 2204 /* AXI write response fifo full interrupt status */ 2205 RK_U32 brsp_done_sta : 1; 2206 /* AXI write response channel error interrupt status */ 2207 RK_U32 berr_done_sta : 1; 2208 /* AXI read channel error interrupt status */ 2209 RK_U32 rerr_done_sta : 1; 2210 /* timeout error interrupt status */ 2211 RK_U32 wdg_done_sta : 1; 2212 RK_U32 reserved : 23; 2213 } hw_status; /* reg007 */ 2214 2215 /* 2216 * ST_BSL 2217 * Address offset: 0x210 Access type: read only 2218 * Bit stream length for current frame 2219 */ 2220 struct { 2221 /* Bit stream length for current frame. */ 2222 RK_U32 bs_lgth : 27; 2223 RK_U32 reserved : 5; 2224 } st_bsl; /* reg132 */ 2225 2226 /* 2227 * ST_SSE_L32 2228 * Address offset: 0x214 Access type: read only 2229 * Low 32 bits of encoding distortion (SSE) 2230 */ 2231 struct { 2232 RK_U32 sse_l32; 2233 } st_sse_l32; /* reg133 */ 2234 2235 /* 2236 * ST_SSE_QP 2237 * Address offset: 0x218 Access type: read only 2238 * High 8 bits of encoding distortion (SSE) and sum of QP for the encoded frame 2239 */ 2240 struct { 2241 /* Sum of QP for the encoded frame. */ 2242 RK_U32 qp_sum : 22; 2243 RK_U32 reserved : 2; 2244 /* High bits of encoding distortion(SSE). */ 2245 RK_U32 sse_h8 : 8; 2246 } st_sse_qp; /* reg134 */ 2247 2248 /* 2249 * ST_SAO 2250 * Address offset: 0x21C Access type: read only 2251 * Number of CTUs which adjusted by SAO 2252 */ 2253 struct { 2254 /* Number of CTUs whose CHROMA component are adjusted by SAO. */ 2255 RK_U32 sao_cnum : 12; 2256 /* Number of CTUs whose LUMA component are adjusted by SAO. */ 2257 RK_U32 sao_ynum : 12; 2258 RK_U32 reserved : 8; 2259 } st_sao; /* reg135 */ 2260 2261 /* reg gap 136~137 */ 2262 RK_U32 reg_136_137[2]; 2263 2264 /* 2265 * ST_ENC 2266 * Address offset: 0x228 Access type: read only 2267 * VEPU working status 2268 */ 2269 struct { 2270 /* 2271 * VEPU working status. 2272 * 2'h0: Idle. 2273 * 2'h1: Working in register conifguration mode. 2274 * 2'h2: Working in link table configuration mode. 2275 */ 2276 RK_U32 st_enc : 2; 2277 /* 2278 * Status of safe clear. 2279 * 1'h0: Safe clear is finished or not started. 2280 * 1'h1: VEPU is performing safe clear. 2281 */ 2282 RK_U32 st_sclr : 1; 2283 RK_U32 reserved : 29; 2284 } st_enc; /* reg138 */ 2285 2286 /* 2287 * ST_LKT 2288 * Address offset: 0x22C Access type: read only 2289 * Status of link table mode encoding 2290 */ 2291 struct { 2292 /* Number of frames has been encoded since link table mode started. */ 2293 RK_U32 fnum_enc : 8; 2294 /* Number of frames has been configured since link table mode started. */ 2295 RK_U32 fnum_cfg : 8; 2296 /* 2297 * Number of frames has been encoded since link table mode started, 2298 * updated only when corresponding link table node send interrupt 2299 * (VEPU_ENC_PIC_node_int==1). 2300 */ 2301 RK_U32 fnum_int : 8; 2302 RK_U32 reserved : 8; 2303 } st_lkt; /* reg139 */ 2304 2305 /* 2306 * ST_NADR 2307 * Address offset: 0x230 Access type: read only 2308 * Address of the processing link table node 2309 */ 2310 struct { 2311 /* High 28 bits of the address for the processing linke table node. */ 2312 RK_U32 node_addr; 2313 } ST_NADR; /* reg140 */ 2314 2315 /* 2316 * ST_BSB 2317 * Address offset: 0x234 Access type: read only 2318 * Status of bit stream buffer 2319 */ 2320 struct { 2321 /* High 28 bits of bit stream buffer write address. */ 2322 RK_U32 bsbw_addr; 2323 } st_bsb; /* reg141 */ 2324 2325 /* 2326 * ST_BUS 2327 * Address offset: 0x238 Access type: read only 2328 * VEPU bus status 2329 */ 2330 struct { 2331 /* 2332 * AXI write response idle. 2333 * [6]: Reconstructed picture channel (AXI0_WID==5) 2334 * [5]: ME information channel (AXI0_WID==4) 2335 * [4]: Co-located Mv channel (AXI0_WID==3) 2336 * [3]: Down-sampled picture channel (AXI0_WID==2) 2337 * [2]: Bit stream channel (AXI0_WID==1) 2338 * [1]: Link table node channel (AXI0_WID==0) 2339 * [0]: Reserved 2340 */ 2341 RK_U32 axib_idl : 7; 2342 /* 2343 * AXI write response outstanding overflow. 2344 * [6]: Reconstructed picture channel (AXI0_WID==5) 2345 * [5]: ME information channel (AXI0_WID==4) 2346 * [4]: Co-located Mv channel (AXI0_WID==3) 2347 * [3]: Down-sampled picture channel (AXI0_WID==2) 2348 * [2]: Bit stream channel (AXI0_WID==1) 2349 * [1]: Link table node channel (AXI0_WID==0) 2350 * [0]: Reserved. 2351 */ 2352 RK_U32 axib_ovfl : 7; 2353 /* 2354 * AXI write response error. 2355 * [6]: Reconstructed picture channel (AXI0_WID==5) 2356 * [5]: ME information channel (AXI0_WID==4) 2357 * [4]: Co-located Mv channel (AXI0_WID==3) 2358 * [3]: Down-sampled picture channel (AXI0_WID==2) 2359 * [2]: Bit stream channel (AXI0_WID==1) 2360 * [1]: Link table node channel (AXI0_WID==0) 2361 * [0]: Reserved. 2362 */ 2363 RK_U32 axib_err : 7; 2364 /* 2365 * AXI read error. 2366 * [5]: ROI configuration (AXI0_ARID==7) 2367 * [4]: Down-sampled picture (AXI0_ARID==6) 2368 * [3]: Co-located Mv (AXI0_ARID==5) 2369 * [2]: Link table (AXI0_ARID==4) 2370 * [1]: Reference picture (AXI0_ARID==1,2,3,8) 2371 * [0]: Video source load (AXI1) 2372 */ 2373 RK_U32 axir_err : 6; 2374 RK_U32 reserved : 5; 2375 } st_bus; /* reg142 */ 2376 2377 /* 2378 * ST_SNUM 2379 * Address offset: 0x23C Access type: read only 2380 * Slice number status 2381 */ 2382 RK_U32 st_slice_number; 2383 2384 /* 2385 * ST_SLEN 2386 * Address offset: 0x240 Access type: read only 2387 * Status of slice length 2388 */ 2389 RK_U32 st_slice_length; 2390 2391 /* 2392 * ST_PNUM_P64 2393 * Address offset: 0x244 Access type: read only 2394 * Number of 64x64 inter predicted blocks 2395 */ 2396 RK_U32 st_lvl64_inter_num; 2397 2398 /* 2399 * ST_PNUM_P32 2400 * Address offset: 0x248 Access type: read only 2401 * Number of 32x32 inter predicted blocks 2402 */ 2403 RK_U32 st_lvl32_inter_num; 2404 2405 /* 2406 * ST_PNUM_P16 2407 * Address offset: 0x24C Access type: read only 2408 * Number of 16x16 inter predicted blocks 2409 */ 2410 RK_U32 st_lvl16_inter_num; 2411 2412 /* 2413 * ST_PNUM_P8 2414 * Address offset: 0x250 Access type: read only 2415 * Number of 8x8 inter predicted blocks 2416 */ 2417 RK_U32 st_lvl8_inter_num; 2418 2419 /* 2420 * ST_PNUM_I32 2421 * Address offset: 0x254 Access type: read only 2422 * Number of 32x32 intra predicted blocks 2423 */ 2424 RK_U32 st_lvl32_intra_num; 2425 2426 /* 2427 * ST_PNUM_I16 2428 * Address offset: 0x258 Access type: read only 2429 * Number of 16x16 intra predicted blocks 2430 */ 2431 RK_U32 st_lvl16_intra_num; 2432 2433 /* 2434 * ST_PNUM_I8 2435 * Address offset: 0x25C Access type: read only 2436 * Number of 8x8 intra predicted blocks 2437 */ 2438 RK_U32 st_lvl8_intra_num; 2439 2440 /* 2441 * ST_PNUM_I4 2442 * Address offset: 0x260 Access type: read only 2443 * Number of 4x4 intra predicted blocks 2444 */ 2445 RK_U32 st_lvl4_intra_num; 2446 2447 /* 2448 * ST_B8_QP0~51 2449 * Address offset: 0x264~0x330 Access type: read only 2450 * Number of block8x8s with QP=0~51 2451 */ 2452 RK_U32 st_cu_num_qp[52]; 2453 2454 /* 2455 * ST_CPLX_TMP 2456 * Address offset: 0x334 Access type: read only 2457 * Temporal complexity(MADP) for current encoding and reference frame 2458 */ 2459 RK_U32 st_madp; 2460 2461 /* 2462 * ST_BNUM_CME 2463 * Address offset: 0x338 Access type: read only 2464 * Number of CME blocks in frame. 2465 * H.264: number CME blocks (4 MBs) in 16x64 aligned extended frame, 2466 * except for the CME blocks configured as force intra. 2467 * HEVC : number CME blocks (CTU) in 64x64 aligned extended frame, 2468 * except for the CME blocks configured as force intra. 2469 */ 2470 RK_U32 st_ctu_num; 2471 2472 /* 2473 * ST_CPLX_SPT 2474 * Address offset: 0x33C Access type: read only 2475 * Spatial complexity(MADI) for current encoding frame 2476 */ 2477 RK_U32 st_madi; 2478 2479 /* 2480 * ST_BNUM_B16 2481 * Address offset: 0x340 Access type: read only 2482 * Number of valid 16x16 blocks for one frame. 2483 */ 2484 RK_U32 st_mb_num; 2485 } Vepu541H264eRegRet; 2486 2487 #endif /* __HAL_H264E_VEPU541_REG_H__ */ 2488