1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #ifndef __EDID_H_ 15 #define __EDID_H_ 16 17 #include <div64.h> 18 #include <linux/types.h> 19 #include <drm_modes.h> 20 #include <i2c.h> 21 22 /* Size of the EDID data */ 23 #define EDID_SIZE 128 24 #define EDID_EXT_SIZE 256 25 #define MODE_LEN 240 26 27 #define CEA_EXT 0x02 28 #define VTB_EXT 0x10 29 #define DI_EXT 0x40 30 #define LS_EXT 0x50 31 #define MI_EXT 0x60 32 #define DISPLAYID_EXT 0x70 33 34 #define EDID_TIMING_ASPECT_SHIFT 6 35 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 36 37 /* need to add 60 */ 38 #define EDID_TIMING_VFREQ_SHIFT 0 39 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 40 41 /* OUI of HDMI vendor specific data block */ 42 #define HDMI_IEEE_OUI 0x000c03 43 44 /* drm mode 4k and 3d */ 45 #define DRM_MODE_FLAG_420_MASK (0x03 << 23) 46 #define DRM_MODE_FLAG_420 BIT(23) 47 #define DRM_MODE_FLAG_420_ONLY BIT(24) 48 49 #define BITS_PER_BYTE 8 50 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) 51 #define GET_BIT(_x, _pos) \ 52 (((_x) >> (_pos)) & 1) 53 #define GET_BITS(_x, _pos_msb, _pos_lsb) \ 54 (((_x) >> (_pos_lsb)) & ((1 << ((_pos_msb) - (_pos_lsb) + 1)) - 1)) 55 #define DRM_MODE(t, c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 56 .clock = (c), .type = (t),\ 57 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 58 .htotal = (ht), .vdisplay = (vd), \ 59 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 60 .vscan = (vs), .flags = (f) 61 62 #define DDC_SEGMENT_ADDR 0x30 63 #define DDC_ADDR 0x50 64 #define HDMI_EDID_BLOCK_SIZE 128 65 #define SCDC_I2C_SLAVE_ADDRESS 0x54 66 67 /* Aspect ratios used in EDID info. */ 68 enum edid_aspect { 69 ASPECT_625 = 0, 70 ASPECT_75, 71 ASPECT_8, 72 ASPECT_5625, 73 }; 74 75 struct est_timings { 76 u8 t1; 77 u8 t2; 78 u8 mfg_rsvd; 79 } __packed; 80 81 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 82 #define EDID_TIMING_ASPECT_SHIFT 6 83 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 84 85 /* need to add 60 */ 86 #define EDID_TIMING_VFREQ_SHIFT 0 87 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 88 89 struct std_timing { 90 u8 hsize; /* need to multiply by 8 then add 248 */ 91 u8 vfreq_aspect; 92 } __packed; 93 94 struct detailed_pixel_timing { 95 u8 hactive_lo; 96 u8 hblank_lo; 97 u8 hactive_hblank_hi; 98 u8 vactive_lo; 99 u8 vblank_lo; 100 u8 vactive_vblank_hi; 101 u8 hsync_offset_lo; 102 u8 hsync_pulse_width_lo; 103 u8 vsync_offset_pulse_width_lo; 104 u8 hsync_vsync_offset_pulse_width_hi; 105 u8 width_mm_lo; 106 u8 height_mm_lo; 107 u8 width_height_mm_hi; 108 u8 hborder; 109 u8 vborder; 110 u8 misc; 111 } __packed; 112 113 /* If it's not pixel timing, it'll be one of the below */ 114 struct detailed_data_string { 115 u8 str[13]; 116 } __packed; 117 118 struct detailed_data_monitor_range { 119 u8 min_vfreq; 120 u8 max_vfreq; 121 u8 min_hfreq_khz; 122 u8 max_hfreq_khz; 123 u8 pixel_clock_mhz; /* need to multiply by 10 */ 124 u8 flags; 125 union { 126 struct { 127 u8 reserved; 128 u8 hfreq_start_khz; /* need to multiply by 2 */ 129 u8 c; /* need to divide by 2 */ 130 __le16 m; 131 u8 k; 132 u8 j; /* need to divide by 2 */ 133 } __packed gtf2; 134 struct { 135 u8 version; 136 u8 data1; /* high 6 bits: extra clock resolution */ 137 u8 data2; /* plus low 2 of above: max hactive */ 138 u8 supported_aspects; 139 u8 flags; /* preferred aspect and blanking support */ 140 u8 supported_scalings; 141 u8 preferred_refresh; 142 } __packed cvt; 143 } formula; 144 } __packed; 145 146 struct detailed_data_wpindex { 147 u8 white_yx_lo; /* Lower 2 bits each */ 148 u8 white_x_hi; 149 u8 white_y_hi; 150 u8 gamma; /* need to divide by 100 then add 1 */ 151 } __packed; 152 153 struct detailed_data_color_point { 154 u8 windex1; 155 u8 wpindex1[3]; 156 u8 windex2; 157 u8 wpindex2[3]; 158 } __packed; 159 160 struct cvt_timing { 161 u8 code[3]; 162 } __packed; 163 164 struct detailed_non_pixel { 165 u8 pad1; 166 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 167 * fb=color point data, fa=standard timing data, 168 * f9=undefined, f8=mfg. reserved 169 */ 170 u8 pad2; 171 union { 172 struct detailed_data_string str; 173 struct detailed_data_monitor_range range; 174 struct detailed_data_wpindex color; 175 struct std_timing timings[6]; 176 struct cvt_timing cvt[4]; 177 } data; 178 } __packed; 179 180 #define EDID_DETAIL_EST_TIMINGS 0xf7 181 #define EDID_DETAIL_CVT_3BYTE 0xf8 182 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 183 #define EDID_DETAIL_STD_MODES 0xfa 184 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 185 #define EDID_DETAIL_MONITOR_NAME 0xfc 186 #define EDID_DETAIL_MONITOR_RANGE 0xfd 187 #define EDID_DETAIL_MONITOR_STRING 0xfe 188 #define EDID_DETAIL_MONITOR_SERIAL 0xff 189 190 struct detailed_timing { 191 __le16 pixel_clock; /* need to multiply by 10 KHz */ 192 union { 193 struct detailed_pixel_timing pixel_data; 194 struct detailed_non_pixel other_data; 195 } data; 196 } __packed; 197 198 /* Detailed timing information used in EDID v1.x */ 199 struct edid_detailed_timing { 200 unsigned char pixel_clock[2]; 201 #define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \ 202 (((((uint32_t)(_x).pixel_clock[1]) << 8) + \ 203 (_x).pixel_clock[0]) * 10000) 204 unsigned char horizontal_active; 205 unsigned char horizontal_blanking; 206 unsigned char horizontal_active_blanking_hi; 207 #define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \ 208 ((GET_BITS((_x).horizontal_active_blanking_hi, 7, 4) << 8) + \ 209 (_x).horizontal_active) 210 #define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \ 211 ((GET_BITS((_x).horizontal_active_blanking_hi, 3, 0) << 8) + \ 212 (_x).horizontal_blanking) 213 unsigned char vertical_active; 214 unsigned char vertical_blanking; 215 unsigned char vertical_active_blanking_hi; 216 #define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \ 217 ((GET_BITS((_x).vertical_active_blanking_hi, 7, 4) << 8) + \ 218 (_x).vertical_active) 219 #define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \ 220 ((GET_BITS((_x).vertical_active_blanking_hi, 3, 0) << 8) + \ 221 (_x).vertical_blanking) 222 unsigned char hsync_offset; 223 unsigned char hsync_pulse_width; 224 unsigned char vsync_offset_pulse_width; 225 unsigned char hsync_vsync_offset_pulse_width_hi; 226 #define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \ 227 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \ 228 (_x).hsync_offset) 229 #define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \ 230 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 5, 4) << 8) + \ 231 (_x).hsync_pulse_width) 232 #define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \ 233 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 3, 2) << 4) + \ 234 GET_BITS((_x).vsync_offset_pulse_width, 7, 4)) 235 #define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \ 236 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 1, 0) << 4) + \ 237 GET_BITS((_x).vsync_offset_pulse_width, 3, 0)) 238 unsigned char himage_size; 239 unsigned char vimage_size; 240 unsigned char himage_vimage_size_hi; 241 #define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \ 242 ((GET_BITS((_x).himage_vimage_size_hi, 7, 4) << 8) + (_x).himage_size) 243 #define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \ 244 ((GET_BITS((_x).himage_vimage_size_hi, 3, 0) << 8) + (_x).vimage_size) 245 unsigned char hborder; 246 unsigned char vborder; 247 unsigned char flags; 248 #define EDID_DETAILED_TIMING_FLAG_INTERLACED(_x) \ 249 GET_BIT((_x).flags, 7) 250 #define EDID_DETAILED_TIMING_FLAG_STEREO(_x) \ 251 GET_BITS((_x).flags, 6, 5) 252 #define EDID_DETAILED_TIMING_FLAG_DIGITAL_COMPOSITE(_x) \ 253 GET_BITS((_x).flags, 4, 3) 254 #define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \ 255 GET_BITS((_x).flags, 2, 1) 256 #define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \ 257 GET_BIT((_x).flags, 2) 258 #define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \ 259 GET_BIT((_x).flags, 1) 260 #define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \ 261 GET_BIT((_x).flags, 0) 262 } __attribute__ ((__packed__)); 263 264 enum edid_monitor_descriptor_types { 265 EDID_MONITOR_DESCRIPTOR_SERIAL = 0xff, 266 EDID_MONITOR_DESCRIPTOR_ASCII = 0xfe, 267 EDID_MONITOR_DESCRIPTOR_RANGE = 0xfd, 268 EDID_MONITOR_DESCRIPTOR_NAME = 0xfc, 269 }; 270 271 struct edid_monitor_descriptor { 272 uint16_t zero_flag_1; 273 unsigned char zero_flag_2; 274 unsigned char type; 275 unsigned char zero_flag_3; 276 union { 277 char string[13]; 278 struct { 279 unsigned char vertical_min; 280 unsigned char vertical_max; 281 unsigned char horizontal_min; 282 unsigned char horizontal_max; 283 unsigned char pixel_clock_max; 284 unsigned char gtf_data[8]; 285 } range_data; 286 } data; 287 } __attribute__ ((__packed__)); 288 289 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 290 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 291 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 292 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 293 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 294 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 295 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 296 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 297 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 298 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 299 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 300 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 301 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 302 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 303 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 304 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 305 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 306 #define DRM_EDID_DIGITAL_TYPE_DVI (1) 307 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 308 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 309 #define DRM_EDID_DIGITAL_TYPE_MDDI (4) 310 #define DRM_EDID_DIGITAL_TYPE_DP (5) 311 312 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 313 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 314 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 315 /* If analog */ 316 /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 317 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) 318 /* If digital */ 319 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 320 #define DRM_EDID_FEATURE_RGB (0 << 3) 321 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 322 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 323 /* both 4:4:4 and 4:2:2 */ 324 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) 325 326 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 327 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 328 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 329 330 #define DRM_EDID_HDMI_DC_48 (1 << 6) 331 #define DRM_EDID_HDMI_DC_36 (1 << 5) 332 #define DRM_EDID_HDMI_DC_30 (1 << 4) 333 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 334 335 /* YCBCR 420 deep color modes */ 336 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 337 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 338 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 339 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 340 DRM_EDID_YCBCR420_DC_36 | \ 341 DRM_EDID_YCBCR420_DC_30) 342 343 /* HDMI 2.1 additional fields */ 344 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 345 #define DRM_EDID_FAPA_START_LOCATION BIT(0) 346 #define DRM_EDID_ALLM BIT(1) 347 #define DRM_EDID_FVA BIT(2) 348 349 /* Deep Color specific */ 350 #define DRM_EDID_DC_30BIT_420 BIT(0) 351 #define DRM_EDID_DC_36BIT_420 BIT(1) 352 #define DRM_EDID_DC_48BIT_420 BIT(2) 353 354 /* VRR specific */ 355 #define DRM_EDID_CNMVRR BIT(3) 356 #define DRM_EDID_CINEMA_VRR BIT(4) 357 #define DRM_EDID_MDELTA BIT(5) 358 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 359 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 360 #define DRM_EDID_VRR_MIN_MASK 0x3f 361 362 /* DSC specific */ 363 #define DRM_EDID_DSC_10BPC BIT(0) 364 #define DRM_EDID_DSC_12BPC BIT(1) 365 #define DRM_EDID_DSC_16BPC BIT(2) 366 #define DRM_EDID_DSC_ALL_BPP BIT(3) 367 #define DRM_EDID_DSC_NATIVE_420 BIT(6) 368 #define DRM_EDID_DSC_1P2 BIT(7) 369 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 370 #define DRM_EDID_DSC_MAX_SLICES 0xf 371 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 372 373 struct edid1_info { 374 unsigned char header[8]; 375 unsigned char manufacturer_name[2]; 376 #define EDID1_INFO_MANUFACTURER_NAME_ZERO(_x) \ 377 GET_BIT(((_x).manufacturer_name[0]), 7) 378 #define EDID1_INFO_MANUFACTURER_NAME_CHAR1(_x) \ 379 GET_BITS(((_x).manufacturer_name[0]), 6, 2) 380 #define EDID1_INFO_MANUFACTURER_NAME_CHAR2(_x) \ 381 ((GET_BITS(((_x).manufacturer_name[0]), 1, 0) << 3) + \ 382 GET_BITS(((_x).manufacturer_name[1]), 7, 5)) 383 #define EDID1_INFO_MANUFACTURER_NAME_CHAR3(_x) \ 384 GET_BITS(((_x).manufacturer_name[1]), 4, 0) 385 unsigned char product_code[2]; 386 #define EDID1_INFO_PRODUCT_CODE(_x) \ 387 (((uint16_t)(_x).product_code[1] << 8) + (_x).product_code[0]) 388 unsigned char serial_number[4]; 389 #define EDID1_INFO_SERIAL_NUMBER(_x) \ 390 (((uint32_t)(_x).serial_number[3] << 24) + \ 391 ((_x).serial_number[2] << 16) + ((_x).serial_number[1] << 8) + \ 392 (_x).serial_number[0]) 393 unsigned char week; 394 unsigned char year; 395 unsigned char version; 396 unsigned char revision; 397 unsigned char video_input_definition; 398 #define EDID1_INFO_VIDEO_INPUT_DIGITAL(_x) \ 399 GET_BIT(((_x).video_input_definition), 7) 400 #define EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(_x) \ 401 GET_BITS(((_x).video_input_definition), 6, 5) 402 #define EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(_x) \ 403 GET_BIT(((_x).video_input_definition), 4) 404 #define EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(_x) \ 405 GET_BIT(((_x).video_input_definition), 3) 406 #define EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(_x) \ 407 GET_BIT(((_x).video_input_definition), 2) 408 #define EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(_x) \ 409 GET_BIT(((_x).video_input_definition), 1) 410 #define EDID1_INFO_VIDEO_INPUT_SERRATION_V(_x) \ 411 GET_BIT(((_x).video_input_definition), 0) 412 unsigned char max_size_horizontal; 413 unsigned char max_size_vertical; 414 unsigned char gamma; 415 unsigned char feature_support; 416 #define EDID1_INFO_FEATURE_STANDBY(_x) \ 417 GET_BIT(((_x).feature_support), 7) 418 #define EDID1_INFO_FEATURE_SUSPEND(_x) \ 419 GET_BIT(((_x).feature_support), 6) 420 #define EDID1_INFO_FEATURE_ACTIVE_OFF(_x) \ 421 GET_BIT(((_x).feature_support), 5) 422 #define EDID1_INFO_FEATURE_DISPLAY_TYPE(_x) \ 423 GET_BITS(((_x).feature_support), 4, 3) 424 #define EDID1_INFO_FEATURE_RGB(_x) \ 425 GET_BIT(((_x).feature_support), 2) 426 #define EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(_x) \ 427 GET_BIT(((_x).feature_support), 1) 428 #define EDID1_INFO_FEATURE_DEFAULT_GTF_SUPPORT(_x) \ 429 GET_BIT(((_x).feature_support), 0) 430 unsigned char color_characteristics[10]; 431 unsigned char established_timings[3]; 432 #define EDID1_INFO_ESTABLISHED_TIMING_720X400_70(_x) \ 433 GET_BIT(((_x).established_timings[0]), 7) 434 #define EDID1_INFO_ESTABLISHED_TIMING_720X400_88(_x) \ 435 GET_BIT(((_x).established_timings[0]), 6) 436 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_60(_x) \ 437 GET_BIT(((_x).established_timings[0]), 5) 438 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_67(_x) \ 439 GET_BIT(((_x).established_timings[0]), 4) 440 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_72(_x) \ 441 GET_BIT(((_x).established_timings[0]), 3) 442 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_75(_x) \ 443 GET_BIT(((_x).established_timings[0]), 2) 444 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_56(_x) \ 445 GET_BIT(((_x).established_timings[0]), 1) 446 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_60(_x) \ 447 GET_BIT(((_x).established_timings[0]), 0) 448 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_72(_x) \ 449 GET_BIT(((_x).established_timings[1]), 7) 450 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_75(_x) \ 451 GET_BIT(((_x).established_timings[1]), 6) 452 #define EDID1_INFO_ESTABLISHED_TIMING_832X624_75(_x) \ 453 GET_BIT(((_x).established_timings[1]), 5) 454 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(_x) \ 455 GET_BIT(((_x).established_timings[1]), 4) 456 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(_x) \ 457 GET_BIT(((_x).established_timings[1]), 3) 458 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(_x) \ 459 GET_BIT(((_x).established_timings[1]), 2) 460 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(_x) \ 461 GET_BIT(((_x).established_timings[1]), 1) 462 #define EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(_x) \ 463 GET_BIT(((_x).established_timings[1]), 0) 464 #define EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(_x) \ 465 GET_BIT(((_x).established_timings[2]), 7) 466 struct { 467 unsigned char xresolution; 468 unsigned char aspect_vfreq; 469 } __attribute__((__packed__)) standard_timings[8]; 470 #define EDID1_INFO_STANDARD_TIMING_XRESOLUTION(_x, _i) \ 471 (((_x).standard_timings[_i]).xresolution) 472 #define EDID1_INFO_STANDARD_TIMING_ASPECT(_x, _i) \ 473 GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 7, 6) 474 #define EDID1_INFO_STANDARD_TIMING_VFREQ(_x, _i) \ 475 GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 5, 0) 476 union { 477 unsigned char timing[72]; 478 struct edid_monitor_descriptor descriptor[4]; 479 } monitor_details; 480 unsigned char extension_flag; 481 unsigned char checksum; 482 } __attribute__ ((__packed__)); 483 484 enum edid_cea861_db_types { 485 EDID_CEA861_DB_AUDIO = 0x01, 486 EDID_CEA861_DB_VIDEO = 0x02, 487 EDID_CEA861_DB_VENDOR = 0x03, 488 EDID_CEA861_DB_SPEAKER = 0x04, 489 EDID_CEA861_DB_USE_EXTENDED = 0x07, 490 }; 491 492 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 493 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 494 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 495 #define EDID_BASIC_AUDIO BIT(6) 496 #define EDID_CEA_YCRCB444 BIT(5) 497 #define EDID_CEA_YCRCB422 BIT(4) 498 #define EDID_CEA_VCDB_QS BIT(6) 499 500 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 501 502 struct edid_cea861_info { 503 unsigned char extension_tag; 504 #define EDID_CEA861_EXTENSION_TAG 0x02 505 unsigned char revision; 506 unsigned char dtd_offset; 507 unsigned char dtd_count; 508 #define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \ 509 GET_BIT(((_x).dtd_count), 7) 510 #define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \ 511 GET_BIT(((_x).dtd_count), 6) 512 #define EDID_CEA861_SUPPORTS_YUV444(_x) \ 513 GET_BIT(((_x).dtd_count), 5) 514 #define EDID_CEA861_SUPPORTS_YUV422(_x) \ 515 GET_BIT(((_x).dtd_count), 4) 516 #define EDID_CEA861_DTD_COUNT(_x) \ 517 GET_BITS(((_x).dtd_count), 3, 0) 518 unsigned char data[124]; 519 #define EDID_CEA861_DB_TYPE(_x, offset) \ 520 GET_BITS((_x).data[offset], 7, 5) 521 #define EDID_CEA861_DB_LEN(_x, offset) \ 522 GET_BITS((_x).data[offset], 4, 0) 523 } __attribute__ ((__packed__)); 524 525 #define DATA_BLOCK_PRODUCT_ID 0x00 526 #define DATA_BLOCK_DISPLAY_PARAMETERS 0x01 527 #define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02 528 #define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03 529 #define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04 530 #define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05 531 #define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06 532 #define DATA_BLOCK_VESA_TIMING 0x07 533 #define DATA_BLOCK_CEA_TIMING 0x08 534 #define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09 535 #define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a 536 #define DATA_BLOCK_GP_ASCII_STRING 0x0b 537 #define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c 538 #define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d 539 #define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e 540 #define DATA_BLOCK_DISPLAY_INTERFACE 0x0f 541 #define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10 542 #define DATA_BLOCK_TILED_DISPLAY 0x12 543 544 struct displayid_hdr { 545 u8 rev; 546 u8 bytes; 547 u8 prod_id; 548 u8 ext_count; 549 } __packed; 550 551 struct displayid_block { 552 u8 tag; 553 u8 rev; 554 u8 num_bytes; 555 } __packed; 556 557 struct displayid_detailed_timings_1 { 558 u8 pixel_clock[3]; 559 u8 flags; 560 u8 hactive[2]; 561 u8 hblank[2]; 562 u8 hsync[2]; 563 u8 hsw[2]; 564 u8 vactive[2]; 565 u8 vblank[2]; 566 u8 vsync[2]; 567 u8 vsw[2]; 568 } __packed; 569 570 struct displayid_detailed_timing_block { 571 struct displayid_block base; 572 struct displayid_detailed_timings_1 timings[0]; 573 }; 574 575 /** 576 * struct drm_scrambling: sink's scrambling support. 577 */ 578 struct drm_scrambling { 579 /** 580 * @supported: scrambling supported for rates > 340 Mhz. 581 */ 582 bool supported; 583 /** 584 * @low_rates: scrambling supported for rates <= 340 Mhz. 585 */ 586 bool low_rates; 587 }; 588 589 /** 590 * struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink 591 * 592 * Provides SCDC register support and capabilities related information on a 593 * HDMI 2.0 sink. In case of a HDMI 1.4 sink, all parameter must be 0. 594 */ 595 596 struct drm_scdc { 597 /** 598 * @supported: status control & data channel present. 599 */ 600 bool supported; 601 /** 602 * @read_request: sink is capable of generating scdc read request. 603 */ 604 bool read_request; 605 /** 606 * @scrambling: sink's scrambling capabilities 607 */ 608 struct drm_scrambling scrambling; 609 }; 610 611 /** 612 * struct drm_hdmi_dsc_cap - DSC capabilities of HDMI sink 613 * 614 * Describes the DSC support provided by HDMI 2.1 sink. 615 * The information is fetched fom additional HFVSDB blocks defined 616 * for HDMI 2.1. 617 */ 618 struct drm_hdmi_dsc_cap { 619 /** @v_1p2: flag for dsc1.2 version support by sink */ 620 bool v_1p2; 621 622 /** @native_420: Does sink support DSC with 4:2:0 compression */ 623 bool native_420; 624 625 /** 626 * @all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2 627 * compressed formats 628 */ 629 bool all_bpp; 630 631 /** 632 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 633 */ 634 u8 bpc_supported; 635 636 /** @max_slices: maximum number of Horizontal slices supported by */ 637 u8 max_slices; 638 639 /** @clk_per_slice : max pixel clock in MHz supported per slice */ 640 int clk_per_slice; 641 642 /** @max_lanes : dsc max lanes supported for Fixed rate Link training */ 643 u8 max_lanes; 644 645 /** @max_frl_rate_per_lane : maximum frl rate with DSC per lane */ 646 u8 max_frl_rate_per_lane; 647 648 /** @total_chunk_kbytes: max size of chunks in KBs supported per line*/ 649 u8 total_chunk_kbytes; 650 }; 651 652 /** 653 * struct drm_hdmi_info - runtime information about the connected HDMI sink 654 * 655 * Describes if a given display supports advanced HDMI 2.0 features. 656 * This information is available in CEA-861-F extension blocks (like HF-VSDB). 657 */ 658 struct drm_hdmi_info { 659 struct drm_scdc scdc; 660 661 /** 662 * @y420_vdb_modes: bitmap of modes which can support ycbcr420 663 * output only (not normal RGB/YCBCR444/422 outputs). There are total 664 * 107 VICs defined by CEA-861-F spec, so the size is 128 bits to map 665 * upto 128 VICs; 666 */ 667 unsigned long y420_vdb_modes[BITS_TO_LONGS(128)]; 668 669 /** 670 * @y420_cmdb_modes: bitmap of modes which can support ycbcr420 671 * output also, along with normal HDMI outputs. There are total 107 672 * VICs defined by CEA-861-F spec, so the size is 128 bits to map upto 673 * 128 VICs; 674 */ 675 unsigned long y420_cmdb_modes[BITS_TO_LONGS(128)]; 676 677 /** @y420_cmdb_map: bitmap of SVD index, to extraxt vcb modes */ 678 u64 y420_cmdb_map; 679 680 /** @y420_dc_modes: bitmap of deep color support index */ 681 u8 y420_dc_modes; 682 683 /** @max_frl_rate_per_lane: support fixed rate link */ 684 u8 max_frl_rate_per_lane; 685 686 /** @max_lanes: supported by sink */ 687 u8 max_lanes; 688 689 /* @add_func: support hdmi2.1 function */ 690 u8 add_func; 691 692 /** @dsc_cap: DSC capabilities of the sink */ 693 struct drm_hdmi_dsc_cap dsc_cap; 694 }; 695 696 enum subpixel_order { 697 subpixelunknown = 0, 698 subpixelhorizontalrgb, 699 subpixelhorizontalbgr, 700 subpixelverticalrgb, 701 subpixelverticalbgr, 702 subpixelnone, 703 }; 704 705 #define DRM_COLOR_FORMAT_RGB444 BIT(0) 706 #define DRM_COLOR_FORMAT_YCRCB444 BIT(1) 707 #define DRM_COLOR_FORMAT_YCRCB422 BIT(2) 708 #define DRM_COLOR_FORMAT_YCRCB420 BIT(3) 709 710 /* 711 * Describes a given display (e.g. CRT or flat panel) and its limitations. 712 */ 713 struct drm_display_info { 714 char name[32]; 715 716 /* Physical size */ 717 unsigned int width_mm; 718 unsigned int height_mm; 719 720 /* Clock limits FIXME: storage format */ 721 unsigned int min_vfreq, max_vfreq; 722 unsigned int min_hfreq, max_hfreq; 723 unsigned int pixel_clock; 724 unsigned int bpc; 725 726 enum subpixel_order subpixel_order; 727 u32 color_formats; 728 729 const u32 *bus_formats; 730 unsigned int num_bus_formats; 731 732 /** 733 * @max_tmds_clock: Maximum TMDS clock rate supported by the 734 * sink in kHz. 0 means undefined. 735 */ 736 int max_tmds_clock; 737 738 /** 739 * @dvi_dual: Dual-link DVI sink? 740 */ 741 bool dvi_dual; 742 743 /* Mask of supported hdmi deep color modes */ 744 u8 edid_hdmi_dc_modes; 745 746 u8 cea_rev; 747 748 /** 749 * @hdmi: advance features of a HDMI sink. 750 */ 751 struct drm_hdmi_info hdmi; 752 }; 753 754 struct edid { 755 u8 header[8]; 756 /* Vendor & product info */ 757 u8 mfg_id[2]; 758 u8 prod_code[2]; 759 u32 serial; /* FIXME: byte order */ 760 u8 mfg_week; 761 u8 mfg_year; 762 /* EDID version */ 763 u8 version; 764 u8 revision; 765 /* Display info: */ 766 u8 input; 767 u8 width_cm; 768 u8 height_cm; 769 u8 gamma; 770 u8 features; 771 /* Color characteristics */ 772 u8 red_green_lo; 773 u8 black_white_lo; 774 u8 red_x; 775 u8 red_y; 776 u8 green_x; 777 u8 green_y; 778 u8 blue_x; 779 u8 blue_y; 780 u8 white_x; 781 u8 white_y; 782 /* Est. timings and mfg rsvd timings*/ 783 struct est_timings established_timings; 784 /* Standard timings 1-8*/ 785 struct std_timing standard_timings[8]; 786 /* Detailing timings 1-4 */ 787 struct detailed_timing detailed_timings[4]; 788 /* Number of 128 byte ext. blocks */ 789 u8 extensions; 790 /* Checksum */ 791 u8 checksum; 792 } __packed; 793 794 enum base_output_format { 795 DRM_HDMI_OUTPUT_DEFAULT_RGB, /* default RGB */ 796 DRM_HDMI_OUTPUT_YCBCR444, /* YCBCR 444 */ 797 DRM_HDMI_OUTPUT_YCBCR422, /* YCBCR 422 */ 798 DRM_HDMI_OUTPUT_YCBCR420, /* YCBCR 420 */ 799 /* (YCbCr444 > YCbCr422 > YCbCr420 > RGB) */ 800 DRM_HDMI_OUTPUT_YCBCR_HQ, 801 /* (YCbCr420 > YCbCr422 > YCbCr444 > RGB) */ 802 DRM_HDMI_OUTPUT_YCBCR_LQ, 803 DRM_HDMI_OUTPUT_INVALID, /* Guess what ? */ 804 }; 805 806 enum base_output_depth { 807 AUTOMATIC = 0, 808 DEPTH_24BIT = 8, 809 DEPTH_30BIT = 10, 810 }; 811 812 struct base_bcsh_info { 813 unsigned short brightness; 814 unsigned short contrast; 815 unsigned short saturation; 816 unsigned short hue; 817 }; 818 819 struct base_overscan { 820 unsigned int maxvalue; 821 unsigned short leftscale; 822 unsigned short rightscale; 823 unsigned short topscale; 824 unsigned short bottomscale; 825 }; 826 827 struct base_drm_display_mode { 828 int clock; /* in kHz */ 829 int hdisplay; 830 int hsync_start; 831 int hsync_end; 832 int htotal; 833 int vdisplay; 834 int vsync_start; 835 int vsync_end; 836 int vtotal; 837 int vrefresh; 838 int vscan; 839 unsigned int flags; 840 int picture_aspect_ratio; 841 }; 842 843 struct base_screen_info { 844 int type; 845 struct base_drm_display_mode mode; /* 52 bytes */ 846 enum base_output_format format; /* 4 bytes */ 847 enum base_output_depth depth; /* 4 bytes */ 848 unsigned int feature; /* 4 bytes */ 849 }; 850 851 struct base_disp_info { 852 struct base_screen_info screen_list[5]; 853 struct base_overscan scan; /* 12 bytes */ 854 }; 855 856 struct base2_cubic_lut_data { 857 u16 size; 858 u16 lred[4913]; 859 u16 lgreen[4913]; 860 u16 lblue[4913]; 861 }; 862 863 struct base2_screen_info { 864 u32 type; 865 u32 id; 866 struct base_drm_display_mode resolution; 867 enum base_output_format format; 868 enum base_output_depth depthc; 869 u32 feature; 870 }; 871 872 struct base2_gamma_lut_data { 873 u16 size; 874 u16 lred[1024]; 875 u16 lgreen[1024]; 876 u16 lblue[1024]; 877 }; 878 879 struct framebuffer_info { 880 u32 framebuffer_width; 881 u32 framebuffer_height; 882 u32 fps; 883 }; 884 885 struct csc_info { 886 u16 hue; 887 u16 saturation; 888 u16 contrast; 889 u16 brightness; 890 u16 r_gain; 891 u16 g_gain; 892 u16 b_gain; 893 u16 r_offset; 894 u16 g_offset; 895 u16 b_offset; 896 u16 csc_enable; 897 }; 898 899 900 #define ACM_GAIN_LUT_HY_LENGTH (9*17) 901 #define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3) 902 #define ACM_GAIN_LUT_HS_LENGTH (13*17) 903 #define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3) 904 #define ACM_DELTA_LUT_H_LENGTH 65 905 #define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3) 906 907 struct acm_data { 908 s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH]; 909 s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH]; 910 s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH]; 911 u16 y_gain; 912 u16 h_gain; 913 u16 s_gain; 914 u16 acm_enable; 915 }; 916 917 struct base2_disp_info { 918 char disp_head_flag[6]; 919 struct base2_screen_info screen_info[4]; 920 struct base_bcsh_info bcsh_info; 921 struct base_overscan overscan_info; 922 struct base2_gamma_lut_data gamma_lut_data; 923 struct base2_cubic_lut_data cubic_lut_data; 924 struct framebuffer_info framebuffer_info; 925 u32 cacm_header; 926 u32 reserved[243]; 927 u32 crc; 928 /* baseparameter version 3.0 add */ 929 struct csc_info csc_info; 930 struct acm_data acm_data; 931 u8 resv2[10*1024]; /* */ 932 u32 crc2; 933 /* baseparameter version 3.0 add */ 934 }; 935 936 struct base2_disp_header { 937 u32 connector_type; 938 u32 connector_id; 939 u32 offset; 940 }; 941 942 struct base2_info { 943 char head_flag[4]; 944 u16 major_version; 945 u16 minor_version; 946 struct base2_disp_header disp_header[8]; 947 struct base2_disp_info disp_info[8]; 948 }; 949 950 /** 951 * Print the EDID info. 952 * 953 * @param edid_info The EDID info to be printed 954 */ 955 void edid_print_info(struct edid1_info *edid_info); 956 957 /** 958 * Check the EDID info. 959 * 960 * @param info The EDID info to be checked 961 * @return 0 on valid, or -1 on invalid 962 */ 963 int edid_check_info(struct edid1_info *info); 964 965 /** 966 * Check checksum of a 128 bytes EDID data block 967 * 968 * @param edid_block EDID block data 969 * 970 * @return 0 on success, or a negative errno on error 971 */ 972 int edid_check_checksum(u8 *edid_block); 973 974 /** 975 * Get the horizontal and vertical rate ranges of the monitor. 976 * 977 * @param edid The EDID info 978 * @param hmin Returns the minimum horizontal rate 979 * @param hmax Returns the maximum horizontal rate 980 * @param vmin Returns the minimum vertical rate 981 * @param vmax Returns the maximum vertical rate 982 * @return 0 on success, or -1 on error 983 */ 984 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 985 unsigned int *hmax, unsigned int *vmin, 986 unsigned int *vmax); 987 988 struct drm_display_mode; 989 struct display_timing; 990 991 struct hdmi_edid_data { 992 struct drm_display_mode *preferred_mode; 993 int modes; 994 struct drm_display_mode *mode_buf; 995 struct drm_display_info display_info; 996 }; 997 998 struct ddc_adapter { 999 int (*ddc_xfer)(struct ddc_adapter *adap, struct i2c_msg *msgs, 1000 int num); 1001 struct udevice *i2c_bus; 1002 struct dm_i2c_ops *ops; 1003 }; 1004 1005 /** 1006 * edid_get_timing() - Get basic digital display parameters 1007 * 1008 * @param buf Buffer containing EDID data 1009 * @param buf_size Size of buffer in bytes 1010 * @param timing Place to put preferring timing information 1011 * @param panel_bits_per_colourp Place to put the number of bits per 1012 * colour supported by the panel. This will be set to 1013 * -1 if not available 1014 * @return 0 if timings are OK, -ve on error 1015 */ 1016 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1017 int *panel_bits_per_colourp); 1018 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1019 int *panel_bits_per_colourp); 1020 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *edid); 1021 bool drm_detect_hdmi_monitor(struct edid *edid); 1022 bool drm_detect_monitor_audio(struct edid *edid); 1023 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len); 1024 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid); 1025 enum hdmi_quantization_range 1026 drm_default_rgb_quant_range(struct drm_display_mode *mode); 1027 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 1028 u8 *value); 1029 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 1030 u8 value); 1031 void drm_mode_sort(struct hdmi_edid_data *edid_data); 1032 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data); 1033 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data); 1034 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 1035 struct base_screen_info *screen_info); 1036 1037 #endif /* __EDID_H_ */ 1038