1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 #ifndef __PHYDMRAINFO_H__ 17 #define __PHYDMRAINFO_H__ 18 19 /*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/ 20 /*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/ 21 /*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/ 22 /*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/ 23 /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ 24 /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ 25 /*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ 26 /*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */ 27 /*#define RAINFO_VERSION "4.3"*/ /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */ 28 #define RAINFO_VERSION "5.0" /*2017.04.20 Dino, the 3rd PHYDM reform*/ 29 30 #define FORCED_UPDATE_RAMASK_PERIOD 5 31 32 #define H2C_MAX_LENGTH 7 33 34 #define RA_FLOOR_UP_GAP 3 35 #define RA_FLOOR_TABLE_SIZE 7 36 37 #define ACTIVE_TP_THRESHOLD 1 38 #define RA_RETRY_DESCEND_NUM 2 39 #define RA_RETRY_LIMIT_LOW 4 40 #define RA_RETRY_LIMIT_HIGH 32 41 42 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 43 #define RA_FIRST_MACID 1 44 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 45 #define RA_FIRST_MACID 0 46 #define WIN_DEFAULT_PORT_MACID 0 47 #define WIN_BT_PORT_MACID 2 48 #else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ 49 #define RA_FIRST_MACID 0 50 #endif 51 52 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 53 #define AP_InitRateAdaptiveState odm_rate_adaptive_state_ap_init 54 #endif 55 56 57 #define DM_RATR_STA_INIT 0 58 #define DM_RATR_STA_HIGH 1 59 #define DM_RATR_STA_MIDDLE 2 60 #define DM_RATR_STA_LOW 3 61 #define DM_RATR_STA_ULTRA_LOW 4 62 63 enum phydm_ra_dbg_para_e { 64 RADBG_PCR_TH_OFFSET = 0, 65 RADBG_RTY_PENALTY = 1, 66 RADBG_N_HIGH = 2, 67 RADBG_N_LOW = 3, 68 RADBG_TRATE_UP_TABLE = 4, 69 RADBG_TRATE_DOWN_TABLE = 5, 70 RADBG_TRYING_NECESSARY = 6, 71 RADBG_TDROPING_NECESSARY = 7, 72 RADBG_RATE_UP_RTY_RATIO = 8, 73 RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ 74 75 RADBG_DEBUG_MONITOR1 = 0xc, 76 RADBG_DEBUG_MONITOR2 = 0xd, 77 RADBG_DEBUG_MONITOR3 = 0xe, 78 RADBG_DEBUG_MONITOR4 = 0xf, 79 RADBG_DEBUG_MONITOR5 = 0x10, 80 NUM_RA_PARA 81 }; 82 83 enum phydm_wireless_mode_e { 84 85 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, 86 PHYDM_WIRELESS_MODE_A = 0x01, 87 PHYDM_WIRELESS_MODE_B = 0x02, 88 PHYDM_WIRELESS_MODE_G = 0x04, 89 PHYDM_WIRELESS_MODE_AUTO = 0x08, 90 PHYDM_WIRELESS_MODE_N_24G = 0x10, 91 PHYDM_WIRELESS_MODE_N_5G = 0x20, 92 PHYDM_WIRELESS_MODE_AC_5G = 0x40, 93 PHYDM_WIRELESS_MODE_AC_24G = 0x80, 94 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, 95 PHYDM_WIRELESS_MODE_MAX = 0x800, 96 PHYDM_WIRELESS_MODE_ALL = 0xFFFF 97 }; 98 99 enum phydm_rateid_idx_e { 100 101 PHYDM_BGN_40M_2SS = 0, 102 PHYDM_BGN_40M_1SS = 1, 103 PHYDM_BGN_20M_2SS = 2, 104 PHYDM_BGN_20M_1SS = 3, 105 PHYDM_GN_N2SS = 4, 106 PHYDM_GN_N1SS = 5, 107 PHYDM_BG = 6, 108 PHYDM_G = 7, 109 PHYDM_B_20M = 8, 110 PHYDM_ARFR0_AC_2SS = 9, 111 PHYDM_ARFR1_AC_1SS = 10, 112 PHYDM_ARFR2_AC_2G_1SS = 11, 113 PHYDM_ARFR3_AC_2G_2SS = 12, 114 PHYDM_ARFR4_AC_3SS = 13, 115 PHYDM_ARFR5_N_3SS = 14 116 }; 117 118 #if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */ 119 struct _odm_ra_info_ { 120 u8 rate_id; 121 u32 rate_mask; 122 u32 ra_use_rate; 123 u8 rate_sgi; 124 u8 rssi_sta_ra; 125 u8 pre_rssi_sta_ra; 126 u8 sgi_enable; 127 u8 decision_rate; 128 u8 pre_rate; 129 u8 highest_rate; 130 u8 lowest_rate; 131 u32 nsc_up; 132 u32 nsc_down; 133 u16 RTY[5]; 134 u32 TOTAL; 135 u16 DROP; 136 u8 active; 137 u16 rpt_time; 138 u8 ra_waiting_counter; 139 u8 ra_pending_counter; 140 u8 ra_drop_after_down; 141 #if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */ 142 u8 pt_active; /* on or off */ 143 u8 pt_try_state; /* 0 trying state, 1 for decision state */ 144 u8 pt_stage; /* 0~6 */ 145 u8 pt_stop_count; /* Stop PT counter */ 146 u8 pt_pre_rate; /* if rate change do PT */ 147 u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 148 u8 pt_mode_ss; /* decide whitch rate should do PT */ 149 u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 150 u8 pt_smooth_factor; 151 #endif 152 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) 153 u8 rate_down_counter; 154 u8 rate_up_counter; 155 u8 rate_direction; 156 u8 bounding_type; 157 u8 bounding_counter; 158 u8 bounding_learning_time; 159 u8 rate_down_start_time; 160 #endif 161 }; 162 #endif 163 164 165 struct _rate_adaptive_table_ { 166 u8 firstconnect; 167 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 168 boolean PT_collision_pre; 169 #endif 170 171 #if (defined(CONFIG_RA_DBG_CMD)) 172 boolean is_ra_dbg_init; 173 174 u8 RTY_P[ODM_NUM_RATE_IDX]; 175 u8 RTY_P_default[ODM_NUM_RATE_IDX]; 176 boolean RTY_P_modify_note[ODM_NUM_RATE_IDX]; 177 178 u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; 179 u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; 180 boolean RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; 181 182 u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; 183 u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; 184 boolean RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; 185 186 boolean ra_para_feedback_req; 187 188 u8 para_idx; 189 u8 rate_idx; 190 u8 value; 191 u16 value_16; 192 u8 rate_length; 193 #endif 194 /*u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/ 195 u8 ra_ratio[ODM_ASSOCIATE_ENTRY_NUM]; 196 u8 mu1_rate[30]; 197 u8 highest_client_tx_order; 198 u16 highest_client_tx_rate_order; 199 u8 power_tracking_flag; 200 u8 RA_threshold_offset; 201 u8 RA_offset_direction; 202 u8 up_ramask_cnt; /*force update_ra_mask counter*/ 203 u8 up_ramask_cnt_tmp; /*Just for debug, should be removed latter*/ 204 205 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) 206 u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; 207 u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; 208 u8 retry_descend_num; 209 u8 retrylimit_low; 210 u8 retrylimit_high; 211 #endif 212 u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */ 213 214 void (*record_ra_info)(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask); 215 }; 216 217 void 218 phydm_h2C_debug( 219 void *p_dm_void, 220 u32 *const dm_value, 221 u32 *_used, 222 char *output, 223 u32 *_out_len 224 ); 225 226 #if (defined(CONFIG_RA_DBG_CMD)) 227 228 void 229 odm_RA_debug( 230 void *p_dm_void, 231 u32 *const dm_value 232 ); 233 234 void 235 odm_ra_para_adjust_init( 236 void *p_dm_void 237 ); 238 239 #endif 240 241 void 242 phydm_ra_debug( 243 void *p_dm_void, 244 char input[][16], 245 u32 *_used, 246 char *output, 247 u32 *_out_len 248 ); 249 250 void 251 odm_c2h_ra_para_report_handler( 252 void *p_dm_void, 253 u8 *cmd_buf, 254 u8 cmd_len 255 ); 256 257 void 258 odm_ra_para_adjust( 259 void *p_dm_void 260 ); 261 262 void 263 phydm_ra_dynamic_retry_count( 264 void *p_dm_void 265 ); 266 267 void 268 phydm_ra_dynamic_retry_limit( 269 void *p_dm_void 270 ); 271 272 void 273 phydm_print_rate( 274 void *p_dm_void, 275 u8 rate, 276 u32 dbg_component 277 ); 278 279 void 280 phydm_c2h_ra_report_handler( 281 void *p_dm_void, 282 u8 *cmd_buf, 283 u8 cmd_len 284 ); 285 286 u8 287 phydm_rate_order_compute( 288 void *p_dm_void, 289 u8 rate_idx 290 ); 291 292 void 293 phydm_ra_info_watchdog( 294 void *p_dm_void 295 ); 296 297 void 298 phydm_ra_info_init( 299 void *p_dm_void 300 ); 301 302 void 303 phydm_modify_RA_PCR_threshold( 304 void *p_dm_void, 305 u8 RA_offset_direction, 306 u8 RA_threshold_offset 307 ); 308 309 u8 310 phydm_vht_en_mapping( 311 void *p_dm_void, 312 u32 wireless_mode 313 ); 314 315 u8 316 phydm_rate_id_mapping( 317 void *p_dm_void, 318 u32 wireless_mode, 319 u8 rf_type, 320 u8 bw 321 ); 322 323 void 324 phydm_update_hal_ra_mask( 325 void *p_dm_void, 326 u32 wireless_mode, 327 u8 rf_type, 328 u8 BW, 329 u8 mimo_ps_enable, 330 u8 disable_cck_rate, 331 u32 *ratr_bitmap_msb_in, 332 u32 *ratr_bitmap_in, 333 u8 tx_rate_level 334 ); 335 336 void 337 phydm_refresh_rate_adaptive_mask( 338 void *p_dm_void 339 ); 340 341 u8 342 phydm_rssi_lv_dec( 343 void *p_dm_void, 344 u32 rssi, 345 u8 ratr_state 346 ); 347 348 void 349 odm_ra_post_action_on_assoc( 350 void *p_dm 351 ); 352 353 u8 354 odm_find_rts_rate( 355 void *p_dm_void, 356 u8 tx_rate, 357 boolean is_erp_protect 358 ); 359 360 void 361 phydm_show_sta_info( 362 void *p_dm_void, 363 char input[][16], 364 u32 *_used, 365 char *output, 366 u32 *_out_len, 367 u32 input_num 368 ); 369 370 #ifdef PHYDM_3RD_REFORM_RA_MASK 371 372 void 373 phydm_ra_registed( 374 void *p_dm_void, 375 u8 macid, 376 u8 rssi_from_assoc 377 ); 378 379 void 380 phydm_ra_offline( 381 void *p_dm_void, 382 u8 macid 383 ); 384 385 386 void 387 phydm_ra_mask_watchdog( 388 void *p_dm_void 389 ); 390 391 #endif 392 393 394 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 395 396 void 397 odm_refresh_basic_rate_mask( 398 void *p_dm_void 399 ); 400 401 void 402 odm_update_init_rate_work_item_callback( 403 void *p_context 404 ); 405 406 void 407 odm_refresh_ldpc_rts_mp( 408 struct _ADAPTER *p_adapter, 409 struct PHY_DM_STRUCT *p_dm, 410 u8 m_mac_id, 411 u8 iot_peer, 412 s32 undecorated_smoothed_pwdb 413 ); 414 415 void 416 odm_rate_adaptive_state_ap_init( 417 void *PADAPTER_VOID, 418 struct cmn_sta_info *p_entry 419 ); 420 421 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 422 423 void 424 phydm_gen_ramask_h2c_AP( 425 void *p_dm_void, 426 struct rtl8192cd_priv *priv, 427 struct sta_info *p_entry, 428 u8 rssi_level 429 ); 430 431 #endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ 432 433 434 #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) 435 void 436 phydm_ra_dynamic_rate_id_on_assoc( 437 void *p_dm_void, 438 u8 wireless_mode, 439 u8 init_rate_id 440 ); 441 442 void 443 phydm_ra_dynamic_rate_id_init( 444 void *p_dm_void 445 ); 446 447 void 448 phydm_update_rate_id( 449 void *p_dm_void, 450 u8 rate, 451 u8 platform_macid 452 ); 453 454 #endif 455 456 #endif /*#ifndef __ODMRAINFO_H__*/ 457