1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7 #include "qla_target.h"
8
9 #include <linux/delay.h>
10 #include <linux/gfp.h>
11
12 #ifdef CONFIG_PPC
13 #define IS_PPCARCH true
14 #else
15 #define IS_PPCARCH false
16 #endif
17
18 static struct mb_cmd_name {
19 uint16_t cmd;
20 const char *str;
21 } mb_str[] = {
22 {MBC_GET_PORT_DATABASE, "GPDB"},
23 {MBC_GET_ID_LIST, "GIDList"},
24 {MBC_GET_LINK_PRIV_STATS, "Stats"},
25 {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
26 };
27
mb_to_str(uint16_t cmd)28 static const char *mb_to_str(uint16_t cmd)
29 {
30 int i;
31 struct mb_cmd_name *e;
32
33 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
34 e = mb_str + i;
35 if (cmd == e->cmd)
36 return e->str;
37 }
38 return "unknown";
39 }
40
41 static struct rom_cmd {
42 uint16_t cmd;
43 } rom_cmds[] = {
44 { MBC_LOAD_RAM },
45 { MBC_EXECUTE_FIRMWARE },
46 { MBC_READ_RAM_WORD },
47 { MBC_MAILBOX_REGISTER_TEST },
48 { MBC_VERIFY_CHECKSUM },
49 { MBC_GET_FIRMWARE_VERSION },
50 { MBC_LOAD_RISC_RAM },
51 { MBC_DUMP_RISC_RAM },
52 { MBC_LOAD_RISC_RAM_EXTENDED },
53 { MBC_DUMP_RISC_RAM_EXTENDED },
54 { MBC_WRITE_RAM_WORD_EXTENDED },
55 { MBC_READ_RAM_EXTENDED },
56 { MBC_GET_RESOURCE_COUNTS },
57 { MBC_SET_FIRMWARE_OPTION },
58 { MBC_MID_INITIALIZE_FIRMWARE },
59 { MBC_GET_FIRMWARE_STATE },
60 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
61 { MBC_GET_RETRY_COUNT },
62 { MBC_TRACE_CONTROL },
63 { MBC_INITIALIZE_MULTIQ },
64 { MBC_IOCB_COMMAND_A64 },
65 { MBC_GET_ADAPTER_LOOP_ID },
66 { MBC_READ_SFP },
67 { MBC_SET_RNID_PARAMS },
68 { MBC_GET_RNID_PARAMS },
69 { MBC_GET_SET_ZIO_THRESHOLD },
70 };
71
is_rom_cmd(uint16_t cmd)72 static int is_rom_cmd(uint16_t cmd)
73 {
74 int i;
75 struct rom_cmd *wc;
76
77 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
78 wc = rom_cmds + i;
79 if (wc->cmd == cmd)
80 return 1;
81 }
82
83 return 0;
84 }
85
86 /*
87 * qla2x00_mailbox_command
88 * Issue mailbox command and waits for completion.
89 *
90 * Input:
91 * ha = adapter block pointer.
92 * mcp = driver internal mbx struct pointer.
93 *
94 * Output:
95 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
96 *
97 * Returns:
98 * 0 : QLA_SUCCESS = cmd performed success
99 * 1 : QLA_FUNCTION_FAILED (error encountered)
100 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
101 *
102 * Context:
103 * Kernel context.
104 */
105 static int
qla2x00_mailbox_command(scsi_qla_host_t * vha,mbx_cmd_t * mcp)106 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
107 {
108 int rval, i;
109 unsigned long flags = 0;
110 device_reg_t *reg;
111 uint8_t abort_active;
112 uint8_t io_lock_on;
113 uint16_t command = 0;
114 uint16_t *iptr;
115 __le16 __iomem *optr;
116 uint32_t cnt;
117 uint32_t mboxes;
118 unsigned long wait_time;
119 struct qla_hw_data *ha = vha->hw;
120 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
121 u32 chip_reset;
122
123
124 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
125
126 if (ha->pdev->error_state == pci_channel_io_perm_failure) {
127 ql_log(ql_log_warn, vha, 0x1001,
128 "PCI channel failed permanently, exiting.\n");
129 return QLA_FUNCTION_TIMEOUT;
130 }
131
132 if (vha->device_flags & DFLG_DEV_FAILED) {
133 ql_log(ql_log_warn, vha, 0x1002,
134 "Device in failed state, exiting.\n");
135 return QLA_FUNCTION_TIMEOUT;
136 }
137
138 /* if PCI error, then avoid mbx processing.*/
139 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
140 test_bit(UNLOADING, &base_vha->dpc_flags)) {
141 ql_log(ql_log_warn, vha, 0xd04e,
142 "PCI error, exiting.\n");
143 return QLA_FUNCTION_TIMEOUT;
144 }
145
146 reg = ha->iobase;
147 io_lock_on = base_vha->flags.init_done;
148
149 rval = QLA_SUCCESS;
150 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
151 chip_reset = ha->chip_reset;
152
153 if (ha->flags.pci_channel_io_perm_failure) {
154 ql_log(ql_log_warn, vha, 0x1003,
155 "Perm failure on EEH timeout MBX, exiting.\n");
156 return QLA_FUNCTION_TIMEOUT;
157 }
158
159 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
160 /* Setting Link-Down error */
161 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
162 ql_log(ql_log_warn, vha, 0x1004,
163 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
164 return QLA_FUNCTION_TIMEOUT;
165 }
166
167 /* check if ISP abort is active and return cmd with timeout */
168 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
169 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
170 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
171 !is_rom_cmd(mcp->mb[0])) {
172 ql_log(ql_log_info, vha, 0x1005,
173 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
174 mcp->mb[0]);
175 return QLA_FUNCTION_TIMEOUT;
176 }
177
178 atomic_inc(&ha->num_pend_mbx_stage1);
179 /*
180 * Wait for active mailbox commands to finish by waiting at most tov
181 * seconds. This is to serialize actual issuing of mailbox cmds during
182 * non ISP abort time.
183 */
184 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
185 /* Timeout occurred. Return error. */
186 ql_log(ql_log_warn, vha, 0xd035,
187 "Cmd access timeout, cmd=0x%x, Exiting.\n",
188 mcp->mb[0]);
189 atomic_dec(&ha->num_pend_mbx_stage1);
190 return QLA_FUNCTION_TIMEOUT;
191 }
192 atomic_dec(&ha->num_pend_mbx_stage1);
193 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
194 rval = QLA_ABORTED;
195 goto premature_exit;
196 }
197
198
199 /* Save mailbox command for debug */
200 ha->mcp = mcp;
201
202 ql_dbg(ql_dbg_mbx, vha, 0x1006,
203 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
204
205 spin_lock_irqsave(&ha->hardware_lock, flags);
206
207 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset ||
208 ha->flags.mbox_busy) {
209 rval = QLA_ABORTED;
210 spin_unlock_irqrestore(&ha->hardware_lock, flags);
211 goto premature_exit;
212 }
213 ha->flags.mbox_busy = 1;
214
215 /* Load mailbox registers. */
216 if (IS_P3P_TYPE(ha))
217 optr = ®->isp82.mailbox_in[0];
218 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
219 optr = ®->isp24.mailbox0;
220 else
221 optr = MAILBOX_REG(ha, ®->isp, 0);
222
223 iptr = mcp->mb;
224 command = mcp->mb[0];
225 mboxes = mcp->out_mb;
226
227 ql_dbg(ql_dbg_mbx, vha, 0x1111,
228 "Mailbox registers (OUT):\n");
229 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
230 if (IS_QLA2200(ha) && cnt == 8)
231 optr = MAILBOX_REG(ha, ®->isp, 8);
232 if (mboxes & BIT_0) {
233 ql_dbg(ql_dbg_mbx, vha, 0x1112,
234 "mbox[%d]<-0x%04x\n", cnt, *iptr);
235 wrt_reg_word(optr, *iptr);
236 } else {
237 wrt_reg_word(optr, 0);
238 }
239
240 mboxes >>= 1;
241 optr++;
242 iptr++;
243 }
244
245 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
246 "I/O Address = %p.\n", optr);
247
248 /* Issue set host interrupt command to send cmd out. */
249 ha->flags.mbox_int = 0;
250 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
251
252 /* Unlock mbx registers and wait for interrupt */
253 ql_dbg(ql_dbg_mbx, vha, 0x100f,
254 "Going to unlock irq & waiting for interrupts. "
255 "jiffies=%lx.\n", jiffies);
256
257 /* Wait for mbx cmd completion until timeout */
258 atomic_inc(&ha->num_pend_mbx_stage2);
259 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
260 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
261
262 if (IS_P3P_TYPE(ha))
263 wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING);
264 else if (IS_FWI2_CAPABLE(ha))
265 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT);
266 else
267 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT);
268 spin_unlock_irqrestore(&ha->hardware_lock, flags);
269
270 wait_time = jiffies;
271 atomic_inc(&ha->num_pend_mbx_stage3);
272 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
273 mcp->tov * HZ)) {
274 ql_dbg(ql_dbg_mbx, vha, 0x117a,
275 "cmd=%x Timeout.\n", command);
276 spin_lock_irqsave(&ha->hardware_lock, flags);
277 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
278 spin_unlock_irqrestore(&ha->hardware_lock, flags);
279
280 if (chip_reset != ha->chip_reset) {
281 spin_lock_irqsave(&ha->hardware_lock, flags);
282 ha->flags.mbox_busy = 0;
283 spin_unlock_irqrestore(&ha->hardware_lock,
284 flags);
285 atomic_dec(&ha->num_pend_mbx_stage2);
286 atomic_dec(&ha->num_pend_mbx_stage3);
287 rval = QLA_ABORTED;
288 goto premature_exit;
289 }
290 } else if (ha->flags.purge_mbox ||
291 chip_reset != ha->chip_reset) {
292 spin_lock_irqsave(&ha->hardware_lock, flags);
293 ha->flags.mbox_busy = 0;
294 spin_unlock_irqrestore(&ha->hardware_lock, flags);
295 atomic_dec(&ha->num_pend_mbx_stage2);
296 atomic_dec(&ha->num_pend_mbx_stage3);
297 rval = QLA_ABORTED;
298 goto premature_exit;
299 }
300 atomic_dec(&ha->num_pend_mbx_stage3);
301
302 if (time_after(jiffies, wait_time + 5 * HZ))
303 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
304 command, jiffies_to_msecs(jiffies - wait_time));
305 } else {
306 ql_dbg(ql_dbg_mbx, vha, 0x1011,
307 "Cmd=%x Polling Mode.\n", command);
308
309 if (IS_P3P_TYPE(ha)) {
310 if (rd_reg_dword(®->isp82.hint) &
311 HINT_MBX_INT_PENDING) {
312 ha->flags.mbox_busy = 0;
313 spin_unlock_irqrestore(&ha->hardware_lock,
314 flags);
315 atomic_dec(&ha->num_pend_mbx_stage2);
316 ql_dbg(ql_dbg_mbx, vha, 0x1012,
317 "Pending mailbox timeout, exiting.\n");
318 rval = QLA_FUNCTION_TIMEOUT;
319 goto premature_exit;
320 }
321 wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING);
322 } else if (IS_FWI2_CAPABLE(ha))
323 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT);
324 else
325 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT);
326 spin_unlock_irqrestore(&ha->hardware_lock, flags);
327
328 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
329 while (!ha->flags.mbox_int) {
330 if (ha->flags.purge_mbox ||
331 chip_reset != ha->chip_reset) {
332 spin_lock_irqsave(&ha->hardware_lock, flags);
333 ha->flags.mbox_busy = 0;
334 spin_unlock_irqrestore(&ha->hardware_lock,
335 flags);
336 atomic_dec(&ha->num_pend_mbx_stage2);
337 rval = QLA_ABORTED;
338 goto premature_exit;
339 }
340
341 if (time_after(jiffies, wait_time))
342 break;
343
344 /* Check for pending interrupts. */
345 qla2x00_poll(ha->rsp_q_map[0]);
346
347 if (!ha->flags.mbox_int &&
348 !(IS_QLA2200(ha) &&
349 command == MBC_LOAD_RISC_RAM_EXTENDED))
350 msleep(10);
351 } /* while */
352 ql_dbg(ql_dbg_mbx, vha, 0x1013,
353 "Waited %d sec.\n",
354 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
355 }
356 atomic_dec(&ha->num_pend_mbx_stage2);
357
358 /* Check whether we timed out */
359 if (ha->flags.mbox_int) {
360 uint16_t *iptr2;
361
362 ql_dbg(ql_dbg_mbx, vha, 0x1014,
363 "Cmd=%x completed.\n", command);
364
365 /* Got interrupt. Clear the flag. */
366 ha->flags.mbox_int = 0;
367 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
368
369 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
370 spin_lock_irqsave(&ha->hardware_lock, flags);
371 ha->flags.mbox_busy = 0;
372 spin_unlock_irqrestore(&ha->hardware_lock, flags);
373
374 /* Setting Link-Down error */
375 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
376 ha->mcp = NULL;
377 rval = QLA_FUNCTION_FAILED;
378 ql_log(ql_log_warn, vha, 0xd048,
379 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
380 goto premature_exit;
381 }
382
383 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
384 ql_dbg(ql_dbg_mbx, vha, 0x11ff,
385 "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
386 MBS_COMMAND_COMPLETE);
387 rval = QLA_FUNCTION_FAILED;
388 }
389
390 /* Load return mailbox registers. */
391 iptr2 = mcp->mb;
392 iptr = (uint16_t *)&ha->mailbox_out[0];
393 mboxes = mcp->in_mb;
394
395 ql_dbg(ql_dbg_mbx, vha, 0x1113,
396 "Mailbox registers (IN):\n");
397 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
398 if (mboxes & BIT_0) {
399 *iptr2 = *iptr;
400 ql_dbg(ql_dbg_mbx, vha, 0x1114,
401 "mbox[%d]->0x%04x\n", cnt, *iptr2);
402 }
403
404 mboxes >>= 1;
405 iptr2++;
406 iptr++;
407 }
408 } else {
409
410 uint16_t mb[8];
411 uint32_t ictrl, host_status, hccr;
412 uint16_t w;
413
414 if (IS_FWI2_CAPABLE(ha)) {
415 mb[0] = rd_reg_word(®->isp24.mailbox0);
416 mb[1] = rd_reg_word(®->isp24.mailbox1);
417 mb[2] = rd_reg_word(®->isp24.mailbox2);
418 mb[3] = rd_reg_word(®->isp24.mailbox3);
419 mb[7] = rd_reg_word(®->isp24.mailbox7);
420 ictrl = rd_reg_dword(®->isp24.ictrl);
421 host_status = rd_reg_dword(®->isp24.host_status);
422 hccr = rd_reg_dword(®->isp24.hccr);
423
424 ql_log(ql_log_warn, vha, 0xd04c,
425 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
426 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
427 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
428 mb[7], host_status, hccr);
429
430 } else {
431 mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0);
432 ictrl = rd_reg_word(®->isp.ictrl);
433 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
434 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
435 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
436 }
437 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
438
439 /* Capture FW dump only, if PCI device active */
440 if (!pci_channel_offline(vha->hw->pdev)) {
441 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
442 if (w == 0xffff || ictrl == 0xffffffff ||
443 (chip_reset != ha->chip_reset)) {
444 /* This is special case if there is unload
445 * of driver happening and if PCI device go
446 * into bad state due to PCI error condition
447 * then only PCI ERR flag would be set.
448 * we will do premature exit for above case.
449 */
450 spin_lock_irqsave(&ha->hardware_lock, flags);
451 ha->flags.mbox_busy = 0;
452 spin_unlock_irqrestore(&ha->hardware_lock,
453 flags);
454 rval = QLA_FUNCTION_TIMEOUT;
455 goto premature_exit;
456 }
457
458 /* Attempt to capture firmware dump for further
459 * anallysis of the current formware state. we do not
460 * need to do this if we are intentionally generating
461 * a dump
462 */
463 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
464 qla2xxx_dump_fw(vha);
465 rval = QLA_FUNCTION_TIMEOUT;
466 }
467 }
468 spin_lock_irqsave(&ha->hardware_lock, flags);
469 ha->flags.mbox_busy = 0;
470 spin_unlock_irqrestore(&ha->hardware_lock, flags);
471
472 /* Clean up */
473 ha->mcp = NULL;
474
475 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
476 ql_dbg(ql_dbg_mbx, vha, 0x101a,
477 "Checking for additional resp interrupt.\n");
478
479 /* polling mode for non isp_abort commands. */
480 qla2x00_poll(ha->rsp_q_map[0]);
481 }
482
483 if (rval == QLA_FUNCTION_TIMEOUT &&
484 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
485 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
486 ha->flags.eeh_busy) {
487 /* not in dpc. schedule it for dpc to take over. */
488 ql_dbg(ql_dbg_mbx, vha, 0x101b,
489 "Timeout, schedule isp_abort_needed.\n");
490
491 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
492 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
493 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
494 if (IS_QLA82XX(ha)) {
495 ql_dbg(ql_dbg_mbx, vha, 0x112a,
496 "disabling pause transmit on port "
497 "0 & 1.\n");
498 qla82xx_wr_32(ha,
499 QLA82XX_CRB_NIU + 0x98,
500 CRB_NIU_XG_PAUSE_CTL_P0|
501 CRB_NIU_XG_PAUSE_CTL_P1);
502 }
503 ql_log(ql_log_info, base_vha, 0x101c,
504 "Mailbox cmd timeout occurred, cmd=0x%x, "
505 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
506 "abort.\n", command, mcp->mb[0],
507 ha->flags.eeh_busy);
508 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
509 qla2xxx_wake_dpc(vha);
510 }
511 } else if (current == ha->dpc_thread) {
512 /* call abort directly since we are in the DPC thread */
513 ql_dbg(ql_dbg_mbx, vha, 0x101d,
514 "Timeout, calling abort_isp.\n");
515
516 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
517 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
518 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
519 if (IS_QLA82XX(ha)) {
520 ql_dbg(ql_dbg_mbx, vha, 0x112b,
521 "disabling pause transmit on port "
522 "0 & 1.\n");
523 qla82xx_wr_32(ha,
524 QLA82XX_CRB_NIU + 0x98,
525 CRB_NIU_XG_PAUSE_CTL_P0|
526 CRB_NIU_XG_PAUSE_CTL_P1);
527 }
528 ql_log(ql_log_info, base_vha, 0x101e,
529 "Mailbox cmd timeout occurred, cmd=0x%x, "
530 "mb[0]=0x%x. Scheduling ISP abort ",
531 command, mcp->mb[0]);
532 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
533 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
534 /* Allow next mbx cmd to come in. */
535 complete(&ha->mbx_cmd_comp);
536 if (ha->isp_ops->abort_isp(vha)) {
537 /* Failed. retry later. */
538 set_bit(ISP_ABORT_NEEDED,
539 &vha->dpc_flags);
540 }
541 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
542 ql_dbg(ql_dbg_mbx, vha, 0x101f,
543 "Finished abort_isp.\n");
544 goto mbx_done;
545 }
546 }
547 }
548
549 premature_exit:
550 /* Allow next mbx cmd to come in. */
551 complete(&ha->mbx_cmd_comp);
552
553 mbx_done:
554 if (rval == QLA_ABORTED) {
555 ql_log(ql_log_info, vha, 0xd035,
556 "Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
557 mcp->mb[0]);
558 } else if (rval) {
559 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
560 pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
561 dev_name(&ha->pdev->dev), 0x1020+0x800,
562 vha->host_no, rval);
563 mboxes = mcp->in_mb;
564 cnt = 4;
565 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
566 if (mboxes & BIT_0) {
567 printk(" mb[%u]=%x", i, mcp->mb[i]);
568 cnt--;
569 }
570 pr_warn(" cmd=%x ****\n", command);
571 }
572 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
573 ql_dbg(ql_dbg_mbx, vha, 0x1198,
574 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
575 rd_reg_dword(®->isp24.host_status),
576 rd_reg_dword(®->isp24.ictrl),
577 rd_reg_dword(®->isp24.istatus));
578 } else {
579 ql_dbg(ql_dbg_mbx, vha, 0x1206,
580 "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
581 rd_reg_word(®->isp.ctrl_status),
582 rd_reg_word(®->isp.ictrl),
583 rd_reg_word(®->isp.istatus));
584 }
585 } else {
586 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
587 }
588
589 return rval;
590 }
591
592 int
qla2x00_load_ram(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t risc_addr,uint32_t risc_code_size)593 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
594 uint32_t risc_code_size)
595 {
596 int rval;
597 struct qla_hw_data *ha = vha->hw;
598 mbx_cmd_t mc;
599 mbx_cmd_t *mcp = &mc;
600
601 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
602 "Entered %s.\n", __func__);
603
604 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
605 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
606 mcp->mb[8] = MSW(risc_addr);
607 mcp->out_mb = MBX_8|MBX_0;
608 } else {
609 mcp->mb[0] = MBC_LOAD_RISC_RAM;
610 mcp->out_mb = MBX_0;
611 }
612 mcp->mb[1] = LSW(risc_addr);
613 mcp->mb[2] = MSW(req_dma);
614 mcp->mb[3] = LSW(req_dma);
615 mcp->mb[6] = MSW(MSD(req_dma));
616 mcp->mb[7] = LSW(MSD(req_dma));
617 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
618 if (IS_FWI2_CAPABLE(ha)) {
619 mcp->mb[4] = MSW(risc_code_size);
620 mcp->mb[5] = LSW(risc_code_size);
621 mcp->out_mb |= MBX_5|MBX_4;
622 } else {
623 mcp->mb[4] = LSW(risc_code_size);
624 mcp->out_mb |= MBX_4;
625 }
626
627 mcp->in_mb = MBX_1|MBX_0;
628 mcp->tov = MBX_TOV_SECONDS;
629 mcp->flags = 0;
630 rval = qla2x00_mailbox_command(vha, mcp);
631
632 if (rval != QLA_SUCCESS) {
633 ql_dbg(ql_dbg_mbx, vha, 0x1023,
634 "Failed=%x mb[0]=%x mb[1]=%x.\n",
635 rval, mcp->mb[0], mcp->mb[1]);
636 } else {
637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
638 "Done %s.\n", __func__);
639 }
640
641 return rval;
642 }
643
644 #define NVME_ENABLE_FLAG BIT_3
645
646 /*
647 * qla2x00_execute_fw
648 * Start adapter firmware.
649 *
650 * Input:
651 * ha = adapter block pointer.
652 * TARGET_QUEUE_LOCK must be released.
653 * ADAPTER_STATE_LOCK must be released.
654 *
655 * Returns:
656 * qla2x00 local function return status code.
657 *
658 * Context:
659 * Kernel context.
660 */
661 int
qla2x00_execute_fw(scsi_qla_host_t * vha,uint32_t risc_addr)662 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
663 {
664 int rval;
665 struct qla_hw_data *ha = vha->hw;
666 mbx_cmd_t mc;
667 mbx_cmd_t *mcp = &mc;
668 u8 semaphore = 0;
669 #define EXE_FW_FORCE_SEMAPHORE BIT_7
670 u8 retry = 3;
671
672 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
673 "Entered %s.\n", __func__);
674
675 again:
676 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
677 mcp->out_mb = MBX_0;
678 mcp->in_mb = MBX_0;
679 if (IS_FWI2_CAPABLE(ha)) {
680 mcp->mb[1] = MSW(risc_addr);
681 mcp->mb[2] = LSW(risc_addr);
682 mcp->mb[3] = 0;
683 mcp->mb[4] = 0;
684 mcp->mb[11] = 0;
685
686 /* Enable BPM? */
687 if (ha->flags.lr_detected) {
688 mcp->mb[4] = BIT_0;
689 if (IS_BPM_RANGE_CAPABLE(ha))
690 mcp->mb[4] |=
691 ha->lr_distance << LR_DIST_FW_POS;
692 }
693
694 if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha)))
695 mcp->mb[4] |= NVME_ENABLE_FLAG;
696
697 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
698 struct nvram_81xx *nv = ha->nvram;
699 /* set minimum speed if specified in nvram */
700 if (nv->min_supported_speed >= 2 &&
701 nv->min_supported_speed <= 5) {
702 mcp->mb[4] |= BIT_4;
703 mcp->mb[11] |= nv->min_supported_speed & 0xF;
704 mcp->out_mb |= MBX_11;
705 mcp->in_mb |= BIT_5;
706 vha->min_supported_speed =
707 nv->min_supported_speed;
708 }
709
710 if (IS_PPCARCH)
711 mcp->mb[11] |= BIT_4;
712 }
713
714 if (ha->flags.exlogins_enabled)
715 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
716
717 if (ha->flags.exchoffld_enabled)
718 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
719
720 if (semaphore)
721 mcp->mb[11] |= EXE_FW_FORCE_SEMAPHORE;
722
723 mcp->out_mb |= MBX_4 | MBX_3 | MBX_2 | MBX_1 | MBX_11;
724 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
725 } else {
726 mcp->mb[1] = LSW(risc_addr);
727 mcp->out_mb |= MBX_1;
728 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
729 mcp->mb[2] = 0;
730 mcp->out_mb |= MBX_2;
731 }
732 }
733
734 mcp->tov = MBX_TOV_SECONDS;
735 mcp->flags = 0;
736 rval = qla2x00_mailbox_command(vha, mcp);
737
738 if (rval != QLA_SUCCESS) {
739 if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR &&
740 mcp->mb[1] == 0x27 && retry) {
741 semaphore = 1;
742 retry--;
743 ql_dbg(ql_dbg_async, vha, 0x1026,
744 "Exe FW: force semaphore.\n");
745 goto again;
746 }
747
748 ql_dbg(ql_dbg_mbx, vha, 0x1026,
749 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
750 return rval;
751 }
752
753 if (!IS_FWI2_CAPABLE(ha))
754 goto done;
755
756 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
757 ql_dbg(ql_dbg_mbx, vha, 0x119a,
758 "fw_ability_mask=%x.\n", ha->fw_ability_mask);
759 ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
760 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
761 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1);
762 ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
763 ha->max_supported_speed == 0 ? "16Gps" :
764 ha->max_supported_speed == 1 ? "32Gps" :
765 ha->max_supported_speed == 2 ? "64Gps" : "unknown");
766 if (vha->min_supported_speed) {
767 ha->min_supported_speed = mcp->mb[5] &
768 (BIT_0 | BIT_1 | BIT_2);
769 ql_dbg(ql_dbg_mbx, vha, 0x119c,
770 "min_supported_speed=%s.\n",
771 ha->min_supported_speed == 6 ? "64Gps" :
772 ha->min_supported_speed == 5 ? "32Gps" :
773 ha->min_supported_speed == 4 ? "16Gps" :
774 ha->min_supported_speed == 3 ? "8Gps" :
775 ha->min_supported_speed == 2 ? "4Gps" : "unknown");
776 }
777 }
778
779 done:
780 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
781 "Done %s.\n", __func__);
782
783 return rval;
784 }
785
786 /*
787 * qla_get_exlogin_status
788 * Get extended login status
789 * uses the memory offload control/status Mailbox
790 *
791 * Input:
792 * ha: adapter state pointer.
793 * fwopt: firmware options
794 *
795 * Returns:
796 * qla2x00 local function status
797 *
798 * Context:
799 * Kernel context.
800 */
801 #define FETCH_XLOGINS_STAT 0x8
802 int
qla_get_exlogin_status(scsi_qla_host_t * vha,uint16_t * buf_sz,uint16_t * ex_logins_cnt)803 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
804 uint16_t *ex_logins_cnt)
805 {
806 int rval;
807 mbx_cmd_t mc;
808 mbx_cmd_t *mcp = &mc;
809
810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
811 "Entered %s\n", __func__);
812
813 memset(mcp->mb, 0 , sizeof(mcp->mb));
814 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
815 mcp->mb[1] = FETCH_XLOGINS_STAT;
816 mcp->out_mb = MBX_1|MBX_0;
817 mcp->in_mb = MBX_10|MBX_4|MBX_0;
818 mcp->tov = MBX_TOV_SECONDS;
819 mcp->flags = 0;
820
821 rval = qla2x00_mailbox_command(vha, mcp);
822 if (rval != QLA_SUCCESS) {
823 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
824 } else {
825 *buf_sz = mcp->mb[4];
826 *ex_logins_cnt = mcp->mb[10];
827
828 ql_log(ql_log_info, vha, 0x1190,
829 "buffer size 0x%x, exchange login count=%d\n",
830 mcp->mb[4], mcp->mb[10]);
831
832 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
833 "Done %s.\n", __func__);
834 }
835
836 return rval;
837 }
838
839 /*
840 * qla_set_exlogin_mem_cfg
841 * set extended login memory configuration
842 * Mbx needs to be issues before init_cb is set
843 *
844 * Input:
845 * ha: adapter state pointer.
846 * buffer: buffer pointer
847 * phys_addr: physical address of buffer
848 * size: size of buffer
849 * TARGET_QUEUE_LOCK must be released
850 * ADAPTER_STATE_LOCK must be release
851 *
852 * Returns:
853 * qla2x00 local funxtion status code.
854 *
855 * Context:
856 * Kernel context.
857 */
858 #define CONFIG_XLOGINS_MEM 0x9
859 int
qla_set_exlogin_mem_cfg(scsi_qla_host_t * vha,dma_addr_t phys_addr)860 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
861 {
862 int rval;
863 mbx_cmd_t mc;
864 mbx_cmd_t *mcp = &mc;
865 struct qla_hw_data *ha = vha->hw;
866
867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
868 "Entered %s.\n", __func__);
869
870 memset(mcp->mb, 0 , sizeof(mcp->mb));
871 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
872 mcp->mb[1] = CONFIG_XLOGINS_MEM;
873 mcp->mb[2] = MSW(phys_addr);
874 mcp->mb[3] = LSW(phys_addr);
875 mcp->mb[6] = MSW(MSD(phys_addr));
876 mcp->mb[7] = LSW(MSD(phys_addr));
877 mcp->mb[8] = MSW(ha->exlogin_size);
878 mcp->mb[9] = LSW(ha->exlogin_size);
879 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
880 mcp->in_mb = MBX_11|MBX_0;
881 mcp->tov = MBX_TOV_SECONDS;
882 mcp->flags = 0;
883 rval = qla2x00_mailbox_command(vha, mcp);
884 if (rval != QLA_SUCCESS) {
885 ql_dbg(ql_dbg_mbx, vha, 0x111b,
886 "EXlogin Failed=%x. MB0=%x MB11=%x\n",
887 rval, mcp->mb[0], mcp->mb[11]);
888 } else {
889 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
890 "Done %s.\n", __func__);
891 }
892
893 return rval;
894 }
895
896 /*
897 * qla_get_exchoffld_status
898 * Get exchange offload status
899 * uses the memory offload control/status Mailbox
900 *
901 * Input:
902 * ha: adapter state pointer.
903 * fwopt: firmware options
904 *
905 * Returns:
906 * qla2x00 local function status
907 *
908 * Context:
909 * Kernel context.
910 */
911 #define FETCH_XCHOFFLD_STAT 0x2
912 int
qla_get_exchoffld_status(scsi_qla_host_t * vha,uint16_t * buf_sz,uint16_t * ex_logins_cnt)913 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
914 uint16_t *ex_logins_cnt)
915 {
916 int rval;
917 mbx_cmd_t mc;
918 mbx_cmd_t *mcp = &mc;
919
920 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
921 "Entered %s\n", __func__);
922
923 memset(mcp->mb, 0 , sizeof(mcp->mb));
924 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
925 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
926 mcp->out_mb = MBX_1|MBX_0;
927 mcp->in_mb = MBX_10|MBX_4|MBX_0;
928 mcp->tov = MBX_TOV_SECONDS;
929 mcp->flags = 0;
930
931 rval = qla2x00_mailbox_command(vha, mcp);
932 if (rval != QLA_SUCCESS) {
933 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
934 } else {
935 *buf_sz = mcp->mb[4];
936 *ex_logins_cnt = mcp->mb[10];
937
938 ql_log(ql_log_info, vha, 0x118e,
939 "buffer size 0x%x, exchange offload count=%d\n",
940 mcp->mb[4], mcp->mb[10]);
941
942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
943 "Done %s.\n", __func__);
944 }
945
946 return rval;
947 }
948
949 /*
950 * qla_set_exchoffld_mem_cfg
951 * Set exchange offload memory configuration
952 * Mbx needs to be issues before init_cb is set
953 *
954 * Input:
955 * ha: adapter state pointer.
956 * buffer: buffer pointer
957 * phys_addr: physical address of buffer
958 * size: size of buffer
959 * TARGET_QUEUE_LOCK must be released
960 * ADAPTER_STATE_LOCK must be release
961 *
962 * Returns:
963 * qla2x00 local funxtion status code.
964 *
965 * Context:
966 * Kernel context.
967 */
968 #define CONFIG_XCHOFFLD_MEM 0x3
969 int
qla_set_exchoffld_mem_cfg(scsi_qla_host_t * vha)970 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
971 {
972 int rval;
973 mbx_cmd_t mc;
974 mbx_cmd_t *mcp = &mc;
975 struct qla_hw_data *ha = vha->hw;
976
977 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
978 "Entered %s.\n", __func__);
979
980 memset(mcp->mb, 0 , sizeof(mcp->mb));
981 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
982 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
983 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
984 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
985 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
986 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
987 mcp->mb[8] = MSW(ha->exchoffld_size);
988 mcp->mb[9] = LSW(ha->exchoffld_size);
989 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
990 mcp->in_mb = MBX_11|MBX_0;
991 mcp->tov = MBX_TOV_SECONDS;
992 mcp->flags = 0;
993 rval = qla2x00_mailbox_command(vha, mcp);
994 if (rval != QLA_SUCCESS) {
995 /*EMPTY*/
996 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
997 } else {
998 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
999 "Done %s.\n", __func__);
1000 }
1001
1002 return rval;
1003 }
1004
1005 /*
1006 * qla2x00_get_fw_version
1007 * Get firmware version.
1008 *
1009 * Input:
1010 * ha: adapter state pointer.
1011 * major: pointer for major number.
1012 * minor: pointer for minor number.
1013 * subminor: pointer for subminor number.
1014 *
1015 * Returns:
1016 * qla2x00 local function return status code.
1017 *
1018 * Context:
1019 * Kernel context.
1020 */
1021 int
qla2x00_get_fw_version(scsi_qla_host_t * vha)1022 qla2x00_get_fw_version(scsi_qla_host_t *vha)
1023 {
1024 int rval;
1025 mbx_cmd_t mc;
1026 mbx_cmd_t *mcp = &mc;
1027 struct qla_hw_data *ha = vha->hw;
1028
1029 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
1030 "Entered %s.\n", __func__);
1031
1032 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
1033 mcp->out_mb = MBX_0;
1034 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1035 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
1036 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
1037 if (IS_FWI2_CAPABLE(ha))
1038 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
1039 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
1040 mcp->in_mb |=
1041 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
1042 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7;
1043
1044 mcp->flags = 0;
1045 mcp->tov = MBX_TOV_SECONDS;
1046 rval = qla2x00_mailbox_command(vha, mcp);
1047 if (rval != QLA_SUCCESS)
1048 goto failed;
1049
1050 /* Return mailbox data. */
1051 ha->fw_major_version = mcp->mb[1];
1052 ha->fw_minor_version = mcp->mb[2];
1053 ha->fw_subminor_version = mcp->mb[3];
1054 ha->fw_attributes = mcp->mb[6];
1055 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
1056 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1057 else
1058 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
1059
1060 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
1061 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1062 ha->mpi_version[1] = mcp->mb[11] >> 8;
1063 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1064 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
1065 ha->phy_version[0] = mcp->mb[8] & 0xff;
1066 ha->phy_version[1] = mcp->mb[9] >> 8;
1067 ha->phy_version[2] = mcp->mb[9] & 0xff;
1068 }
1069
1070 if (IS_FWI2_CAPABLE(ha)) {
1071 ha->fw_attributes_h = mcp->mb[15];
1072 ha->fw_attributes_ext[0] = mcp->mb[16];
1073 ha->fw_attributes_ext[1] = mcp->mb[17];
1074 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
1075 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
1076 __func__, mcp->mb[15], mcp->mb[6]);
1077 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
1078 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
1079 __func__, mcp->mb[17], mcp->mb[16]);
1080
1081 if (ha->fw_attributes_h & 0x4)
1082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
1083 "%s: Firmware supports Extended Login 0x%x\n",
1084 __func__, ha->fw_attributes_h);
1085
1086 if (ha->fw_attributes_h & 0x8)
1087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
1088 "%s: Firmware supports Exchange Offload 0x%x\n",
1089 __func__, ha->fw_attributes_h);
1090
1091 /*
1092 * FW supports nvme and driver load parameter requested nvme.
1093 * BIT 26 of fw_attributes indicates NVMe support.
1094 */
1095 if ((ha->fw_attributes_h &
1096 (FW_ATTR_H_NVME | FW_ATTR_H_NVME_UPDATED)) &&
1097 ql2xnvmeenable) {
1098 if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
1099 vha->flags.nvme_first_burst = 1;
1100
1101 vha->flags.nvme_enabled = 1;
1102 ql_log(ql_log_info, vha, 0xd302,
1103 "%s: FC-NVMe is Enabled (0x%x)\n",
1104 __func__, ha->fw_attributes_h);
1105 }
1106
1107 /* BIT_13 of Extended FW Attributes informs about NVMe2 support */
1108 if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
1109 ql_log(ql_log_info, vha, 0xd302,
1110 "Firmware supports NVMe2 0x%x\n",
1111 ha->fw_attributes_ext[0]);
1112 vha->flags.nvme2_enabled = 1;
1113 }
1114 }
1115
1116 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1117 ha->serdes_version[0] = mcp->mb[7] & 0xff;
1118 ha->serdes_version[1] = mcp->mb[8] >> 8;
1119 ha->serdes_version[2] = mcp->mb[8] & 0xff;
1120 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1121 ha->mpi_version[1] = mcp->mb[11] >> 8;
1122 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1123 ha->pep_version[0] = mcp->mb[13] & 0xff;
1124 ha->pep_version[1] = mcp->mb[14] >> 8;
1125 ha->pep_version[2] = mcp->mb[14] & 0xff;
1126 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
1127 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
1128 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
1129 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
1130 if (IS_QLA28XX(ha)) {
1131 if (mcp->mb[16] & BIT_10)
1132 ha->flags.secure_fw = 1;
1133
1134 ql_log(ql_log_info, vha, 0xffff,
1135 "Secure Flash Update in FW: %s\n",
1136 (ha->flags.secure_fw) ? "Supported" :
1137 "Not Supported");
1138 }
1139
1140 if (ha->flags.scm_supported_a &&
1141 (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
1142 ha->flags.scm_supported_f = 1;
1143 ha->sf_init_cb->flags |= cpu_to_le16(BIT_13);
1144 }
1145 ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
1146 (ha->flags.scm_supported_f) ? "Supported" :
1147 "Not Supported");
1148
1149 if (vha->flags.nvme2_enabled) {
1150 /* set BIT_15 of special feature control block for SLER */
1151 ha->sf_init_cb->flags |= cpu_to_le16(BIT_15);
1152 /* set BIT_14 of special feature control block for PI CTRL*/
1153 ha->sf_init_cb->flags |= cpu_to_le16(BIT_14);
1154 }
1155 }
1156
1157 failed:
1158 if (rval != QLA_SUCCESS) {
1159 /*EMPTY*/
1160 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1161 } else {
1162 /*EMPTY*/
1163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
1164 "Done %s.\n", __func__);
1165 }
1166 return rval;
1167 }
1168
1169 /*
1170 * qla2x00_get_fw_options
1171 * Set firmware options.
1172 *
1173 * Input:
1174 * ha = adapter block pointer.
1175 * fwopt = pointer for firmware options.
1176 *
1177 * Returns:
1178 * qla2x00 local function return status code.
1179 *
1180 * Context:
1181 * Kernel context.
1182 */
1183 int
qla2x00_get_fw_options(scsi_qla_host_t * vha,uint16_t * fwopts)1184 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1185 {
1186 int rval;
1187 mbx_cmd_t mc;
1188 mbx_cmd_t *mcp = &mc;
1189
1190 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1191 "Entered %s.\n", __func__);
1192
1193 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1194 mcp->out_mb = MBX_0;
1195 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1196 mcp->tov = MBX_TOV_SECONDS;
1197 mcp->flags = 0;
1198 rval = qla2x00_mailbox_command(vha, mcp);
1199
1200 if (rval != QLA_SUCCESS) {
1201 /*EMPTY*/
1202 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1203 } else {
1204 fwopts[0] = mcp->mb[0];
1205 fwopts[1] = mcp->mb[1];
1206 fwopts[2] = mcp->mb[2];
1207 fwopts[3] = mcp->mb[3];
1208
1209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1210 "Done %s.\n", __func__);
1211 }
1212
1213 return rval;
1214 }
1215
1216
1217 /*
1218 * qla2x00_set_fw_options
1219 * Set firmware options.
1220 *
1221 * Input:
1222 * ha = adapter block pointer.
1223 * fwopt = pointer for firmware options.
1224 *
1225 * Returns:
1226 * qla2x00 local function return status code.
1227 *
1228 * Context:
1229 * Kernel context.
1230 */
1231 int
qla2x00_set_fw_options(scsi_qla_host_t * vha,uint16_t * fwopts)1232 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1233 {
1234 int rval;
1235 mbx_cmd_t mc;
1236 mbx_cmd_t *mcp = &mc;
1237
1238 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1239 "Entered %s.\n", __func__);
1240
1241 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1242 mcp->mb[1] = fwopts[1];
1243 mcp->mb[2] = fwopts[2];
1244 mcp->mb[3] = fwopts[3];
1245 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1246 mcp->in_mb = MBX_0;
1247 if (IS_FWI2_CAPABLE(vha->hw)) {
1248 mcp->in_mb |= MBX_1;
1249 mcp->mb[10] = fwopts[10];
1250 mcp->out_mb |= MBX_10;
1251 } else {
1252 mcp->mb[10] = fwopts[10];
1253 mcp->mb[11] = fwopts[11];
1254 mcp->mb[12] = 0; /* Undocumented, but used */
1255 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1256 }
1257 mcp->tov = MBX_TOV_SECONDS;
1258 mcp->flags = 0;
1259 rval = qla2x00_mailbox_command(vha, mcp);
1260
1261 fwopts[0] = mcp->mb[0];
1262
1263 if (rval != QLA_SUCCESS) {
1264 /*EMPTY*/
1265 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1266 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1267 } else {
1268 /*EMPTY*/
1269 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1270 "Done %s.\n", __func__);
1271 }
1272
1273 return rval;
1274 }
1275
1276 /*
1277 * qla2x00_mbx_reg_test
1278 * Mailbox register wrap test.
1279 *
1280 * Input:
1281 * ha = adapter block pointer.
1282 * TARGET_QUEUE_LOCK must be released.
1283 * ADAPTER_STATE_LOCK must be released.
1284 *
1285 * Returns:
1286 * qla2x00 local function return status code.
1287 *
1288 * Context:
1289 * Kernel context.
1290 */
1291 int
qla2x00_mbx_reg_test(scsi_qla_host_t * vha)1292 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1293 {
1294 int rval;
1295 mbx_cmd_t mc;
1296 mbx_cmd_t *mcp = &mc;
1297
1298 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1299 "Entered %s.\n", __func__);
1300
1301 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1302 mcp->mb[1] = 0xAAAA;
1303 mcp->mb[2] = 0x5555;
1304 mcp->mb[3] = 0xAA55;
1305 mcp->mb[4] = 0x55AA;
1306 mcp->mb[5] = 0xA5A5;
1307 mcp->mb[6] = 0x5A5A;
1308 mcp->mb[7] = 0x2525;
1309 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1310 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1311 mcp->tov = MBX_TOV_SECONDS;
1312 mcp->flags = 0;
1313 rval = qla2x00_mailbox_command(vha, mcp);
1314
1315 if (rval == QLA_SUCCESS) {
1316 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1317 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1318 rval = QLA_FUNCTION_FAILED;
1319 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1320 mcp->mb[7] != 0x2525)
1321 rval = QLA_FUNCTION_FAILED;
1322 }
1323
1324 if (rval != QLA_SUCCESS) {
1325 /*EMPTY*/
1326 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1327 } else {
1328 /*EMPTY*/
1329 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1330 "Done %s.\n", __func__);
1331 }
1332
1333 return rval;
1334 }
1335
1336 /*
1337 * qla2x00_verify_checksum
1338 * Verify firmware checksum.
1339 *
1340 * Input:
1341 * ha = adapter block pointer.
1342 * TARGET_QUEUE_LOCK must be released.
1343 * ADAPTER_STATE_LOCK must be released.
1344 *
1345 * Returns:
1346 * qla2x00 local function return status code.
1347 *
1348 * Context:
1349 * Kernel context.
1350 */
1351 int
qla2x00_verify_checksum(scsi_qla_host_t * vha,uint32_t risc_addr)1352 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1353 {
1354 int rval;
1355 mbx_cmd_t mc;
1356 mbx_cmd_t *mcp = &mc;
1357
1358 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1359 "Entered %s.\n", __func__);
1360
1361 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1362 mcp->out_mb = MBX_0;
1363 mcp->in_mb = MBX_0;
1364 if (IS_FWI2_CAPABLE(vha->hw)) {
1365 mcp->mb[1] = MSW(risc_addr);
1366 mcp->mb[2] = LSW(risc_addr);
1367 mcp->out_mb |= MBX_2|MBX_1;
1368 mcp->in_mb |= MBX_2|MBX_1;
1369 } else {
1370 mcp->mb[1] = LSW(risc_addr);
1371 mcp->out_mb |= MBX_1;
1372 mcp->in_mb |= MBX_1;
1373 }
1374
1375 mcp->tov = MBX_TOV_SECONDS;
1376 mcp->flags = 0;
1377 rval = qla2x00_mailbox_command(vha, mcp);
1378
1379 if (rval != QLA_SUCCESS) {
1380 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1381 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1382 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1383 } else {
1384 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1385 "Done %s.\n", __func__);
1386 }
1387
1388 return rval;
1389 }
1390
1391 /*
1392 * qla2x00_issue_iocb
1393 * Issue IOCB using mailbox command
1394 *
1395 * Input:
1396 * ha = adapter state pointer.
1397 * buffer = buffer pointer.
1398 * phys_addr = physical address of buffer.
1399 * size = size of buffer.
1400 * TARGET_QUEUE_LOCK must be released.
1401 * ADAPTER_STATE_LOCK must be released.
1402 *
1403 * Returns:
1404 * qla2x00 local function return status code.
1405 *
1406 * Context:
1407 * Kernel context.
1408 */
1409 int
qla2x00_issue_iocb_timeout(scsi_qla_host_t * vha,void * buffer,dma_addr_t phys_addr,size_t size,uint32_t tov)1410 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
1411 dma_addr_t phys_addr, size_t size, uint32_t tov)
1412 {
1413 int rval;
1414 mbx_cmd_t mc;
1415 mbx_cmd_t *mcp = &mc;
1416
1417 if (!vha->hw->flags.fw_started)
1418 return QLA_INVALID_COMMAND;
1419
1420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1421 "Entered %s.\n", __func__);
1422
1423 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1424 mcp->mb[1] = 0;
1425 mcp->mb[2] = MSW(LSD(phys_addr));
1426 mcp->mb[3] = LSW(LSD(phys_addr));
1427 mcp->mb[6] = MSW(MSD(phys_addr));
1428 mcp->mb[7] = LSW(MSD(phys_addr));
1429 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1430 mcp->in_mb = MBX_1|MBX_0;
1431 mcp->tov = tov;
1432 mcp->flags = 0;
1433 rval = qla2x00_mailbox_command(vha, mcp);
1434
1435 if (rval != QLA_SUCCESS) {
1436 /*EMPTY*/
1437 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1438 } else {
1439 sts_entry_t *sts_entry = buffer;
1440
1441 /* Mask reserved bits. */
1442 sts_entry->entry_status &=
1443 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
1444 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1445 "Done %s (status=%x).\n", __func__,
1446 sts_entry->entry_status);
1447 }
1448
1449 return rval;
1450 }
1451
1452 int
qla2x00_issue_iocb(scsi_qla_host_t * vha,void * buffer,dma_addr_t phys_addr,size_t size)1453 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
1454 size_t size)
1455 {
1456 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
1457 MBX_TOV_SECONDS);
1458 }
1459
1460 /*
1461 * qla2x00_abort_command
1462 * Abort command aborts a specified IOCB.
1463 *
1464 * Input:
1465 * ha = adapter block pointer.
1466 * sp = SB structure pointer.
1467 *
1468 * Returns:
1469 * qla2x00 local function return status code.
1470 *
1471 * Context:
1472 * Kernel context.
1473 */
1474 int
qla2x00_abort_command(srb_t * sp)1475 qla2x00_abort_command(srb_t *sp)
1476 {
1477 unsigned long flags = 0;
1478 int rval;
1479 uint32_t handle = 0;
1480 mbx_cmd_t mc;
1481 mbx_cmd_t *mcp = &mc;
1482 fc_port_t *fcport = sp->fcport;
1483 scsi_qla_host_t *vha = fcport->vha;
1484 struct qla_hw_data *ha = vha->hw;
1485 struct req_que *req;
1486 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1487
1488 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1489 "Entered %s.\n", __func__);
1490
1491 if (sp->qpair)
1492 req = sp->qpair->req;
1493 else
1494 req = vha->req;
1495
1496 spin_lock_irqsave(&ha->hardware_lock, flags);
1497 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1498 if (req->outstanding_cmds[handle] == sp)
1499 break;
1500 }
1501 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1502
1503 if (handle == req->num_outstanding_cmds) {
1504 /* command not found */
1505 return QLA_FUNCTION_FAILED;
1506 }
1507
1508 mcp->mb[0] = MBC_ABORT_COMMAND;
1509 if (HAS_EXTENDED_IDS(ha))
1510 mcp->mb[1] = fcport->loop_id;
1511 else
1512 mcp->mb[1] = fcport->loop_id << 8;
1513 mcp->mb[2] = (uint16_t)handle;
1514 mcp->mb[3] = (uint16_t)(handle >> 16);
1515 mcp->mb[6] = (uint16_t)cmd->device->lun;
1516 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1517 mcp->in_mb = MBX_0;
1518 mcp->tov = MBX_TOV_SECONDS;
1519 mcp->flags = 0;
1520 rval = qla2x00_mailbox_command(vha, mcp);
1521
1522 if (rval != QLA_SUCCESS) {
1523 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1524 } else {
1525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1526 "Done %s.\n", __func__);
1527 }
1528
1529 return rval;
1530 }
1531
1532 int
qla2x00_abort_target(struct fc_port * fcport,uint64_t l,int tag)1533 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1534 {
1535 int rval, rval2;
1536 mbx_cmd_t mc;
1537 mbx_cmd_t *mcp = &mc;
1538 scsi_qla_host_t *vha;
1539
1540 vha = fcport->vha;
1541
1542 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1543 "Entered %s.\n", __func__);
1544
1545 mcp->mb[0] = MBC_ABORT_TARGET;
1546 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
1547 if (HAS_EXTENDED_IDS(vha->hw)) {
1548 mcp->mb[1] = fcport->loop_id;
1549 mcp->mb[10] = 0;
1550 mcp->out_mb |= MBX_10;
1551 } else {
1552 mcp->mb[1] = fcport->loop_id << 8;
1553 }
1554 mcp->mb[2] = vha->hw->loop_reset_delay;
1555 mcp->mb[9] = vha->vp_idx;
1556
1557 mcp->in_mb = MBX_0;
1558 mcp->tov = MBX_TOV_SECONDS;
1559 mcp->flags = 0;
1560 rval = qla2x00_mailbox_command(vha, mcp);
1561 if (rval != QLA_SUCCESS) {
1562 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1563 "Failed=%x.\n", rval);
1564 }
1565
1566 /* Issue marker IOCB. */
1567 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
1568 MK_SYNC_ID);
1569 if (rval2 != QLA_SUCCESS) {
1570 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1571 "Failed to issue marker IOCB (%x).\n", rval2);
1572 } else {
1573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1574 "Done %s.\n", __func__);
1575 }
1576
1577 return rval;
1578 }
1579
1580 int
qla2x00_lun_reset(struct fc_port * fcport,uint64_t l,int tag)1581 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
1582 {
1583 int rval, rval2;
1584 mbx_cmd_t mc;
1585 mbx_cmd_t *mcp = &mc;
1586 scsi_qla_host_t *vha;
1587
1588 vha = fcport->vha;
1589
1590 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1591 "Entered %s.\n", __func__);
1592
1593 mcp->mb[0] = MBC_LUN_RESET;
1594 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
1595 if (HAS_EXTENDED_IDS(vha->hw))
1596 mcp->mb[1] = fcport->loop_id;
1597 else
1598 mcp->mb[1] = fcport->loop_id << 8;
1599 mcp->mb[2] = (u32)l;
1600 mcp->mb[3] = 0;
1601 mcp->mb[9] = vha->vp_idx;
1602
1603 mcp->in_mb = MBX_0;
1604 mcp->tov = MBX_TOV_SECONDS;
1605 mcp->flags = 0;
1606 rval = qla2x00_mailbox_command(vha, mcp);
1607 if (rval != QLA_SUCCESS) {
1608 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
1609 }
1610
1611 /* Issue marker IOCB. */
1612 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
1613 MK_SYNC_ID_LUN);
1614 if (rval2 != QLA_SUCCESS) {
1615 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1616 "Failed to issue marker IOCB (%x).\n", rval2);
1617 } else {
1618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1619 "Done %s.\n", __func__);
1620 }
1621
1622 return rval;
1623 }
1624
1625 /*
1626 * qla2x00_get_adapter_id
1627 * Get adapter ID and topology.
1628 *
1629 * Input:
1630 * ha = adapter block pointer.
1631 * id = pointer for loop ID.
1632 * al_pa = pointer for AL_PA.
1633 * area = pointer for area.
1634 * domain = pointer for domain.
1635 * top = pointer for topology.
1636 * TARGET_QUEUE_LOCK must be released.
1637 * ADAPTER_STATE_LOCK must be released.
1638 *
1639 * Returns:
1640 * qla2x00 local function return status code.
1641 *
1642 * Context:
1643 * Kernel context.
1644 */
1645 int
qla2x00_get_adapter_id(scsi_qla_host_t * vha,uint16_t * id,uint8_t * al_pa,uint8_t * area,uint8_t * domain,uint16_t * top,uint16_t * sw_cap)1646 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1647 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1648 {
1649 int rval;
1650 mbx_cmd_t mc;
1651 mbx_cmd_t *mcp = &mc;
1652
1653 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1654 "Entered %s.\n", __func__);
1655
1656 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1657 mcp->mb[9] = vha->vp_idx;
1658 mcp->out_mb = MBX_9|MBX_0;
1659 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1660 if (IS_CNA_CAPABLE(vha->hw))
1661 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1662 if (IS_FWI2_CAPABLE(vha->hw))
1663 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
1664 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw))
1665 mcp->in_mb |= MBX_15|MBX_21|MBX_22|MBX_23;
1666
1667 mcp->tov = MBX_TOV_SECONDS;
1668 mcp->flags = 0;
1669 rval = qla2x00_mailbox_command(vha, mcp);
1670 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1671 rval = QLA_COMMAND_ERROR;
1672 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1673 rval = QLA_INVALID_COMMAND;
1674
1675 /* Return data. */
1676 *id = mcp->mb[1];
1677 *al_pa = LSB(mcp->mb[2]);
1678 *area = MSB(mcp->mb[2]);
1679 *domain = LSB(mcp->mb[3]);
1680 *top = mcp->mb[6];
1681 *sw_cap = mcp->mb[7];
1682
1683 if (rval != QLA_SUCCESS) {
1684 /*EMPTY*/
1685 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1686 } else {
1687 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1688 "Done %s.\n", __func__);
1689
1690 if (IS_CNA_CAPABLE(vha->hw)) {
1691 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1692 vha->fcoe_fcf_idx = mcp->mb[10];
1693 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1694 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1695 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1696 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1697 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1698 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1699 }
1700 /* If FA-WWN supported */
1701 if (IS_FAWWN_CAPABLE(vha->hw)) {
1702 if (mcp->mb[7] & BIT_14) {
1703 vha->port_name[0] = MSB(mcp->mb[16]);
1704 vha->port_name[1] = LSB(mcp->mb[16]);
1705 vha->port_name[2] = MSB(mcp->mb[17]);
1706 vha->port_name[3] = LSB(mcp->mb[17]);
1707 vha->port_name[4] = MSB(mcp->mb[18]);
1708 vha->port_name[5] = LSB(mcp->mb[18]);
1709 vha->port_name[6] = MSB(mcp->mb[19]);
1710 vha->port_name[7] = LSB(mcp->mb[19]);
1711 fc_host_port_name(vha->host) =
1712 wwn_to_u64(vha->port_name);
1713 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1714 "FA-WWN acquired %016llx\n",
1715 wwn_to_u64(vha->port_name));
1716 }
1717 }
1718
1719 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) {
1720 vha->bbcr = mcp->mb[15];
1721 if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) {
1722 ql_log(ql_log_info, vha, 0x11a4,
1723 "SCM: EDC ELS completed, flags 0x%x\n",
1724 mcp->mb[21]);
1725 }
1726 if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) {
1727 vha->hw->flags.scm_enabled = 1;
1728 vha->scm_fabric_connection_flags |=
1729 SCM_FLAG_RDF_COMPLETED;
1730 ql_log(ql_log_info, vha, 0x11a5,
1731 "SCM: RDF ELS completed, flags 0x%x\n",
1732 mcp->mb[23]);
1733 }
1734 }
1735 }
1736
1737 return rval;
1738 }
1739
1740 /*
1741 * qla2x00_get_retry_cnt
1742 * Get current firmware login retry count and delay.
1743 *
1744 * Input:
1745 * ha = adapter block pointer.
1746 * retry_cnt = pointer to login retry count.
1747 * tov = pointer to login timeout value.
1748 *
1749 * Returns:
1750 * qla2x00 local function return status code.
1751 *
1752 * Context:
1753 * Kernel context.
1754 */
1755 int
qla2x00_get_retry_cnt(scsi_qla_host_t * vha,uint8_t * retry_cnt,uint8_t * tov,uint16_t * r_a_tov)1756 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1757 uint16_t *r_a_tov)
1758 {
1759 int rval;
1760 uint16_t ratov;
1761 mbx_cmd_t mc;
1762 mbx_cmd_t *mcp = &mc;
1763
1764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1765 "Entered %s.\n", __func__);
1766
1767 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1768 mcp->out_mb = MBX_0;
1769 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1770 mcp->tov = MBX_TOV_SECONDS;
1771 mcp->flags = 0;
1772 rval = qla2x00_mailbox_command(vha, mcp);
1773
1774 if (rval != QLA_SUCCESS) {
1775 /*EMPTY*/
1776 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1777 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1778 } else {
1779 /* Convert returned data and check our values. */
1780 *r_a_tov = mcp->mb[3] / 2;
1781 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1782 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1783 /* Update to the larger values */
1784 *retry_cnt = (uint8_t)mcp->mb[1];
1785 *tov = ratov;
1786 }
1787
1788 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
1789 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1790 }
1791
1792 return rval;
1793 }
1794
1795 /*
1796 * qla2x00_init_firmware
1797 * Initialize adapter firmware.
1798 *
1799 * Input:
1800 * ha = adapter block pointer.
1801 * dptr = Initialization control block pointer.
1802 * size = size of initialization control block.
1803 * TARGET_QUEUE_LOCK must be released.
1804 * ADAPTER_STATE_LOCK must be released.
1805 *
1806 * Returns:
1807 * qla2x00 local function return status code.
1808 *
1809 * Context:
1810 * Kernel context.
1811 */
1812 int
qla2x00_init_firmware(scsi_qla_host_t * vha,uint16_t size)1813 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1814 {
1815 int rval;
1816 mbx_cmd_t mc;
1817 mbx_cmd_t *mcp = &mc;
1818 struct qla_hw_data *ha = vha->hw;
1819
1820 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1821 "Entered %s.\n", __func__);
1822
1823 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1824 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
1825 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1826
1827 if (ha->flags.npiv_supported)
1828 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1829 else
1830 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1831
1832 mcp->mb[1] = 0;
1833 mcp->mb[2] = MSW(ha->init_cb_dma);
1834 mcp->mb[3] = LSW(ha->init_cb_dma);
1835 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1836 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1837 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1838 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1839 mcp->mb[1] = BIT_0;
1840 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1841 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1842 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1843 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1844 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1845 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1846 }
1847
1848 if (ha->flags.scm_supported_f || vha->flags.nvme2_enabled) {
1849 mcp->mb[1] |= BIT_1;
1850 mcp->mb[16] = MSW(ha->sf_init_cb_dma);
1851 mcp->mb[17] = LSW(ha->sf_init_cb_dma);
1852 mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma));
1853 mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma));
1854 mcp->mb[15] = sizeof(*ha->sf_init_cb);
1855 mcp->out_mb |= MBX_19|MBX_18|MBX_17|MBX_16|MBX_15;
1856 }
1857
1858 /* 1 and 2 should normally be captured. */
1859 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1860 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1861 /* mb3 is additional info about the installed SFP. */
1862 mcp->in_mb |= MBX_3;
1863 mcp->buf_size = size;
1864 mcp->flags = MBX_DMA_OUT;
1865 mcp->tov = MBX_TOV_SECONDS;
1866 rval = qla2x00_mailbox_command(vha, mcp);
1867
1868 if (rval != QLA_SUCCESS) {
1869 /*EMPTY*/
1870 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1871 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
1872 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1873 if (ha->init_cb) {
1874 ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
1875 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1876 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
1877 }
1878 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1879 ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
1880 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1881 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
1882 }
1883 } else {
1884 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1885 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1886 ql_dbg(ql_dbg_mbx, vha, 0x119d,
1887 "Invalid SFP/Validation Failed\n");
1888 }
1889 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1890 "Done %s.\n", __func__);
1891 }
1892
1893 return rval;
1894 }
1895
1896
1897 /*
1898 * qla2x00_get_port_database
1899 * Issue normal/enhanced get port database mailbox command
1900 * and copy device name as necessary.
1901 *
1902 * Input:
1903 * ha = adapter state pointer.
1904 * dev = structure pointer.
1905 * opt = enhanced cmd option byte.
1906 *
1907 * Returns:
1908 * qla2x00 local function return status code.
1909 *
1910 * Context:
1911 * Kernel context.
1912 */
1913 int
qla2x00_get_port_database(scsi_qla_host_t * vha,fc_port_t * fcport,uint8_t opt)1914 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1915 {
1916 int rval;
1917 mbx_cmd_t mc;
1918 mbx_cmd_t *mcp = &mc;
1919 port_database_t *pd;
1920 struct port_database_24xx *pd24;
1921 dma_addr_t pd_dma;
1922 struct qla_hw_data *ha = vha->hw;
1923
1924 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1925 "Entered %s.\n", __func__);
1926
1927 pd24 = NULL;
1928 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1929 if (pd == NULL) {
1930 ql_log(ql_log_warn, vha, 0x1050,
1931 "Failed to allocate port database structure.\n");
1932 fcport->query = 0;
1933 return QLA_MEMORY_ALLOC_FAILED;
1934 }
1935
1936 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1937 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1938 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1939 mcp->mb[2] = MSW(pd_dma);
1940 mcp->mb[3] = LSW(pd_dma);
1941 mcp->mb[6] = MSW(MSD(pd_dma));
1942 mcp->mb[7] = LSW(MSD(pd_dma));
1943 mcp->mb[9] = vha->vp_idx;
1944 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1945 mcp->in_mb = MBX_0;
1946 if (IS_FWI2_CAPABLE(ha)) {
1947 mcp->mb[1] = fcport->loop_id;
1948 mcp->mb[10] = opt;
1949 mcp->out_mb |= MBX_10|MBX_1;
1950 mcp->in_mb |= MBX_1;
1951 } else if (HAS_EXTENDED_IDS(ha)) {
1952 mcp->mb[1] = fcport->loop_id;
1953 mcp->mb[10] = opt;
1954 mcp->out_mb |= MBX_10|MBX_1;
1955 } else {
1956 mcp->mb[1] = fcport->loop_id << 8 | opt;
1957 mcp->out_mb |= MBX_1;
1958 }
1959 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1960 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1961 mcp->flags = MBX_DMA_IN;
1962 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1963 rval = qla2x00_mailbox_command(vha, mcp);
1964 if (rval != QLA_SUCCESS)
1965 goto gpd_error_out;
1966
1967 if (IS_FWI2_CAPABLE(ha)) {
1968 uint64_t zero = 0;
1969 u8 current_login_state, last_login_state;
1970
1971 pd24 = (struct port_database_24xx *) pd;
1972
1973 /* Check for logged in state. */
1974 if (NVME_TARGET(ha, fcport)) {
1975 current_login_state = pd24->current_login_state >> 4;
1976 last_login_state = pd24->last_login_state >> 4;
1977 } else {
1978 current_login_state = pd24->current_login_state & 0xf;
1979 last_login_state = pd24->last_login_state & 0xf;
1980 }
1981 fcport->current_login_state = pd24->current_login_state;
1982 fcport->last_login_state = pd24->last_login_state;
1983
1984 /* Check for logged in state. */
1985 if (current_login_state != PDS_PRLI_COMPLETE &&
1986 last_login_state != PDS_PRLI_COMPLETE) {
1987 ql_dbg(ql_dbg_mbx, vha, 0x119a,
1988 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
1989 current_login_state, last_login_state,
1990 fcport->loop_id);
1991 rval = QLA_FUNCTION_FAILED;
1992
1993 if (!fcport->query)
1994 goto gpd_error_out;
1995 }
1996
1997 if (fcport->loop_id == FC_NO_LOOP_ID ||
1998 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1999 memcmp(fcport->port_name, pd24->port_name, 8))) {
2000 /* We lost the device mid way. */
2001 rval = QLA_NOT_LOGGED_IN;
2002 goto gpd_error_out;
2003 }
2004
2005 /* Names are little-endian. */
2006 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
2007 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
2008
2009 /* Get port_id of device. */
2010 fcport->d_id.b.domain = pd24->port_id[0];
2011 fcport->d_id.b.area = pd24->port_id[1];
2012 fcport->d_id.b.al_pa = pd24->port_id[2];
2013 fcport->d_id.b.rsvd_1 = 0;
2014
2015 /* If not target must be initiator or unknown type. */
2016 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
2017 fcport->port_type = FCT_INITIATOR;
2018 else
2019 fcport->port_type = FCT_TARGET;
2020
2021 /* Passback COS information. */
2022 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
2023 FC_COS_CLASS2 : FC_COS_CLASS3;
2024
2025 if (pd24->prli_svc_param_word_3[0] & BIT_7)
2026 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
2027 } else {
2028 uint64_t zero = 0;
2029
2030 /* Check for logged in state. */
2031 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
2032 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
2033 ql_dbg(ql_dbg_mbx, vha, 0x100a,
2034 "Unable to verify login-state (%x/%x) - "
2035 "portid=%02x%02x%02x.\n", pd->master_state,
2036 pd->slave_state, fcport->d_id.b.domain,
2037 fcport->d_id.b.area, fcport->d_id.b.al_pa);
2038 rval = QLA_FUNCTION_FAILED;
2039 goto gpd_error_out;
2040 }
2041
2042 if (fcport->loop_id == FC_NO_LOOP_ID ||
2043 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
2044 memcmp(fcport->port_name, pd->port_name, 8))) {
2045 /* We lost the device mid way. */
2046 rval = QLA_NOT_LOGGED_IN;
2047 goto gpd_error_out;
2048 }
2049
2050 /* Names are little-endian. */
2051 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
2052 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
2053
2054 /* Get port_id of device. */
2055 fcport->d_id.b.domain = pd->port_id[0];
2056 fcport->d_id.b.area = pd->port_id[3];
2057 fcport->d_id.b.al_pa = pd->port_id[2];
2058 fcport->d_id.b.rsvd_1 = 0;
2059
2060 /* If not target must be initiator or unknown type. */
2061 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
2062 fcport->port_type = FCT_INITIATOR;
2063 else
2064 fcport->port_type = FCT_TARGET;
2065
2066 /* Passback COS information. */
2067 fcport->supported_classes = (pd->options & BIT_4) ?
2068 FC_COS_CLASS2 : FC_COS_CLASS3;
2069 }
2070
2071 gpd_error_out:
2072 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
2073 fcport->query = 0;
2074
2075 if (rval != QLA_SUCCESS) {
2076 ql_dbg(ql_dbg_mbx, vha, 0x1052,
2077 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
2078 mcp->mb[0], mcp->mb[1]);
2079 } else {
2080 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
2081 "Done %s.\n", __func__);
2082 }
2083
2084 return rval;
2085 }
2086
2087 int
qla24xx_get_port_database(scsi_qla_host_t * vha,u16 nport_handle,struct port_database_24xx * pdb)2088 qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle,
2089 struct port_database_24xx *pdb)
2090 {
2091 mbx_cmd_t mc;
2092 mbx_cmd_t *mcp = &mc;
2093 dma_addr_t pdb_dma;
2094 int rval;
2095
2096 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115,
2097 "Entered %s.\n", __func__);
2098
2099 memset(pdb, 0, sizeof(*pdb));
2100
2101 pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb,
2102 sizeof(*pdb), DMA_FROM_DEVICE);
2103 if (!pdb_dma) {
2104 ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n");
2105 return QLA_MEMORY_ALLOC_FAILED;
2106 }
2107
2108 mcp->mb[0] = MBC_GET_PORT_DATABASE;
2109 mcp->mb[1] = nport_handle;
2110 mcp->mb[2] = MSW(LSD(pdb_dma));
2111 mcp->mb[3] = LSW(LSD(pdb_dma));
2112 mcp->mb[6] = MSW(MSD(pdb_dma));
2113 mcp->mb[7] = LSW(MSD(pdb_dma));
2114 mcp->mb[9] = 0;
2115 mcp->mb[10] = 0;
2116 mcp->out_mb = MBX_10|MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2117 mcp->in_mb = MBX_1|MBX_0;
2118 mcp->buf_size = sizeof(*pdb);
2119 mcp->flags = MBX_DMA_IN;
2120 mcp->tov = vha->hw->login_timeout * 2;
2121 rval = qla2x00_mailbox_command(vha, mcp);
2122
2123 if (rval != QLA_SUCCESS) {
2124 ql_dbg(ql_dbg_mbx, vha, 0x111a,
2125 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2126 rval, mcp->mb[0], mcp->mb[1]);
2127 } else {
2128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b,
2129 "Done %s.\n", __func__);
2130 }
2131
2132 dma_unmap_single(&vha->hw->pdev->dev, pdb_dma,
2133 sizeof(*pdb), DMA_FROM_DEVICE);
2134
2135 return rval;
2136 }
2137
2138 /*
2139 * qla2x00_get_firmware_state
2140 * Get adapter firmware state.
2141 *
2142 * Input:
2143 * ha = adapter block pointer.
2144 * dptr = pointer for firmware state.
2145 * TARGET_QUEUE_LOCK must be released.
2146 * ADAPTER_STATE_LOCK must be released.
2147 *
2148 * Returns:
2149 * qla2x00 local function return status code.
2150 *
2151 * Context:
2152 * Kernel context.
2153 */
2154 int
qla2x00_get_firmware_state(scsi_qla_host_t * vha,uint16_t * states)2155 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
2156 {
2157 int rval;
2158 mbx_cmd_t mc;
2159 mbx_cmd_t *mcp = &mc;
2160 struct qla_hw_data *ha = vha->hw;
2161
2162 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
2163 "Entered %s.\n", __func__);
2164
2165 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
2166 mcp->out_mb = MBX_0;
2167 if (IS_FWI2_CAPABLE(vha->hw))
2168 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2169 else
2170 mcp->in_mb = MBX_1|MBX_0;
2171 mcp->tov = MBX_TOV_SECONDS;
2172 mcp->flags = 0;
2173 rval = qla2x00_mailbox_command(vha, mcp);
2174
2175 /* Return firmware states. */
2176 states[0] = mcp->mb[1];
2177 if (IS_FWI2_CAPABLE(vha->hw)) {
2178 states[1] = mcp->mb[2];
2179 states[2] = mcp->mb[3]; /* SFP info */
2180 states[3] = mcp->mb[4];
2181 states[4] = mcp->mb[5];
2182 states[5] = mcp->mb[6]; /* DPORT status */
2183 }
2184
2185 if (rval != QLA_SUCCESS) {
2186 /*EMPTY*/
2187 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
2188 } else {
2189 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
2190 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
2191 ql_dbg(ql_dbg_mbx, vha, 0x119e,
2192 "Invalid SFP/Validation Failed\n");
2193 }
2194 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
2195 "Done %s.\n", __func__);
2196 }
2197
2198 return rval;
2199 }
2200
2201 /*
2202 * qla2x00_get_port_name
2203 * Issue get port name mailbox command.
2204 * Returned name is in big endian format.
2205 *
2206 * Input:
2207 * ha = adapter block pointer.
2208 * loop_id = loop ID of device.
2209 * name = pointer for name.
2210 * TARGET_QUEUE_LOCK must be released.
2211 * ADAPTER_STATE_LOCK must be released.
2212 *
2213 * Returns:
2214 * qla2x00 local function return status code.
2215 *
2216 * Context:
2217 * Kernel context.
2218 */
2219 int
qla2x00_get_port_name(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t * name,uint8_t opt)2220 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
2221 uint8_t opt)
2222 {
2223 int rval;
2224 mbx_cmd_t mc;
2225 mbx_cmd_t *mcp = &mc;
2226
2227 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
2228 "Entered %s.\n", __func__);
2229
2230 mcp->mb[0] = MBC_GET_PORT_NAME;
2231 mcp->mb[9] = vha->vp_idx;
2232 mcp->out_mb = MBX_9|MBX_1|MBX_0;
2233 if (HAS_EXTENDED_IDS(vha->hw)) {
2234 mcp->mb[1] = loop_id;
2235 mcp->mb[10] = opt;
2236 mcp->out_mb |= MBX_10;
2237 } else {
2238 mcp->mb[1] = loop_id << 8 | opt;
2239 }
2240
2241 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2242 mcp->tov = MBX_TOV_SECONDS;
2243 mcp->flags = 0;
2244 rval = qla2x00_mailbox_command(vha, mcp);
2245
2246 if (rval != QLA_SUCCESS) {
2247 /*EMPTY*/
2248 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
2249 } else {
2250 if (name != NULL) {
2251 /* This function returns name in big endian. */
2252 name[0] = MSB(mcp->mb[2]);
2253 name[1] = LSB(mcp->mb[2]);
2254 name[2] = MSB(mcp->mb[3]);
2255 name[3] = LSB(mcp->mb[3]);
2256 name[4] = MSB(mcp->mb[6]);
2257 name[5] = LSB(mcp->mb[6]);
2258 name[6] = MSB(mcp->mb[7]);
2259 name[7] = LSB(mcp->mb[7]);
2260 }
2261
2262 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2263 "Done %s.\n", __func__);
2264 }
2265
2266 return rval;
2267 }
2268
2269 /*
2270 * qla24xx_link_initialization
2271 * Issue link initialization mailbox command.
2272 *
2273 * Input:
2274 * ha = adapter block pointer.
2275 * TARGET_QUEUE_LOCK must be released.
2276 * ADAPTER_STATE_LOCK must be released.
2277 *
2278 * Returns:
2279 * qla2x00 local function return status code.
2280 *
2281 * Context:
2282 * Kernel context.
2283 */
2284 int
qla24xx_link_initialize(scsi_qla_host_t * vha)2285 qla24xx_link_initialize(scsi_qla_host_t *vha)
2286 {
2287 int rval;
2288 mbx_cmd_t mc;
2289 mbx_cmd_t *mcp = &mc;
2290
2291 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2292 "Entered %s.\n", __func__);
2293
2294 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2295 return QLA_FUNCTION_FAILED;
2296
2297 mcp->mb[0] = MBC_LINK_INITIALIZATION;
2298 mcp->mb[1] = BIT_4;
2299 if (vha->hw->operating_mode == LOOP)
2300 mcp->mb[1] |= BIT_6;
2301 else
2302 mcp->mb[1] |= BIT_5;
2303 mcp->mb[2] = 0;
2304 mcp->mb[3] = 0;
2305 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2306 mcp->in_mb = MBX_0;
2307 mcp->tov = MBX_TOV_SECONDS;
2308 mcp->flags = 0;
2309 rval = qla2x00_mailbox_command(vha, mcp);
2310
2311 if (rval != QLA_SUCCESS) {
2312 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2313 } else {
2314 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2315 "Done %s.\n", __func__);
2316 }
2317
2318 return rval;
2319 }
2320
2321 /*
2322 * qla2x00_lip_reset
2323 * Issue LIP reset mailbox command.
2324 *
2325 * Input:
2326 * ha = adapter block pointer.
2327 * TARGET_QUEUE_LOCK must be released.
2328 * ADAPTER_STATE_LOCK must be released.
2329 *
2330 * Returns:
2331 * qla2x00 local function return status code.
2332 *
2333 * Context:
2334 * Kernel context.
2335 */
2336 int
qla2x00_lip_reset(scsi_qla_host_t * vha)2337 qla2x00_lip_reset(scsi_qla_host_t *vha)
2338 {
2339 int rval;
2340 mbx_cmd_t mc;
2341 mbx_cmd_t *mcp = &mc;
2342
2343 ql_dbg(ql_dbg_disc, vha, 0x105a,
2344 "Entered %s.\n", __func__);
2345
2346 if (IS_CNA_CAPABLE(vha->hw)) {
2347 /* Logout across all FCFs. */
2348 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2349 mcp->mb[1] = BIT_1;
2350 mcp->mb[2] = 0;
2351 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2352 } else if (IS_FWI2_CAPABLE(vha->hw)) {
2353 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2354 mcp->mb[1] = BIT_4;
2355 mcp->mb[2] = 0;
2356 mcp->mb[3] = vha->hw->loop_reset_delay;
2357 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2358 } else {
2359 mcp->mb[0] = MBC_LIP_RESET;
2360 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2361 if (HAS_EXTENDED_IDS(vha->hw)) {
2362 mcp->mb[1] = 0x00ff;
2363 mcp->mb[10] = 0;
2364 mcp->out_mb |= MBX_10;
2365 } else {
2366 mcp->mb[1] = 0xff00;
2367 }
2368 mcp->mb[2] = vha->hw->loop_reset_delay;
2369 mcp->mb[3] = 0;
2370 }
2371 mcp->in_mb = MBX_0;
2372 mcp->tov = MBX_TOV_SECONDS;
2373 mcp->flags = 0;
2374 rval = qla2x00_mailbox_command(vha, mcp);
2375
2376 if (rval != QLA_SUCCESS) {
2377 /*EMPTY*/
2378 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
2379 } else {
2380 /*EMPTY*/
2381 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2382 "Done %s.\n", __func__);
2383 }
2384
2385 return rval;
2386 }
2387
2388 /*
2389 * qla2x00_send_sns
2390 * Send SNS command.
2391 *
2392 * Input:
2393 * ha = adapter block pointer.
2394 * sns = pointer for command.
2395 * cmd_size = command size.
2396 * buf_size = response/command size.
2397 * TARGET_QUEUE_LOCK must be released.
2398 * ADAPTER_STATE_LOCK must be released.
2399 *
2400 * Returns:
2401 * qla2x00 local function return status code.
2402 *
2403 * Context:
2404 * Kernel context.
2405 */
2406 int
qla2x00_send_sns(scsi_qla_host_t * vha,dma_addr_t sns_phys_address,uint16_t cmd_size,size_t buf_size)2407 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
2408 uint16_t cmd_size, size_t buf_size)
2409 {
2410 int rval;
2411 mbx_cmd_t mc;
2412 mbx_cmd_t *mcp = &mc;
2413
2414 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2415 "Entered %s.\n", __func__);
2416
2417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
2418 "Retry cnt=%d ratov=%d total tov=%d.\n",
2419 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
2420
2421 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2422 mcp->mb[1] = cmd_size;
2423 mcp->mb[2] = MSW(sns_phys_address);
2424 mcp->mb[3] = LSW(sns_phys_address);
2425 mcp->mb[6] = MSW(MSD(sns_phys_address));
2426 mcp->mb[7] = LSW(MSD(sns_phys_address));
2427 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2428 mcp->in_mb = MBX_0|MBX_1;
2429 mcp->buf_size = buf_size;
2430 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
2431 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2432 rval = qla2x00_mailbox_command(vha, mcp);
2433
2434 if (rval != QLA_SUCCESS) {
2435 /*EMPTY*/
2436 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2437 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2438 rval, mcp->mb[0], mcp->mb[1]);
2439 } else {
2440 /*EMPTY*/
2441 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2442 "Done %s.\n", __func__);
2443 }
2444
2445 return rval;
2446 }
2447
2448 int
qla24xx_login_fabric(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa,uint16_t * mb,uint8_t opt)2449 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2450 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2451 {
2452 int rval;
2453
2454 struct logio_entry_24xx *lg;
2455 dma_addr_t lg_dma;
2456 uint32_t iop[2];
2457 struct qla_hw_data *ha = vha->hw;
2458 struct req_que *req;
2459
2460 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2461 "Entered %s.\n", __func__);
2462
2463 if (vha->vp_idx && vha->qpair)
2464 req = vha->qpair->req;
2465 else
2466 req = ha->req_q_map[0];
2467
2468 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2469 if (lg == NULL) {
2470 ql_log(ql_log_warn, vha, 0x1062,
2471 "Failed to allocate login IOCB.\n");
2472 return QLA_MEMORY_ALLOC_FAILED;
2473 }
2474
2475 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2476 lg->entry_count = 1;
2477 lg->handle = make_handle(req->id, lg->handle);
2478 lg->nport_handle = cpu_to_le16(loop_id);
2479 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
2480 if (opt & BIT_0)
2481 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
2482 if (opt & BIT_1)
2483 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
2484 lg->port_id[0] = al_pa;
2485 lg->port_id[1] = area;
2486 lg->port_id[2] = domain;
2487 lg->vp_index = vha->vp_idx;
2488 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2489 (ha->r_a_tov / 10 * 2) + 2);
2490 if (rval != QLA_SUCCESS) {
2491 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2492 "Failed to issue login IOCB (%x).\n", rval);
2493 } else if (lg->entry_status != 0) {
2494 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2495 "Failed to complete IOCB -- error status (%x).\n",
2496 lg->entry_status);
2497 rval = QLA_FUNCTION_FAILED;
2498 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
2499 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2500 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2501
2502 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2503 "Failed to complete IOCB -- completion status (%x) "
2504 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2505 iop[0], iop[1]);
2506
2507 switch (iop[0]) {
2508 case LSC_SCODE_PORTID_USED:
2509 mb[0] = MBS_PORT_ID_USED;
2510 mb[1] = LSW(iop[1]);
2511 break;
2512 case LSC_SCODE_NPORT_USED:
2513 mb[0] = MBS_LOOP_ID_USED;
2514 break;
2515 case LSC_SCODE_NOLINK:
2516 case LSC_SCODE_NOIOCB:
2517 case LSC_SCODE_NOXCB:
2518 case LSC_SCODE_CMD_FAILED:
2519 case LSC_SCODE_NOFABRIC:
2520 case LSC_SCODE_FW_NOT_READY:
2521 case LSC_SCODE_NOT_LOGGED_IN:
2522 case LSC_SCODE_NOPCB:
2523 case LSC_SCODE_ELS_REJECT:
2524 case LSC_SCODE_CMD_PARAM_ERR:
2525 case LSC_SCODE_NONPORT:
2526 case LSC_SCODE_LOGGED_IN:
2527 case LSC_SCODE_NOFLOGI_ACC:
2528 default:
2529 mb[0] = MBS_COMMAND_ERROR;
2530 break;
2531 }
2532 } else {
2533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2534 "Done %s.\n", __func__);
2535
2536 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2537
2538 mb[0] = MBS_COMMAND_COMPLETE;
2539 mb[1] = 0;
2540 if (iop[0] & BIT_4) {
2541 if (iop[0] & BIT_8)
2542 mb[1] |= BIT_1;
2543 } else
2544 mb[1] = BIT_0;
2545
2546 /* Passback COS information. */
2547 mb[10] = 0;
2548 if (lg->io_parameter[7] || lg->io_parameter[8])
2549 mb[10] |= BIT_0; /* Class 2. */
2550 if (lg->io_parameter[9] || lg->io_parameter[10])
2551 mb[10] |= BIT_1; /* Class 3. */
2552 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2553 mb[10] |= BIT_7; /* Confirmed Completion
2554 * Allowed
2555 */
2556 }
2557
2558 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2559
2560 return rval;
2561 }
2562
2563 /*
2564 * qla2x00_login_fabric
2565 * Issue login fabric port mailbox command.
2566 *
2567 * Input:
2568 * ha = adapter block pointer.
2569 * loop_id = device loop ID.
2570 * domain = device domain.
2571 * area = device area.
2572 * al_pa = device AL_PA.
2573 * status = pointer for return status.
2574 * opt = command options.
2575 * TARGET_QUEUE_LOCK must be released.
2576 * ADAPTER_STATE_LOCK must be released.
2577 *
2578 * Returns:
2579 * qla2x00 local function return status code.
2580 *
2581 * Context:
2582 * Kernel context.
2583 */
2584 int
qla2x00_login_fabric(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa,uint16_t * mb,uint8_t opt)2585 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2586 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2587 {
2588 int rval;
2589 mbx_cmd_t mc;
2590 mbx_cmd_t *mcp = &mc;
2591 struct qla_hw_data *ha = vha->hw;
2592
2593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2594 "Entered %s.\n", __func__);
2595
2596 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2597 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2598 if (HAS_EXTENDED_IDS(ha)) {
2599 mcp->mb[1] = loop_id;
2600 mcp->mb[10] = opt;
2601 mcp->out_mb |= MBX_10;
2602 } else {
2603 mcp->mb[1] = (loop_id << 8) | opt;
2604 }
2605 mcp->mb[2] = domain;
2606 mcp->mb[3] = area << 8 | al_pa;
2607
2608 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2609 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2610 mcp->flags = 0;
2611 rval = qla2x00_mailbox_command(vha, mcp);
2612
2613 /* Return mailbox statuses. */
2614 if (mb != NULL) {
2615 mb[0] = mcp->mb[0];
2616 mb[1] = mcp->mb[1];
2617 mb[2] = mcp->mb[2];
2618 mb[6] = mcp->mb[6];
2619 mb[7] = mcp->mb[7];
2620 /* COS retrieved from Get-Port-Database mailbox command. */
2621 mb[10] = 0;
2622 }
2623
2624 if (rval != QLA_SUCCESS) {
2625 /* RLU tmp code: need to change main mailbox_command function to
2626 * return ok even when the mailbox completion value is not
2627 * SUCCESS. The caller needs to be responsible to interpret
2628 * the return values of this mailbox command if we're not
2629 * to change too much of the existing code.
2630 */
2631 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2632 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2633 mcp->mb[0] == 0x4006)
2634 rval = QLA_SUCCESS;
2635
2636 /*EMPTY*/
2637 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2638 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2639 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
2640 } else {
2641 /*EMPTY*/
2642 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2643 "Done %s.\n", __func__);
2644 }
2645
2646 return rval;
2647 }
2648
2649 /*
2650 * qla2x00_login_local_device
2651 * Issue login loop port mailbox command.
2652 *
2653 * Input:
2654 * ha = adapter block pointer.
2655 * loop_id = device loop ID.
2656 * opt = command options.
2657 *
2658 * Returns:
2659 * Return status code.
2660 *
2661 * Context:
2662 * Kernel context.
2663 *
2664 */
2665 int
qla2x00_login_local_device(scsi_qla_host_t * vha,fc_port_t * fcport,uint16_t * mb_ret,uint8_t opt)2666 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
2667 uint16_t *mb_ret, uint8_t opt)
2668 {
2669 int rval;
2670 mbx_cmd_t mc;
2671 mbx_cmd_t *mcp = &mc;
2672 struct qla_hw_data *ha = vha->hw;
2673
2674 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2675 "Entered %s.\n", __func__);
2676
2677 if (IS_FWI2_CAPABLE(ha))
2678 return qla24xx_login_fabric(vha, fcport->loop_id,
2679 fcport->d_id.b.domain, fcport->d_id.b.area,
2680 fcport->d_id.b.al_pa, mb_ret, opt);
2681
2682 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2683 if (HAS_EXTENDED_IDS(ha))
2684 mcp->mb[1] = fcport->loop_id;
2685 else
2686 mcp->mb[1] = fcport->loop_id << 8;
2687 mcp->mb[2] = opt;
2688 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2689 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2690 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2691 mcp->flags = 0;
2692 rval = qla2x00_mailbox_command(vha, mcp);
2693
2694 /* Return mailbox statuses. */
2695 if (mb_ret != NULL) {
2696 mb_ret[0] = mcp->mb[0];
2697 mb_ret[1] = mcp->mb[1];
2698 mb_ret[6] = mcp->mb[6];
2699 mb_ret[7] = mcp->mb[7];
2700 }
2701
2702 if (rval != QLA_SUCCESS) {
2703 /* AV tmp code: need to change main mailbox_command function to
2704 * return ok even when the mailbox completion value is not
2705 * SUCCESS. The caller needs to be responsible to interpret
2706 * the return values of this mailbox command if we're not
2707 * to change too much of the existing code.
2708 */
2709 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2710 rval = QLA_SUCCESS;
2711
2712 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2713 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2714 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
2715 } else {
2716 /*EMPTY*/
2717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2718 "Done %s.\n", __func__);
2719 }
2720
2721 return (rval);
2722 }
2723
2724 int
qla24xx_fabric_logout(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa)2725 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2726 uint8_t area, uint8_t al_pa)
2727 {
2728 int rval;
2729 struct logio_entry_24xx *lg;
2730 dma_addr_t lg_dma;
2731 struct qla_hw_data *ha = vha->hw;
2732 struct req_que *req;
2733
2734 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2735 "Entered %s.\n", __func__);
2736
2737 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2738 if (lg == NULL) {
2739 ql_log(ql_log_warn, vha, 0x106e,
2740 "Failed to allocate logout IOCB.\n");
2741 return QLA_MEMORY_ALLOC_FAILED;
2742 }
2743
2744 req = vha->req;
2745 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2746 lg->entry_count = 1;
2747 lg->handle = make_handle(req->id, lg->handle);
2748 lg->nport_handle = cpu_to_le16(loop_id);
2749 lg->control_flags =
2750 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2751 LCF_FREE_NPORT);
2752 lg->port_id[0] = al_pa;
2753 lg->port_id[1] = area;
2754 lg->port_id[2] = domain;
2755 lg->vp_index = vha->vp_idx;
2756 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2757 (ha->r_a_tov / 10 * 2) + 2);
2758 if (rval != QLA_SUCCESS) {
2759 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2760 "Failed to issue logout IOCB (%x).\n", rval);
2761 } else if (lg->entry_status != 0) {
2762 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2763 "Failed to complete IOCB -- error status (%x).\n",
2764 lg->entry_status);
2765 rval = QLA_FUNCTION_FAILED;
2766 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
2767 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2768 "Failed to complete IOCB -- completion status (%x) "
2769 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2770 le32_to_cpu(lg->io_parameter[0]),
2771 le32_to_cpu(lg->io_parameter[1]));
2772 } else {
2773 /*EMPTY*/
2774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2775 "Done %s.\n", __func__);
2776 }
2777
2778 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2779
2780 return rval;
2781 }
2782
2783 /*
2784 * qla2x00_fabric_logout
2785 * Issue logout fabric port mailbox command.
2786 *
2787 * Input:
2788 * ha = adapter block pointer.
2789 * loop_id = device loop ID.
2790 * TARGET_QUEUE_LOCK must be released.
2791 * ADAPTER_STATE_LOCK must be released.
2792 *
2793 * Returns:
2794 * qla2x00 local function return status code.
2795 *
2796 * Context:
2797 * Kernel context.
2798 */
2799 int
qla2x00_fabric_logout(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa)2800 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2801 uint8_t area, uint8_t al_pa)
2802 {
2803 int rval;
2804 mbx_cmd_t mc;
2805 mbx_cmd_t *mcp = &mc;
2806
2807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2808 "Entered %s.\n", __func__);
2809
2810 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2811 mcp->out_mb = MBX_1|MBX_0;
2812 if (HAS_EXTENDED_IDS(vha->hw)) {
2813 mcp->mb[1] = loop_id;
2814 mcp->mb[10] = 0;
2815 mcp->out_mb |= MBX_10;
2816 } else {
2817 mcp->mb[1] = loop_id << 8;
2818 }
2819
2820 mcp->in_mb = MBX_1|MBX_0;
2821 mcp->tov = MBX_TOV_SECONDS;
2822 mcp->flags = 0;
2823 rval = qla2x00_mailbox_command(vha, mcp);
2824
2825 if (rval != QLA_SUCCESS) {
2826 /*EMPTY*/
2827 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2828 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
2829 } else {
2830 /*EMPTY*/
2831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2832 "Done %s.\n", __func__);
2833 }
2834
2835 return rval;
2836 }
2837
2838 /*
2839 * qla2x00_full_login_lip
2840 * Issue full login LIP mailbox command.
2841 *
2842 * Input:
2843 * ha = adapter block pointer.
2844 * TARGET_QUEUE_LOCK must be released.
2845 * ADAPTER_STATE_LOCK must be released.
2846 *
2847 * Returns:
2848 * qla2x00 local function return status code.
2849 *
2850 * Context:
2851 * Kernel context.
2852 */
2853 int
qla2x00_full_login_lip(scsi_qla_host_t * vha)2854 qla2x00_full_login_lip(scsi_qla_host_t *vha)
2855 {
2856 int rval;
2857 mbx_cmd_t mc;
2858 mbx_cmd_t *mcp = &mc;
2859
2860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2861 "Entered %s.\n", __func__);
2862
2863 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2864 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
2865 mcp->mb[2] = 0;
2866 mcp->mb[3] = 0;
2867 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2868 mcp->in_mb = MBX_0;
2869 mcp->tov = MBX_TOV_SECONDS;
2870 mcp->flags = 0;
2871 rval = qla2x00_mailbox_command(vha, mcp);
2872
2873 if (rval != QLA_SUCCESS) {
2874 /*EMPTY*/
2875 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2876 } else {
2877 /*EMPTY*/
2878 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2879 "Done %s.\n", __func__);
2880 }
2881
2882 return rval;
2883 }
2884
2885 /*
2886 * qla2x00_get_id_list
2887 *
2888 * Input:
2889 * ha = adapter block pointer.
2890 *
2891 * Returns:
2892 * qla2x00 local function return status code.
2893 *
2894 * Context:
2895 * Kernel context.
2896 */
2897 int
qla2x00_get_id_list(scsi_qla_host_t * vha,void * id_list,dma_addr_t id_list_dma,uint16_t * entries)2898 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2899 uint16_t *entries)
2900 {
2901 int rval;
2902 mbx_cmd_t mc;
2903 mbx_cmd_t *mcp = &mc;
2904
2905 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2906 "Entered %s.\n", __func__);
2907
2908 if (id_list == NULL)
2909 return QLA_FUNCTION_FAILED;
2910
2911 mcp->mb[0] = MBC_GET_ID_LIST;
2912 mcp->out_mb = MBX_0;
2913 if (IS_FWI2_CAPABLE(vha->hw)) {
2914 mcp->mb[2] = MSW(id_list_dma);
2915 mcp->mb[3] = LSW(id_list_dma);
2916 mcp->mb[6] = MSW(MSD(id_list_dma));
2917 mcp->mb[7] = LSW(MSD(id_list_dma));
2918 mcp->mb[8] = 0;
2919 mcp->mb[9] = vha->vp_idx;
2920 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2921 } else {
2922 mcp->mb[1] = MSW(id_list_dma);
2923 mcp->mb[2] = LSW(id_list_dma);
2924 mcp->mb[3] = MSW(MSD(id_list_dma));
2925 mcp->mb[6] = LSW(MSD(id_list_dma));
2926 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2927 }
2928 mcp->in_mb = MBX_1|MBX_0;
2929 mcp->tov = MBX_TOV_SECONDS;
2930 mcp->flags = 0;
2931 rval = qla2x00_mailbox_command(vha, mcp);
2932
2933 if (rval != QLA_SUCCESS) {
2934 /*EMPTY*/
2935 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2936 } else {
2937 *entries = mcp->mb[1];
2938 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2939 "Done %s.\n", __func__);
2940 }
2941
2942 return rval;
2943 }
2944
2945 /*
2946 * qla2x00_get_resource_cnts
2947 * Get current firmware resource counts.
2948 *
2949 * Input:
2950 * ha = adapter block pointer.
2951 *
2952 * Returns:
2953 * qla2x00 local function return status code.
2954 *
2955 * Context:
2956 * Kernel context.
2957 */
2958 int
qla2x00_get_resource_cnts(scsi_qla_host_t * vha)2959 qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
2960 {
2961 struct qla_hw_data *ha = vha->hw;
2962 int rval;
2963 mbx_cmd_t mc;
2964 mbx_cmd_t *mcp = &mc;
2965
2966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2967 "Entered %s.\n", __func__);
2968
2969 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2970 mcp->out_mb = MBX_0;
2971 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2972 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2973 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2974 mcp->in_mb |= MBX_12;
2975 mcp->tov = MBX_TOV_SECONDS;
2976 mcp->flags = 0;
2977 rval = qla2x00_mailbox_command(vha, mcp);
2978
2979 if (rval != QLA_SUCCESS) {
2980 /*EMPTY*/
2981 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2982 "Failed mb[0]=%x.\n", mcp->mb[0]);
2983 } else {
2984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
2985 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2986 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2987 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2988 mcp->mb[11], mcp->mb[12]);
2989
2990 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2991 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2992 ha->cur_fw_xcb_count = mcp->mb[3];
2993 ha->orig_fw_xcb_count = mcp->mb[6];
2994 ha->cur_fw_iocb_count = mcp->mb[7];
2995 ha->orig_fw_iocb_count = mcp->mb[10];
2996 if (ha->flags.npiv_supported)
2997 ha->max_npiv_vports = mcp->mb[11];
2998 if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2999 ha->fw_max_fcf_count = mcp->mb[12];
3000 }
3001
3002 return (rval);
3003 }
3004
3005 /*
3006 * qla2x00_get_fcal_position_map
3007 * Get FCAL (LILP) position map using mailbox command
3008 *
3009 * Input:
3010 * ha = adapter state pointer.
3011 * pos_map = buffer pointer (can be NULL).
3012 *
3013 * Returns:
3014 * qla2x00 local function return status code.
3015 *
3016 * Context:
3017 * Kernel context.
3018 */
3019 int
qla2x00_get_fcal_position_map(scsi_qla_host_t * vha,char * pos_map,u8 * num_entries)3020 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map,
3021 u8 *num_entries)
3022 {
3023 int rval;
3024 mbx_cmd_t mc;
3025 mbx_cmd_t *mcp = &mc;
3026 char *pmap;
3027 dma_addr_t pmap_dma;
3028 struct qla_hw_data *ha = vha->hw;
3029
3030 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
3031 "Entered %s.\n", __func__);
3032
3033 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
3034 if (pmap == NULL) {
3035 ql_log(ql_log_warn, vha, 0x1080,
3036 "Memory alloc failed.\n");
3037 return QLA_MEMORY_ALLOC_FAILED;
3038 }
3039
3040 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
3041 mcp->mb[2] = MSW(pmap_dma);
3042 mcp->mb[3] = LSW(pmap_dma);
3043 mcp->mb[6] = MSW(MSD(pmap_dma));
3044 mcp->mb[7] = LSW(MSD(pmap_dma));
3045 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3046 mcp->in_mb = MBX_1|MBX_0;
3047 mcp->buf_size = FCAL_MAP_SIZE;
3048 mcp->flags = MBX_DMA_IN;
3049 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
3050 rval = qla2x00_mailbox_command(vha, mcp);
3051
3052 if (rval == QLA_SUCCESS) {
3053 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
3054 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
3055 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
3056 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
3057 pmap, pmap[0] + 1);
3058
3059 if (pos_map)
3060 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
3061 if (num_entries)
3062 *num_entries = pmap[0];
3063 }
3064 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
3065
3066 if (rval != QLA_SUCCESS) {
3067 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
3068 } else {
3069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
3070 "Done %s.\n", __func__);
3071 }
3072
3073 return rval;
3074 }
3075
3076 /*
3077 * qla2x00_get_link_status
3078 *
3079 * Input:
3080 * ha = adapter block pointer.
3081 * loop_id = device loop ID.
3082 * ret_buf = pointer to link status return buffer.
3083 *
3084 * Returns:
3085 * 0 = success.
3086 * BIT_0 = mem alloc error.
3087 * BIT_1 = mailbox error.
3088 */
3089 int
qla2x00_get_link_status(scsi_qla_host_t * vha,uint16_t loop_id,struct link_statistics * stats,dma_addr_t stats_dma)3090 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
3091 struct link_statistics *stats, dma_addr_t stats_dma)
3092 {
3093 int rval;
3094 mbx_cmd_t mc;
3095 mbx_cmd_t *mcp = &mc;
3096 uint32_t *iter = (uint32_t *)stats;
3097 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
3098 struct qla_hw_data *ha = vha->hw;
3099
3100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
3101 "Entered %s.\n", __func__);
3102
3103 mcp->mb[0] = MBC_GET_LINK_STATUS;
3104 mcp->mb[2] = MSW(LSD(stats_dma));
3105 mcp->mb[3] = LSW(LSD(stats_dma));
3106 mcp->mb[6] = MSW(MSD(stats_dma));
3107 mcp->mb[7] = LSW(MSD(stats_dma));
3108 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3109 mcp->in_mb = MBX_0;
3110 if (IS_FWI2_CAPABLE(ha)) {
3111 mcp->mb[1] = loop_id;
3112 mcp->mb[4] = 0;
3113 mcp->mb[10] = 0;
3114 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
3115 mcp->in_mb |= MBX_1;
3116 } else if (HAS_EXTENDED_IDS(ha)) {
3117 mcp->mb[1] = loop_id;
3118 mcp->mb[10] = 0;
3119 mcp->out_mb |= MBX_10|MBX_1;
3120 } else {
3121 mcp->mb[1] = loop_id << 8;
3122 mcp->out_mb |= MBX_1;
3123 }
3124 mcp->tov = MBX_TOV_SECONDS;
3125 mcp->flags = IOCTL_CMD;
3126 rval = qla2x00_mailbox_command(vha, mcp);
3127
3128 if (rval == QLA_SUCCESS) {
3129 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3130 ql_dbg(ql_dbg_mbx, vha, 0x1085,
3131 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3132 rval = QLA_FUNCTION_FAILED;
3133 } else {
3134 /* Re-endianize - firmware data is le32. */
3135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
3136 "Done %s.\n", __func__);
3137 for ( ; dwords--; iter++)
3138 le32_to_cpus(iter);
3139 }
3140 } else {
3141 /* Failed. */
3142 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
3143 }
3144
3145 return rval;
3146 }
3147
3148 int
qla24xx_get_isp_stats(scsi_qla_host_t * vha,struct link_statistics * stats,dma_addr_t stats_dma,uint16_t options)3149 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
3150 dma_addr_t stats_dma, uint16_t options)
3151 {
3152 int rval;
3153 mbx_cmd_t mc;
3154 mbx_cmd_t *mcp = &mc;
3155 uint32_t *iter = (uint32_t *)stats;
3156 ushort dwords = sizeof(*stats)/sizeof(*iter);
3157
3158 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3159 "Entered %s.\n", __func__);
3160
3161 memset(&mc, 0, sizeof(mc));
3162 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
3163 mc.mb[2] = MSW(LSD(stats_dma));
3164 mc.mb[3] = LSW(LSD(stats_dma));
3165 mc.mb[6] = MSW(MSD(stats_dma));
3166 mc.mb[7] = LSW(MSD(stats_dma));
3167 mc.mb[8] = dwords;
3168 mc.mb[9] = vha->vp_idx;
3169 mc.mb[10] = options;
3170
3171 rval = qla24xx_send_mb_cmd(vha, &mc);
3172
3173 if (rval == QLA_SUCCESS) {
3174 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3175 ql_dbg(ql_dbg_mbx, vha, 0x1089,
3176 "Failed mb[0]=%x.\n", mcp->mb[0]);
3177 rval = QLA_FUNCTION_FAILED;
3178 } else {
3179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3180 "Done %s.\n", __func__);
3181 /* Re-endianize - firmware data is le32. */
3182 for ( ; dwords--; iter++)
3183 le32_to_cpus(iter);
3184 }
3185 } else {
3186 /* Failed. */
3187 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
3188 }
3189
3190 return rval;
3191 }
3192
3193 int
qla24xx_abort_command(srb_t * sp)3194 qla24xx_abort_command(srb_t *sp)
3195 {
3196 int rval;
3197 unsigned long flags = 0;
3198
3199 struct abort_entry_24xx *abt;
3200 dma_addr_t abt_dma;
3201 uint32_t handle;
3202 fc_port_t *fcport = sp->fcport;
3203 struct scsi_qla_host *vha = fcport->vha;
3204 struct qla_hw_data *ha = vha->hw;
3205 struct req_que *req = vha->req;
3206 struct qla_qpair *qpair = sp->qpair;
3207
3208 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3209 "Entered %s.\n", __func__);
3210
3211 if (sp->qpair)
3212 req = sp->qpair->req;
3213 else
3214 return QLA_FUNCTION_FAILED;
3215
3216 if (ql2xasynctmfenable)
3217 return qla24xx_async_abort_command(sp);
3218
3219 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
3220 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
3221 if (req->outstanding_cmds[handle] == sp)
3222 break;
3223 }
3224 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
3225 if (handle == req->num_outstanding_cmds) {
3226 /* Command not found. */
3227 return QLA_FUNCTION_FAILED;
3228 }
3229
3230 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
3231 if (abt == NULL) {
3232 ql_log(ql_log_warn, vha, 0x108d,
3233 "Failed to allocate abort IOCB.\n");
3234 return QLA_MEMORY_ALLOC_FAILED;
3235 }
3236
3237 abt->entry_type = ABORT_IOCB_TYPE;
3238 abt->entry_count = 1;
3239 abt->handle = make_handle(req->id, abt->handle);
3240 abt->nport_handle = cpu_to_le16(fcport->loop_id);
3241 abt->handle_to_abort = make_handle(req->id, handle);
3242 abt->port_id[0] = fcport->d_id.b.al_pa;
3243 abt->port_id[1] = fcport->d_id.b.area;
3244 abt->port_id[2] = fcport->d_id.b.domain;
3245 abt->vp_index = fcport->vha->vp_idx;
3246
3247 abt->req_que_no = cpu_to_le16(req->id);
3248
3249 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
3250 if (rval != QLA_SUCCESS) {
3251 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3252 "Failed to issue IOCB (%x).\n", rval);
3253 } else if (abt->entry_status != 0) {
3254 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3255 "Failed to complete IOCB -- error status (%x).\n",
3256 abt->entry_status);
3257 rval = QLA_FUNCTION_FAILED;
3258 } else if (abt->nport_handle != cpu_to_le16(0)) {
3259 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3260 "Failed to complete IOCB -- completion status (%x).\n",
3261 le16_to_cpu(abt->nport_handle));
3262 if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR))
3263 rval = QLA_FUNCTION_PARAMETER_ERROR;
3264 else
3265 rval = QLA_FUNCTION_FAILED;
3266 } else {
3267 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3268 "Done %s.\n", __func__);
3269 }
3270
3271 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3272
3273 return rval;
3274 }
3275
3276 struct tsk_mgmt_cmd {
3277 union {
3278 struct tsk_mgmt_entry tsk;
3279 struct sts_entry_24xx sts;
3280 } p;
3281 };
3282
3283 static int
__qla24xx_issue_tmf(char * name,uint32_t type,struct fc_port * fcport,uint64_t l,int tag)3284 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
3285 uint64_t l, int tag)
3286 {
3287 int rval, rval2;
3288 struct tsk_mgmt_cmd *tsk;
3289 struct sts_entry_24xx *sts;
3290 dma_addr_t tsk_dma;
3291 scsi_qla_host_t *vha;
3292 struct qla_hw_data *ha;
3293 struct req_que *req;
3294 struct qla_qpair *qpair;
3295
3296 vha = fcport->vha;
3297 ha = vha->hw;
3298 req = vha->req;
3299
3300 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3301 "Entered %s.\n", __func__);
3302
3303 if (vha->vp_idx && vha->qpair) {
3304 /* NPIV port */
3305 qpair = vha->qpair;
3306 req = qpair->req;
3307 }
3308
3309 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
3310 if (tsk == NULL) {
3311 ql_log(ql_log_warn, vha, 0x1093,
3312 "Failed to allocate task management IOCB.\n");
3313 return QLA_MEMORY_ALLOC_FAILED;
3314 }
3315
3316 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3317 tsk->p.tsk.entry_count = 1;
3318 tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle);
3319 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
3320 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
3321 tsk->p.tsk.control_flags = cpu_to_le32(type);
3322 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3323 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3324 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
3325 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
3326 if (type == TCF_LUN_RESET) {
3327 int_to_scsilun(l, &tsk->p.tsk.lun);
3328 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3329 sizeof(tsk->p.tsk.lun));
3330 }
3331
3332 sts = &tsk->p.sts;
3333 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
3334 if (rval != QLA_SUCCESS) {
3335 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3336 "Failed to issue %s reset IOCB (%x).\n", name, rval);
3337 } else if (sts->entry_status != 0) {
3338 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3339 "Failed to complete IOCB -- error status (%x).\n",
3340 sts->entry_status);
3341 rval = QLA_FUNCTION_FAILED;
3342 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
3343 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3344 "Failed to complete IOCB -- completion status (%x).\n",
3345 le16_to_cpu(sts->comp_status));
3346 rval = QLA_FUNCTION_FAILED;
3347 } else if (le16_to_cpu(sts->scsi_status) &
3348 SS_RESPONSE_INFO_LEN_VALID) {
3349 if (le32_to_cpu(sts->rsp_data_len) < 4) {
3350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
3351 "Ignoring inconsistent data length -- not enough "
3352 "response info (%d).\n",
3353 le32_to_cpu(sts->rsp_data_len));
3354 } else if (sts->data[3]) {
3355 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3356 "Failed to complete IOCB -- response (%x).\n",
3357 sts->data[3]);
3358 rval = QLA_FUNCTION_FAILED;
3359 }
3360 }
3361
3362 /* Issue marker IOCB. */
3363 rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
3364 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
3365 if (rval2 != QLA_SUCCESS) {
3366 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3367 "Failed to issue marker IOCB (%x).\n", rval2);
3368 } else {
3369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3370 "Done %s.\n", __func__);
3371 }
3372
3373 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
3374
3375 return rval;
3376 }
3377
3378 int
qla24xx_abort_target(struct fc_port * fcport,uint64_t l,int tag)3379 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
3380 {
3381 struct qla_hw_data *ha = fcport->vha->hw;
3382
3383 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3384 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3385
3386 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
3387 }
3388
3389 int
qla24xx_lun_reset(struct fc_port * fcport,uint64_t l,int tag)3390 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
3391 {
3392 struct qla_hw_data *ha = fcport->vha->hw;
3393
3394 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3395 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3396
3397 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
3398 }
3399
3400 int
qla2x00_system_error(scsi_qla_host_t * vha)3401 qla2x00_system_error(scsi_qla_host_t *vha)
3402 {
3403 int rval;
3404 mbx_cmd_t mc;
3405 mbx_cmd_t *mcp = &mc;
3406 struct qla_hw_data *ha = vha->hw;
3407
3408 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
3409 return QLA_FUNCTION_FAILED;
3410
3411 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3412 "Entered %s.\n", __func__);
3413
3414 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3415 mcp->out_mb = MBX_0;
3416 mcp->in_mb = MBX_0;
3417 mcp->tov = 5;
3418 mcp->flags = 0;
3419 rval = qla2x00_mailbox_command(vha, mcp);
3420
3421 if (rval != QLA_SUCCESS) {
3422 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
3423 } else {
3424 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3425 "Done %s.\n", __func__);
3426 }
3427
3428 return rval;
3429 }
3430
3431 int
qla2x00_write_serdes_word(scsi_qla_host_t * vha,uint16_t addr,uint16_t data)3432 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3433 {
3434 int rval;
3435 mbx_cmd_t mc;
3436 mbx_cmd_t *mcp = &mc;
3437
3438 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3439 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3440 return QLA_FUNCTION_FAILED;
3441
3442 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3443 "Entered %s.\n", __func__);
3444
3445 mcp->mb[0] = MBC_WRITE_SERDES;
3446 mcp->mb[1] = addr;
3447 if (IS_QLA2031(vha->hw))
3448 mcp->mb[2] = data & 0xff;
3449 else
3450 mcp->mb[2] = data;
3451
3452 mcp->mb[3] = 0;
3453 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3454 mcp->in_mb = MBX_0;
3455 mcp->tov = MBX_TOV_SECONDS;
3456 mcp->flags = 0;
3457 rval = qla2x00_mailbox_command(vha, mcp);
3458
3459 if (rval != QLA_SUCCESS) {
3460 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3461 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3462 } else {
3463 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3464 "Done %s.\n", __func__);
3465 }
3466
3467 return rval;
3468 }
3469
3470 int
qla2x00_read_serdes_word(scsi_qla_host_t * vha,uint16_t addr,uint16_t * data)3471 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3472 {
3473 int rval;
3474 mbx_cmd_t mc;
3475 mbx_cmd_t *mcp = &mc;
3476
3477 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3478 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3479 return QLA_FUNCTION_FAILED;
3480
3481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3482 "Entered %s.\n", __func__);
3483
3484 mcp->mb[0] = MBC_READ_SERDES;
3485 mcp->mb[1] = addr;
3486 mcp->mb[3] = 0;
3487 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3488 mcp->in_mb = MBX_1|MBX_0;
3489 mcp->tov = MBX_TOV_SECONDS;
3490 mcp->flags = 0;
3491 rval = qla2x00_mailbox_command(vha, mcp);
3492
3493 if (IS_QLA2031(vha->hw))
3494 *data = mcp->mb[1] & 0xff;
3495 else
3496 *data = mcp->mb[1];
3497
3498 if (rval != QLA_SUCCESS) {
3499 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3500 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3501 } else {
3502 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3503 "Done %s.\n", __func__);
3504 }
3505
3506 return rval;
3507 }
3508
3509 int
qla8044_write_serdes_word(scsi_qla_host_t * vha,uint32_t addr,uint32_t data)3510 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3511 {
3512 int rval;
3513 mbx_cmd_t mc;
3514 mbx_cmd_t *mcp = &mc;
3515
3516 if (!IS_QLA8044(vha->hw))
3517 return QLA_FUNCTION_FAILED;
3518
3519 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
3520 "Entered %s.\n", __func__);
3521
3522 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3523 mcp->mb[1] = HCS_WRITE_SERDES;
3524 mcp->mb[3] = LSW(addr);
3525 mcp->mb[4] = MSW(addr);
3526 mcp->mb[5] = LSW(data);
3527 mcp->mb[6] = MSW(data);
3528 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3529 mcp->in_mb = MBX_0;
3530 mcp->tov = MBX_TOV_SECONDS;
3531 mcp->flags = 0;
3532 rval = qla2x00_mailbox_command(vha, mcp);
3533
3534 if (rval != QLA_SUCCESS) {
3535 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
3536 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3537 } else {
3538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3539 "Done %s.\n", __func__);
3540 }
3541
3542 return rval;
3543 }
3544
3545 int
qla8044_read_serdes_word(scsi_qla_host_t * vha,uint32_t addr,uint32_t * data)3546 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3547 {
3548 int rval;
3549 mbx_cmd_t mc;
3550 mbx_cmd_t *mcp = &mc;
3551
3552 if (!IS_QLA8044(vha->hw))
3553 return QLA_FUNCTION_FAILED;
3554
3555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3556 "Entered %s.\n", __func__);
3557
3558 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3559 mcp->mb[1] = HCS_READ_SERDES;
3560 mcp->mb[3] = LSW(addr);
3561 mcp->mb[4] = MSW(addr);
3562 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3563 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3564 mcp->tov = MBX_TOV_SECONDS;
3565 mcp->flags = 0;
3566 rval = qla2x00_mailbox_command(vha, mcp);
3567
3568 *data = mcp->mb[2] << 16 | mcp->mb[1];
3569
3570 if (rval != QLA_SUCCESS) {
3571 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3572 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3573 } else {
3574 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3575 "Done %s.\n", __func__);
3576 }
3577
3578 return rval;
3579 }
3580
3581 /**
3582 * qla2x00_set_serdes_params() -
3583 * @vha: HA context
3584 * @sw_em_1g: serial link options
3585 * @sw_em_2g: serial link options
3586 * @sw_em_4g: serial link options
3587 *
3588 * Returns
3589 */
3590 int
qla2x00_set_serdes_params(scsi_qla_host_t * vha,uint16_t sw_em_1g,uint16_t sw_em_2g,uint16_t sw_em_4g)3591 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
3592 uint16_t sw_em_2g, uint16_t sw_em_4g)
3593 {
3594 int rval;
3595 mbx_cmd_t mc;
3596 mbx_cmd_t *mcp = &mc;
3597
3598 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3599 "Entered %s.\n", __func__);
3600
3601 mcp->mb[0] = MBC_SERDES_PARAMS;
3602 mcp->mb[1] = BIT_0;
3603 mcp->mb[2] = sw_em_1g | BIT_15;
3604 mcp->mb[3] = sw_em_2g | BIT_15;
3605 mcp->mb[4] = sw_em_4g | BIT_15;
3606 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3607 mcp->in_mb = MBX_0;
3608 mcp->tov = MBX_TOV_SECONDS;
3609 mcp->flags = 0;
3610 rval = qla2x00_mailbox_command(vha, mcp);
3611
3612 if (rval != QLA_SUCCESS) {
3613 /*EMPTY*/
3614 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3615 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3616 } else {
3617 /*EMPTY*/
3618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3619 "Done %s.\n", __func__);
3620 }
3621
3622 return rval;
3623 }
3624
3625 int
qla2x00_stop_firmware(scsi_qla_host_t * vha)3626 qla2x00_stop_firmware(scsi_qla_host_t *vha)
3627 {
3628 int rval;
3629 mbx_cmd_t mc;
3630 mbx_cmd_t *mcp = &mc;
3631
3632 if (!IS_FWI2_CAPABLE(vha->hw))
3633 return QLA_FUNCTION_FAILED;
3634
3635 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3636 "Entered %s.\n", __func__);
3637
3638 mcp->mb[0] = MBC_STOP_FIRMWARE;
3639 mcp->mb[1] = 0;
3640 mcp->out_mb = MBX_1|MBX_0;
3641 mcp->in_mb = MBX_0;
3642 mcp->tov = 5;
3643 mcp->flags = 0;
3644 rval = qla2x00_mailbox_command(vha, mcp);
3645
3646 if (rval != QLA_SUCCESS) {
3647 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
3648 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3649 rval = QLA_INVALID_COMMAND;
3650 } else {
3651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3652 "Done %s.\n", __func__);
3653 }
3654
3655 return rval;
3656 }
3657
3658 int
qla2x00_enable_eft_trace(scsi_qla_host_t * vha,dma_addr_t eft_dma,uint16_t buffers)3659 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
3660 uint16_t buffers)
3661 {
3662 int rval;
3663 mbx_cmd_t mc;
3664 mbx_cmd_t *mcp = &mc;
3665
3666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3667 "Entered %s.\n", __func__);
3668
3669 if (!IS_FWI2_CAPABLE(vha->hw))
3670 return QLA_FUNCTION_FAILED;
3671
3672 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3673 return QLA_FUNCTION_FAILED;
3674
3675 mcp->mb[0] = MBC_TRACE_CONTROL;
3676 mcp->mb[1] = TC_EFT_ENABLE;
3677 mcp->mb[2] = LSW(eft_dma);
3678 mcp->mb[3] = MSW(eft_dma);
3679 mcp->mb[4] = LSW(MSD(eft_dma));
3680 mcp->mb[5] = MSW(MSD(eft_dma));
3681 mcp->mb[6] = buffers;
3682 mcp->mb[7] = TC_AEN_DISABLE;
3683 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3684 mcp->in_mb = MBX_1|MBX_0;
3685 mcp->tov = MBX_TOV_SECONDS;
3686 mcp->flags = 0;
3687 rval = qla2x00_mailbox_command(vha, mcp);
3688 if (rval != QLA_SUCCESS) {
3689 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3690 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3691 rval, mcp->mb[0], mcp->mb[1]);
3692 } else {
3693 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3694 "Done %s.\n", __func__);
3695 }
3696
3697 return rval;
3698 }
3699
3700 int
qla2x00_disable_eft_trace(scsi_qla_host_t * vha)3701 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
3702 {
3703 int rval;
3704 mbx_cmd_t mc;
3705 mbx_cmd_t *mcp = &mc;
3706
3707 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3708 "Entered %s.\n", __func__);
3709
3710 if (!IS_FWI2_CAPABLE(vha->hw))
3711 return QLA_FUNCTION_FAILED;
3712
3713 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3714 return QLA_FUNCTION_FAILED;
3715
3716 mcp->mb[0] = MBC_TRACE_CONTROL;
3717 mcp->mb[1] = TC_EFT_DISABLE;
3718 mcp->out_mb = MBX_1|MBX_0;
3719 mcp->in_mb = MBX_1|MBX_0;
3720 mcp->tov = MBX_TOV_SECONDS;
3721 mcp->flags = 0;
3722 rval = qla2x00_mailbox_command(vha, mcp);
3723 if (rval != QLA_SUCCESS) {
3724 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3725 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3726 rval, mcp->mb[0], mcp->mb[1]);
3727 } else {
3728 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3729 "Done %s.\n", __func__);
3730 }
3731
3732 return rval;
3733 }
3734
3735 int
qla2x00_enable_fce_trace(scsi_qla_host_t * vha,dma_addr_t fce_dma,uint16_t buffers,uint16_t * mb,uint32_t * dwords)3736 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
3737 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3738 {
3739 int rval;
3740 mbx_cmd_t mc;
3741 mbx_cmd_t *mcp = &mc;
3742
3743 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3744 "Entered %s.\n", __func__);
3745
3746 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3747 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
3748 !IS_QLA28XX(vha->hw))
3749 return QLA_FUNCTION_FAILED;
3750
3751 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3752 return QLA_FUNCTION_FAILED;
3753
3754 mcp->mb[0] = MBC_TRACE_CONTROL;
3755 mcp->mb[1] = TC_FCE_ENABLE;
3756 mcp->mb[2] = LSW(fce_dma);
3757 mcp->mb[3] = MSW(fce_dma);
3758 mcp->mb[4] = LSW(MSD(fce_dma));
3759 mcp->mb[5] = MSW(MSD(fce_dma));
3760 mcp->mb[6] = buffers;
3761 mcp->mb[7] = TC_AEN_DISABLE;
3762 mcp->mb[8] = 0;
3763 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3764 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3765 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3766 MBX_1|MBX_0;
3767 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3768 mcp->tov = MBX_TOV_SECONDS;
3769 mcp->flags = 0;
3770 rval = qla2x00_mailbox_command(vha, mcp);
3771 if (rval != QLA_SUCCESS) {
3772 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3773 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3774 rval, mcp->mb[0], mcp->mb[1]);
3775 } else {
3776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3777 "Done %s.\n", __func__);
3778
3779 if (mb)
3780 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3781 if (dwords)
3782 *dwords = buffers;
3783 }
3784
3785 return rval;
3786 }
3787
3788 int
qla2x00_disable_fce_trace(scsi_qla_host_t * vha,uint64_t * wr,uint64_t * rd)3789 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
3790 {
3791 int rval;
3792 mbx_cmd_t mc;
3793 mbx_cmd_t *mcp = &mc;
3794
3795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3796 "Entered %s.\n", __func__);
3797
3798 if (!IS_FWI2_CAPABLE(vha->hw))
3799 return QLA_FUNCTION_FAILED;
3800
3801 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3802 return QLA_FUNCTION_FAILED;
3803
3804 mcp->mb[0] = MBC_TRACE_CONTROL;
3805 mcp->mb[1] = TC_FCE_DISABLE;
3806 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3807 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3808 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3809 MBX_1|MBX_0;
3810 mcp->tov = MBX_TOV_SECONDS;
3811 mcp->flags = 0;
3812 rval = qla2x00_mailbox_command(vha, mcp);
3813 if (rval != QLA_SUCCESS) {
3814 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3815 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3816 rval, mcp->mb[0], mcp->mb[1]);
3817 } else {
3818 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3819 "Done %s.\n", __func__);
3820
3821 if (wr)
3822 *wr = (uint64_t) mcp->mb[5] << 48 |
3823 (uint64_t) mcp->mb[4] << 32 |
3824 (uint64_t) mcp->mb[3] << 16 |
3825 (uint64_t) mcp->mb[2];
3826 if (rd)
3827 *rd = (uint64_t) mcp->mb[9] << 48 |
3828 (uint64_t) mcp->mb[8] << 32 |
3829 (uint64_t) mcp->mb[7] << 16 |
3830 (uint64_t) mcp->mb[6];
3831 }
3832
3833 return rval;
3834 }
3835
3836 int
qla2x00_get_idma_speed(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t * port_speed,uint16_t * mb)3837 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3838 uint16_t *port_speed, uint16_t *mb)
3839 {
3840 int rval;
3841 mbx_cmd_t mc;
3842 mbx_cmd_t *mcp = &mc;
3843
3844 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3845 "Entered %s.\n", __func__);
3846
3847 if (!IS_IIDMA_CAPABLE(vha->hw))
3848 return QLA_FUNCTION_FAILED;
3849
3850 mcp->mb[0] = MBC_PORT_PARAMS;
3851 mcp->mb[1] = loop_id;
3852 mcp->mb[2] = mcp->mb[3] = 0;
3853 mcp->mb[9] = vha->vp_idx;
3854 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3855 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3856 mcp->tov = MBX_TOV_SECONDS;
3857 mcp->flags = 0;
3858 rval = qla2x00_mailbox_command(vha, mcp);
3859
3860 /* Return mailbox statuses. */
3861 if (mb) {
3862 mb[0] = mcp->mb[0];
3863 mb[1] = mcp->mb[1];
3864 mb[3] = mcp->mb[3];
3865 }
3866
3867 if (rval != QLA_SUCCESS) {
3868 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
3869 } else {
3870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3871 "Done %s.\n", __func__);
3872 if (port_speed)
3873 *port_speed = mcp->mb[3];
3874 }
3875
3876 return rval;
3877 }
3878
3879 int
qla2x00_set_idma_speed(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t port_speed,uint16_t * mb)3880 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3881 uint16_t port_speed, uint16_t *mb)
3882 {
3883 int rval;
3884 mbx_cmd_t mc;
3885 mbx_cmd_t *mcp = &mc;
3886
3887 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3888 "Entered %s.\n", __func__);
3889
3890 if (!IS_IIDMA_CAPABLE(vha->hw))
3891 return QLA_FUNCTION_FAILED;
3892
3893 mcp->mb[0] = MBC_PORT_PARAMS;
3894 mcp->mb[1] = loop_id;
3895 mcp->mb[2] = BIT_0;
3896 mcp->mb[3] = port_speed & 0x3F;
3897 mcp->mb[9] = vha->vp_idx;
3898 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3899 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3900 mcp->tov = MBX_TOV_SECONDS;
3901 mcp->flags = 0;
3902 rval = qla2x00_mailbox_command(vha, mcp);
3903
3904 /* Return mailbox statuses. */
3905 if (mb) {
3906 mb[0] = mcp->mb[0];
3907 mb[1] = mcp->mb[1];
3908 mb[3] = mcp->mb[3];
3909 }
3910
3911 if (rval != QLA_SUCCESS) {
3912 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3913 "Failed=%x.\n", rval);
3914 } else {
3915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3916 "Done %s.\n", __func__);
3917 }
3918
3919 return rval;
3920 }
3921
3922 void
qla24xx_report_id_acquisition(scsi_qla_host_t * vha,struct vp_rpt_id_entry_24xx * rptid_entry)3923 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
3924 struct vp_rpt_id_entry_24xx *rptid_entry)
3925 {
3926 struct qla_hw_data *ha = vha->hw;
3927 scsi_qla_host_t *vp = NULL;
3928 unsigned long flags;
3929 int found;
3930 port_id_t id;
3931 struct fc_port *fcport;
3932
3933 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3934 "Entered %s.\n", __func__);
3935
3936 if (rptid_entry->entry_status != 0)
3937 return;
3938
3939 id.b.domain = rptid_entry->port_id[2];
3940 id.b.area = rptid_entry->port_id[1];
3941 id.b.al_pa = rptid_entry->port_id[0];
3942 id.b.rsvd_1 = 0;
3943 ha->flags.n2n_ae = 0;
3944
3945 if (rptid_entry->format == 0) {
3946 /* loop */
3947 ql_dbg(ql_dbg_async, vha, 0x10b7,
3948 "Format 0 : Number of VPs setup %d, number of "
3949 "VPs acquired %d.\n", rptid_entry->vp_setup,
3950 rptid_entry->vp_acquired);
3951 ql_dbg(ql_dbg_async, vha, 0x10b8,
3952 "Primary port id %02x%02x%02x.\n",
3953 rptid_entry->port_id[2], rptid_entry->port_id[1],
3954 rptid_entry->port_id[0]);
3955 ha->current_topology = ISP_CFG_NL;
3956 qlt_update_host_map(vha, id);
3957
3958 } else if (rptid_entry->format == 1) {
3959 /* fabric */
3960 ql_dbg(ql_dbg_async, vha, 0x10b9,
3961 "Format 1: VP[%d] enabled - status %d - with "
3962 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3963 rptid_entry->vp_status,
3964 rptid_entry->port_id[2], rptid_entry->port_id[1],
3965 rptid_entry->port_id[0]);
3966 ql_dbg(ql_dbg_async, vha, 0x5075,
3967 "Format 1: Remote WWPN %8phC.\n",
3968 rptid_entry->u.f1.port_name);
3969
3970 ql_dbg(ql_dbg_async, vha, 0x5075,
3971 "Format 1: WWPN %8phC.\n",
3972 vha->port_name);
3973
3974 switch (rptid_entry->u.f1.flags & TOPO_MASK) {
3975 case TOPO_N2N:
3976 ha->current_topology = ISP_CFG_N;
3977 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
3978 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3979 fcport->scan_state = QLA_FCPORT_SCAN;
3980 fcport->n2n_flag = 0;
3981 }
3982 id.b24 = 0;
3983 if (wwn_to_u64(vha->port_name) >
3984 wwn_to_u64(rptid_entry->u.f1.port_name)) {
3985 vha->d_id.b24 = 0;
3986 vha->d_id.b.al_pa = 1;
3987 ha->flags.n2n_bigger = 1;
3988
3989 id.b.al_pa = 2;
3990 ql_dbg(ql_dbg_async, vha, 0x5075,
3991 "Format 1: assign local id %x remote id %x\n",
3992 vha->d_id.b24, id.b24);
3993 } else {
3994 ql_dbg(ql_dbg_async, vha, 0x5075,
3995 "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3996 rptid_entry->u.f1.port_name);
3997 ha->flags.n2n_bigger = 0;
3998 }
3999
4000 fcport = qla2x00_find_fcport_by_wwpn(vha,
4001 rptid_entry->u.f1.port_name, 1);
4002 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4003
4004
4005 if (fcport) {
4006 fcport->plogi_nack_done_deadline = jiffies + HZ;
4007 fcport->dm_login_expire = jiffies +
4008 QLA_N2N_WAIT_TIME * HZ;
4009 fcport->scan_state = QLA_FCPORT_FOUND;
4010 fcport->n2n_flag = 1;
4011 fcport->keep_nport_handle = 1;
4012
4013 if (wwn_to_u64(vha->port_name) >
4014 wwn_to_u64(fcport->port_name)) {
4015 fcport->d_id = id;
4016 }
4017
4018 switch (fcport->disc_state) {
4019 case DSC_DELETED:
4020 set_bit(RELOGIN_NEEDED,
4021 &vha->dpc_flags);
4022 break;
4023 case DSC_DELETE_PEND:
4024 break;
4025 default:
4026 qlt_schedule_sess_for_deletion(fcport);
4027 break;
4028 }
4029 } else {
4030 qla24xx_post_newsess_work(vha, &id,
4031 rptid_entry->u.f1.port_name,
4032 rptid_entry->u.f1.node_name,
4033 NULL,
4034 FS_FCP_IS_N2N);
4035 }
4036
4037 /* if our portname is higher then initiate N2N login */
4038
4039 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
4040 return;
4041 break;
4042 case TOPO_FL:
4043 ha->current_topology = ISP_CFG_FL;
4044 break;
4045 case TOPO_F:
4046 ha->current_topology = ISP_CFG_F;
4047 break;
4048 default:
4049 break;
4050 }
4051
4052 ha->flags.gpsc_supported = 1;
4053 ha->current_topology = ISP_CFG_F;
4054 /* buffer to buffer credit flag */
4055 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
4056
4057 if (rptid_entry->vp_idx == 0) {
4058 if (rptid_entry->vp_status == VP_STAT_COMPL) {
4059 /* FA-WWN is only for physical port */
4060 if (qla_ini_mode_enabled(vha) &&
4061 ha->flags.fawwpn_enabled &&
4062 (rptid_entry->u.f1.flags &
4063 BIT_6)) {
4064 memcpy(vha->port_name,
4065 rptid_entry->u.f1.port_name,
4066 WWN_SIZE);
4067 }
4068
4069 qlt_update_host_map(vha, id);
4070 }
4071
4072 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
4073 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
4074 } else {
4075 if (rptid_entry->vp_status != VP_STAT_COMPL &&
4076 rptid_entry->vp_status != VP_STAT_ID_CHG) {
4077 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
4078 "Could not acquire ID for VP[%d].\n",
4079 rptid_entry->vp_idx);
4080 return;
4081 }
4082
4083 found = 0;
4084 spin_lock_irqsave(&ha->vport_slock, flags);
4085 list_for_each_entry(vp, &ha->vp_list, list) {
4086 if (rptid_entry->vp_idx == vp->vp_idx) {
4087 found = 1;
4088 break;
4089 }
4090 }
4091 spin_unlock_irqrestore(&ha->vport_slock, flags);
4092
4093 if (!found)
4094 return;
4095
4096 qlt_update_host_map(vp, id);
4097
4098 /*
4099 * Cannot configure here as we are still sitting on the
4100 * response queue. Handle it in dpc context.
4101 */
4102 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
4103 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
4104 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
4105 }
4106 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
4107 qla2xxx_wake_dpc(vha);
4108 } else if (rptid_entry->format == 2) {
4109 ql_dbg(ql_dbg_async, vha, 0x505f,
4110 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
4111 rptid_entry->port_id[2], rptid_entry->port_id[1],
4112 rptid_entry->port_id[0]);
4113
4114 ql_dbg(ql_dbg_async, vha, 0x5075,
4115 "N2N: Remote WWPN %8phC.\n",
4116 rptid_entry->u.f2.port_name);
4117
4118 /* N2N. direct connect */
4119 ha->current_topology = ISP_CFG_N;
4120 ha->flags.rida_fmt2 = 1;
4121 vha->d_id.b.domain = rptid_entry->port_id[2];
4122 vha->d_id.b.area = rptid_entry->port_id[1];
4123 vha->d_id.b.al_pa = rptid_entry->port_id[0];
4124
4125 ha->flags.n2n_ae = 1;
4126 spin_lock_irqsave(&ha->vport_slock, flags);
4127 qlt_update_vp_map(vha, SET_AL_PA);
4128 spin_unlock_irqrestore(&ha->vport_slock, flags);
4129
4130 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4131 fcport->scan_state = QLA_FCPORT_SCAN;
4132 fcport->n2n_flag = 0;
4133 }
4134
4135 fcport = qla2x00_find_fcport_by_wwpn(vha,
4136 rptid_entry->u.f2.port_name, 1);
4137
4138 if (fcport) {
4139 fcport->login_retry = vha->hw->login_retry_count;
4140 fcport->plogi_nack_done_deadline = jiffies + HZ;
4141 fcport->scan_state = QLA_FCPORT_FOUND;
4142 fcport->keep_nport_handle = 1;
4143 fcport->n2n_flag = 1;
4144 fcport->d_id.b.domain =
4145 rptid_entry->u.f2.remote_nport_id[2];
4146 fcport->d_id.b.area =
4147 rptid_entry->u.f2.remote_nport_id[1];
4148 fcport->d_id.b.al_pa =
4149 rptid_entry->u.f2.remote_nport_id[0];
4150 }
4151 }
4152 }
4153
4154 /*
4155 * qla24xx_modify_vp_config
4156 * Change VP configuration for vha
4157 *
4158 * Input:
4159 * vha = adapter block pointer.
4160 *
4161 * Returns:
4162 * qla2xxx local function return status code.
4163 *
4164 * Context:
4165 * Kernel context.
4166 */
4167 int
qla24xx_modify_vp_config(scsi_qla_host_t * vha)4168 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
4169 {
4170 int rval;
4171 struct vp_config_entry_24xx *vpmod;
4172 dma_addr_t vpmod_dma;
4173 struct qla_hw_data *ha = vha->hw;
4174 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4175
4176 /* This can be called by the parent */
4177
4178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
4179 "Entered %s.\n", __func__);
4180
4181 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
4182 if (!vpmod) {
4183 ql_log(ql_log_warn, vha, 0x10bc,
4184 "Failed to allocate modify VP IOCB.\n");
4185 return QLA_MEMORY_ALLOC_FAILED;
4186 }
4187
4188 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
4189 vpmod->entry_count = 1;
4190 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
4191 vpmod->vp_count = 1;
4192 vpmod->vp_index1 = vha->vp_idx;
4193 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
4194
4195 qlt_modify_vp_config(vha, vpmod);
4196
4197 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
4198 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
4199 vpmod->entry_count = 1;
4200
4201 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
4202 if (rval != QLA_SUCCESS) {
4203 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
4204 "Failed to issue VP config IOCB (%x).\n", rval);
4205 } else if (vpmod->comp_status != 0) {
4206 ql_dbg(ql_dbg_mbx, vha, 0x10be,
4207 "Failed to complete IOCB -- error status (%x).\n",
4208 vpmod->comp_status);
4209 rval = QLA_FUNCTION_FAILED;
4210 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
4211 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
4212 "Failed to complete IOCB -- completion status (%x).\n",
4213 le16_to_cpu(vpmod->comp_status));
4214 rval = QLA_FUNCTION_FAILED;
4215 } else {
4216 /* EMPTY */
4217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
4218 "Done %s.\n", __func__);
4219 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
4220 }
4221 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
4222
4223 return rval;
4224 }
4225
4226 /*
4227 * qla2x00_send_change_request
4228 * Receive or disable RSCN request from fabric controller
4229 *
4230 * Input:
4231 * ha = adapter block pointer
4232 * format = registration format:
4233 * 0 - Reserved
4234 * 1 - Fabric detected registration
4235 * 2 - N_port detected registration
4236 * 3 - Full registration
4237 * FF - clear registration
4238 * vp_idx = Virtual port index
4239 *
4240 * Returns:
4241 * qla2x00 local function return status code.
4242 *
4243 * Context:
4244 * Kernel Context
4245 */
4246
4247 int
qla2x00_send_change_request(scsi_qla_host_t * vha,uint16_t format,uint16_t vp_idx)4248 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
4249 uint16_t vp_idx)
4250 {
4251 int rval;
4252 mbx_cmd_t mc;
4253 mbx_cmd_t *mcp = &mc;
4254
4255 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
4256 "Entered %s.\n", __func__);
4257
4258 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
4259 mcp->mb[1] = format;
4260 mcp->mb[9] = vp_idx;
4261 mcp->out_mb = MBX_9|MBX_1|MBX_0;
4262 mcp->in_mb = MBX_0|MBX_1;
4263 mcp->tov = MBX_TOV_SECONDS;
4264 mcp->flags = 0;
4265 rval = qla2x00_mailbox_command(vha, mcp);
4266
4267 if (rval == QLA_SUCCESS) {
4268 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
4269 rval = BIT_1;
4270 }
4271 } else
4272 rval = BIT_1;
4273
4274 return rval;
4275 }
4276
4277 int
qla2x00_dump_ram(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t addr,uint32_t size)4278 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
4279 uint32_t size)
4280 {
4281 int rval;
4282 mbx_cmd_t mc;
4283 mbx_cmd_t *mcp = &mc;
4284
4285 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
4286 "Entered %s.\n", __func__);
4287
4288 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
4289 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4290 mcp->mb[8] = MSW(addr);
4291 mcp->mb[10] = 0;
4292 mcp->out_mb = MBX_10|MBX_8|MBX_0;
4293 } else {
4294 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4295 mcp->out_mb = MBX_0;
4296 }
4297 mcp->mb[1] = LSW(addr);
4298 mcp->mb[2] = MSW(req_dma);
4299 mcp->mb[3] = LSW(req_dma);
4300 mcp->mb[6] = MSW(MSD(req_dma));
4301 mcp->mb[7] = LSW(MSD(req_dma));
4302 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
4303 if (IS_FWI2_CAPABLE(vha->hw)) {
4304 mcp->mb[4] = MSW(size);
4305 mcp->mb[5] = LSW(size);
4306 mcp->out_mb |= MBX_5|MBX_4;
4307 } else {
4308 mcp->mb[4] = LSW(size);
4309 mcp->out_mb |= MBX_4;
4310 }
4311
4312 mcp->in_mb = MBX_0;
4313 mcp->tov = MBX_TOV_SECONDS;
4314 mcp->flags = 0;
4315 rval = qla2x00_mailbox_command(vha, mcp);
4316
4317 if (rval != QLA_SUCCESS) {
4318 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4319 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4320 } else {
4321 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4322 "Done %s.\n", __func__);
4323 }
4324
4325 return rval;
4326 }
4327 /* 84XX Support **************************************************************/
4328
4329 struct cs84xx_mgmt_cmd {
4330 union {
4331 struct verify_chip_entry_84xx req;
4332 struct verify_chip_rsp_84xx rsp;
4333 } p;
4334 };
4335
4336 int
qla84xx_verify_chip(struct scsi_qla_host * vha,uint16_t * status)4337 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4338 {
4339 int rval, retry;
4340 struct cs84xx_mgmt_cmd *mn;
4341 dma_addr_t mn_dma;
4342 uint16_t options;
4343 unsigned long flags;
4344 struct qla_hw_data *ha = vha->hw;
4345
4346 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4347 "Entered %s.\n", __func__);
4348
4349 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4350 if (mn == NULL) {
4351 return QLA_MEMORY_ALLOC_FAILED;
4352 }
4353
4354 /* Force Update? */
4355 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4356 /* Diagnostic firmware? */
4357 /* options |= MENLO_DIAG_FW; */
4358 /* We update the firmware with only one data sequence. */
4359 options |= VCO_END_OF_DATA;
4360
4361 do {
4362 retry = 0;
4363 memset(mn, 0, sizeof(*mn));
4364 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4365 mn->p.req.entry_count = 1;
4366 mn->p.req.options = cpu_to_le16(options);
4367
4368 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4369 "Dump of Verify Request.\n");
4370 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4371 mn, sizeof(*mn));
4372
4373 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4374 if (rval != QLA_SUCCESS) {
4375 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4376 "Failed to issue verify IOCB (%x).\n", rval);
4377 goto verify_done;
4378 }
4379
4380 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4381 "Dump of Verify Response.\n");
4382 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4383 mn, sizeof(*mn));
4384
4385 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4386 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4387 le16_to_cpu(mn->p.rsp.failure_code) : 0;
4388 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
4389 "cs=%x fc=%x.\n", status[0], status[1]);
4390
4391 if (status[0] != CS_COMPLETE) {
4392 rval = QLA_FUNCTION_FAILED;
4393 if (!(options & VCO_DONT_UPDATE_FW)) {
4394 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4395 "Firmware update failed. Retrying "
4396 "without update firmware.\n");
4397 options |= VCO_DONT_UPDATE_FW;
4398 options &= ~VCO_FORCE_UPDATE;
4399 retry = 1;
4400 }
4401 } else {
4402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
4403 "Firmware updated to %x.\n",
4404 le32_to_cpu(mn->p.rsp.fw_ver));
4405
4406 /* NOTE: we only update OP firmware. */
4407 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4408 ha->cs84xx->op_fw_version =
4409 le32_to_cpu(mn->p.rsp.fw_ver);
4410 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4411 flags);
4412 }
4413 } while (retry);
4414
4415 verify_done:
4416 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4417
4418 if (rval != QLA_SUCCESS) {
4419 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4420 "Failed=%x.\n", rval);
4421 } else {
4422 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4423 "Done %s.\n", __func__);
4424 }
4425
4426 return rval;
4427 }
4428
4429 int
qla25xx_init_req_que(struct scsi_qla_host * vha,struct req_que * req)4430 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
4431 {
4432 int rval;
4433 unsigned long flags;
4434 mbx_cmd_t mc;
4435 mbx_cmd_t *mcp = &mc;
4436 struct qla_hw_data *ha = vha->hw;
4437
4438 if (!ha->flags.fw_started)
4439 return QLA_SUCCESS;
4440
4441 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4442 "Entered %s.\n", __func__);
4443
4444 if (IS_SHADOW_REG_CAPABLE(ha))
4445 req->options |= BIT_13;
4446
4447 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
4448 mcp->mb[1] = req->options;
4449 mcp->mb[2] = MSW(LSD(req->dma));
4450 mcp->mb[3] = LSW(LSD(req->dma));
4451 mcp->mb[6] = MSW(MSD(req->dma));
4452 mcp->mb[7] = LSW(MSD(req->dma));
4453 mcp->mb[5] = req->length;
4454 if (req->rsp)
4455 mcp->mb[10] = req->rsp->id;
4456 mcp->mb[12] = req->qos;
4457 mcp->mb[11] = req->vp_idx;
4458 mcp->mb[13] = req->rid;
4459 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4460 mcp->mb[15] = 0;
4461
4462 mcp->mb[4] = req->id;
4463 /* que in ptr index */
4464 mcp->mb[8] = 0;
4465 /* que out ptr index */
4466 mcp->mb[9] = *req->out_ptr = 0;
4467 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4468 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4469 mcp->in_mb = MBX_0;
4470 mcp->flags = MBX_DMA_OUT;
4471 mcp->tov = MBX_TOV_SECONDS * 2;
4472
4473 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4474 IS_QLA28XX(ha))
4475 mcp->in_mb |= MBX_1;
4476 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4477 mcp->out_mb |= MBX_15;
4478 /* debug q create issue in SR-IOV */
4479 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4480 }
4481
4482 spin_lock_irqsave(&ha->hardware_lock, flags);
4483 if (!(req->options & BIT_0)) {
4484 wrt_reg_dword(req->req_q_in, 0);
4485 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4486 wrt_reg_dword(req->req_q_out, 0);
4487 }
4488 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4489
4490 rval = qla2x00_mailbox_command(vha, mcp);
4491 if (rval != QLA_SUCCESS) {
4492 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4493 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4494 } else {
4495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4496 "Done %s.\n", __func__);
4497 }
4498
4499 return rval;
4500 }
4501
4502 int
qla25xx_init_rsp_que(struct scsi_qla_host * vha,struct rsp_que * rsp)4503 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
4504 {
4505 int rval;
4506 unsigned long flags;
4507 mbx_cmd_t mc;
4508 mbx_cmd_t *mcp = &mc;
4509 struct qla_hw_data *ha = vha->hw;
4510
4511 if (!ha->flags.fw_started)
4512 return QLA_SUCCESS;
4513
4514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4515 "Entered %s.\n", __func__);
4516
4517 if (IS_SHADOW_REG_CAPABLE(ha))
4518 rsp->options |= BIT_13;
4519
4520 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
4521 mcp->mb[1] = rsp->options;
4522 mcp->mb[2] = MSW(LSD(rsp->dma));
4523 mcp->mb[3] = LSW(LSD(rsp->dma));
4524 mcp->mb[6] = MSW(MSD(rsp->dma));
4525 mcp->mb[7] = LSW(MSD(rsp->dma));
4526 mcp->mb[5] = rsp->length;
4527 mcp->mb[14] = rsp->msix->entry;
4528 mcp->mb[13] = rsp->rid;
4529 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4530 mcp->mb[15] = 0;
4531
4532 mcp->mb[4] = rsp->id;
4533 /* que in ptr index */
4534 mcp->mb[8] = *rsp->in_ptr = 0;
4535 /* que out ptr index */
4536 mcp->mb[9] = 0;
4537 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
4538 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4539 mcp->in_mb = MBX_0;
4540 mcp->flags = MBX_DMA_OUT;
4541 mcp->tov = MBX_TOV_SECONDS * 2;
4542
4543 if (IS_QLA81XX(ha)) {
4544 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4545 mcp->in_mb |= MBX_1;
4546 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4547 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4548 mcp->in_mb |= MBX_1;
4549 /* debug q create issue in SR-IOV */
4550 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4551 }
4552
4553 spin_lock_irqsave(&ha->hardware_lock, flags);
4554 if (!(rsp->options & BIT_0)) {
4555 wrt_reg_dword(rsp->rsp_q_out, 0);
4556 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4557 wrt_reg_dword(rsp->rsp_q_in, 0);
4558 }
4559
4560 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4561
4562 rval = qla2x00_mailbox_command(vha, mcp);
4563 if (rval != QLA_SUCCESS) {
4564 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4565 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4566 } else {
4567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4568 "Done %s.\n", __func__);
4569 }
4570
4571 return rval;
4572 }
4573
4574 int
qla81xx_idc_ack(scsi_qla_host_t * vha,uint16_t * mb)4575 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4576 {
4577 int rval;
4578 mbx_cmd_t mc;
4579 mbx_cmd_t *mcp = &mc;
4580
4581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4582 "Entered %s.\n", __func__);
4583
4584 mcp->mb[0] = MBC_IDC_ACK;
4585 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4586 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4587 mcp->in_mb = MBX_0;
4588 mcp->tov = MBX_TOV_SECONDS;
4589 mcp->flags = 0;
4590 rval = qla2x00_mailbox_command(vha, mcp);
4591
4592 if (rval != QLA_SUCCESS) {
4593 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4594 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4595 } else {
4596 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4597 "Done %s.\n", __func__);
4598 }
4599
4600 return rval;
4601 }
4602
4603 int
qla81xx_fac_get_sector_size(scsi_qla_host_t * vha,uint32_t * sector_size)4604 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4605 {
4606 int rval;
4607 mbx_cmd_t mc;
4608 mbx_cmd_t *mcp = &mc;
4609
4610 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4611 "Entered %s.\n", __func__);
4612
4613 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4614 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4615 return QLA_FUNCTION_FAILED;
4616
4617 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4618 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4619 mcp->out_mb = MBX_1|MBX_0;
4620 mcp->in_mb = MBX_1|MBX_0;
4621 mcp->tov = MBX_TOV_SECONDS;
4622 mcp->flags = 0;
4623 rval = qla2x00_mailbox_command(vha, mcp);
4624
4625 if (rval != QLA_SUCCESS) {
4626 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4627 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4628 rval, mcp->mb[0], mcp->mb[1]);
4629 } else {
4630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4631 "Done %s.\n", __func__);
4632 *sector_size = mcp->mb[1];
4633 }
4634
4635 return rval;
4636 }
4637
4638 int
qla81xx_fac_do_write_enable(scsi_qla_host_t * vha,int enable)4639 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4640 {
4641 int rval;
4642 mbx_cmd_t mc;
4643 mbx_cmd_t *mcp = &mc;
4644
4645 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4646 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4647 return QLA_FUNCTION_FAILED;
4648
4649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4650 "Entered %s.\n", __func__);
4651
4652 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4653 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4654 FAC_OPT_CMD_WRITE_PROTECT;
4655 mcp->out_mb = MBX_1|MBX_0;
4656 mcp->in_mb = MBX_1|MBX_0;
4657 mcp->tov = MBX_TOV_SECONDS;
4658 mcp->flags = 0;
4659 rval = qla2x00_mailbox_command(vha, mcp);
4660
4661 if (rval != QLA_SUCCESS) {
4662 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4663 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4664 rval, mcp->mb[0], mcp->mb[1]);
4665 } else {
4666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4667 "Done %s.\n", __func__);
4668 }
4669
4670 return rval;
4671 }
4672
4673 int
qla81xx_fac_erase_sector(scsi_qla_host_t * vha,uint32_t start,uint32_t finish)4674 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4675 {
4676 int rval;
4677 mbx_cmd_t mc;
4678 mbx_cmd_t *mcp = &mc;
4679
4680 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4681 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4682 return QLA_FUNCTION_FAILED;
4683
4684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4685 "Entered %s.\n", __func__);
4686
4687 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4688 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4689 mcp->mb[2] = LSW(start);
4690 mcp->mb[3] = MSW(start);
4691 mcp->mb[4] = LSW(finish);
4692 mcp->mb[5] = MSW(finish);
4693 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4694 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4695 mcp->tov = MBX_TOV_SECONDS;
4696 mcp->flags = 0;
4697 rval = qla2x00_mailbox_command(vha, mcp);
4698
4699 if (rval != QLA_SUCCESS) {
4700 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4701 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4702 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4703 } else {
4704 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4705 "Done %s.\n", __func__);
4706 }
4707
4708 return rval;
4709 }
4710
4711 int
qla81xx_fac_semaphore_access(scsi_qla_host_t * vha,int lock)4712 qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
4713 {
4714 int rval = QLA_SUCCESS;
4715 mbx_cmd_t mc;
4716 mbx_cmd_t *mcp = &mc;
4717 struct qla_hw_data *ha = vha->hw;
4718
4719 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
4720 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4721 return rval;
4722
4723 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4724 "Entered %s.\n", __func__);
4725
4726 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4727 mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
4728 FAC_OPT_CMD_UNLOCK_SEMAPHORE);
4729 mcp->out_mb = MBX_1|MBX_0;
4730 mcp->in_mb = MBX_1|MBX_0;
4731 mcp->tov = MBX_TOV_SECONDS;
4732 mcp->flags = 0;
4733 rval = qla2x00_mailbox_command(vha, mcp);
4734
4735 if (rval != QLA_SUCCESS) {
4736 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4737 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4738 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4739 } else {
4740 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4741 "Done %s.\n", __func__);
4742 }
4743
4744 return rval;
4745 }
4746
4747 int
qla81xx_restart_mpi_firmware(scsi_qla_host_t * vha)4748 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4749 {
4750 int rval = 0;
4751 mbx_cmd_t mc;
4752 mbx_cmd_t *mcp = &mc;
4753
4754 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4755 "Entered %s.\n", __func__);
4756
4757 mcp->mb[0] = MBC_RESTART_MPI_FW;
4758 mcp->out_mb = MBX_0;
4759 mcp->in_mb = MBX_0|MBX_1;
4760 mcp->tov = MBX_TOV_SECONDS;
4761 mcp->flags = 0;
4762 rval = qla2x00_mailbox_command(vha, mcp);
4763
4764 if (rval != QLA_SUCCESS) {
4765 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4766 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4767 rval, mcp->mb[0], mcp->mb[1]);
4768 } else {
4769 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4770 "Done %s.\n", __func__);
4771 }
4772
4773 return rval;
4774 }
4775
4776 int
qla82xx_set_driver_version(scsi_qla_host_t * vha,char * version)4777 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4778 {
4779 int rval;
4780 mbx_cmd_t mc;
4781 mbx_cmd_t *mcp = &mc;
4782 int i;
4783 int len;
4784 __le16 *str;
4785 struct qla_hw_data *ha = vha->hw;
4786
4787 if (!IS_P3P_TYPE(ha))
4788 return QLA_FUNCTION_FAILED;
4789
4790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4791 "Entered %s.\n", __func__);
4792
4793 str = (__force __le16 *)version;
4794 len = strlen(version);
4795
4796 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4797 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4798 mcp->out_mb = MBX_1|MBX_0;
4799 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4800 mcp->mb[i] = le16_to_cpup(str);
4801 mcp->out_mb |= 1<<i;
4802 }
4803 for (; i < 16; i++) {
4804 mcp->mb[i] = 0;
4805 mcp->out_mb |= 1<<i;
4806 }
4807 mcp->in_mb = MBX_1|MBX_0;
4808 mcp->tov = MBX_TOV_SECONDS;
4809 mcp->flags = 0;
4810 rval = qla2x00_mailbox_command(vha, mcp);
4811
4812 if (rval != QLA_SUCCESS) {
4813 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4814 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4815 } else {
4816 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4817 "Done %s.\n", __func__);
4818 }
4819
4820 return rval;
4821 }
4822
4823 int
qla25xx_set_driver_version(scsi_qla_host_t * vha,char * version)4824 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4825 {
4826 int rval;
4827 mbx_cmd_t mc;
4828 mbx_cmd_t *mcp = &mc;
4829 int len;
4830 uint16_t dwlen;
4831 uint8_t *str;
4832 dma_addr_t str_dma;
4833 struct qla_hw_data *ha = vha->hw;
4834
4835 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4836 IS_P3P_TYPE(ha))
4837 return QLA_FUNCTION_FAILED;
4838
4839 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4840 "Entered %s.\n", __func__);
4841
4842 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4843 if (!str) {
4844 ql_log(ql_log_warn, vha, 0x117f,
4845 "Failed to allocate driver version param.\n");
4846 return QLA_MEMORY_ALLOC_FAILED;
4847 }
4848
4849 memcpy(str, "\x7\x3\x11\x0", 4);
4850 dwlen = str[0];
4851 len = dwlen * 4 - 4;
4852 memset(str + 4, 0, len);
4853 if (len > strlen(version))
4854 len = strlen(version);
4855 memcpy(str + 4, version, len);
4856
4857 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4858 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4859 mcp->mb[2] = MSW(LSD(str_dma));
4860 mcp->mb[3] = LSW(LSD(str_dma));
4861 mcp->mb[6] = MSW(MSD(str_dma));
4862 mcp->mb[7] = LSW(MSD(str_dma));
4863 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4864 mcp->in_mb = MBX_1|MBX_0;
4865 mcp->tov = MBX_TOV_SECONDS;
4866 mcp->flags = 0;
4867 rval = qla2x00_mailbox_command(vha, mcp);
4868
4869 if (rval != QLA_SUCCESS) {
4870 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4871 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4872 } else {
4873 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4874 "Done %s.\n", __func__);
4875 }
4876
4877 dma_pool_free(ha->s_dma_pool, str, str_dma);
4878
4879 return rval;
4880 }
4881
4882 int
qla24xx_get_port_login_templ(scsi_qla_host_t * vha,dma_addr_t buf_dma,void * buf,uint16_t bufsiz)4883 qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
4884 void *buf, uint16_t bufsiz)
4885 {
4886 int rval, i;
4887 mbx_cmd_t mc;
4888 mbx_cmd_t *mcp = &mc;
4889 uint32_t *bp;
4890
4891 if (!IS_FWI2_CAPABLE(vha->hw))
4892 return QLA_FUNCTION_FAILED;
4893
4894 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4895 "Entered %s.\n", __func__);
4896
4897 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4898 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
4899 mcp->mb[2] = MSW(buf_dma);
4900 mcp->mb[3] = LSW(buf_dma);
4901 mcp->mb[6] = MSW(MSD(buf_dma));
4902 mcp->mb[7] = LSW(MSD(buf_dma));
4903 mcp->mb[8] = bufsiz/4;
4904 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4905 mcp->in_mb = MBX_1|MBX_0;
4906 mcp->tov = MBX_TOV_SECONDS;
4907 mcp->flags = 0;
4908 rval = qla2x00_mailbox_command(vha, mcp);
4909
4910 if (rval != QLA_SUCCESS) {
4911 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4912 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4913 } else {
4914 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4915 "Done %s.\n", __func__);
4916 bp = (uint32_t *) buf;
4917 for (i = 0; i < (bufsiz-4)/4; i++, bp++)
4918 *bp = le32_to_cpu((__force __le32)*bp);
4919 }
4920
4921 return rval;
4922 }
4923
4924 #define PUREX_CMD_COUNT 2
4925 int
qla25xx_set_els_cmds_supported(scsi_qla_host_t * vha)4926 qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha)
4927 {
4928 int rval;
4929 mbx_cmd_t mc;
4930 mbx_cmd_t *mcp = &mc;
4931 uint8_t *els_cmd_map;
4932 dma_addr_t els_cmd_map_dma;
4933 uint8_t cmd_opcode[PUREX_CMD_COUNT];
4934 uint8_t i, index, purex_bit;
4935 struct qla_hw_data *ha = vha->hw;
4936
4937 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) &&
4938 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4939 return QLA_SUCCESS;
4940
4941 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197,
4942 "Entered %s.\n", __func__);
4943
4944 els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
4945 &els_cmd_map_dma, GFP_KERNEL);
4946 if (!els_cmd_map) {
4947 ql_log(ql_log_warn, vha, 0x7101,
4948 "Failed to allocate RDP els command param.\n");
4949 return QLA_MEMORY_ALLOC_FAILED;
4950 }
4951
4952 /* List of Purex ELS */
4953 cmd_opcode[0] = ELS_FPIN;
4954 cmd_opcode[1] = ELS_RDP;
4955
4956 for (i = 0; i < PUREX_CMD_COUNT; i++) {
4957 index = cmd_opcode[i] / 8;
4958 purex_bit = cmd_opcode[i] % 8;
4959 els_cmd_map[index] |= 1 << purex_bit;
4960 }
4961
4962 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4963 mcp->mb[1] = RNID_TYPE_ELS_CMD << 8;
4964 mcp->mb[2] = MSW(LSD(els_cmd_map_dma));
4965 mcp->mb[3] = LSW(LSD(els_cmd_map_dma));
4966 mcp->mb[6] = MSW(MSD(els_cmd_map_dma));
4967 mcp->mb[7] = LSW(MSD(els_cmd_map_dma));
4968 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4969 mcp->in_mb = MBX_1|MBX_0;
4970 mcp->tov = MBX_TOV_SECONDS;
4971 mcp->flags = MBX_DMA_OUT;
4972 mcp->buf_size = ELS_CMD_MAP_SIZE;
4973 rval = qla2x00_mailbox_command(vha, mcp);
4974
4975 if (rval != QLA_SUCCESS) {
4976 ql_dbg(ql_dbg_mbx, vha, 0x118d,
4977 "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]);
4978 } else {
4979 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
4980 "Done %s.\n", __func__);
4981 }
4982
4983 dma_free_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
4984 els_cmd_map, els_cmd_map_dma);
4985
4986 return rval;
4987 }
4988
4989 static int
qla2x00_read_asic_temperature(scsi_qla_host_t * vha,uint16_t * temp)4990 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4991 {
4992 int rval;
4993 mbx_cmd_t mc;
4994 mbx_cmd_t *mcp = &mc;
4995
4996 if (!IS_FWI2_CAPABLE(vha->hw))
4997 return QLA_FUNCTION_FAILED;
4998
4999 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
5000 "Entered %s.\n", __func__);
5001
5002 mcp->mb[0] = MBC_GET_RNID_PARAMS;
5003 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
5004 mcp->out_mb = MBX_1|MBX_0;
5005 mcp->in_mb = MBX_1|MBX_0;
5006 mcp->tov = MBX_TOV_SECONDS;
5007 mcp->flags = 0;
5008 rval = qla2x00_mailbox_command(vha, mcp);
5009 *temp = mcp->mb[1];
5010
5011 if (rval != QLA_SUCCESS) {
5012 ql_dbg(ql_dbg_mbx, vha, 0x115a,
5013 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
5014 } else {
5015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
5016 "Done %s.\n", __func__);
5017 }
5018
5019 return rval;
5020 }
5021
5022 int
qla2x00_read_sfp(scsi_qla_host_t * vha,dma_addr_t sfp_dma,uint8_t * sfp,uint16_t dev,uint16_t off,uint16_t len,uint16_t opt)5023 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
5024 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
5025 {
5026 int rval;
5027 mbx_cmd_t mc;
5028 mbx_cmd_t *mcp = &mc;
5029 struct qla_hw_data *ha = vha->hw;
5030
5031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
5032 "Entered %s.\n", __func__);
5033
5034 if (!IS_FWI2_CAPABLE(ha))
5035 return QLA_FUNCTION_FAILED;
5036
5037 if (len == 1)
5038 opt |= BIT_0;
5039
5040 mcp->mb[0] = MBC_READ_SFP;
5041 mcp->mb[1] = dev;
5042 mcp->mb[2] = MSW(LSD(sfp_dma));
5043 mcp->mb[3] = LSW(LSD(sfp_dma));
5044 mcp->mb[6] = MSW(MSD(sfp_dma));
5045 mcp->mb[7] = LSW(MSD(sfp_dma));
5046 mcp->mb[8] = len;
5047 mcp->mb[9] = off;
5048 mcp->mb[10] = opt;
5049 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5050 mcp->in_mb = MBX_1|MBX_0;
5051 mcp->tov = MBX_TOV_SECONDS;
5052 mcp->flags = 0;
5053 rval = qla2x00_mailbox_command(vha, mcp);
5054
5055 if (opt & BIT_0)
5056 *sfp = mcp->mb[1];
5057
5058 if (rval != QLA_SUCCESS) {
5059 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
5060 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5061 if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
5062 /* sfp is not there */
5063 rval = QLA_INTERFACE_ERROR;
5064 }
5065 } else {
5066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
5067 "Done %s.\n", __func__);
5068 }
5069
5070 return rval;
5071 }
5072
5073 int
qla2x00_write_sfp(scsi_qla_host_t * vha,dma_addr_t sfp_dma,uint8_t * sfp,uint16_t dev,uint16_t off,uint16_t len,uint16_t opt)5074 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
5075 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
5076 {
5077 int rval;
5078 mbx_cmd_t mc;
5079 mbx_cmd_t *mcp = &mc;
5080 struct qla_hw_data *ha = vha->hw;
5081
5082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
5083 "Entered %s.\n", __func__);
5084
5085 if (!IS_FWI2_CAPABLE(ha))
5086 return QLA_FUNCTION_FAILED;
5087
5088 if (len == 1)
5089 opt |= BIT_0;
5090
5091 if (opt & BIT_0)
5092 len = *sfp;
5093
5094 mcp->mb[0] = MBC_WRITE_SFP;
5095 mcp->mb[1] = dev;
5096 mcp->mb[2] = MSW(LSD(sfp_dma));
5097 mcp->mb[3] = LSW(LSD(sfp_dma));
5098 mcp->mb[6] = MSW(MSD(sfp_dma));
5099 mcp->mb[7] = LSW(MSD(sfp_dma));
5100 mcp->mb[8] = len;
5101 mcp->mb[9] = off;
5102 mcp->mb[10] = opt;
5103 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5104 mcp->in_mb = MBX_1|MBX_0;
5105 mcp->tov = MBX_TOV_SECONDS;
5106 mcp->flags = 0;
5107 rval = qla2x00_mailbox_command(vha, mcp);
5108
5109 if (rval != QLA_SUCCESS) {
5110 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
5111 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5112 } else {
5113 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
5114 "Done %s.\n", __func__);
5115 }
5116
5117 return rval;
5118 }
5119
5120 int
qla2x00_get_xgmac_stats(scsi_qla_host_t * vha,dma_addr_t stats_dma,uint16_t size_in_bytes,uint16_t * actual_size)5121 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
5122 uint16_t size_in_bytes, uint16_t *actual_size)
5123 {
5124 int rval;
5125 mbx_cmd_t mc;
5126 mbx_cmd_t *mcp = &mc;
5127
5128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
5129 "Entered %s.\n", __func__);
5130
5131 if (!IS_CNA_CAPABLE(vha->hw))
5132 return QLA_FUNCTION_FAILED;
5133
5134 mcp->mb[0] = MBC_GET_XGMAC_STATS;
5135 mcp->mb[2] = MSW(stats_dma);
5136 mcp->mb[3] = LSW(stats_dma);
5137 mcp->mb[6] = MSW(MSD(stats_dma));
5138 mcp->mb[7] = LSW(MSD(stats_dma));
5139 mcp->mb[8] = size_in_bytes >> 2;
5140 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
5141 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5142 mcp->tov = MBX_TOV_SECONDS;
5143 mcp->flags = 0;
5144 rval = qla2x00_mailbox_command(vha, mcp);
5145
5146 if (rval != QLA_SUCCESS) {
5147 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
5148 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5149 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
5150 } else {
5151 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
5152 "Done %s.\n", __func__);
5153
5154
5155 *actual_size = mcp->mb[2] << 2;
5156 }
5157
5158 return rval;
5159 }
5160
5161 int
qla2x00_get_dcbx_params(scsi_qla_host_t * vha,dma_addr_t tlv_dma,uint16_t size)5162 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
5163 uint16_t size)
5164 {
5165 int rval;
5166 mbx_cmd_t mc;
5167 mbx_cmd_t *mcp = &mc;
5168
5169 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
5170 "Entered %s.\n", __func__);
5171
5172 if (!IS_CNA_CAPABLE(vha->hw))
5173 return QLA_FUNCTION_FAILED;
5174
5175 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
5176 mcp->mb[1] = 0;
5177 mcp->mb[2] = MSW(tlv_dma);
5178 mcp->mb[3] = LSW(tlv_dma);
5179 mcp->mb[6] = MSW(MSD(tlv_dma));
5180 mcp->mb[7] = LSW(MSD(tlv_dma));
5181 mcp->mb[8] = size;
5182 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5183 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5184 mcp->tov = MBX_TOV_SECONDS;
5185 mcp->flags = 0;
5186 rval = qla2x00_mailbox_command(vha, mcp);
5187
5188 if (rval != QLA_SUCCESS) {
5189 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
5190 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5191 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
5192 } else {
5193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
5194 "Done %s.\n", __func__);
5195 }
5196
5197 return rval;
5198 }
5199
5200 int
qla2x00_read_ram_word(scsi_qla_host_t * vha,uint32_t risc_addr,uint32_t * data)5201 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
5202 {
5203 int rval;
5204 mbx_cmd_t mc;
5205 mbx_cmd_t *mcp = &mc;
5206
5207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
5208 "Entered %s.\n", __func__);
5209
5210 if (!IS_FWI2_CAPABLE(vha->hw))
5211 return QLA_FUNCTION_FAILED;
5212
5213 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
5214 mcp->mb[1] = LSW(risc_addr);
5215 mcp->mb[8] = MSW(risc_addr);
5216 mcp->out_mb = MBX_8|MBX_1|MBX_0;
5217 mcp->in_mb = MBX_3|MBX_2|MBX_0;
5218 mcp->tov = MBX_TOV_SECONDS;
5219 mcp->flags = 0;
5220 rval = qla2x00_mailbox_command(vha, mcp);
5221 if (rval != QLA_SUCCESS) {
5222 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
5223 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5224 } else {
5225 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
5226 "Done %s.\n", __func__);
5227 *data = mcp->mb[3] << 16 | mcp->mb[2];
5228 }
5229
5230 return rval;
5231 }
5232
5233 int
qla2x00_loopback_test(scsi_qla_host_t * vha,struct msg_echo_lb * mreq,uint16_t * mresp)5234 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5235 uint16_t *mresp)
5236 {
5237 int rval;
5238 mbx_cmd_t mc;
5239 mbx_cmd_t *mcp = &mc;
5240
5241 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
5242 "Entered %s.\n", __func__);
5243
5244 memset(mcp->mb, 0 , sizeof(mcp->mb));
5245 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
5246 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
5247
5248 /* transfer count */
5249 mcp->mb[10] = LSW(mreq->transfer_size);
5250 mcp->mb[11] = MSW(mreq->transfer_size);
5251
5252 /* send data address */
5253 mcp->mb[14] = LSW(mreq->send_dma);
5254 mcp->mb[15] = MSW(mreq->send_dma);
5255 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5256 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5257
5258 /* receive data address */
5259 mcp->mb[16] = LSW(mreq->rcv_dma);
5260 mcp->mb[17] = MSW(mreq->rcv_dma);
5261 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5262 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5263
5264 /* Iteration count */
5265 mcp->mb[18] = LSW(mreq->iteration_count);
5266 mcp->mb[19] = MSW(mreq->iteration_count);
5267
5268 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
5269 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
5270 if (IS_CNA_CAPABLE(vha->hw))
5271 mcp->out_mb |= MBX_2;
5272 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
5273
5274 mcp->buf_size = mreq->transfer_size;
5275 mcp->tov = MBX_TOV_SECONDS;
5276 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5277
5278 rval = qla2x00_mailbox_command(vha, mcp);
5279
5280 if (rval != QLA_SUCCESS) {
5281 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
5282 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
5283 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
5284 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
5285 } else {
5286 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
5287 "Done %s.\n", __func__);
5288 }
5289
5290 /* Copy mailbox information */
5291 memcpy( mresp, mcp->mb, 64);
5292 return rval;
5293 }
5294
5295 int
qla2x00_echo_test(scsi_qla_host_t * vha,struct msg_echo_lb * mreq,uint16_t * mresp)5296 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5297 uint16_t *mresp)
5298 {
5299 int rval;
5300 mbx_cmd_t mc;
5301 mbx_cmd_t *mcp = &mc;
5302 struct qla_hw_data *ha = vha->hw;
5303
5304 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
5305 "Entered %s.\n", __func__);
5306
5307 memset(mcp->mb, 0 , sizeof(mcp->mb));
5308 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
5309 /* BIT_6 specifies 64bit address */
5310 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
5311 if (IS_CNA_CAPABLE(ha)) {
5312 mcp->mb[2] = vha->fcoe_fcf_idx;
5313 }
5314 mcp->mb[16] = LSW(mreq->rcv_dma);
5315 mcp->mb[17] = MSW(mreq->rcv_dma);
5316 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5317 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5318
5319 mcp->mb[10] = LSW(mreq->transfer_size);
5320
5321 mcp->mb[14] = LSW(mreq->send_dma);
5322 mcp->mb[15] = MSW(mreq->send_dma);
5323 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5324 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5325
5326 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
5327 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
5328 if (IS_CNA_CAPABLE(ha))
5329 mcp->out_mb |= MBX_2;
5330
5331 mcp->in_mb = MBX_0;
5332 if (IS_CNA_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
5333 IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5334 mcp->in_mb |= MBX_1;
5335 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
5336 IS_QLA28XX(ha))
5337 mcp->in_mb |= MBX_3;
5338
5339 mcp->tov = MBX_TOV_SECONDS;
5340 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5341 mcp->buf_size = mreq->transfer_size;
5342
5343 rval = qla2x00_mailbox_command(vha, mcp);
5344
5345 if (rval != QLA_SUCCESS) {
5346 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
5347 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5348 rval, mcp->mb[0], mcp->mb[1]);
5349 } else {
5350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
5351 "Done %s.\n", __func__);
5352 }
5353
5354 /* Copy mailbox information */
5355 memcpy(mresp, mcp->mb, 64);
5356 return rval;
5357 }
5358
5359 int
qla84xx_reset_chip(scsi_qla_host_t * vha,uint16_t enable_diagnostic)5360 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
5361 {
5362 int rval;
5363 mbx_cmd_t mc;
5364 mbx_cmd_t *mcp = &mc;
5365
5366 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
5367 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
5368
5369 mcp->mb[0] = MBC_ISP84XX_RESET;
5370 mcp->mb[1] = enable_diagnostic;
5371 mcp->out_mb = MBX_1|MBX_0;
5372 mcp->in_mb = MBX_1|MBX_0;
5373 mcp->tov = MBX_TOV_SECONDS;
5374 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5375 rval = qla2x00_mailbox_command(vha, mcp);
5376
5377 if (rval != QLA_SUCCESS)
5378 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
5379 else
5380 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
5381 "Done %s.\n", __func__);
5382
5383 return rval;
5384 }
5385
5386 int
qla2x00_write_ram_word(scsi_qla_host_t * vha,uint32_t risc_addr,uint32_t data)5387 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
5388 {
5389 int rval;
5390 mbx_cmd_t mc;
5391 mbx_cmd_t *mcp = &mc;
5392
5393 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
5394 "Entered %s.\n", __func__);
5395
5396 if (!IS_FWI2_CAPABLE(vha->hw))
5397 return QLA_FUNCTION_FAILED;
5398
5399 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
5400 mcp->mb[1] = LSW(risc_addr);
5401 mcp->mb[2] = LSW(data);
5402 mcp->mb[3] = MSW(data);
5403 mcp->mb[8] = MSW(risc_addr);
5404 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
5405 mcp->in_mb = MBX_1|MBX_0;
5406 mcp->tov = MBX_TOV_SECONDS;
5407 mcp->flags = 0;
5408 rval = qla2x00_mailbox_command(vha, mcp);
5409 if (rval != QLA_SUCCESS) {
5410 ql_dbg(ql_dbg_mbx, vha, 0x1101,
5411 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5412 rval, mcp->mb[0], mcp->mb[1]);
5413 } else {
5414 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5415 "Done %s.\n", __func__);
5416 }
5417
5418 return rval;
5419 }
5420
5421 int
qla81xx_write_mpi_register(scsi_qla_host_t * vha,uint16_t * mb)5422 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
5423 {
5424 int rval;
5425 uint32_t stat, timer;
5426 uint16_t mb0 = 0;
5427 struct qla_hw_data *ha = vha->hw;
5428 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5429
5430 rval = QLA_SUCCESS;
5431
5432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
5433 "Entered %s.\n", __func__);
5434
5435 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5436
5437 /* Write the MBC data to the registers */
5438 wrt_reg_word(®->mailbox0, MBC_WRITE_MPI_REGISTER);
5439 wrt_reg_word(®->mailbox1, mb[0]);
5440 wrt_reg_word(®->mailbox2, mb[1]);
5441 wrt_reg_word(®->mailbox3, mb[2]);
5442 wrt_reg_word(®->mailbox4, mb[3]);
5443
5444 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT);
5445
5446 /* Poll for MBC interrupt */
5447 for (timer = 6000000; timer; timer--) {
5448 /* Check for pending interrupts. */
5449 stat = rd_reg_dword(®->host_status);
5450 if (stat & HSRX_RISC_INT) {
5451 stat &= 0xff;
5452
5453 if (stat == 0x1 || stat == 0x2 ||
5454 stat == 0x10 || stat == 0x11) {
5455 set_bit(MBX_INTERRUPT,
5456 &ha->mbx_cmd_flags);
5457 mb0 = rd_reg_word(®->mailbox0);
5458 wrt_reg_dword(®->hccr,
5459 HCCRX_CLR_RISC_INT);
5460 rd_reg_dword(®->hccr);
5461 break;
5462 }
5463 }
5464 udelay(5);
5465 }
5466
5467 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5468 rval = mb0 & MBS_MASK;
5469 else
5470 rval = QLA_FUNCTION_FAILED;
5471
5472 if (rval != QLA_SUCCESS) {
5473 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5474 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
5475 } else {
5476 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5477 "Done %s.\n", __func__);
5478 }
5479
5480 return rval;
5481 }
5482
5483 /* Set the specified data rate */
5484 int
qla2x00_set_data_rate(scsi_qla_host_t * vha,uint16_t mode)5485 qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
5486 {
5487 int rval;
5488 mbx_cmd_t mc;
5489 mbx_cmd_t *mcp = &mc;
5490 struct qla_hw_data *ha = vha->hw;
5491 uint16_t val;
5492
5493 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5494 "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
5495 mode);
5496
5497 if (!IS_FWI2_CAPABLE(ha))
5498 return QLA_FUNCTION_FAILED;
5499
5500 memset(mcp, 0, sizeof(*mcp));
5501 switch (ha->set_data_rate) {
5502 case PORT_SPEED_AUTO:
5503 case PORT_SPEED_4GB:
5504 case PORT_SPEED_8GB:
5505 case PORT_SPEED_16GB:
5506 case PORT_SPEED_32GB:
5507 val = ha->set_data_rate;
5508 break;
5509 default:
5510 ql_log(ql_log_warn, vha, 0x1199,
5511 "Unrecognized speed setting:%d. Setting Autoneg\n",
5512 ha->set_data_rate);
5513 val = ha->set_data_rate = PORT_SPEED_AUTO;
5514 break;
5515 }
5516
5517 mcp->mb[0] = MBC_DATA_RATE;
5518 mcp->mb[1] = mode;
5519 mcp->mb[2] = val;
5520
5521 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5522 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5523 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5524 mcp->in_mb |= MBX_4|MBX_3;
5525 mcp->tov = MBX_TOV_SECONDS;
5526 mcp->flags = 0;
5527 rval = qla2x00_mailbox_command(vha, mcp);
5528 if (rval != QLA_SUCCESS) {
5529 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5530 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5531 } else {
5532 if (mcp->mb[1] != 0x7)
5533 ql_dbg(ql_dbg_mbx, vha, 0x1179,
5534 "Speed set:0x%x\n", mcp->mb[1]);
5535
5536 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5537 "Done %s.\n", __func__);
5538 }
5539
5540 return rval;
5541 }
5542
5543 int
qla2x00_get_data_rate(scsi_qla_host_t * vha)5544 qla2x00_get_data_rate(scsi_qla_host_t *vha)
5545 {
5546 int rval;
5547 mbx_cmd_t mc;
5548 mbx_cmd_t *mcp = &mc;
5549 struct qla_hw_data *ha = vha->hw;
5550
5551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5552 "Entered %s.\n", __func__);
5553
5554 if (!IS_FWI2_CAPABLE(ha))
5555 return QLA_FUNCTION_FAILED;
5556
5557 mcp->mb[0] = MBC_DATA_RATE;
5558 mcp->mb[1] = QLA_GET_DATA_RATE;
5559 mcp->out_mb = MBX_1|MBX_0;
5560 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5561 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5562 mcp->in_mb |= MBX_4|MBX_3;
5563 mcp->tov = MBX_TOV_SECONDS;
5564 mcp->flags = 0;
5565 rval = qla2x00_mailbox_command(vha, mcp);
5566 if (rval != QLA_SUCCESS) {
5567 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5568 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5569 } else {
5570 if (mcp->mb[1] != 0x7)
5571 ha->link_data_rate = mcp->mb[1];
5572
5573 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
5574 if (mcp->mb[4] & BIT_0)
5575 ql_log(ql_log_info, vha, 0x11a2,
5576 "FEC=enabled (data rate).\n");
5577 }
5578
5579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5580 "Done %s.\n", __func__);
5581 if (mcp->mb[1] != 0x7)
5582 ha->link_data_rate = mcp->mb[1];
5583 }
5584
5585 return rval;
5586 }
5587
5588 int
qla81xx_get_port_config(scsi_qla_host_t * vha,uint16_t * mb)5589 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5590 {
5591 int rval;
5592 mbx_cmd_t mc;
5593 mbx_cmd_t *mcp = &mc;
5594 struct qla_hw_data *ha = vha->hw;
5595
5596 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5597 "Entered %s.\n", __func__);
5598
5599 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5600 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5601 return QLA_FUNCTION_FAILED;
5602 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5603 mcp->out_mb = MBX_0;
5604 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5605 mcp->tov = MBX_TOV_SECONDS;
5606 mcp->flags = 0;
5607
5608 rval = qla2x00_mailbox_command(vha, mcp);
5609
5610 if (rval != QLA_SUCCESS) {
5611 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5612 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5613 } else {
5614 /* Copy all bits to preserve original value */
5615 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5616
5617 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5618 "Done %s.\n", __func__);
5619 }
5620 return rval;
5621 }
5622
5623 int
qla81xx_set_port_config(scsi_qla_host_t * vha,uint16_t * mb)5624 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5625 {
5626 int rval;
5627 mbx_cmd_t mc;
5628 mbx_cmd_t *mcp = &mc;
5629
5630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5631 "Entered %s.\n", __func__);
5632
5633 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5634 /* Copy all bits to preserve original setting */
5635 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5636 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5637 mcp->in_mb = MBX_0;
5638 mcp->tov = MBX_TOV_SECONDS;
5639 mcp->flags = 0;
5640 rval = qla2x00_mailbox_command(vha, mcp);
5641
5642 if (rval != QLA_SUCCESS) {
5643 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5644 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5645 } else
5646 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5647 "Done %s.\n", __func__);
5648
5649 return rval;
5650 }
5651
5652
5653 int
qla24xx_set_fcp_prio(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t priority,uint16_t * mb)5654 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5655 uint16_t *mb)
5656 {
5657 int rval;
5658 mbx_cmd_t mc;
5659 mbx_cmd_t *mcp = &mc;
5660 struct qla_hw_data *ha = vha->hw;
5661
5662 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5663 "Entered %s.\n", __func__);
5664
5665 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5666 return QLA_FUNCTION_FAILED;
5667
5668 mcp->mb[0] = MBC_PORT_PARAMS;
5669 mcp->mb[1] = loop_id;
5670 if (ha->flags.fcp_prio_enabled)
5671 mcp->mb[2] = BIT_1;
5672 else
5673 mcp->mb[2] = BIT_2;
5674 mcp->mb[4] = priority & 0xf;
5675 mcp->mb[9] = vha->vp_idx;
5676 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5677 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5678 mcp->tov = MBX_TOV_SECONDS;
5679 mcp->flags = 0;
5680 rval = qla2x00_mailbox_command(vha, mcp);
5681 if (mb != NULL) {
5682 mb[0] = mcp->mb[0];
5683 mb[1] = mcp->mb[1];
5684 mb[3] = mcp->mb[3];
5685 mb[4] = mcp->mb[4];
5686 }
5687
5688 if (rval != QLA_SUCCESS) {
5689 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
5690 } else {
5691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5692 "Done %s.\n", __func__);
5693 }
5694
5695 return rval;
5696 }
5697
5698 int
qla2x00_get_thermal_temp(scsi_qla_host_t * vha,uint16_t * temp)5699 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
5700 {
5701 int rval = QLA_FUNCTION_FAILED;
5702 struct qla_hw_data *ha = vha->hw;
5703 uint8_t byte;
5704
5705 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5706 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5707 "Thermal not supported by this card.\n");
5708 return rval;
5709 }
5710
5711 if (IS_QLA25XX(ha)) {
5712 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5713 ha->pdev->subsystem_device == 0x0175) {
5714 rval = qla2x00_read_sfp(vha, 0, &byte,
5715 0x98, 0x1, 1, BIT_13|BIT_0);
5716 *temp = byte;
5717 return rval;
5718 }
5719 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5720 ha->pdev->subsystem_device == 0x338e) {
5721 rval = qla2x00_read_sfp(vha, 0, &byte,
5722 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5723 *temp = byte;
5724 return rval;
5725 }
5726 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5727 "Thermal not supported by this card.\n");
5728 return rval;
5729 }
5730
5731 if (IS_QLA82XX(ha)) {
5732 *temp = qla82xx_read_temperature(vha);
5733 rval = QLA_SUCCESS;
5734 return rval;
5735 } else if (IS_QLA8044(ha)) {
5736 *temp = qla8044_read_temperature(vha);
5737 rval = QLA_SUCCESS;
5738 return rval;
5739 }
5740
5741 rval = qla2x00_read_asic_temperature(vha, temp);
5742 return rval;
5743 }
5744
5745 int
qla82xx_mbx_intr_enable(scsi_qla_host_t * vha)5746 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5747 {
5748 int rval;
5749 struct qla_hw_data *ha = vha->hw;
5750 mbx_cmd_t mc;
5751 mbx_cmd_t *mcp = &mc;
5752
5753 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5754 "Entered %s.\n", __func__);
5755
5756 if (!IS_FWI2_CAPABLE(ha))
5757 return QLA_FUNCTION_FAILED;
5758
5759 memset(mcp, 0, sizeof(mbx_cmd_t));
5760 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
5761 mcp->mb[1] = 1;
5762
5763 mcp->out_mb = MBX_1|MBX_0;
5764 mcp->in_mb = MBX_0;
5765 mcp->tov = MBX_TOV_SECONDS;
5766 mcp->flags = 0;
5767
5768 rval = qla2x00_mailbox_command(vha, mcp);
5769 if (rval != QLA_SUCCESS) {
5770 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5771 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5772 } else {
5773 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5774 "Done %s.\n", __func__);
5775 }
5776
5777 return rval;
5778 }
5779
5780 int
qla82xx_mbx_intr_disable(scsi_qla_host_t * vha)5781 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5782 {
5783 int rval;
5784 struct qla_hw_data *ha = vha->hw;
5785 mbx_cmd_t mc;
5786 mbx_cmd_t *mcp = &mc;
5787
5788 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5789 "Entered %s.\n", __func__);
5790
5791 if (!IS_P3P_TYPE(ha))
5792 return QLA_FUNCTION_FAILED;
5793
5794 memset(mcp, 0, sizeof(mbx_cmd_t));
5795 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
5796 mcp->mb[1] = 0;
5797
5798 mcp->out_mb = MBX_1|MBX_0;
5799 mcp->in_mb = MBX_0;
5800 mcp->tov = MBX_TOV_SECONDS;
5801 mcp->flags = 0;
5802
5803 rval = qla2x00_mailbox_command(vha, mcp);
5804 if (rval != QLA_SUCCESS) {
5805 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5806 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5807 } else {
5808 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5809 "Done %s.\n", __func__);
5810 }
5811
5812 return rval;
5813 }
5814
5815 int
qla82xx_md_get_template_size(scsi_qla_host_t * vha)5816 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5817 {
5818 struct qla_hw_data *ha = vha->hw;
5819 mbx_cmd_t mc;
5820 mbx_cmd_t *mcp = &mc;
5821 int rval = QLA_FUNCTION_FAILED;
5822
5823 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5824 "Entered %s.\n", __func__);
5825
5826 memset(mcp->mb, 0 , sizeof(mcp->mb));
5827 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5828 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5829 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5830 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5831
5832 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5833 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5834 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5835
5836 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5837 mcp->tov = MBX_TOV_SECONDS;
5838 rval = qla2x00_mailbox_command(vha, mcp);
5839
5840 /* Always copy back return mailbox values. */
5841 if (rval != QLA_SUCCESS) {
5842 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5843 "mailbox command FAILED=0x%x, subcode=%x.\n",
5844 (mcp->mb[1] << 16) | mcp->mb[0],
5845 (mcp->mb[3] << 16) | mcp->mb[2]);
5846 } else {
5847 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5848 "Done %s.\n", __func__);
5849 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5850 if (!ha->md_template_size) {
5851 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5852 "Null template size obtained.\n");
5853 rval = QLA_FUNCTION_FAILED;
5854 }
5855 }
5856 return rval;
5857 }
5858
5859 int
qla82xx_md_get_template(scsi_qla_host_t * vha)5860 qla82xx_md_get_template(scsi_qla_host_t *vha)
5861 {
5862 struct qla_hw_data *ha = vha->hw;
5863 mbx_cmd_t mc;
5864 mbx_cmd_t *mcp = &mc;
5865 int rval = QLA_FUNCTION_FAILED;
5866
5867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5868 "Entered %s.\n", __func__);
5869
5870 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5871 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5872 if (!ha->md_tmplt_hdr) {
5873 ql_log(ql_log_warn, vha, 0x1124,
5874 "Unable to allocate memory for Minidump template.\n");
5875 return rval;
5876 }
5877
5878 memset(mcp->mb, 0 , sizeof(mcp->mb));
5879 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5880 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5881 mcp->mb[2] = LSW(RQST_TMPLT);
5882 mcp->mb[3] = MSW(RQST_TMPLT);
5883 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5884 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5885 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5886 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5887 mcp->mb[8] = LSW(ha->md_template_size);
5888 mcp->mb[9] = MSW(ha->md_template_size);
5889
5890 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5891 mcp->tov = MBX_TOV_SECONDS;
5892 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5893 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5894 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5895 rval = qla2x00_mailbox_command(vha, mcp);
5896
5897 if (rval != QLA_SUCCESS) {
5898 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5899 "mailbox command FAILED=0x%x, subcode=%x.\n",
5900 ((mcp->mb[1] << 16) | mcp->mb[0]),
5901 ((mcp->mb[3] << 16) | mcp->mb[2]));
5902 } else
5903 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5904 "Done %s.\n", __func__);
5905 return rval;
5906 }
5907
5908 int
qla8044_md_get_template(scsi_qla_host_t * vha)5909 qla8044_md_get_template(scsi_qla_host_t *vha)
5910 {
5911 struct qla_hw_data *ha = vha->hw;
5912 mbx_cmd_t mc;
5913 mbx_cmd_t *mcp = &mc;
5914 int rval = QLA_FUNCTION_FAILED;
5915 int offset = 0, size = MINIDUMP_SIZE_36K;
5916
5917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5918 "Entered %s.\n", __func__);
5919
5920 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5921 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5922 if (!ha->md_tmplt_hdr) {
5923 ql_log(ql_log_warn, vha, 0xb11b,
5924 "Unable to allocate memory for Minidump template.\n");
5925 return rval;
5926 }
5927
5928 memset(mcp->mb, 0 , sizeof(mcp->mb));
5929 while (offset < ha->md_template_size) {
5930 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5931 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5932 mcp->mb[2] = LSW(RQST_TMPLT);
5933 mcp->mb[3] = MSW(RQST_TMPLT);
5934 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5935 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5936 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5937 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5938 mcp->mb[8] = LSW(size);
5939 mcp->mb[9] = MSW(size);
5940 mcp->mb[10] = offset & 0x0000FFFF;
5941 mcp->mb[11] = offset & 0xFFFF0000;
5942 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5943 mcp->tov = MBX_TOV_SECONDS;
5944 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5945 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5946 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5947 rval = qla2x00_mailbox_command(vha, mcp);
5948
5949 if (rval != QLA_SUCCESS) {
5950 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5951 "mailbox command FAILED=0x%x, subcode=%x.\n",
5952 ((mcp->mb[1] << 16) | mcp->mb[0]),
5953 ((mcp->mb[3] << 16) | mcp->mb[2]));
5954 return rval;
5955 } else
5956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5957 "Done %s.\n", __func__);
5958 offset = offset + size;
5959 }
5960 return rval;
5961 }
5962
5963 int
qla81xx_set_led_config(scsi_qla_host_t * vha,uint16_t * led_cfg)5964 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5965 {
5966 int rval;
5967 struct qla_hw_data *ha = vha->hw;
5968 mbx_cmd_t mc;
5969 mbx_cmd_t *mcp = &mc;
5970
5971 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5972 return QLA_FUNCTION_FAILED;
5973
5974 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5975 "Entered %s.\n", __func__);
5976
5977 memset(mcp, 0, sizeof(mbx_cmd_t));
5978 mcp->mb[0] = MBC_SET_LED_CONFIG;
5979 mcp->mb[1] = led_cfg[0];
5980 mcp->mb[2] = led_cfg[1];
5981 if (IS_QLA8031(ha)) {
5982 mcp->mb[3] = led_cfg[2];
5983 mcp->mb[4] = led_cfg[3];
5984 mcp->mb[5] = led_cfg[4];
5985 mcp->mb[6] = led_cfg[5];
5986 }
5987
5988 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5989 if (IS_QLA8031(ha))
5990 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5991 mcp->in_mb = MBX_0;
5992 mcp->tov = MBX_TOV_SECONDS;
5993 mcp->flags = 0;
5994
5995 rval = qla2x00_mailbox_command(vha, mcp);
5996 if (rval != QLA_SUCCESS) {
5997 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5998 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5999 } else {
6000 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
6001 "Done %s.\n", __func__);
6002 }
6003
6004 return rval;
6005 }
6006
6007 int
qla81xx_get_led_config(scsi_qla_host_t * vha,uint16_t * led_cfg)6008 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
6009 {
6010 int rval;
6011 struct qla_hw_data *ha = vha->hw;
6012 mbx_cmd_t mc;
6013 mbx_cmd_t *mcp = &mc;
6014
6015 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
6016 return QLA_FUNCTION_FAILED;
6017
6018 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
6019 "Entered %s.\n", __func__);
6020
6021 memset(mcp, 0, sizeof(mbx_cmd_t));
6022 mcp->mb[0] = MBC_GET_LED_CONFIG;
6023
6024 mcp->out_mb = MBX_0;
6025 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6026 if (IS_QLA8031(ha))
6027 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
6028 mcp->tov = MBX_TOV_SECONDS;
6029 mcp->flags = 0;
6030
6031 rval = qla2x00_mailbox_command(vha, mcp);
6032 if (rval != QLA_SUCCESS) {
6033 ql_dbg(ql_dbg_mbx, vha, 0x1137,
6034 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6035 } else {
6036 led_cfg[0] = mcp->mb[1];
6037 led_cfg[1] = mcp->mb[2];
6038 if (IS_QLA8031(ha)) {
6039 led_cfg[2] = mcp->mb[3];
6040 led_cfg[3] = mcp->mb[4];
6041 led_cfg[4] = mcp->mb[5];
6042 led_cfg[5] = mcp->mb[6];
6043 }
6044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
6045 "Done %s.\n", __func__);
6046 }
6047
6048 return rval;
6049 }
6050
6051 int
qla82xx_mbx_beacon_ctl(scsi_qla_host_t * vha,int enable)6052 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
6053 {
6054 int rval;
6055 struct qla_hw_data *ha = vha->hw;
6056 mbx_cmd_t mc;
6057 mbx_cmd_t *mcp = &mc;
6058
6059 if (!IS_P3P_TYPE(ha))
6060 return QLA_FUNCTION_FAILED;
6061
6062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
6063 "Entered %s.\n", __func__);
6064
6065 memset(mcp, 0, sizeof(mbx_cmd_t));
6066 mcp->mb[0] = MBC_SET_LED_CONFIG;
6067 if (enable)
6068 mcp->mb[7] = 0xE;
6069 else
6070 mcp->mb[7] = 0xD;
6071
6072 mcp->out_mb = MBX_7|MBX_0;
6073 mcp->in_mb = MBX_0;
6074 mcp->tov = MBX_TOV_SECONDS;
6075 mcp->flags = 0;
6076
6077 rval = qla2x00_mailbox_command(vha, mcp);
6078 if (rval != QLA_SUCCESS) {
6079 ql_dbg(ql_dbg_mbx, vha, 0x1128,
6080 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6081 } else {
6082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
6083 "Done %s.\n", __func__);
6084 }
6085
6086 return rval;
6087 }
6088
6089 int
qla83xx_wr_reg(scsi_qla_host_t * vha,uint32_t reg,uint32_t data)6090 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6091 {
6092 int rval;
6093 struct qla_hw_data *ha = vha->hw;
6094 mbx_cmd_t mc;
6095 mbx_cmd_t *mcp = &mc;
6096
6097 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6098 return QLA_FUNCTION_FAILED;
6099
6100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
6101 "Entered %s.\n", __func__);
6102
6103 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6104 mcp->mb[1] = LSW(reg);
6105 mcp->mb[2] = MSW(reg);
6106 mcp->mb[3] = LSW(data);
6107 mcp->mb[4] = MSW(data);
6108 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6109
6110 mcp->in_mb = MBX_1|MBX_0;
6111 mcp->tov = MBX_TOV_SECONDS;
6112 mcp->flags = 0;
6113 rval = qla2x00_mailbox_command(vha, mcp);
6114
6115 if (rval != QLA_SUCCESS) {
6116 ql_dbg(ql_dbg_mbx, vha, 0x1131,
6117 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6118 } else {
6119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6120 "Done %s.\n", __func__);
6121 }
6122
6123 return rval;
6124 }
6125
6126 int
qla2x00_port_logout(scsi_qla_host_t * vha,struct fc_port * fcport)6127 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
6128 {
6129 int rval;
6130 struct qla_hw_data *ha = vha->hw;
6131 mbx_cmd_t mc;
6132 mbx_cmd_t *mcp = &mc;
6133
6134 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
6135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
6136 "Implicit LOGO Unsupported.\n");
6137 return QLA_FUNCTION_FAILED;
6138 }
6139
6140
6141 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
6142 "Entering %s.\n", __func__);
6143
6144 /* Perform Implicit LOGO. */
6145 mcp->mb[0] = MBC_PORT_LOGOUT;
6146 mcp->mb[1] = fcport->loop_id;
6147 mcp->mb[10] = BIT_15;
6148 mcp->out_mb = MBX_10|MBX_1|MBX_0;
6149 mcp->in_mb = MBX_0;
6150 mcp->tov = MBX_TOV_SECONDS;
6151 mcp->flags = 0;
6152 rval = qla2x00_mailbox_command(vha, mcp);
6153 if (rval != QLA_SUCCESS)
6154 ql_dbg(ql_dbg_mbx, vha, 0x113d,
6155 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6156 else
6157 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
6158 "Done %s.\n", __func__);
6159
6160 return rval;
6161 }
6162
6163 int
qla83xx_rd_reg(scsi_qla_host_t * vha,uint32_t reg,uint32_t * data)6164 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
6165 {
6166 int rval;
6167 mbx_cmd_t mc;
6168 mbx_cmd_t *mcp = &mc;
6169 struct qla_hw_data *ha = vha->hw;
6170 unsigned long retry_max_time = jiffies + (2 * HZ);
6171
6172 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6173 return QLA_FUNCTION_FAILED;
6174
6175 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
6176
6177 retry_rd_reg:
6178 mcp->mb[0] = MBC_READ_REMOTE_REG;
6179 mcp->mb[1] = LSW(reg);
6180 mcp->mb[2] = MSW(reg);
6181 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6182 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
6183 mcp->tov = MBX_TOV_SECONDS;
6184 mcp->flags = 0;
6185 rval = qla2x00_mailbox_command(vha, mcp);
6186
6187 if (rval != QLA_SUCCESS) {
6188 ql_dbg(ql_dbg_mbx, vha, 0x114c,
6189 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6190 rval, mcp->mb[0], mcp->mb[1]);
6191 } else {
6192 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
6193 if (*data == QLA8XXX_BAD_VALUE) {
6194 /*
6195 * During soft-reset CAMRAM register reads might
6196 * return 0xbad0bad0. So retry for MAX of 2 sec
6197 * while reading camram registers.
6198 */
6199 if (time_after(jiffies, retry_max_time)) {
6200 ql_dbg(ql_dbg_mbx, vha, 0x1141,
6201 "Failure to read CAMRAM register. "
6202 "data=0x%x.\n", *data);
6203 return QLA_FUNCTION_FAILED;
6204 }
6205 msleep(100);
6206 goto retry_rd_reg;
6207 }
6208 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
6209 }
6210
6211 return rval;
6212 }
6213
6214 int
qla83xx_restart_nic_firmware(scsi_qla_host_t * vha)6215 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
6216 {
6217 int rval;
6218 mbx_cmd_t mc;
6219 mbx_cmd_t *mcp = &mc;
6220 struct qla_hw_data *ha = vha->hw;
6221
6222 if (!IS_QLA83XX(ha))
6223 return QLA_FUNCTION_FAILED;
6224
6225 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
6226
6227 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
6228 mcp->out_mb = MBX_0;
6229 mcp->in_mb = MBX_1|MBX_0;
6230 mcp->tov = MBX_TOV_SECONDS;
6231 mcp->flags = 0;
6232 rval = qla2x00_mailbox_command(vha, mcp);
6233
6234 if (rval != QLA_SUCCESS) {
6235 ql_dbg(ql_dbg_mbx, vha, 0x1144,
6236 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6237 rval, mcp->mb[0], mcp->mb[1]);
6238 qla2xxx_dump_fw(vha);
6239 } else {
6240 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
6241 }
6242
6243 return rval;
6244 }
6245
6246 int
qla83xx_access_control(scsi_qla_host_t * vha,uint16_t options,uint32_t start_addr,uint32_t end_addr,uint16_t * sector_size)6247 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
6248 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
6249 {
6250 int rval;
6251 mbx_cmd_t mc;
6252 mbx_cmd_t *mcp = &mc;
6253 uint8_t subcode = (uint8_t)options;
6254 struct qla_hw_data *ha = vha->hw;
6255
6256 if (!IS_QLA8031(ha))
6257 return QLA_FUNCTION_FAILED;
6258
6259 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
6260
6261 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
6262 mcp->mb[1] = options;
6263 mcp->out_mb = MBX_1|MBX_0;
6264 if (subcode & BIT_2) {
6265 mcp->mb[2] = LSW(start_addr);
6266 mcp->mb[3] = MSW(start_addr);
6267 mcp->mb[4] = LSW(end_addr);
6268 mcp->mb[5] = MSW(end_addr);
6269 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
6270 }
6271 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6272 if (!(subcode & (BIT_2 | BIT_5)))
6273 mcp->in_mb |= MBX_4|MBX_3;
6274 mcp->tov = MBX_TOV_SECONDS;
6275 mcp->flags = 0;
6276 rval = qla2x00_mailbox_command(vha, mcp);
6277
6278 if (rval != QLA_SUCCESS) {
6279 ql_dbg(ql_dbg_mbx, vha, 0x1147,
6280 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
6281 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
6282 mcp->mb[4]);
6283 qla2xxx_dump_fw(vha);
6284 } else {
6285 if (subcode & BIT_5)
6286 *sector_size = mcp->mb[1];
6287 else if (subcode & (BIT_6 | BIT_7)) {
6288 ql_dbg(ql_dbg_mbx, vha, 0x1148,
6289 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6290 } else if (subcode & (BIT_3 | BIT_4)) {
6291 ql_dbg(ql_dbg_mbx, vha, 0x1149,
6292 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6293 }
6294 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
6295 }
6296
6297 return rval;
6298 }
6299
6300 int
qla2x00_dump_mctp_data(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t addr,uint32_t size)6301 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
6302 uint32_t size)
6303 {
6304 int rval;
6305 mbx_cmd_t mc;
6306 mbx_cmd_t *mcp = &mc;
6307
6308 if (!IS_MCTP_CAPABLE(vha->hw))
6309 return QLA_FUNCTION_FAILED;
6310
6311 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
6312 "Entered %s.\n", __func__);
6313
6314 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
6315 mcp->mb[1] = LSW(addr);
6316 mcp->mb[2] = MSW(req_dma);
6317 mcp->mb[3] = LSW(req_dma);
6318 mcp->mb[4] = MSW(size);
6319 mcp->mb[5] = LSW(size);
6320 mcp->mb[6] = MSW(MSD(req_dma));
6321 mcp->mb[7] = LSW(MSD(req_dma));
6322 mcp->mb[8] = MSW(addr);
6323 /* Setting RAM ID to valid */
6324 /* For MCTP RAM ID is 0x40 */
6325 mcp->mb[10] = BIT_7 | 0x40;
6326
6327 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
6328 MBX_0;
6329
6330 mcp->in_mb = MBX_0;
6331 mcp->tov = MBX_TOV_SECONDS;
6332 mcp->flags = 0;
6333 rval = qla2x00_mailbox_command(vha, mcp);
6334
6335 if (rval != QLA_SUCCESS) {
6336 ql_dbg(ql_dbg_mbx, vha, 0x114e,
6337 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6338 } else {
6339 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
6340 "Done %s.\n", __func__);
6341 }
6342
6343 return rval;
6344 }
6345
6346 int
qla26xx_dport_diagnostics(scsi_qla_host_t * vha,void * dd_buf,uint size,uint options)6347 qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
6348 void *dd_buf, uint size, uint options)
6349 {
6350 int rval;
6351 mbx_cmd_t mc;
6352 mbx_cmd_t *mcp = &mc;
6353 dma_addr_t dd_dma;
6354
6355 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
6356 !IS_QLA28XX(vha->hw))
6357 return QLA_FUNCTION_FAILED;
6358
6359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
6360 "Entered %s.\n", __func__);
6361
6362 dd_dma = dma_map_single(&vha->hw->pdev->dev,
6363 dd_buf, size, DMA_FROM_DEVICE);
6364 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
6365 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
6366 return QLA_MEMORY_ALLOC_FAILED;
6367 }
6368
6369 memset(dd_buf, 0, size);
6370
6371 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
6372 mcp->mb[1] = options;
6373 mcp->mb[2] = MSW(LSD(dd_dma));
6374 mcp->mb[3] = LSW(LSD(dd_dma));
6375 mcp->mb[6] = MSW(MSD(dd_dma));
6376 mcp->mb[7] = LSW(MSD(dd_dma));
6377 mcp->mb[8] = size;
6378 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6379 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
6380 mcp->buf_size = size;
6381 mcp->flags = MBX_DMA_IN;
6382 mcp->tov = MBX_TOV_SECONDS * 4;
6383 rval = qla2x00_mailbox_command(vha, mcp);
6384
6385 if (rval != QLA_SUCCESS) {
6386 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
6387 } else {
6388 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
6389 "Done %s.\n", __func__);
6390 }
6391
6392 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
6393 size, DMA_FROM_DEVICE);
6394
6395 return rval;
6396 }
6397
qla2x00_async_mb_sp_done(srb_t * sp,int res)6398 static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
6399 {
6400 sp->u.iocb_cmd.u.mbx.rc = res;
6401
6402 complete(&sp->u.iocb_cmd.u.mbx.comp);
6403 /* don't free sp here. Let the caller do the free */
6404 }
6405
6406 /*
6407 * This mailbox uses the iocb interface to send MB command.
6408 * This allows non-critial (non chip setup) command to go
6409 * out in parrallel.
6410 */
qla24xx_send_mb_cmd(struct scsi_qla_host * vha,mbx_cmd_t * mcp)6411 int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
6412 {
6413 int rval = QLA_FUNCTION_FAILED;
6414 srb_t *sp;
6415 struct srb_iocb *c;
6416
6417 if (!vha->hw->flags.fw_started)
6418 goto done;
6419
6420 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
6421 if (!sp)
6422 goto done;
6423
6424 sp->type = SRB_MB_IOCB;
6425 sp->name = mb_to_str(mcp->mb[0]);
6426
6427 c = &sp->u.iocb_cmd;
6428 c->timeout = qla2x00_async_iocb_timeout;
6429 init_completion(&c->u.mbx.comp);
6430
6431 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
6432
6433 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
6434
6435 sp->done = qla2x00_async_mb_sp_done;
6436
6437 rval = qla2x00_start_sp(sp);
6438 if (rval != QLA_SUCCESS) {
6439 ql_dbg(ql_dbg_mbx, vha, 0x1018,
6440 "%s: %s Failed submission. %x.\n",
6441 __func__, sp->name, rval);
6442 goto done_free_sp;
6443 }
6444
6445 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
6446 sp->name, sp->handle);
6447
6448 wait_for_completion(&c->u.mbx.comp);
6449 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
6450
6451 rval = c->u.mbx.rc;
6452 switch (rval) {
6453 case QLA_FUNCTION_TIMEOUT:
6454 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
6455 __func__, sp->name, rval);
6456 break;
6457 case QLA_SUCCESS:
6458 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
6459 __func__, sp->name);
6460 break;
6461 default:
6462 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
6463 __func__, sp->name, rval);
6464 break;
6465 }
6466
6467 done_free_sp:
6468 sp->free(sp);
6469 done:
6470 return rval;
6471 }
6472
6473 /*
6474 * qla24xx_gpdb_wait
6475 * NOTE: Do not call this routine from DPC thread
6476 */
qla24xx_gpdb_wait(struct scsi_qla_host * vha,fc_port_t * fcport,u8 opt)6477 int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
6478 {
6479 int rval = QLA_FUNCTION_FAILED;
6480 dma_addr_t pd_dma;
6481 struct port_database_24xx *pd;
6482 struct qla_hw_data *ha = vha->hw;
6483 mbx_cmd_t mc;
6484
6485 if (!vha->hw->flags.fw_started)
6486 goto done;
6487
6488 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
6489 if (pd == NULL) {
6490 ql_log(ql_log_warn, vha, 0xd047,
6491 "Failed to allocate port database structure.\n");
6492 goto done_free_sp;
6493 }
6494
6495 memset(&mc, 0, sizeof(mc));
6496 mc.mb[0] = MBC_GET_PORT_DATABASE;
6497 mc.mb[1] = fcport->loop_id;
6498 mc.mb[2] = MSW(pd_dma);
6499 mc.mb[3] = LSW(pd_dma);
6500 mc.mb[6] = MSW(MSD(pd_dma));
6501 mc.mb[7] = LSW(MSD(pd_dma));
6502 mc.mb[9] = vha->vp_idx;
6503 mc.mb[10] = opt;
6504
6505 rval = qla24xx_send_mb_cmd(vha, &mc);
6506 if (rval != QLA_SUCCESS) {
6507 ql_dbg(ql_dbg_mbx, vha, 0x1193,
6508 "%s: %8phC fail\n", __func__, fcport->port_name);
6509 goto done_free_sp;
6510 }
6511
6512 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
6513
6514 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
6515 __func__, fcport->port_name);
6516
6517 done_free_sp:
6518 if (pd)
6519 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
6520 done:
6521 return rval;
6522 }
6523
__qla24xx_parse_gpdb(struct scsi_qla_host * vha,fc_port_t * fcport,struct port_database_24xx * pd)6524 int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
6525 struct port_database_24xx *pd)
6526 {
6527 int rval = QLA_SUCCESS;
6528 uint64_t zero = 0;
6529 u8 current_login_state, last_login_state;
6530
6531 if (NVME_TARGET(vha->hw, fcport)) {
6532 current_login_state = pd->current_login_state >> 4;
6533 last_login_state = pd->last_login_state >> 4;
6534 } else {
6535 current_login_state = pd->current_login_state & 0xf;
6536 last_login_state = pd->last_login_state & 0xf;
6537 }
6538
6539 /* Check for logged in state. */
6540 if (current_login_state != PDS_PRLI_COMPLETE) {
6541 ql_dbg(ql_dbg_mbx, vha, 0x119a,
6542 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
6543 current_login_state, last_login_state, fcport->loop_id);
6544 rval = QLA_FUNCTION_FAILED;
6545 goto gpd_error_out;
6546 }
6547
6548 if (fcport->loop_id == FC_NO_LOOP_ID ||
6549 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6550 memcmp(fcport->port_name, pd->port_name, 8))) {
6551 /* We lost the device mid way. */
6552 rval = QLA_NOT_LOGGED_IN;
6553 goto gpd_error_out;
6554 }
6555
6556 /* Names are little-endian. */
6557 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6558 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6559
6560 /* Get port_id of device. */
6561 fcport->d_id.b.domain = pd->port_id[0];
6562 fcport->d_id.b.area = pd->port_id[1];
6563 fcport->d_id.b.al_pa = pd->port_id[2];
6564 fcport->d_id.b.rsvd_1 = 0;
6565
6566 if (NVME_TARGET(vha->hw, fcport)) {
6567 fcport->port_type = FCT_NVME;
6568 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
6569 fcport->port_type |= FCT_NVME_INITIATOR;
6570 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6571 fcport->port_type |= FCT_NVME_TARGET;
6572 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
6573 fcport->port_type |= FCT_NVME_DISCOVERY;
6574 } else {
6575 /* If not target must be initiator or unknown type. */
6576 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6577 fcport->port_type = FCT_INITIATOR;
6578 else
6579 fcport->port_type = FCT_TARGET;
6580 }
6581 /* Passback COS information. */
6582 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6583 FC_COS_CLASS2 : FC_COS_CLASS3;
6584
6585 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6586 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6587 fcport->conf_compl_supported = 1;
6588 }
6589
6590 gpd_error_out:
6591 return rval;
6592 }
6593
6594 /*
6595 * qla24xx_gidlist__wait
6596 * NOTE: don't call this routine from DPC thread.
6597 */
qla24xx_gidlist_wait(struct scsi_qla_host * vha,void * id_list,dma_addr_t id_list_dma,uint16_t * entries)6598 int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6599 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6600 {
6601 int rval = QLA_FUNCTION_FAILED;
6602 mbx_cmd_t mc;
6603
6604 if (!vha->hw->flags.fw_started)
6605 goto done;
6606
6607 memset(&mc, 0, sizeof(mc));
6608 mc.mb[0] = MBC_GET_ID_LIST;
6609 mc.mb[2] = MSW(id_list_dma);
6610 mc.mb[3] = LSW(id_list_dma);
6611 mc.mb[6] = MSW(MSD(id_list_dma));
6612 mc.mb[7] = LSW(MSD(id_list_dma));
6613 mc.mb[8] = 0;
6614 mc.mb[9] = vha->vp_idx;
6615
6616 rval = qla24xx_send_mb_cmd(vha, &mc);
6617 if (rval != QLA_SUCCESS) {
6618 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6619 "%s: fail\n", __func__);
6620 } else {
6621 *entries = mc.mb[1];
6622 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6623 "%s: done\n", __func__);
6624 }
6625 done:
6626 return rval;
6627 }
6628
qla27xx_set_zio_threshold(scsi_qla_host_t * vha,uint16_t value)6629 int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6630 {
6631 int rval;
6632 mbx_cmd_t mc;
6633 mbx_cmd_t *mcp = &mc;
6634
6635 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6636 "Entered %s\n", __func__);
6637
6638 memset(mcp->mb, 0 , sizeof(mcp->mb));
6639 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6640 mcp->mb[1] = 1;
6641 mcp->mb[2] = value;
6642 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6643 mcp->in_mb = MBX_2 | MBX_0;
6644 mcp->tov = MBX_TOV_SECONDS;
6645 mcp->flags = 0;
6646
6647 rval = qla2x00_mailbox_command(vha, mcp);
6648
6649 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6650 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6651
6652 return rval;
6653 }
6654
qla27xx_get_zio_threshold(scsi_qla_host_t * vha,uint16_t * value)6655 int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6656 {
6657 int rval;
6658 mbx_cmd_t mc;
6659 mbx_cmd_t *mcp = &mc;
6660
6661 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6662 "Entered %s\n", __func__);
6663
6664 memset(mcp->mb, 0, sizeof(mcp->mb));
6665 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6666 mcp->mb[1] = 0;
6667 mcp->out_mb = MBX_1 | MBX_0;
6668 mcp->in_mb = MBX_2 | MBX_0;
6669 mcp->tov = MBX_TOV_SECONDS;
6670 mcp->flags = 0;
6671
6672 rval = qla2x00_mailbox_command(vha, mcp);
6673 if (rval == QLA_SUCCESS)
6674 *value = mc.mb[2];
6675
6676 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6677 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6678
6679 return rval;
6680 }
6681
6682 int
qla2x00_read_sfp_dev(struct scsi_qla_host * vha,char * buf,int count)6683 qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
6684 {
6685 struct qla_hw_data *ha = vha->hw;
6686 uint16_t iter, addr, offset;
6687 dma_addr_t phys_addr;
6688 int rval, c;
6689 u8 *sfp_data;
6690
6691 memset(ha->sfp_data, 0, SFP_DEV_SIZE);
6692 addr = 0xa0;
6693 phys_addr = ha->sfp_data_dma;
6694 sfp_data = ha->sfp_data;
6695 offset = c = 0;
6696
6697 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
6698 if (iter == 4) {
6699 /* Skip to next device address. */
6700 addr = 0xa2;
6701 offset = 0;
6702 }
6703
6704 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
6705 addr, offset, SFP_BLOCK_SIZE, BIT_1);
6706 if (rval != QLA_SUCCESS) {
6707 ql_log(ql_log_warn, vha, 0x706d,
6708 "Unable to read SFP data (%x/%x/%x).\n", rval,
6709 addr, offset);
6710
6711 return rval;
6712 }
6713
6714 if (buf && (c < count)) {
6715 u16 sz;
6716
6717 if ((count - c) >= SFP_BLOCK_SIZE)
6718 sz = SFP_BLOCK_SIZE;
6719 else
6720 sz = count - c;
6721
6722 memcpy(buf, sfp_data, sz);
6723 buf += SFP_BLOCK_SIZE;
6724 c += sz;
6725 }
6726 phys_addr += SFP_BLOCK_SIZE;
6727 sfp_data += SFP_BLOCK_SIZE;
6728 offset += SFP_BLOCK_SIZE;
6729 }
6730
6731 return rval;
6732 }
6733
qla24xx_res_count_wait(struct scsi_qla_host * vha,uint16_t * out_mb,int out_mb_sz)6734 int qla24xx_res_count_wait(struct scsi_qla_host *vha,
6735 uint16_t *out_mb, int out_mb_sz)
6736 {
6737 int rval = QLA_FUNCTION_FAILED;
6738 mbx_cmd_t mc;
6739
6740 if (!vha->hw->flags.fw_started)
6741 goto done;
6742
6743 memset(&mc, 0, sizeof(mc));
6744 mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
6745
6746 rval = qla24xx_send_mb_cmd(vha, &mc);
6747 if (rval != QLA_SUCCESS) {
6748 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6749 "%s: fail\n", __func__);
6750 } else {
6751 if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
6752 memcpy(out_mb, mc.mb, out_mb_sz);
6753 else
6754 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
6755
6756 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6757 "%s: done\n", __func__);
6758 }
6759 done:
6760 return rval;
6761 }
6762
qla28xx_secure_flash_update(scsi_qla_host_t * vha,uint16_t opts,uint16_t region,uint32_t len,dma_addr_t sfub_dma_addr,uint32_t sfub_len)6763 int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
6764 uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
6765 uint32_t sfub_len)
6766 {
6767 int rval;
6768 mbx_cmd_t mc;
6769 mbx_cmd_t *mcp = &mc;
6770
6771 mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
6772 mcp->mb[1] = opts;
6773 mcp->mb[2] = region;
6774 mcp->mb[3] = MSW(len);
6775 mcp->mb[4] = LSW(len);
6776 mcp->mb[5] = MSW(sfub_dma_addr);
6777 mcp->mb[6] = LSW(sfub_dma_addr);
6778 mcp->mb[7] = MSW(MSD(sfub_dma_addr));
6779 mcp->mb[8] = LSW(MSD(sfub_dma_addr));
6780 mcp->mb[9] = sfub_len;
6781 mcp->out_mb =
6782 MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6783 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6784 mcp->tov = MBX_TOV_SECONDS;
6785 mcp->flags = 0;
6786 rval = qla2x00_mailbox_command(vha, mcp);
6787
6788 if (rval != QLA_SUCCESS) {
6789 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
6790 __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
6791 mcp->mb[2]);
6792 }
6793
6794 return rval;
6795 }
6796
qla2xxx_write_remote_register(scsi_qla_host_t * vha,uint32_t addr,uint32_t data)6797 int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6798 uint32_t data)
6799 {
6800 int rval;
6801 mbx_cmd_t mc;
6802 mbx_cmd_t *mcp = &mc;
6803
6804 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6805 "Entered %s.\n", __func__);
6806
6807 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6808 mcp->mb[1] = LSW(addr);
6809 mcp->mb[2] = MSW(addr);
6810 mcp->mb[3] = LSW(data);
6811 mcp->mb[4] = MSW(data);
6812 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6813 mcp->in_mb = MBX_1|MBX_0;
6814 mcp->tov = MBX_TOV_SECONDS;
6815 mcp->flags = 0;
6816 rval = qla2x00_mailbox_command(vha, mcp);
6817
6818 if (rval != QLA_SUCCESS) {
6819 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6820 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6821 } else {
6822 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6823 "Done %s.\n", __func__);
6824 }
6825
6826 return rval;
6827 }
6828
qla2xxx_read_remote_register(scsi_qla_host_t * vha,uint32_t addr,uint32_t * data)6829 int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6830 uint32_t *data)
6831 {
6832 int rval;
6833 mbx_cmd_t mc;
6834 mbx_cmd_t *mcp = &mc;
6835
6836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6837 "Entered %s.\n", __func__);
6838
6839 mcp->mb[0] = MBC_READ_REMOTE_REG;
6840 mcp->mb[1] = LSW(addr);
6841 mcp->mb[2] = MSW(addr);
6842 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6843 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6844 mcp->tov = MBX_TOV_SECONDS;
6845 mcp->flags = 0;
6846 rval = qla2x00_mailbox_command(vha, mcp);
6847
6848 *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]);
6849
6850 if (rval != QLA_SUCCESS) {
6851 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6852 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6853 } else {
6854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6855 "Done %s.\n", __func__);
6856 }
6857
6858 return rval;
6859 }
6860
6861 int
ql26xx_led_config(scsi_qla_host_t * vha,uint16_t options,uint16_t * led)6862 ql26xx_led_config(scsi_qla_host_t *vha, uint16_t options, uint16_t *led)
6863 {
6864 struct qla_hw_data *ha = vha->hw;
6865 mbx_cmd_t mc;
6866 mbx_cmd_t *mcp = &mc;
6867 int rval;
6868
6869 if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6870 return QLA_FUNCTION_FAILED;
6871
6872 ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n",
6873 __func__, options);
6874
6875 mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG;
6876 mcp->mb[1] = options;
6877 mcp->out_mb = MBX_1|MBX_0;
6878 mcp->in_mb = MBX_1|MBX_0;
6879 if (options & BIT_0) {
6880 if (options & BIT_1) {
6881 mcp->mb[2] = led[2];
6882 mcp->out_mb |= MBX_2;
6883 }
6884 if (options & BIT_2) {
6885 mcp->mb[3] = led[0];
6886 mcp->out_mb |= MBX_3;
6887 }
6888 if (options & BIT_3) {
6889 mcp->mb[4] = led[1];
6890 mcp->out_mb |= MBX_4;
6891 }
6892 } else {
6893 mcp->in_mb |= MBX_4|MBX_3|MBX_2;
6894 }
6895 mcp->tov = MBX_TOV_SECONDS;
6896 mcp->flags = 0;
6897 rval = qla2x00_mailbox_command(vha, mcp);
6898 if (rval) {
6899 ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n",
6900 __func__, rval, mcp->mb[0], mcp->mb[1]);
6901 return rval;
6902 }
6903
6904 if (options & BIT_0) {
6905 ha->beacon_blink_led = 0;
6906 ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__);
6907 } else {
6908 led[2] = mcp->mb[2];
6909 led[0] = mcp->mb[3];
6910 led[1] = mcp->mb[4];
6911 ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n",
6912 __func__, led[0], led[1], led[2]);
6913 }
6914
6915 return rval;
6916 }
6917