1 /*
2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/build_message.h>
17 #include <common/debug.h>
18 #include <context.h>
19 #include <drivers/auth/auth_mod.h>
20 #include <drivers/auth/crypto_mod.h>
21 #include <drivers/console.h>
22 #include <lib/bootmarker_capture.h>
23 #include <lib/cpus/errata.h>
24 #include <lib/el3_runtime/context_mgmt.h>
25 #include <lib/extensions/pauth.h>
26 #include <lib/pmf/pmf.h>
27 #include <lib/utils.h>
28 #include <plat/common/platform.h>
29 #include <smccc_helpers.h>
30 #include <tools_share/uuid.h>
31
32 #include "bl1_private.h"
33
34 static void bl1_load_bl2(void);
35
36 #if ENABLE_PAUTH
37 uint64_t bl1_apiakey[2];
38 #endif
39
40 #if ENABLE_RUNTIME_INSTRUMENTATION
PMF_REGISTER_SERVICE(bl_svc,PMF_RT_INSTR_SVC_ID,BL_TOTAL_IDS,PMF_DUMP_ENABLE)41 PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
42 BL_TOTAL_IDS, PMF_DUMP_ENABLE)
43 #endif
44
45 /*******************************************************************************
46 * Setup function for BL1.
47 * Also perform late architectural and platform specific initialization.
48 * It also queries the platform to load and run next BL image. Only called
49 * by the primary cpu after a cold boot.
50 ******************************************************************************/
51 void __no_pauth bl1_main(void)
52 {
53 unsigned int image_id;
54
55 /* Enable early console if EARLY_CONSOLE flag is enabled */
56 plat_setup_early_console();
57
58 /* Perform early platform-specific setup */
59 bl1_early_platform_setup();
60
61 /* Perform late platform-specific setup */
62 bl1_plat_arch_setup();
63
64 /* Init registers that don't get contexted */
65 cm_manage_extensions_el3(plat_my_core_pos());
66
67 /* When BL2 runs in Secure world, it needs a coherent context. */
68 #if !BL2_RUNS_AT_EL3
69 /* Init per-world context registers. */
70 cm_manage_extensions_per_world();
71 #endif
72
73 #if ENABLE_RUNTIME_INSTRUMENTATION
74 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT);
75 #endif
76
77 /* Announce our arrival */
78 NOTICE(FIRMWARE_WELCOME_STR);
79 NOTICE("BL1: %s\n", build_version_string);
80 NOTICE("BL1: %s\n", build_message);
81
82 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
83
84 print_errata_status();
85
86 #if ENABLE_ASSERTIONS
87 u_register_t val;
88 /*
89 * Ensure that MMU/Caches and coherency are turned on
90 */
91 #ifdef __aarch64__
92 val = read_sctlr_el3();
93 #else
94 val = read_sctlr();
95 #endif
96 assert((val & SCTLR_M_BIT) != 0);
97 assert((val & SCTLR_C_BIT) != 0);
98 assert((val & SCTLR_I_BIT) != 0);
99 /*
100 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
101 * provided platform value
102 */
103 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
104 /*
105 * If CWG is zero, then no CWG information is available but we can
106 * at least check the platform value is less than the architectural
107 * maximum.
108 */
109 if (val != 0)
110 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
111 else
112 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
113 #endif /* ENABLE_ASSERTIONS */
114
115 /* Perform remaining generic architectural setup from EL3 */
116 bl1_arch_setup();
117
118 crypto_mod_init();
119
120 /* Initialize authentication module */
121 auth_mod_init();
122
123 /* Initialize the measured boot */
124 bl1_plat_mboot_init();
125
126 if (is_feat_crypto_supported()) {
127 disable_fpregs_traps_el3();
128 }
129
130 /* Perform platform setup in BL1. */
131 bl1_platform_setup();
132
133 /* Get the image id of next image to load and run. */
134 image_id = bl1_plat_get_next_image_id();
135
136 /*
137 * We currently interpret any image id other than
138 * BL2_IMAGE_ID as the start of firmware update.
139 */
140 if (image_id == BL2_IMAGE_ID) {
141 #if ENABLE_RUNTIME_INSTRUMENTATION
142 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_AUTH_START, PMF_CACHE_MAINT);
143 #endif
144
145 bl1_load_bl2();
146
147 #if ENABLE_RUNTIME_INSTRUMENTATION
148 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_AUTH_END, PMF_CACHE_MAINT);
149 #endif
150 } else {
151 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
152 }
153
154 if (is_feat_crypto_supported()) {
155 enable_fpregs_traps_el3();
156 }
157
158 /* Teardown the measured boot driver */
159 bl1_plat_mboot_finish();
160
161 crypto_mod_finish();
162
163 bl1_prepare_next_image(image_id);
164
165 #if ENABLE_RUNTIME_INSTRUMENTATION
166 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT);
167 #endif
168
169 console_flush();
170
171 /* Disable pointer authentication before jumping to next boot image. */
172 if (is_feat_pauth_supported()) {
173 pauth_disable_el3();
174 }
175 }
176
177 /*******************************************************************************
178 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
179 * Called by the primary cpu after a cold boot.
180 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
181 * loader etc.
182 ******************************************************************************/
bl1_load_bl2(void)183 static void bl1_load_bl2(void)
184 {
185 image_desc_t *desc;
186 image_info_t *info;
187 int err;
188
189 /* Get the image descriptor */
190 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
191 assert(desc != NULL);
192
193 /* Get the image info */
194 info = &desc->image_info;
195 INFO("BL1: Loading BL2\n");
196
197 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
198 if (err != 0) {
199 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
200 plat_error_handler(err);
201 }
202
203 err = load_auth_image(BL2_IMAGE_ID, info);
204 if (err != 0) {
205 ERROR("Failed to load BL2 firmware.\n");
206 plat_error_handler(err);
207 }
208
209 /* Allow platform to handle image information. */
210 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
211 if (err != 0) {
212 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
213 plat_error_handler(err);
214 }
215
216 NOTICE("BL1: Booting BL2\n");
217 }
218
219 /*******************************************************************************
220 * Function called just before handing over to the next BL to inform the user
221 * about the boot progress. In debug mode, also print details about the BL
222 * image's execution context.
223 ******************************************************************************/
bl1_print_next_bl_ep_info(const entry_point_info_t * bl_ep_info)224 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
225 {
226 #ifdef __aarch64__
227 NOTICE("BL1: Booting BL31\n");
228 #else
229 NOTICE("BL1: Booting BL32\n");
230 #endif /* __aarch64__ */
231 print_entry_point_info(bl_ep_info);
232 }
233
234 #if SPIN_ON_BL1_EXIT
print_debug_loop_message(void)235 void print_debug_loop_message(void)
236 {
237 NOTICE("BL1: Debug loop, spinning forever\n");
238 NOTICE("BL1: Please connect the debugger to continue\n");
239 }
240 #endif
241
242 /*******************************************************************************
243 * Top level handler for servicing BL1 SMCs.
244 ******************************************************************************/
bl1_smc_handler(unsigned int smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,unsigned int flags)245 u_register_t bl1_smc_handler(unsigned int smc_fid,
246 u_register_t x1,
247 u_register_t x2,
248 u_register_t x3,
249 u_register_t x4,
250 void *cookie,
251 void *handle,
252 unsigned int flags)
253 {
254 /* BL1 Service UUID */
255 DEFINE_SVC_UUID2(bl1_svc_uid,
256 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
257 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
258
259
260 #if TRUSTED_BOARD_BOOT
261 /*
262 * Dispatch FWU calls to FWU SMC handler and return its return
263 * value
264 */
265 if (is_fwu_fid(smc_fid)) {
266 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
267 handle, flags);
268 }
269 #endif
270
271 switch (smc_fid) {
272 case BL1_SMC_CALL_COUNT:
273 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
274
275 case BL1_SMC_UID:
276 SMC_UUID_RET(handle, bl1_svc_uid);
277
278 case BL1_SMC_VERSION:
279 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
280
281 default:
282 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
283 SMC_RET1(handle, SMC_UNK);
284 }
285 }
286
287 #if __aarch64__
bl1_smc_wrapper_aarch64(cpu_context_t * ctx)288 u_register_t bl1_smc_wrapper_aarch64(cpu_context_t *ctx)
289 {
290 u_register_t x1, x2, x3, x4;
291 unsigned int smc_fid, flags;
292 gp_regs_t *gpregs = get_gpregs_ctx(ctx);
293
294 smc_fid = read_ctx_reg(gpregs, CTX_GPREG_X0);
295 x1 = read_ctx_reg(gpregs, CTX_GPREG_X1);
296 x2 = read_ctx_reg(gpregs, CTX_GPREG_X2);
297 x3 = read_ctx_reg(gpregs, CTX_GPREG_X3);
298 x4 = read_ctx_reg(gpregs, CTX_GPREG_X4);
299
300 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
301 flags = read_scr_el3() & SCR_NS_BIT;
302
303 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, NULL, ctx, flags);
304 }
305 #else
306 /*******************************************************************************
307 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
308 * compliance when invoking bl1_smc_handler.
309 ******************************************************************************/
bl1_smc_wrapper_aarch32(uint32_t smc_fid,void * cookie,void * handle,unsigned int flags)310 u_register_t bl1_smc_wrapper_aarch32(uint32_t smc_fid,
311 void *cookie,
312 void *handle,
313 unsigned int flags)
314 {
315 u_register_t x1, x2, x3, x4;
316
317 assert(handle != NULL);
318
319 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
320 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
321 }
322 #endif
323