1 /*
2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * ZynqMP system level PM-API functions for pin control.
10 */
11
12 #include <string.h>
13
14 #include <arch_helpers.h>
15 #include <plat/common/platform.h>
16
17 #include "pm_api_pinctrl.h"
18 #include "pm_client.h"
19 #include "pm_common.h"
20 #include "pm_ipi.h"
21 #include "zynqmp_pm_api_sys.h"
22
23 struct pinctrl_function {
24 char name[FUNCTION_NAME_LEN];
25 uint16_t group_base;
26 uint8_t group_size;
27 uint8_t regval;
28 };
29
30 /* Max groups for one pin */
31 #define MAX_PIN_GROUPS (13U)
32
33 struct zynqmp_pin_group {
34 uint16_t (*groups)[];
35 };
36
37 static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = {
38 [PINCTRL_FUNC_CAN0] = {
39 .name = "can0",
40 .regval = 0x20,
41 .group_base = PINCTRL_GRP_CAN0_0,
42 .group_size = PINCTRL_GRP_CAN0_18 - PINCTRL_GRP_CAN0_0 + 1U,
43 },
44 [PINCTRL_FUNC_CAN1] = {
45 .name = "can1",
46 .regval = 0x20,
47 .group_base = PINCTRL_GRP_CAN1_0,
48 .group_size = PINCTRL_GRP_CAN1_19 - PINCTRL_GRP_CAN1_0 + 1U,
49 },
50 [PINCTRL_FUNC_ETHERNET0] = {
51 .name = "ethernet0",
52 .regval = 0x02,
53 .group_base = PINCTRL_GRP_ETHERNET0_0,
54 .group_size = PINCTRL_GRP_ETHERNET0_0 - PINCTRL_GRP_ETHERNET0_0 + 1U,
55 },
56 [PINCTRL_FUNC_ETHERNET1] = {
57 .name = "ethernet1",
58 .regval = 0x02,
59 .group_base = PINCTRL_GRP_ETHERNET1_0,
60 .group_size = PINCTRL_GRP_ETHERNET1_0 - PINCTRL_GRP_ETHERNET1_0 + 1U,
61 },
62 [PINCTRL_FUNC_ETHERNET2] = {
63 .name = "ethernet2",
64 .regval = 0x02,
65 .group_base = PINCTRL_GRP_ETHERNET2_0,
66 .group_size = PINCTRL_GRP_ETHERNET2_0 - PINCTRL_GRP_ETHERNET2_0 + 1U,
67 },
68 [PINCTRL_FUNC_ETHERNET3] = {
69 .name = "ethernet3",
70 .regval = 0x02,
71 .group_base = PINCTRL_GRP_ETHERNET3_0,
72 .group_size = PINCTRL_GRP_ETHERNET3_0 - PINCTRL_GRP_ETHERNET3_0 + 1U,
73 },
74 [PINCTRL_FUNC_GEMTSU0] = {
75 .name = "gemtsu0",
76 .regval = 0x02,
77 .group_base = PINCTRL_GRP_GEMTSU0_0,
78 .group_size = PINCTRL_GRP_GEMTSU0_2 - PINCTRL_GRP_GEMTSU0_0 + 1U,
79 },
80 [PINCTRL_FUNC_GPIO0] = {
81 .name = "gpio0",
82 .regval = 0x00,
83 .group_base = PINCTRL_GRP_GPIO0_0,
84 .group_size = PINCTRL_GRP_GPIO0_77 - PINCTRL_GRP_GPIO0_0 + 1U,
85 },
86 [PINCTRL_FUNC_I2C0] = {
87 .name = "i2c0",
88 .regval = 0x40,
89 .group_base = PINCTRL_GRP_I2C0_0,
90 .group_size = PINCTRL_GRP_I2C0_18 - PINCTRL_GRP_I2C0_0 + 1U,
91 },
92 [PINCTRL_FUNC_I2C1] = {
93 .name = "i2c1",
94 .regval = 0x40,
95 .group_base = PINCTRL_GRP_I2C1_0,
96 .group_size = PINCTRL_GRP_I2C1_19 - PINCTRL_GRP_I2C1_0 + 1U,
97 },
98 [PINCTRL_FUNC_MDIO0] = {
99 .name = "mdio0",
100 .regval = 0x60,
101 .group_base = PINCTRL_GRP_MDIO0_0,
102 .group_size = PINCTRL_GRP_MDIO0_0 - PINCTRL_GRP_MDIO0_0 + 1U,
103 },
104 [PINCTRL_FUNC_MDIO1] = {
105 .name = "mdio1",
106 .regval = 0x80,
107 .group_base = PINCTRL_GRP_MDIO1_0,
108 .group_size = PINCTRL_GRP_MDIO1_1 - PINCTRL_GRP_MDIO1_0 + 1U,
109 },
110 [PINCTRL_FUNC_MDIO2] = {
111 .name = "mdio2",
112 .regval = 0xa0,
113 .group_base = PINCTRL_GRP_MDIO2_0,
114 .group_size = PINCTRL_GRP_MDIO2_0 - PINCTRL_GRP_MDIO2_0 + 1U,
115 },
116 [PINCTRL_FUNC_MDIO3] = {
117 .name = "mdio3",
118 .regval = 0xc0,
119 .group_base = PINCTRL_GRP_MDIO3_0,
120 .group_size = PINCTRL_GRP_MDIO3_0 - PINCTRL_GRP_MDIO3_0 + 1U,
121 },
122 [PINCTRL_FUNC_QSPI0] = {
123 .name = "qspi0",
124 .regval = 0x02,
125 .group_base = PINCTRL_GRP_QSPI0_0,
126 .group_size = PINCTRL_GRP_QSPI0_1 - PINCTRL_GRP_QSPI0_0 + 1U,
127 },
128 [PINCTRL_FUNC_QSPI_FBCLK] = {
129 .name = "qspi_fbclk",
130 .regval = 0x02,
131 .group_base = PINCTRL_GRP_QSPI_FBCLK,
132 .group_size = PINCTRL_GRP_QSPI_FBCLK - PINCTRL_GRP_QSPI_FBCLK + 1U,
133 },
134 [PINCTRL_FUNC_QSPI_SS] = {
135 .name = "qspi_ss",
136 .regval = 0x02,
137 .group_base = PINCTRL_GRP_QSPI_SS,
138 .group_size = PINCTRL_GRP_QSPI_SS_1 - PINCTRL_GRP_QSPI_SS + 1U,
139 },
140 [PINCTRL_FUNC_SPI0] = {
141 .name = "spi0",
142 .regval = 0x80,
143 .group_base = PINCTRL_GRP_SPI0_0,
144 .group_size = PINCTRL_GRP_SPI0_5 - PINCTRL_GRP_SPI0_0 + 1U,
145 },
146 [PINCTRL_FUNC_SPI1] = {
147 .name = "spi1",
148 .regval = 0x80,
149 .group_base = PINCTRL_GRP_SPI1_0,
150 .group_size = PINCTRL_GRP_SPI1_5 - PINCTRL_GRP_SPI1_0 + 1U,
151 },
152 [PINCTRL_FUNC_SPI0_SS] = {
153 .name = "spi0_ss",
154 .regval = 0x80,
155 .group_base = PINCTRL_GRP_SPI0_0_SS0,
156 .group_size = PINCTRL_GRP_SPI0_5_SS2 - PINCTRL_GRP_SPI0_0_SS0 + 1U,
157 },
158 [PINCTRL_FUNC_SPI1_SS] = {
159 .name = "spi1_ss",
160 .regval = 0x80,
161 .group_base = PINCTRL_GRP_SPI1_0_SS0,
162 .group_size = PINCTRL_GRP_SPI1_5_SS2 - PINCTRL_GRP_SPI1_0_SS0 + 1U,
163 },
164 [PINCTRL_FUNC_SDIO0] = {
165 .name = "sdio0",
166 .regval = 0x08,
167 .group_base = PINCTRL_GRP_SDIO0_0,
168 .group_size = PINCTRL_GRP_SDIO0_1BIT_2_7 - PINCTRL_GRP_SDIO0_0 + 1U,
169 },
170 [PINCTRL_FUNC_SDIO0_PC] = {
171 .name = "sdio0_pc",
172 .regval = 0x08,
173 .group_base = PINCTRL_GRP_SDIO0_0_PC,
174 .group_size = PINCTRL_GRP_SDIO0_2_PC - PINCTRL_GRP_SDIO0_0_PC + 1U,
175 },
176 [PINCTRL_FUNC_SDIO0_CD] = {
177 .name = "sdio0_cd",
178 .regval = 0x08,
179 .group_base = PINCTRL_GRP_SDIO0_0_CD,
180 .group_size = PINCTRL_GRP_SDIO0_2_CD - PINCTRL_GRP_SDIO0_0_CD + 1U,
181 },
182 [PINCTRL_FUNC_SDIO0_WP] = {
183 .name = "sdio0_wp",
184 .regval = 0x08,
185 .group_base = PINCTRL_GRP_SDIO0_0_WP,
186 .group_size = PINCTRL_GRP_SDIO0_2_WP - PINCTRL_GRP_SDIO0_0_WP + 1U,
187 },
188 [PINCTRL_FUNC_SDIO1] = {
189 .name = "sdio1",
190 .regval = 0x10,
191 .group_base = PINCTRL_GRP_SDIO1_0,
192 .group_size = PINCTRL_GRP_SDIO1_1BIT_1_3 - PINCTRL_GRP_SDIO1_0 + 1U,
193 },
194 [PINCTRL_FUNC_SDIO1_PC] = {
195 .name = "sdio1_pc",
196 .regval = 0x10,
197 .group_base = PINCTRL_GRP_SDIO1_0_PC,
198 .group_size = PINCTRL_GRP_SDIO1_1_PC - PINCTRL_GRP_SDIO1_0_PC + 1U,
199 },
200 [PINCTRL_FUNC_SDIO1_CD] = {
201 .name = "sdio1_cd",
202 .regval = 0x10,
203 .group_base = PINCTRL_GRP_SDIO1_0_CD,
204 .group_size = PINCTRL_GRP_SDIO1_1_CD - PINCTRL_GRP_SDIO1_0_CD + 1U,
205 },
206 [PINCTRL_FUNC_SDIO1_WP] = {
207 .name = "sdio1_wp",
208 .regval = 0x10,
209 .group_base = PINCTRL_GRP_SDIO1_0_WP,
210 .group_size = PINCTRL_GRP_SDIO1_1_WP - PINCTRL_GRP_SDIO1_0_WP + 1U,
211 },
212 [PINCTRL_FUNC_NAND0] = {
213 .name = "nand0",
214 .regval = 0x04,
215 .group_base = PINCTRL_GRP_NAND0_0,
216 .group_size = PINCTRL_GRP_NAND0_0 - PINCTRL_GRP_NAND0_0 + 1U,
217 },
218 [PINCTRL_FUNC_NAND0_CE] = {
219 .name = "nand0_ce",
220 .regval = 0x04,
221 .group_base = PINCTRL_GRP_NAND0_0_CE,
222 .group_size = PINCTRL_GRP_NAND0_1_CE - PINCTRL_GRP_NAND0_0_CE + 1U,
223 },
224 [PINCTRL_FUNC_NAND0_RB] = {
225 .name = "nand0_rb",
226 .regval = 0x04,
227 .group_base = PINCTRL_GRP_NAND0_0_RB,
228 .group_size = PINCTRL_GRP_NAND0_1_RB - PINCTRL_GRP_NAND0_0_RB + 1U,
229 },
230 [PINCTRL_FUNC_NAND0_DQS] = {
231 .name = "nand0_dqs",
232 .regval = 0x04,
233 .group_base = PINCTRL_GRP_NAND0_0_DQS,
234 .group_size = PINCTRL_GRP_NAND0_1_DQS - PINCTRL_GRP_NAND0_0_DQS + 1U,
235 },
236 [PINCTRL_FUNC_TTC0_CLK] = {
237 .name = "ttc0_clk",
238 .regval = 0xa0,
239 .group_base = PINCTRL_GRP_TTC0_0_CLK,
240 .group_size = PINCTRL_GRP_TTC0_8_CLK - PINCTRL_GRP_TTC0_0_CLK + 1U,
241 },
242 [PINCTRL_FUNC_TTC0_WAV] = {
243 .name = "ttc0_wav",
244 .regval = 0xa0,
245 .group_base = PINCTRL_GRP_TTC0_0_WAV,
246 .group_size = PINCTRL_GRP_TTC0_8_WAV - PINCTRL_GRP_TTC0_0_WAV + 1U,
247 },
248 [PINCTRL_FUNC_TTC1_CLK] = {
249 .name = "ttc1_clk",
250 .regval = 0xa0,
251 .group_base = PINCTRL_GRP_TTC1_0_CLK,
252 .group_size = PINCTRL_GRP_TTC1_8_CLK - PINCTRL_GRP_TTC1_0_CLK + 1U,
253 },
254 [PINCTRL_FUNC_TTC1_WAV] = {
255 .name = "ttc1_wav",
256 .regval = 0xa0,
257 .group_base = PINCTRL_GRP_TTC1_0_WAV,
258 .group_size = PINCTRL_GRP_TTC1_8_WAV - PINCTRL_GRP_TTC1_0_WAV + 1U,
259 },
260 [PINCTRL_FUNC_TTC2_CLK] = {
261 .name = "ttc2_clk",
262 .regval = 0xa0,
263 .group_base = PINCTRL_GRP_TTC2_0_CLK,
264 .group_size = PINCTRL_GRP_TTC2_8_CLK - PINCTRL_GRP_TTC2_0_CLK + 1U,
265 },
266 [PINCTRL_FUNC_TTC2_WAV] = {
267 .name = "ttc2_wav",
268 .regval = 0xa0,
269 .group_base = PINCTRL_GRP_TTC2_0_WAV,
270 .group_size = PINCTRL_GRP_TTC2_8_WAV - PINCTRL_GRP_TTC2_0_WAV + 1U,
271 },
272 [PINCTRL_FUNC_TTC3_CLK] = {
273 .name = "ttc3_clk",
274 .regval = 0xa0,
275 .group_base = PINCTRL_GRP_TTC3_0_CLK,
276 .group_size = PINCTRL_GRP_TTC3_8_CLK - PINCTRL_GRP_TTC3_0_CLK + 1U,
277 },
278 [PINCTRL_FUNC_TTC3_WAV] = {
279 .name = "ttc3_wav",
280 .regval = 0xa0,
281 .group_base = PINCTRL_GRP_TTC3_0_WAV,
282 .group_size = PINCTRL_GRP_TTC3_8_WAV - PINCTRL_GRP_TTC3_0_WAV + 1U,
283 },
284 [PINCTRL_FUNC_UART0] = {
285 .name = "uart0",
286 .regval = 0xc0,
287 .group_base = PINCTRL_GRP_UART0_0,
288 .group_size = PINCTRL_GRP_UART0_18 - PINCTRL_GRP_UART0_0 + 1U,
289 },
290 [PINCTRL_FUNC_UART1] = {
291 .name = "uart1",
292 .regval = 0xc0,
293 .group_base = PINCTRL_GRP_UART1_0,
294 .group_size = PINCTRL_GRP_UART1_18 - PINCTRL_GRP_UART1_0 + 1U,
295 },
296 [PINCTRL_FUNC_USB0] = {
297 .name = "usb0",
298 .regval = 0x04,
299 .group_base = PINCTRL_GRP_USB0_0,
300 .group_size = PINCTRL_GRP_USB0_0 - PINCTRL_GRP_USB0_0 + 1U,
301 },
302 [PINCTRL_FUNC_USB1] = {
303 .name = "usb1",
304 .regval = 0x04,
305 .group_base = PINCTRL_GRP_USB1_0,
306 .group_size = PINCTRL_GRP_USB1_0 - PINCTRL_GRP_USB1_0 + 1U,
307 },
308 [PINCTRL_FUNC_SWDT0_CLK] = {
309 .name = "swdt0_clk",
310 .regval = 0x60,
311 .group_base = PINCTRL_GRP_SWDT0_0_CLK,
312 .group_size = PINCTRL_GRP_SWDT0_12_CLK - PINCTRL_GRP_SWDT0_0_CLK + 1U,
313 },
314 [PINCTRL_FUNC_SWDT0_RST] = {
315 .name = "swdt0_rst",
316 .regval = 0x60,
317 .group_base = PINCTRL_GRP_SWDT0_0_RST,
318 .group_size = PINCTRL_GRP_SWDT0_12_RST - PINCTRL_GRP_SWDT0_0_RST + 1U,
319 },
320 [PINCTRL_FUNC_SWDT1_CLK] = {
321 .name = "swdt1_clk",
322 .regval = 0x60,
323 .group_base = PINCTRL_GRP_SWDT1_0_CLK,
324 .group_size = PINCTRL_GRP_SWDT1_12_CLK - PINCTRL_GRP_SWDT1_0_CLK + 1U,
325 },
326 [PINCTRL_FUNC_SWDT1_RST] = {
327 .name = "swdt1_rst",
328 .regval = 0x60,
329 .group_base = PINCTRL_GRP_SWDT1_0_RST,
330 .group_size = PINCTRL_GRP_SWDT1_12_RST - PINCTRL_GRP_SWDT1_0_RST + 1U,
331 },
332 [PINCTRL_FUNC_PMU0] = {
333 .name = "pmu0",
334 .regval = 0x08,
335 .group_base = PINCTRL_GRP_PMU0_0,
336 .group_size = PINCTRL_GRP_PMU0_11 - PINCTRL_GRP_PMU0_0 + 1U,
337 },
338 [PINCTRL_FUNC_PCIE0] = {
339 .name = "pcie0",
340 .regval = 0x04,
341 .group_base = PINCTRL_GRP_PCIE0_0,
342 .group_size = PINCTRL_GRP_PCIE0_7 - PINCTRL_GRP_PCIE0_0 + 1U,
343 },
344 [PINCTRL_FUNC_CSU0] = {
345 .name = "csu0",
346 .regval = 0x18,
347 .group_base = PINCTRL_GRP_CSU0_0,
348 .group_size = PINCTRL_GRP_CSU0_11 - PINCTRL_GRP_CSU0_0 + 1U,
349 },
350 [PINCTRL_FUNC_DPAUX0] = {
351 .name = "dpaux0",
352 .regval = 0x18,
353 .group_base = PINCTRL_GRP_DPAUX0_0,
354 .group_size = PINCTRL_GRP_DPAUX0_3 - PINCTRL_GRP_DPAUX0_0 + 1U,
355 },
356 [PINCTRL_FUNC_PJTAG0] = {
357 .name = "pjtag0",
358 .regval = 0x60,
359 .group_base = PINCTRL_GRP_PJTAG0_0,
360 .group_size = PINCTRL_GRP_PJTAG0_5 - PINCTRL_GRP_PJTAG0_0 + 1U,
361 },
362 [PINCTRL_FUNC_TRACE0] = {
363 .name = "trace0",
364 .regval = 0xe0,
365 .group_base = PINCTRL_GRP_TRACE0_0,
366 .group_size = PINCTRL_GRP_TRACE0_2 - PINCTRL_GRP_TRACE0_0 + 1U,
367 },
368 [PINCTRL_FUNC_TRACE0_CLK] = {
369 .name = "trace0_clk",
370 .regval = 0xe0,
371 .group_base = PINCTRL_GRP_TRACE0_0_CLK,
372 .group_size = PINCTRL_GRP_TRACE0_2_CLK - PINCTRL_GRP_TRACE0_0_CLK + 1U,
373 },
374 [PINCTRL_FUNC_TESTSCAN0] = {
375 .name = "testscan0",
376 .regval = 0x10,
377 .group_base = PINCTRL_GRP_TESTSCAN0_0,
378 .group_size = PINCTRL_GRP_TESTSCAN0_0 - PINCTRL_GRP_TESTSCAN0_0 + 1U,
379 },
380 };
381
382 static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
383 [PINCTRL_PIN_0] = {
384 .groups = &((uint16_t []) {
385 PINCTRL_GRP_QSPI0_0,
386 PINCTRL_GRP_QSPI0_1,
387 PINCTRL_GRP_RESERVED,
388 PINCTRL_GRP_RESERVED,
389 PINCTRL_GRP_TESTSCAN0_0,
390 PINCTRL_GRP_RESERVED,
391 PINCTRL_GRP_GPIO0_0,
392 PINCTRL_GRP_CAN1_0,
393 PINCTRL_GRP_I2C1_0,
394 PINCTRL_GRP_PJTAG0_0,
395 PINCTRL_GRP_SPI0_0,
396 PINCTRL_GRP_TTC3_0_CLK,
397 PINCTRL_GRP_UART1_0,
398 PINCTRL_GRP_TRACE0_0_CLK,
399 END_OF_GROUPS,
400 }),
401 },
402 [PINCTRL_PIN_1] = {
403 .groups = &((uint16_t []) {
404 PINCTRL_GRP_QSPI0_0,
405 PINCTRL_GRP_QSPI0_1,
406 PINCTRL_GRP_RESERVED,
407 PINCTRL_GRP_RESERVED,
408 PINCTRL_GRP_TESTSCAN0_0,
409 PINCTRL_GRP_RESERVED,
410 PINCTRL_GRP_GPIO0_1,
411 PINCTRL_GRP_CAN1_0,
412 PINCTRL_GRP_I2C1_0,
413 PINCTRL_GRP_PJTAG0_0,
414 PINCTRL_GRP_SPI0_0_SS2,
415 PINCTRL_GRP_TTC3_0_WAV,
416 PINCTRL_GRP_UART1_0,
417 PINCTRL_GRP_TRACE0_0_CLK,
418 END_OF_GROUPS,
419 }),
420 },
421 [PINCTRL_PIN_2] = {
422 .groups = &((uint16_t []) {
423 PINCTRL_GRP_QSPI0_0,
424 PINCTRL_GRP_QSPI0_1,
425 PINCTRL_GRP_RESERVED,
426 PINCTRL_GRP_RESERVED,
427 PINCTRL_GRP_TESTSCAN0_0,
428 PINCTRL_GRP_RESERVED,
429 PINCTRL_GRP_GPIO0_2,
430 PINCTRL_GRP_CAN0_0,
431 PINCTRL_GRP_I2C0_0,
432 PINCTRL_GRP_PJTAG0_0,
433 PINCTRL_GRP_SPI0_0_SS1,
434 PINCTRL_GRP_TTC2_0_CLK,
435 PINCTRL_GRP_UART0_0,
436 PINCTRL_GRP_TRACE0_0,
437 END_OF_GROUPS,
438 }),
439 },
440 [PINCTRL_PIN_3] = {
441 .groups = &((uint16_t []) {
442 PINCTRL_GRP_QSPI0_0,
443 PINCTRL_GRP_QSPI0_1,
444 PINCTRL_GRP_RESERVED,
445 PINCTRL_GRP_RESERVED,
446 PINCTRL_GRP_TESTSCAN0_0,
447 PINCTRL_GRP_RESERVED,
448 PINCTRL_GRP_GPIO0_3,
449 PINCTRL_GRP_CAN0_0,
450 PINCTRL_GRP_I2C0_0,
451 PINCTRL_GRP_PJTAG0_0,
452 PINCTRL_GRP_SPI0_0_SS0,
453 PINCTRL_GRP_TTC2_0_WAV,
454 PINCTRL_GRP_UART0_0,
455 PINCTRL_GRP_TRACE0_0,
456 END_OF_GROUPS,
457 }),
458 },
459 [PINCTRL_PIN_4] = {
460 .groups = &((uint16_t []) {
461 PINCTRL_GRP_QSPI0_0,
462 PINCTRL_GRP_QSPI0_1,
463 PINCTRL_GRP_RESERVED,
464 PINCTRL_GRP_RESERVED,
465 PINCTRL_GRP_TESTSCAN0_0,
466 PINCTRL_GRP_RESERVED,
467 PINCTRL_GRP_GPIO0_4,
468 PINCTRL_GRP_CAN1_1,
469 PINCTRL_GRP_I2C1_1,
470 PINCTRL_GRP_SWDT1_0_CLK,
471 PINCTRL_GRP_SPI0_0,
472 PINCTRL_GRP_TTC1_0_CLK,
473 PINCTRL_GRP_UART1_1,
474 PINCTRL_GRP_TRACE0_0,
475 END_OF_GROUPS,
476 }),
477 },
478 [PINCTRL_PIN_5] = {
479 .groups = &((uint16_t []) {
480 PINCTRL_GRP_QSPI_SS,
481 PINCTRL_GRP_QSPI_SS_1,
482 PINCTRL_GRP_RESERVED,
483 PINCTRL_GRP_RESERVED,
484 PINCTRL_GRP_TESTSCAN0_0,
485 PINCTRL_GRP_RESERVED,
486 PINCTRL_GRP_GPIO0_5,
487 PINCTRL_GRP_CAN1_1,
488 PINCTRL_GRP_I2C1_1,
489 PINCTRL_GRP_SWDT1_0_RST,
490 PINCTRL_GRP_SPI0_0,
491 PINCTRL_GRP_TTC1_0_WAV,
492 PINCTRL_GRP_UART1_1,
493 PINCTRL_GRP_TRACE0_0,
494 END_OF_GROUPS,
495 }),
496 },
497 [PINCTRL_PIN_6] = {
498 .groups = &((uint16_t []) {
499 PINCTRL_GRP_QSPI_FBCLK,
500 PINCTRL_GRP_RESERVED,
501 PINCTRL_GRP_RESERVED,
502 PINCTRL_GRP_TESTSCAN0_0,
503 PINCTRL_GRP_RESERVED,
504 PINCTRL_GRP_GPIO0_6,
505 PINCTRL_GRP_CAN0_1,
506 PINCTRL_GRP_I2C0_1,
507 PINCTRL_GRP_SWDT0_0_CLK,
508 PINCTRL_GRP_SPI1_0,
509 PINCTRL_GRP_TTC0_0_CLK,
510 PINCTRL_GRP_UART0_1,
511 PINCTRL_GRP_TRACE0_0,
512 END_OF_GROUPS,
513 }),
514 },
515 [PINCTRL_PIN_7] = {
516 .groups = &((uint16_t []) {
517 PINCTRL_GRP_QSPI_SS,
518 PINCTRL_GRP_RESERVED,
519 PINCTRL_GRP_RESERVED,
520 PINCTRL_GRP_TESTSCAN0_0,
521 PINCTRL_GRP_RESERVED,
522 PINCTRL_GRP_GPIO0_7,
523 PINCTRL_GRP_CAN0_1,
524 PINCTRL_GRP_I2C0_1,
525 PINCTRL_GRP_SWDT0_0_RST,
526 PINCTRL_GRP_SPI1_0_SS2,
527 PINCTRL_GRP_TTC0_0_WAV,
528 PINCTRL_GRP_UART0_1,
529 PINCTRL_GRP_TRACE0_0,
530 END_OF_GROUPS,
531 }),
532 },
533 [PINCTRL_PIN_8] = {
534 .groups = &((uint16_t []) {
535 PINCTRL_GRP_QSPI0_0,
536 PINCTRL_GRP_RESERVED,
537 PINCTRL_GRP_RESERVED,
538 PINCTRL_GRP_TESTSCAN0_0,
539 PINCTRL_GRP_RESERVED,
540 PINCTRL_GRP_GPIO0_8,
541 PINCTRL_GRP_CAN1_2,
542 PINCTRL_GRP_I2C1_2,
543 PINCTRL_GRP_SWDT1_1_CLK,
544 PINCTRL_GRP_SPI1_0_SS1,
545 PINCTRL_GRP_TTC3_1_CLK,
546 PINCTRL_GRP_UART1_2,
547 PINCTRL_GRP_TRACE0_0,
548 END_OF_GROUPS,
549 }),
550 },
551 [PINCTRL_PIN_9] = {
552 .groups = &((uint16_t []) {
553 PINCTRL_GRP_QSPI0_0,
554 PINCTRL_GRP_NAND0_0_CE,
555 PINCTRL_GRP_RESERVED,
556 PINCTRL_GRP_TESTSCAN0_0,
557 PINCTRL_GRP_RESERVED,
558 PINCTRL_GRP_GPIO0_9,
559 PINCTRL_GRP_CAN1_2,
560 PINCTRL_GRP_I2C1_2,
561 PINCTRL_GRP_SWDT1_1_RST,
562 PINCTRL_GRP_SPI1_0_SS0,
563 PINCTRL_GRP_TTC3_1_WAV,
564 PINCTRL_GRP_UART1_2,
565 PINCTRL_GRP_TRACE0_0,
566 END_OF_GROUPS,
567 }),
568 },
569 [PINCTRL_PIN_10] = {
570 .groups = &((uint16_t []) {
571 PINCTRL_GRP_QSPI0_0,
572 PINCTRL_GRP_NAND0_0_RB,
573 PINCTRL_GRP_RESERVED,
574 PINCTRL_GRP_TESTSCAN0_0,
575 PINCTRL_GRP_RESERVED,
576 PINCTRL_GRP_GPIO0_10,
577 PINCTRL_GRP_CAN0_2,
578 PINCTRL_GRP_I2C0_2,
579 PINCTRL_GRP_SWDT0_1_CLK,
580 PINCTRL_GRP_SPI1_0,
581 PINCTRL_GRP_TTC2_1_CLK,
582 PINCTRL_GRP_UART0_2,
583 PINCTRL_GRP_TRACE0_0,
584 END_OF_GROUPS,
585 }),
586 },
587 [PINCTRL_PIN_11] = {
588 .groups = &((uint16_t []) {
589 PINCTRL_GRP_QSPI0_0,
590 PINCTRL_GRP_NAND0_0_RB,
591 PINCTRL_GRP_RESERVED,
592 PINCTRL_GRP_TESTSCAN0_0,
593 PINCTRL_GRP_RESERVED,
594 PINCTRL_GRP_GPIO0_11,
595 PINCTRL_GRP_CAN0_2,
596 PINCTRL_GRP_I2C0_2,
597 PINCTRL_GRP_SWDT0_1_RST,
598 PINCTRL_GRP_SPI1_0,
599 PINCTRL_GRP_TTC2_1_WAV,
600 PINCTRL_GRP_UART0_2,
601 PINCTRL_GRP_TRACE0_0,
602 END_OF_GROUPS,
603 }),
604 },
605 [PINCTRL_PIN_12] = {
606 .groups = &((uint16_t []) {
607 PINCTRL_GRP_QSPI0_0,
608 PINCTRL_GRP_NAND0_0_DQS,
609 PINCTRL_GRP_RESERVED,
610 PINCTRL_GRP_TESTSCAN0_0,
611 PINCTRL_GRP_RESERVED,
612 PINCTRL_GRP_GPIO0_12,
613 PINCTRL_GRP_CAN1_3,
614 PINCTRL_GRP_I2C1_3,
615 PINCTRL_GRP_PJTAG0_1,
616 PINCTRL_GRP_SPI0_1,
617 PINCTRL_GRP_TTC1_1_CLK,
618 PINCTRL_GRP_UART1_3,
619 PINCTRL_GRP_TRACE0_0,
620 END_OF_GROUPS,
621 }),
622 },
623 [PINCTRL_PIN_13] = {
624 .groups = &((uint16_t []) {
625 PINCTRL_GRP_RESERVED,
626 PINCTRL_GRP_NAND0_0,
627 PINCTRL_GRP_SDIO0_0,
628 PINCTRL_GRP_TESTSCAN0_0,
629 PINCTRL_GRP_RESERVED,
630 PINCTRL_GRP_GPIO0_13,
631 PINCTRL_GRP_CAN1_3,
632 PINCTRL_GRP_I2C1_3,
633 PINCTRL_GRP_PJTAG0_1,
634 PINCTRL_GRP_SPI0_1_SS2,
635 PINCTRL_GRP_TTC1_1_WAV,
636 PINCTRL_GRP_UART1_3,
637 PINCTRL_GRP_TRACE0_0,
638 PINCTRL_GRP_SDIO0_4BIT_0_0,
639 PINCTRL_GRP_SDIO0_1BIT_0_0,
640 END_OF_GROUPS,
641 }),
642 },
643 [PINCTRL_PIN_14] = {
644 .groups = &((uint16_t []) {
645 PINCTRL_GRP_RESERVED,
646 PINCTRL_GRP_NAND0_0,
647 PINCTRL_GRP_SDIO0_0,
648 PINCTRL_GRP_TESTSCAN0_0,
649 PINCTRL_GRP_RESERVED,
650 PINCTRL_GRP_GPIO0_14,
651 PINCTRL_GRP_CAN0_3,
652 PINCTRL_GRP_I2C0_3,
653 PINCTRL_GRP_PJTAG0_1,
654 PINCTRL_GRP_SPI0_1_SS1,
655 PINCTRL_GRP_TTC0_1_CLK,
656 PINCTRL_GRP_UART0_3,
657 PINCTRL_GRP_TRACE0_0,
658 PINCTRL_GRP_SDIO0_4BIT_0_0,
659 PINCTRL_GRP_SDIO0_1BIT_0_1,
660 END_OF_GROUPS,
661 }),
662 },
663 [PINCTRL_PIN_15] = {
664 .groups = &((uint16_t []) {
665 PINCTRL_GRP_RESERVED,
666 PINCTRL_GRP_NAND0_0,
667 PINCTRL_GRP_SDIO0_0,
668 PINCTRL_GRP_TESTSCAN0_0,
669 PINCTRL_GRP_RESERVED,
670 PINCTRL_GRP_GPIO0_15,
671 PINCTRL_GRP_CAN0_3,
672 PINCTRL_GRP_I2C0_3,
673 PINCTRL_GRP_PJTAG0_1,
674 PINCTRL_GRP_SPI0_1_SS0,
675 PINCTRL_GRP_TTC0_1_WAV,
676 PINCTRL_GRP_UART0_3,
677 PINCTRL_GRP_TRACE0_0,
678 PINCTRL_GRP_SDIO0_4BIT_0_0,
679 PINCTRL_GRP_SDIO0_1BIT_0_2,
680 END_OF_GROUPS,
681 }),
682 },
683 [PINCTRL_PIN_16] = {
684 .groups = &((uint16_t []) {
685 PINCTRL_GRP_RESERVED,
686 PINCTRL_GRP_NAND0_0,
687 PINCTRL_GRP_SDIO0_0,
688 PINCTRL_GRP_TESTSCAN0_0,
689 PINCTRL_GRP_RESERVED,
690 PINCTRL_GRP_GPIO0_16,
691 PINCTRL_GRP_CAN1_4,
692 PINCTRL_GRP_I2C1_4,
693 PINCTRL_GRP_SWDT1_2_CLK,
694 PINCTRL_GRP_SPI0_1,
695 PINCTRL_GRP_TTC3_2_CLK,
696 PINCTRL_GRP_UART1_4,
697 PINCTRL_GRP_TRACE0_0,
698 PINCTRL_GRP_SDIO0_4BIT_0_0,
699 PINCTRL_GRP_SDIO0_1BIT_0_3,
700 END_OF_GROUPS,
701 }),
702 },
703 [PINCTRL_PIN_17] = {
704 .groups = &((uint16_t []) {
705 PINCTRL_GRP_RESERVED,
706 PINCTRL_GRP_NAND0_0,
707 PINCTRL_GRP_SDIO0_0,
708 PINCTRL_GRP_TESTSCAN0_0,
709 PINCTRL_GRP_RESERVED,
710 PINCTRL_GRP_GPIO0_17,
711 PINCTRL_GRP_CAN1_4,
712 PINCTRL_GRP_I2C1_4,
713 PINCTRL_GRP_SWDT1_2_RST,
714 PINCTRL_GRP_SPI0_1,
715 PINCTRL_GRP_TTC3_2_WAV,
716 PINCTRL_GRP_UART1_4,
717 PINCTRL_GRP_TRACE0_0,
718 PINCTRL_GRP_SDIO0_4BIT_0_1,
719 PINCTRL_GRP_SDIO0_1BIT_0_4,
720 END_OF_GROUPS,
721 }),
722 },
723 [PINCTRL_PIN_18] = {
724 .groups = &((uint16_t []) {
725 PINCTRL_GRP_RESERVED,
726 PINCTRL_GRP_NAND0_0,
727 PINCTRL_GRP_SDIO0_0,
728 PINCTRL_GRP_TESTSCAN0_0,
729 PINCTRL_GRP_CSU0_0,
730 PINCTRL_GRP_GPIO0_18,
731 PINCTRL_GRP_CAN0_4,
732 PINCTRL_GRP_I2C0_4,
733 PINCTRL_GRP_SWDT0_2_CLK,
734 PINCTRL_GRP_SPI1_1,
735 PINCTRL_GRP_TTC2_2_CLK,
736 PINCTRL_GRP_UART0_4,
737 PINCTRL_GRP_RESERVED,
738 PINCTRL_GRP_SDIO0_4BIT_0_1,
739 PINCTRL_GRP_SDIO0_1BIT_0_5,
740 END_OF_GROUPS,
741 }),
742 },
743 [PINCTRL_PIN_19] = {
744 .groups = &((uint16_t []) {
745 PINCTRL_GRP_RESERVED,
746 PINCTRL_GRP_NAND0_0,
747 PINCTRL_GRP_SDIO0_0,
748 PINCTRL_GRP_TESTSCAN0_0,
749 PINCTRL_GRP_CSU0_1,
750 PINCTRL_GRP_GPIO0_19,
751 PINCTRL_GRP_CAN0_4,
752 PINCTRL_GRP_I2C0_4,
753 PINCTRL_GRP_SWDT0_2_RST,
754 PINCTRL_GRP_SPI1_1_SS2,
755 PINCTRL_GRP_TTC2_2_WAV,
756 PINCTRL_GRP_UART0_4,
757 PINCTRL_GRP_RESERVED,
758 PINCTRL_GRP_SDIO0_4BIT_0_1,
759 PINCTRL_GRP_SDIO0_1BIT_0_6,
760 END_OF_GROUPS,
761 }),
762 },
763 [PINCTRL_PIN_20] = {
764 .groups = &((uint16_t []) {
765 PINCTRL_GRP_RESERVED,
766 PINCTRL_GRP_NAND0_0,
767 PINCTRL_GRP_SDIO0_0,
768 PINCTRL_GRP_TESTSCAN0_0,
769 PINCTRL_GRP_CSU0_2,
770 PINCTRL_GRP_GPIO0_20,
771 PINCTRL_GRP_CAN1_5,
772 PINCTRL_GRP_I2C1_5,
773 PINCTRL_GRP_SWDT1_3_CLK,
774 PINCTRL_GRP_SPI1_1_SS1,
775 PINCTRL_GRP_TTC1_2_CLK,
776 PINCTRL_GRP_UART1_5,
777 PINCTRL_GRP_RESERVED,
778 PINCTRL_GRP_SDIO0_4BIT_0_1,
779 PINCTRL_GRP_SDIO0_1BIT_0_7,
780 END_OF_GROUPS,
781 }),
782 },
783 [PINCTRL_PIN_21] = {
784 .groups = &((uint16_t []) {
785 PINCTRL_GRP_RESERVED,
786 PINCTRL_GRP_NAND0_0,
787 PINCTRL_GRP_SDIO0_0,
788 PINCTRL_GRP_TESTSCAN0_0,
789 PINCTRL_GRP_CSU0_3,
790 PINCTRL_GRP_GPIO0_21,
791 PINCTRL_GRP_CAN1_5,
792 PINCTRL_GRP_I2C1_5,
793 PINCTRL_GRP_SWDT1_3_RST,
794 PINCTRL_GRP_SPI1_1_SS0,
795 PINCTRL_GRP_TTC1_2_WAV,
796 PINCTRL_GRP_UART1_5,
797 PINCTRL_GRP_RESERVED,
798 PINCTRL_GRP_SDIO0_4BIT_0_0,
799 PINCTRL_GRP_SDIO0_4BIT_0_1,
800 PINCTRL_GRP_SDIO0_1BIT_0_0,
801 PINCTRL_GRP_SDIO0_1BIT_0_1,
802 PINCTRL_GRP_SDIO0_1BIT_0_2,
803 PINCTRL_GRP_SDIO0_1BIT_0_3,
804 PINCTRL_GRP_SDIO0_1BIT_0_4,
805 PINCTRL_GRP_SDIO0_1BIT_0_5,
806 PINCTRL_GRP_SDIO0_1BIT_0_6,
807 PINCTRL_GRP_SDIO0_1BIT_0_7,
808 END_OF_GROUPS,
809 }),
810 },
811 [PINCTRL_PIN_22] = {
812 .groups = &((uint16_t []) {
813 PINCTRL_GRP_RESERVED,
814 PINCTRL_GRP_NAND0_0,
815 PINCTRL_GRP_SDIO0_0,
816 PINCTRL_GRP_TESTSCAN0_0,
817 PINCTRL_GRP_CSU0_4,
818 PINCTRL_GRP_GPIO0_22,
819 PINCTRL_GRP_CAN0_5,
820 PINCTRL_GRP_I2C0_5,
821 PINCTRL_GRP_SWDT0_3_CLK,
822 PINCTRL_GRP_SPI1_1,
823 PINCTRL_GRP_TTC0_2_CLK,
824 PINCTRL_GRP_UART0_5,
825 PINCTRL_GRP_RESERVED,
826 PINCTRL_GRP_SDIO0_4BIT_0_0,
827 PINCTRL_GRP_SDIO0_4BIT_0_1,
828 PINCTRL_GRP_SDIO0_1BIT_0_0,
829 PINCTRL_GRP_SDIO0_1BIT_0_1,
830 PINCTRL_GRP_SDIO0_1BIT_0_2,
831 PINCTRL_GRP_SDIO0_1BIT_0_3,
832 PINCTRL_GRP_SDIO0_1BIT_0_4,
833 PINCTRL_GRP_SDIO0_1BIT_0_5,
834 PINCTRL_GRP_SDIO0_1BIT_0_6,
835 PINCTRL_GRP_SDIO0_1BIT_0_7,
836 END_OF_GROUPS,
837 }),
838 },
839 [PINCTRL_PIN_23] = {
840 .groups = &((uint16_t []) {
841 PINCTRL_GRP_RESERVED,
842 PINCTRL_GRP_NAND0_0,
843 PINCTRL_GRP_SDIO0_0_PC,
844 PINCTRL_GRP_TESTSCAN0_0,
845 PINCTRL_GRP_CSU0_5,
846 PINCTRL_GRP_GPIO0_23,
847 PINCTRL_GRP_CAN0_5,
848 PINCTRL_GRP_I2C0_5,
849 PINCTRL_GRP_SWDT0_3_RST,
850 PINCTRL_GRP_SPI1_1,
851 PINCTRL_GRP_TTC0_2_WAV,
852 PINCTRL_GRP_UART0_5,
853 PINCTRL_GRP_RESERVED,
854 END_OF_GROUPS,
855 }),
856 },
857 [PINCTRL_PIN_24] = {
858 .groups = &((uint16_t []) {
859 PINCTRL_GRP_RESERVED,
860 PINCTRL_GRP_NAND0_0,
861 PINCTRL_GRP_SDIO0_0_CD,
862 PINCTRL_GRP_TESTSCAN0_0,
863 PINCTRL_GRP_CSU0_6,
864 PINCTRL_GRP_GPIO0_24,
865 PINCTRL_GRP_CAN1_6,
866 PINCTRL_GRP_I2C1_6,
867 PINCTRL_GRP_SWDT1_4_CLK,
868 PINCTRL_GRP_RESERVED,
869 PINCTRL_GRP_TTC3_3_CLK,
870 PINCTRL_GRP_UART1_6,
871 PINCTRL_GRP_RESERVED,
872 END_OF_GROUPS,
873 }),
874 },
875 [PINCTRL_PIN_25] = {
876 .groups = &((uint16_t []) {
877 PINCTRL_GRP_RESERVED,
878 PINCTRL_GRP_NAND0_0,
879 PINCTRL_GRP_SDIO0_0_WP,
880 PINCTRL_GRP_TESTSCAN0_0,
881 PINCTRL_GRP_CSU0_7,
882 PINCTRL_GRP_GPIO0_25,
883 PINCTRL_GRP_CAN1_6,
884 PINCTRL_GRP_I2C1_6,
885 PINCTRL_GRP_SWDT1_4_RST,
886 PINCTRL_GRP_RESERVED,
887 PINCTRL_GRP_TTC3_3_WAV,
888 PINCTRL_GRP_UART1_6,
889 PINCTRL_GRP_RESERVED,
890 END_OF_GROUPS,
891 }),
892 },
893 [PINCTRL_PIN_26] = {
894 .groups = &((uint16_t []) {
895 PINCTRL_GRP_ETHERNET0_0,
896 PINCTRL_GRP_GEMTSU0_0,
897 PINCTRL_GRP_NAND0_1_CE,
898 PINCTRL_GRP_PMU0_0,
899 PINCTRL_GRP_TESTSCAN0_0,
900 PINCTRL_GRP_CSU0_8,
901 PINCTRL_GRP_GPIO0_26,
902 PINCTRL_GRP_CAN0_6,
903 PINCTRL_GRP_I2C0_6,
904 PINCTRL_GRP_PJTAG0_2,
905 PINCTRL_GRP_SPI0_2,
906 PINCTRL_GRP_TTC2_3_CLK,
907 PINCTRL_GRP_UART0_6,
908 PINCTRL_GRP_TRACE0_1,
909 END_OF_GROUPS,
910 }),
911 },
912 [PINCTRL_PIN_27] = {
913 .groups = &((uint16_t []) {
914 PINCTRL_GRP_ETHERNET0_0,
915 PINCTRL_GRP_NAND0_1_RB,
916 PINCTRL_GRP_PMU0_1,
917 PINCTRL_GRP_TESTSCAN0_0,
918 PINCTRL_GRP_DPAUX0_0,
919 PINCTRL_GRP_GPIO0_27,
920 PINCTRL_GRP_CAN0_6,
921 PINCTRL_GRP_I2C0_6,
922 PINCTRL_GRP_PJTAG0_2,
923 PINCTRL_GRP_SPI0_2_SS2,
924 PINCTRL_GRP_TTC2_3_WAV,
925 PINCTRL_GRP_UART0_6,
926 PINCTRL_GRP_TRACE0_1,
927 END_OF_GROUPS,
928 }),
929 },
930 [PINCTRL_PIN_28] = {
931 .groups = &((uint16_t []) {
932 PINCTRL_GRP_ETHERNET0_0,
933 PINCTRL_GRP_NAND0_1_RB,
934 PINCTRL_GRP_PMU0_2,
935 PINCTRL_GRP_TESTSCAN0_0,
936 PINCTRL_GRP_DPAUX0_0,
937 PINCTRL_GRP_GPIO0_28,
938 PINCTRL_GRP_CAN1_7,
939 PINCTRL_GRP_I2C1_7,
940 PINCTRL_GRP_PJTAG0_2,
941 PINCTRL_GRP_SPI0_2_SS1,
942 PINCTRL_GRP_TTC1_3_CLK,
943 PINCTRL_GRP_UART1_7,
944 PINCTRL_GRP_TRACE0_1,
945 END_OF_GROUPS,
946 }),
947 },
948 [PINCTRL_PIN_29] = {
949 .groups = &((uint16_t []) {
950 PINCTRL_GRP_ETHERNET0_0,
951 PINCTRL_GRP_PCIE0_0,
952 PINCTRL_GRP_PMU0_3,
953 PINCTRL_GRP_TESTSCAN0_0,
954 PINCTRL_GRP_DPAUX0_1,
955 PINCTRL_GRP_GPIO0_29,
956 PINCTRL_GRP_CAN1_7,
957 PINCTRL_GRP_I2C1_7,
958 PINCTRL_GRP_PJTAG0_2,
959 PINCTRL_GRP_SPI0_2_SS0,
960 PINCTRL_GRP_TTC1_3_WAV,
961 PINCTRL_GRP_UART1_7,
962 PINCTRL_GRP_TRACE0_1,
963 END_OF_GROUPS,
964 }),
965 },
966 [PINCTRL_PIN_30] = {
967 .groups = &((uint16_t []) {
968 PINCTRL_GRP_ETHERNET0_0,
969 PINCTRL_GRP_PCIE0_1,
970 PINCTRL_GRP_PMU0_4,
971 PINCTRL_GRP_TESTSCAN0_0,
972 PINCTRL_GRP_DPAUX0_1,
973 PINCTRL_GRP_GPIO0_30,
974 PINCTRL_GRP_CAN0_7,
975 PINCTRL_GRP_I2C0_7,
976 PINCTRL_GRP_SWDT0_4_CLK,
977 PINCTRL_GRP_SPI0_2,
978 PINCTRL_GRP_TTC0_3_CLK,
979 PINCTRL_GRP_UART0_7,
980 PINCTRL_GRP_TRACE0_1,
981 END_OF_GROUPS,
982 }),
983 },
984 [PINCTRL_PIN_31] = {
985 .groups = &((uint16_t []) {
986 PINCTRL_GRP_ETHERNET0_0,
987 PINCTRL_GRP_PCIE0_2,
988 PINCTRL_GRP_PMU0_5,
989 PINCTRL_GRP_TESTSCAN0_0,
990 PINCTRL_GRP_CSU0_9,
991 PINCTRL_GRP_GPIO0_31,
992 PINCTRL_GRP_CAN0_7,
993 PINCTRL_GRP_I2C0_7,
994 PINCTRL_GRP_SWDT0_4_RST,
995 PINCTRL_GRP_SPI0_2,
996 PINCTRL_GRP_TTC0_3_WAV,
997 PINCTRL_GRP_UART0_7,
998 PINCTRL_GRP_TRACE0_1,
999 END_OF_GROUPS,
1000 }),
1001 },
1002 [PINCTRL_PIN_32] = {
1003 .groups = &((uint16_t []) {
1004 PINCTRL_GRP_ETHERNET0_0,
1005 PINCTRL_GRP_NAND0_1_DQS,
1006 PINCTRL_GRP_PMU0_6,
1007 PINCTRL_GRP_TESTSCAN0_0,
1008 PINCTRL_GRP_CSU0_10,
1009 PINCTRL_GRP_GPIO0_32,
1010 PINCTRL_GRP_CAN1_8,
1011 PINCTRL_GRP_I2C1_8,
1012 PINCTRL_GRP_SWDT1_5_CLK,
1013 PINCTRL_GRP_SPI1_2,
1014 PINCTRL_GRP_TTC3_4_CLK,
1015 PINCTRL_GRP_UART1_8,
1016 PINCTRL_GRP_TRACE0_1,
1017 END_OF_GROUPS,
1018 }),
1019 },
1020 [PINCTRL_PIN_33] = {
1021 .groups = &((uint16_t []) {
1022 PINCTRL_GRP_ETHERNET0_0,
1023 PINCTRL_GRP_PCIE0_3,
1024 PINCTRL_GRP_PMU0_7,
1025 PINCTRL_GRP_TESTSCAN0_0,
1026 PINCTRL_GRP_CSU0_11,
1027 PINCTRL_GRP_GPIO0_33,
1028 PINCTRL_GRP_CAN1_8,
1029 PINCTRL_GRP_I2C1_8,
1030 PINCTRL_GRP_SWDT1_5_RST,
1031 PINCTRL_GRP_SPI1_2_SS2,
1032 PINCTRL_GRP_TTC3_4_WAV,
1033 PINCTRL_GRP_UART1_8,
1034 PINCTRL_GRP_TRACE0_1,
1035 END_OF_GROUPS,
1036 }),
1037 },
1038 [PINCTRL_PIN_34] = {
1039 .groups = &((uint16_t []) {
1040 PINCTRL_GRP_ETHERNET0_0,
1041 PINCTRL_GRP_PCIE0_4,
1042 PINCTRL_GRP_PMU0_8,
1043 PINCTRL_GRP_TESTSCAN0_0,
1044 PINCTRL_GRP_DPAUX0_2,
1045 PINCTRL_GRP_GPIO0_34,
1046 PINCTRL_GRP_CAN0_8,
1047 PINCTRL_GRP_I2C0_8,
1048 PINCTRL_GRP_SWDT0_5_CLK,
1049 PINCTRL_GRP_SPI1_2_SS1,
1050 PINCTRL_GRP_TTC2_4_CLK,
1051 PINCTRL_GRP_UART0_8,
1052 PINCTRL_GRP_TRACE0_1,
1053 END_OF_GROUPS,
1054 }),
1055 },
1056 [PINCTRL_PIN_35] = {
1057 .groups = &((uint16_t []) {
1058 PINCTRL_GRP_ETHERNET0_0,
1059 PINCTRL_GRP_PCIE0_5,
1060 PINCTRL_GRP_PMU0_9,
1061 PINCTRL_GRP_TESTSCAN0_0,
1062 PINCTRL_GRP_DPAUX0_2,
1063 PINCTRL_GRP_GPIO0_35,
1064 PINCTRL_GRP_CAN0_8,
1065 PINCTRL_GRP_I2C0_8,
1066 PINCTRL_GRP_SWDT0_5_RST,
1067 PINCTRL_GRP_SPI1_2_SS0,
1068 PINCTRL_GRP_TTC2_4_WAV,
1069 PINCTRL_GRP_UART0_8,
1070 PINCTRL_GRP_TRACE0_1,
1071 END_OF_GROUPS,
1072 }),
1073 },
1074 [PINCTRL_PIN_36] = {
1075 .groups = &((uint16_t []) {
1076 PINCTRL_GRP_ETHERNET0_0,
1077 PINCTRL_GRP_PCIE0_6,
1078 PINCTRL_GRP_PMU0_10,
1079 PINCTRL_GRP_TESTSCAN0_0,
1080 PINCTRL_GRP_DPAUX0_3,
1081 PINCTRL_GRP_GPIO0_36,
1082 PINCTRL_GRP_CAN1_9,
1083 PINCTRL_GRP_I2C1_9,
1084 PINCTRL_GRP_SWDT1_6_CLK,
1085 PINCTRL_GRP_SPI1_2,
1086 PINCTRL_GRP_TTC1_4_CLK,
1087 PINCTRL_GRP_UART1_9,
1088 PINCTRL_GRP_TRACE0_1,
1089 END_OF_GROUPS,
1090 }),
1091 },
1092 [PINCTRL_PIN_37] = {
1093 .groups = &((uint16_t []) {
1094 PINCTRL_GRP_ETHERNET0_0,
1095 PINCTRL_GRP_PCIE0_7,
1096 PINCTRL_GRP_PMU0_11,
1097 PINCTRL_GRP_TESTSCAN0_0,
1098 PINCTRL_GRP_DPAUX0_3,
1099 PINCTRL_GRP_GPIO0_37,
1100 PINCTRL_GRP_CAN1_9,
1101 PINCTRL_GRP_I2C1_9,
1102 PINCTRL_GRP_SWDT1_6_RST,
1103 PINCTRL_GRP_SPI1_2,
1104 PINCTRL_GRP_TTC1_4_WAV,
1105 PINCTRL_GRP_UART1_9,
1106 PINCTRL_GRP_TRACE0_1,
1107 END_OF_GROUPS,
1108 }),
1109 },
1110 [PINCTRL_PIN_38] = {
1111 .groups = &((uint16_t []) {
1112 PINCTRL_GRP_ETHERNET1_0,
1113 PINCTRL_GRP_RESERVED,
1114 PINCTRL_GRP_SDIO0_1,
1115 PINCTRL_GRP_RESERVED,
1116 PINCTRL_GRP_RESERVED,
1117 PINCTRL_GRP_GPIO0_38,
1118 PINCTRL_GRP_CAN0_9,
1119 PINCTRL_GRP_I2C0_9,
1120 PINCTRL_GRP_PJTAG0_3,
1121 PINCTRL_GRP_SPI0_3,
1122 PINCTRL_GRP_TTC0_4_CLK,
1123 PINCTRL_GRP_UART0_9,
1124 PINCTRL_GRP_TRACE0_1_CLK,
1125 PINCTRL_GRP_SDIO0_4BIT_1_0,
1126 PINCTRL_GRP_SDIO0_4BIT_1_1,
1127 PINCTRL_GRP_SDIO0_1BIT_1_0,
1128 PINCTRL_GRP_SDIO0_1BIT_1_1,
1129 PINCTRL_GRP_SDIO0_1BIT_1_2,
1130 PINCTRL_GRP_SDIO0_1BIT_1_3,
1131 PINCTRL_GRP_SDIO0_1BIT_1_4,
1132 PINCTRL_GRP_SDIO0_1BIT_1_5,
1133 PINCTRL_GRP_SDIO0_1BIT_1_6,
1134 PINCTRL_GRP_SDIO0_1BIT_1_7,
1135 END_OF_GROUPS,
1136 }),
1137 },
1138 [PINCTRL_PIN_39] = {
1139 .groups = &((uint16_t []) {
1140 PINCTRL_GRP_ETHERNET1_0,
1141 PINCTRL_GRP_RESERVED,
1142 PINCTRL_GRP_SDIO0_1_CD,
1143 PINCTRL_GRP_SDIO1_0,
1144 PINCTRL_GRP_RESERVED,
1145 PINCTRL_GRP_GPIO0_39,
1146 PINCTRL_GRP_CAN0_9,
1147 PINCTRL_GRP_I2C0_9,
1148 PINCTRL_GRP_PJTAG0_3,
1149 PINCTRL_GRP_SPI0_3_SS2,
1150 PINCTRL_GRP_TTC0_4_WAV,
1151 PINCTRL_GRP_UART0_9,
1152 PINCTRL_GRP_TRACE0_1_CLK,
1153 PINCTRL_GRP_SDIO1_4BIT_0_0,
1154 PINCTRL_GRP_SDIO1_1BIT_0_0,
1155 END_OF_GROUPS,
1156 }),
1157 },
1158 [PINCTRL_PIN_40] = {
1159 .groups = &((uint16_t []) {
1160 PINCTRL_GRP_ETHERNET1_0,
1161 PINCTRL_GRP_RESERVED,
1162 PINCTRL_GRP_SDIO0_1,
1163 PINCTRL_GRP_SDIO1_0,
1164 PINCTRL_GRP_RESERVED,
1165 PINCTRL_GRP_GPIO0_40,
1166 PINCTRL_GRP_CAN1_10,
1167 PINCTRL_GRP_I2C1_10,
1168 PINCTRL_GRP_PJTAG0_3,
1169 PINCTRL_GRP_SPI0_3_SS1,
1170 PINCTRL_GRP_TTC3_5_CLK,
1171 PINCTRL_GRP_UART1_10,
1172 PINCTRL_GRP_TRACE0_1,
1173 PINCTRL_GRP_SDIO0_4BIT_1_0,
1174 PINCTRL_GRP_SDIO0_4BIT_1_1,
1175 PINCTRL_GRP_SDIO0_1BIT_1_0,
1176 PINCTRL_GRP_SDIO0_1BIT_1_1,
1177 PINCTRL_GRP_SDIO0_1BIT_1_2,
1178 PINCTRL_GRP_SDIO0_1BIT_1_3,
1179 PINCTRL_GRP_SDIO0_1BIT_1_4,
1180 PINCTRL_GRP_SDIO0_1BIT_1_5,
1181 PINCTRL_GRP_SDIO0_1BIT_1_6,
1182 PINCTRL_GRP_SDIO0_1BIT_1_7,
1183 PINCTRL_GRP_SDIO1_4BIT_0_0,
1184 PINCTRL_GRP_SDIO1_1BIT_0_1,
1185 END_OF_GROUPS,
1186 }),
1187 },
1188 [PINCTRL_PIN_41] = {
1189 .groups = &((uint16_t []) {
1190 PINCTRL_GRP_ETHERNET1_0,
1191 PINCTRL_GRP_RESERVED,
1192 PINCTRL_GRP_SDIO0_1,
1193 PINCTRL_GRP_SDIO1_0,
1194 PINCTRL_GRP_RESERVED,
1195 PINCTRL_GRP_GPIO0_41,
1196 PINCTRL_GRP_CAN1_10,
1197 PINCTRL_GRP_I2C1_10,
1198 PINCTRL_GRP_PJTAG0_3,
1199 PINCTRL_GRP_SPI0_3_SS0,
1200 PINCTRL_GRP_TTC3_5_WAV,
1201 PINCTRL_GRP_UART1_10,
1202 PINCTRL_GRP_TRACE0_1,
1203 PINCTRL_GRP_SDIO0_4BIT_1_0,
1204 PINCTRL_GRP_SDIO0_1BIT_1_0,
1205 PINCTRL_GRP_SDIO1_4BIT_0_0,
1206 PINCTRL_GRP_SDIO1_1BIT_0_2,
1207 END_OF_GROUPS,
1208 }),
1209 },
1210 [PINCTRL_PIN_42] = {
1211 .groups = &((uint16_t []) {
1212 PINCTRL_GRP_ETHERNET1_0,
1213 PINCTRL_GRP_RESERVED,
1214 PINCTRL_GRP_SDIO0_1,
1215 PINCTRL_GRP_SDIO1_0,
1216 PINCTRL_GRP_RESERVED,
1217 PINCTRL_GRP_GPIO0_42,
1218 PINCTRL_GRP_CAN0_10,
1219 PINCTRL_GRP_I2C0_10,
1220 PINCTRL_GRP_SWDT0_6_CLK,
1221 PINCTRL_GRP_SPI0_3,
1222 PINCTRL_GRP_TTC2_5_CLK,
1223 PINCTRL_GRP_UART0_10,
1224 PINCTRL_GRP_TRACE0_1,
1225 PINCTRL_GRP_SDIO0_1,
1226 PINCTRL_GRP_SDIO0_4BIT_1_0,
1227 PINCTRL_GRP_SDIO0_1BIT_1_1,
1228 PINCTRL_GRP_SDIO1_4BIT_0_0,
1229 PINCTRL_GRP_SDIO1_1BIT_0_3,
1230 END_OF_GROUPS,
1231 }),
1232 },
1233 [PINCTRL_PIN_43] = {
1234 .groups = &((uint16_t []) {
1235 PINCTRL_GRP_ETHERNET1_0,
1236 PINCTRL_GRP_RESERVED,
1237 PINCTRL_GRP_SDIO0_1,
1238 PINCTRL_GRP_SDIO1_0_PC,
1239 PINCTRL_GRP_RESERVED,
1240 PINCTRL_GRP_GPIO0_43,
1241 PINCTRL_GRP_CAN0_10,
1242 PINCTRL_GRP_I2C0_10,
1243 PINCTRL_GRP_SWDT0_6_RST,
1244 PINCTRL_GRP_SPI0_3,
1245 PINCTRL_GRP_TTC2_5_WAV,
1246 PINCTRL_GRP_UART0_10,
1247 PINCTRL_GRP_TRACE0_1,
1248 PINCTRL_GRP_SDIO0_4BIT_1_0,
1249 PINCTRL_GRP_SDIO0_1BIT_1_2,
1250 END_OF_GROUPS,
1251 }),
1252 },
1253 [PINCTRL_PIN_44] = {
1254 .groups = &((uint16_t []) {
1255 PINCTRL_GRP_ETHERNET1_0,
1256 PINCTRL_GRP_RESERVED,
1257 PINCTRL_GRP_SDIO0_1,
1258 PINCTRL_GRP_SDIO1_0_WP,
1259 PINCTRL_GRP_RESERVED,
1260 PINCTRL_GRP_GPIO0_44,
1261 PINCTRL_GRP_CAN1_11,
1262 PINCTRL_GRP_I2C1_11,
1263 PINCTRL_GRP_SWDT1_7_CLK,
1264 PINCTRL_GRP_SPI1_3,
1265 PINCTRL_GRP_TTC1_5_CLK,
1266 PINCTRL_GRP_UART1_11,
1267 PINCTRL_GRP_RESERVED,
1268 PINCTRL_GRP_SDIO0_4BIT_1_0,
1269 PINCTRL_GRP_SDIO0_1BIT_1_3,
1270 END_OF_GROUPS,
1271 }),
1272 },
1273 [PINCTRL_PIN_45] = {
1274 .groups = &((uint16_t []) {
1275 PINCTRL_GRP_ETHERNET1_0,
1276 PINCTRL_GRP_RESERVED,
1277 PINCTRL_GRP_SDIO0_1,
1278 PINCTRL_GRP_SDIO1_0_CD,
1279 PINCTRL_GRP_RESERVED,
1280 PINCTRL_GRP_GPIO0_45,
1281 PINCTRL_GRP_CAN1_11,
1282 PINCTRL_GRP_I2C1_11,
1283 PINCTRL_GRP_SWDT1_7_RST,
1284 PINCTRL_GRP_SPI1_3_SS2,
1285 PINCTRL_GRP_TTC1_5_WAV,
1286 PINCTRL_GRP_UART1_11,
1287 PINCTRL_GRP_RESERVED,
1288 PINCTRL_GRP_SDIO0_4BIT_1_1,
1289 PINCTRL_GRP_SDIO0_1BIT_1_4,
1290 END_OF_GROUPS,
1291 }),
1292 },
1293 [PINCTRL_PIN_46] = {
1294 .groups = &((uint16_t []) {
1295 PINCTRL_GRP_ETHERNET1_0,
1296 PINCTRL_GRP_RESERVED,
1297 PINCTRL_GRP_SDIO0_1,
1298 PINCTRL_GRP_SDIO1_0,
1299 PINCTRL_GRP_RESERVED,
1300 PINCTRL_GRP_GPIO0_46,
1301 PINCTRL_GRP_CAN0_11,
1302 PINCTRL_GRP_I2C0_11,
1303 PINCTRL_GRP_SWDT0_7_CLK,
1304 PINCTRL_GRP_SPI1_3_SS1,
1305 PINCTRL_GRP_TTC0_5_CLK,
1306 PINCTRL_GRP_UART0_11,
1307 PINCTRL_GRP_RESERVED,
1308 PINCTRL_GRP_SDIO0_4BIT_1_1,
1309 PINCTRL_GRP_SDIO0_1BIT_1_5,
1310 PINCTRL_GRP_SDIO1_4BIT_0_1,
1311 PINCTRL_GRP_SDIO1_1BIT_0_4,
1312 END_OF_GROUPS,
1313 }),
1314 },
1315 [PINCTRL_PIN_47] = {
1316 .groups = &((uint16_t []) {
1317 PINCTRL_GRP_ETHERNET1_0,
1318 PINCTRL_GRP_RESERVED,
1319 PINCTRL_GRP_SDIO0_1,
1320 PINCTRL_GRP_SDIO1_0,
1321 PINCTRL_GRP_RESERVED,
1322 PINCTRL_GRP_GPIO0_47,
1323 PINCTRL_GRP_CAN0_11,
1324 PINCTRL_GRP_I2C0_11,
1325 PINCTRL_GRP_SWDT0_7_RST,
1326 PINCTRL_GRP_SPI1_3_SS0,
1327 PINCTRL_GRP_TTC0_5_WAV,
1328 PINCTRL_GRP_UART0_11,
1329 PINCTRL_GRP_RESERVED,
1330 PINCTRL_GRP_SDIO0_4BIT_1_1,
1331 PINCTRL_GRP_SDIO0_1BIT_1_6,
1332 PINCTRL_GRP_SDIO1_4BIT_0_1,
1333 PINCTRL_GRP_SDIO1_1BIT_0_5,
1334 END_OF_GROUPS,
1335 }),
1336 },
1337 [PINCTRL_PIN_48] = {
1338 .groups = &((uint16_t []) {
1339 PINCTRL_GRP_ETHERNET1_0,
1340 PINCTRL_GRP_RESERVED,
1341 PINCTRL_GRP_SDIO0_1,
1342 PINCTRL_GRP_SDIO1_0,
1343 PINCTRL_GRP_RESERVED,
1344 PINCTRL_GRP_GPIO0_48,
1345 PINCTRL_GRP_CAN1_12,
1346 PINCTRL_GRP_I2C1_12,
1347 PINCTRL_GRP_SWDT1_8_CLK,
1348 PINCTRL_GRP_SPI1_3,
1349 PINCTRL_GRP_TTC3_6_CLK,
1350 PINCTRL_GRP_UART1_12,
1351 PINCTRL_GRP_RESERVED,
1352 PINCTRL_GRP_SDIO0_4BIT_1_1,
1353 PINCTRL_GRP_SDIO0_1BIT_1_7,
1354 PINCTRL_GRP_SDIO1_4BIT_0_1,
1355 PINCTRL_GRP_SDIO1_1BIT_0_6,
1356 END_OF_GROUPS,
1357 }),
1358 },
1359 [PINCTRL_PIN_49] = {
1360 .groups = &((uint16_t []) {
1361 PINCTRL_GRP_ETHERNET1_0,
1362 PINCTRL_GRP_RESERVED,
1363 PINCTRL_GRP_SDIO0_1_PC,
1364 PINCTRL_GRP_SDIO1_0,
1365 PINCTRL_GRP_RESERVED,
1366 PINCTRL_GRP_GPIO0_49,
1367 PINCTRL_GRP_CAN1_12,
1368 PINCTRL_GRP_I2C1_12,
1369 PINCTRL_GRP_SWDT1_8_RST,
1370 PINCTRL_GRP_SPI1_3,
1371 PINCTRL_GRP_TTC3_6_WAV,
1372 PINCTRL_GRP_UART1_12,
1373 PINCTRL_GRP_RESERVED,
1374 PINCTRL_GRP_SDIO1_4BIT_0_1,
1375 PINCTRL_GRP_SDIO1_1BIT_0_7,
1376 END_OF_GROUPS,
1377 }),
1378 },
1379 [PINCTRL_PIN_50] = {
1380 .groups = &((uint16_t []) {
1381 PINCTRL_GRP_GEMTSU0_1,
1382 PINCTRL_GRP_RESERVED,
1383 PINCTRL_GRP_SDIO0_1_WP,
1384 PINCTRL_GRP_SDIO1_0,
1385 PINCTRL_GRP_RESERVED,
1386 PINCTRL_GRP_GPIO0_50,
1387 PINCTRL_GRP_CAN0_12,
1388 PINCTRL_GRP_I2C0_12,
1389 PINCTRL_GRP_SWDT0_8_CLK,
1390 PINCTRL_GRP_MDIO1_0,
1391 PINCTRL_GRP_TTC2_6_CLK,
1392 PINCTRL_GRP_UART0_12,
1393 PINCTRL_GRP_RESERVED,
1394 PINCTRL_GRP_SDIO1_4BIT_0_0,
1395 PINCTRL_GRP_SDIO1_4BIT_0_1,
1396 PINCTRL_GRP_SDIO1_1BIT_0_0,
1397 PINCTRL_GRP_SDIO1_1BIT_0_1,
1398 PINCTRL_GRP_SDIO1_1BIT_0_2,
1399 PINCTRL_GRP_SDIO1_1BIT_0_3,
1400 PINCTRL_GRP_SDIO1_1BIT_0_4,
1401 PINCTRL_GRP_SDIO1_1BIT_0_5,
1402 PINCTRL_GRP_SDIO1_1BIT_0_6,
1403 PINCTRL_GRP_SDIO1_1BIT_0_7,
1404 END_OF_GROUPS,
1405 }),
1406 },
1407 [PINCTRL_PIN_51] = {
1408 .groups = &((uint16_t []) {
1409 PINCTRL_GRP_GEMTSU0_2,
1410 PINCTRL_GRP_RESERVED,
1411 PINCTRL_GRP_RESERVED,
1412 PINCTRL_GRP_SDIO1_0,
1413 PINCTRL_GRP_RESERVED,
1414 PINCTRL_GRP_GPIO0_51,
1415 PINCTRL_GRP_CAN0_12,
1416 PINCTRL_GRP_I2C0_12,
1417 PINCTRL_GRP_SWDT0_8_RST,
1418 PINCTRL_GRP_MDIO1_0,
1419 PINCTRL_GRP_TTC2_6_WAV,
1420 PINCTRL_GRP_UART0_12,
1421 PINCTRL_GRP_RESERVED,
1422 PINCTRL_GRP_SDIO1_4BIT_0_0,
1423 PINCTRL_GRP_SDIO1_4BIT_0_1,
1424 PINCTRL_GRP_SDIO1_1BIT_0_0,
1425 PINCTRL_GRP_SDIO1_1BIT_0_1,
1426 PINCTRL_GRP_SDIO1_1BIT_0_2,
1427 PINCTRL_GRP_SDIO1_1BIT_0_3,
1428 PINCTRL_GRP_SDIO1_1BIT_0_4,
1429 PINCTRL_GRP_SDIO1_1BIT_0_5,
1430 PINCTRL_GRP_SDIO1_1BIT_0_6,
1431 PINCTRL_GRP_SDIO1_1BIT_0_7,
1432 END_OF_GROUPS,
1433 }),
1434 },
1435 [PINCTRL_PIN_52] = {
1436 .groups = &((uint16_t []) {
1437 PINCTRL_GRP_ETHERNET2_0,
1438 PINCTRL_GRP_USB0_0,
1439 PINCTRL_GRP_RESERVED,
1440 PINCTRL_GRP_RESERVED,
1441 PINCTRL_GRP_RESERVED,
1442 PINCTRL_GRP_GPIO0_52,
1443 PINCTRL_GRP_CAN1_13,
1444 PINCTRL_GRP_I2C1_13,
1445 PINCTRL_GRP_PJTAG0_4,
1446 PINCTRL_GRP_SPI0_4,
1447 PINCTRL_GRP_TTC1_6_CLK,
1448 PINCTRL_GRP_UART1_13,
1449 PINCTRL_GRP_TRACE0_2_CLK,
1450 END_OF_GROUPS,
1451 }),
1452 },
1453 [PINCTRL_PIN_53] = {
1454 .groups = &((uint16_t []) {
1455 PINCTRL_GRP_ETHERNET2_0,
1456 PINCTRL_GRP_USB0_0,
1457 PINCTRL_GRP_RESERVED,
1458 PINCTRL_GRP_RESERVED,
1459 PINCTRL_GRP_RESERVED,
1460 PINCTRL_GRP_GPIO0_53,
1461 PINCTRL_GRP_CAN1_13,
1462 PINCTRL_GRP_I2C1_13,
1463 PINCTRL_GRP_PJTAG0_4,
1464 PINCTRL_GRP_SPI0_4_SS2,
1465 PINCTRL_GRP_TTC1_6_WAV,
1466 PINCTRL_GRP_UART1_13,
1467 PINCTRL_GRP_TRACE0_2_CLK,
1468 END_OF_GROUPS,
1469 }),
1470 },
1471 [PINCTRL_PIN_54] = {
1472 .groups = &((uint16_t []) {
1473 PINCTRL_GRP_ETHERNET2_0,
1474 PINCTRL_GRP_USB0_0,
1475 PINCTRL_GRP_RESERVED,
1476 PINCTRL_GRP_RESERVED,
1477 PINCTRL_GRP_RESERVED,
1478 PINCTRL_GRP_GPIO0_54,
1479 PINCTRL_GRP_CAN0_13,
1480 PINCTRL_GRP_I2C0_13,
1481 PINCTRL_GRP_PJTAG0_4,
1482 PINCTRL_GRP_SPI0_4_SS1,
1483 PINCTRL_GRP_TTC0_6_CLK,
1484 PINCTRL_GRP_UART0_13,
1485 PINCTRL_GRP_TRACE0_2,
1486 END_OF_GROUPS,
1487 }),
1488 },
1489 [PINCTRL_PIN_55] = {
1490 .groups = &((uint16_t []) {
1491 PINCTRL_GRP_ETHERNET2_0,
1492 PINCTRL_GRP_USB0_0,
1493 PINCTRL_GRP_RESERVED,
1494 PINCTRL_GRP_RESERVED,
1495 PINCTRL_GRP_RESERVED,
1496 PINCTRL_GRP_GPIO0_55,
1497 PINCTRL_GRP_CAN0_13,
1498 PINCTRL_GRP_I2C0_13,
1499 PINCTRL_GRP_PJTAG0_4,
1500 PINCTRL_GRP_SPI0_4_SS0,
1501 PINCTRL_GRP_TTC0_6_WAV,
1502 PINCTRL_GRP_UART0_13,
1503 PINCTRL_GRP_TRACE0_2,
1504 END_OF_GROUPS,
1505 }),
1506 },
1507 [PINCTRL_PIN_56] = {
1508 .groups = &((uint16_t []) {
1509 PINCTRL_GRP_ETHERNET2_0,
1510 PINCTRL_GRP_USB0_0,
1511 PINCTRL_GRP_RESERVED,
1512 PINCTRL_GRP_RESERVED,
1513 PINCTRL_GRP_RESERVED,
1514 PINCTRL_GRP_GPIO0_56,
1515 PINCTRL_GRP_CAN1_14,
1516 PINCTRL_GRP_I2C1_14,
1517 PINCTRL_GRP_SWDT1_9_CLK,
1518 PINCTRL_GRP_SPI0_4,
1519 PINCTRL_GRP_TTC3_7_CLK,
1520 PINCTRL_GRP_UART1_14,
1521 PINCTRL_GRP_TRACE0_2,
1522 END_OF_GROUPS,
1523 }),
1524 },
1525 [PINCTRL_PIN_57] = {
1526 .groups = &((uint16_t []) {
1527 PINCTRL_GRP_ETHERNET2_0,
1528 PINCTRL_GRP_USB0_0,
1529 PINCTRL_GRP_RESERVED,
1530 PINCTRL_GRP_RESERVED,
1531 PINCTRL_GRP_RESERVED,
1532 PINCTRL_GRP_GPIO0_57,
1533 PINCTRL_GRP_CAN1_14,
1534 PINCTRL_GRP_I2C1_14,
1535 PINCTRL_GRP_SWDT1_9_RST,
1536 PINCTRL_GRP_SPI0_4,
1537 PINCTRL_GRP_TTC3_7_WAV,
1538 PINCTRL_GRP_UART1_14,
1539 PINCTRL_GRP_TRACE0_2,
1540 END_OF_GROUPS,
1541 }),
1542 },
1543 [PINCTRL_PIN_58] = {
1544 .groups = &((uint16_t []) {
1545 PINCTRL_GRP_ETHERNET2_0,
1546 PINCTRL_GRP_USB0_0,
1547 PINCTRL_GRP_RESERVED,
1548 PINCTRL_GRP_RESERVED,
1549 PINCTRL_GRP_RESERVED,
1550 PINCTRL_GRP_GPIO0_58,
1551 PINCTRL_GRP_CAN0_14,
1552 PINCTRL_GRP_I2C0_14,
1553 PINCTRL_GRP_PJTAG0_5,
1554 PINCTRL_GRP_SPI1_4,
1555 PINCTRL_GRP_TTC2_7_CLK,
1556 PINCTRL_GRP_UART0_14,
1557 PINCTRL_GRP_TRACE0_2,
1558 END_OF_GROUPS,
1559 }),
1560 },
1561 [PINCTRL_PIN_59] = {
1562 .groups = &((uint16_t []) {
1563 PINCTRL_GRP_ETHERNET2_0,
1564 PINCTRL_GRP_USB0_0,
1565 PINCTRL_GRP_RESERVED,
1566 PINCTRL_GRP_RESERVED,
1567 PINCTRL_GRP_RESERVED,
1568 PINCTRL_GRP_GPIO0_59,
1569 PINCTRL_GRP_CAN0_14,
1570 PINCTRL_GRP_I2C0_14,
1571 PINCTRL_GRP_PJTAG0_5,
1572 PINCTRL_GRP_SPI1_4_SS2,
1573 PINCTRL_GRP_TTC2_7_WAV,
1574 PINCTRL_GRP_UART0_14,
1575 PINCTRL_GRP_TRACE0_2,
1576 END_OF_GROUPS,
1577 }),
1578 },
1579 [PINCTRL_PIN_60] = {
1580 .groups = &((uint16_t []) {
1581 PINCTRL_GRP_ETHERNET2_0,
1582 PINCTRL_GRP_USB0_0,
1583 PINCTRL_GRP_RESERVED,
1584 PINCTRL_GRP_RESERVED,
1585 PINCTRL_GRP_RESERVED,
1586 PINCTRL_GRP_GPIO0_60,
1587 PINCTRL_GRP_CAN1_15,
1588 PINCTRL_GRP_I2C1_15,
1589 PINCTRL_GRP_PJTAG0_5,
1590 PINCTRL_GRP_SPI1_4_SS1,
1591 PINCTRL_GRP_TTC1_7_CLK,
1592 PINCTRL_GRP_UART1_15,
1593 PINCTRL_GRP_TRACE0_2,
1594 END_OF_GROUPS,
1595 }),
1596 },
1597 [PINCTRL_PIN_61] = {
1598 .groups = &((uint16_t []) {
1599 PINCTRL_GRP_ETHERNET2_0,
1600 PINCTRL_GRP_USB0_0,
1601 PINCTRL_GRP_RESERVED,
1602 PINCTRL_GRP_RESERVED,
1603 PINCTRL_GRP_RESERVED,
1604 PINCTRL_GRP_GPIO0_61,
1605 PINCTRL_GRP_CAN1_15,
1606 PINCTRL_GRP_I2C1_15,
1607 PINCTRL_GRP_PJTAG0_5,
1608 PINCTRL_GRP_SPI1_4_SS0,
1609 PINCTRL_GRP_TTC1_7_WAV,
1610 PINCTRL_GRP_UART1_15,
1611 PINCTRL_GRP_TRACE0_2,
1612 END_OF_GROUPS,
1613 }),
1614 },
1615 [PINCTRL_PIN_62] = {
1616 .groups = &((uint16_t []) {
1617 PINCTRL_GRP_ETHERNET2_0,
1618 PINCTRL_GRP_USB0_0,
1619 PINCTRL_GRP_RESERVED,
1620 PINCTRL_GRP_RESERVED,
1621 PINCTRL_GRP_RESERVED,
1622 PINCTRL_GRP_GPIO0_62,
1623 PINCTRL_GRP_CAN0_15,
1624 PINCTRL_GRP_I2C0_15,
1625 PINCTRL_GRP_SWDT0_9_CLK,
1626 PINCTRL_GRP_SPI1_4,
1627 PINCTRL_GRP_TTC0_7_CLK,
1628 PINCTRL_GRP_UART0_15,
1629 PINCTRL_GRP_TRACE0_2,
1630 END_OF_GROUPS,
1631 }),
1632 },
1633 [PINCTRL_PIN_63] = {
1634 .groups = &((uint16_t []) {
1635 PINCTRL_GRP_ETHERNET2_0,
1636 PINCTRL_GRP_USB0_0,
1637 PINCTRL_GRP_RESERVED,
1638 PINCTRL_GRP_RESERVED,
1639 PINCTRL_GRP_RESERVED,
1640 PINCTRL_GRP_GPIO0_63,
1641 PINCTRL_GRP_CAN0_15,
1642 PINCTRL_GRP_I2C0_15,
1643 PINCTRL_GRP_SWDT0_9_RST,
1644 PINCTRL_GRP_SPI1_4,
1645 PINCTRL_GRP_TTC0_7_WAV,
1646 PINCTRL_GRP_UART0_15,
1647 PINCTRL_GRP_TRACE0_2,
1648 END_OF_GROUPS,
1649 }),
1650 },
1651 [PINCTRL_PIN_64] = {
1652 .groups = &((uint16_t []) {
1653 PINCTRL_GRP_ETHERNET3_0,
1654 PINCTRL_GRP_USB1_0,
1655 PINCTRL_GRP_SDIO0_2,
1656 PINCTRL_GRP_RESERVED,
1657 PINCTRL_GRP_RESERVED,
1658 PINCTRL_GRP_GPIO0_64,
1659 PINCTRL_GRP_CAN1_16,
1660 PINCTRL_GRP_I2C1_16,
1661 PINCTRL_GRP_SWDT1_10_CLK,
1662 PINCTRL_GRP_SPI0_5,
1663 PINCTRL_GRP_TTC3_8_CLK,
1664 PINCTRL_GRP_UART1_16,
1665 PINCTRL_GRP_TRACE0_2,
1666 PINCTRL_GRP_SDIO0_4BIT_2_0,
1667 PINCTRL_GRP_SDIO0_4BIT_2_1,
1668 PINCTRL_GRP_SDIO0_1BIT_2_0,
1669 PINCTRL_GRP_SDIO0_1BIT_2_1,
1670 PINCTRL_GRP_SDIO0_1BIT_2_2,
1671 PINCTRL_GRP_SDIO0_1BIT_2_3,
1672 PINCTRL_GRP_SDIO0_1BIT_2_4,
1673 PINCTRL_GRP_SDIO0_1BIT_2_5,
1674 PINCTRL_GRP_SDIO0_1BIT_2_6,
1675 PINCTRL_GRP_SDIO0_1BIT_2_7,
1676 END_OF_GROUPS,
1677 }),
1678 },
1679 [PINCTRL_PIN_65] = {
1680 .groups = &((uint16_t []) {
1681 PINCTRL_GRP_ETHERNET3_0,
1682 PINCTRL_GRP_USB1_0,
1683 PINCTRL_GRP_SDIO0_2_CD,
1684 PINCTRL_GRP_RESERVED,
1685 PINCTRL_GRP_RESERVED,
1686 PINCTRL_GRP_GPIO0_65,
1687 PINCTRL_GRP_CAN1_16,
1688 PINCTRL_GRP_I2C1_16,
1689 PINCTRL_GRP_SWDT1_10_RST,
1690 PINCTRL_GRP_SPI0_5_SS2,
1691 PINCTRL_GRP_TTC3_8_WAV,
1692 PINCTRL_GRP_UART1_16,
1693 PINCTRL_GRP_TRACE0_2,
1694 END_OF_GROUPS,
1695 }),
1696 },
1697 [PINCTRL_PIN_66] = {
1698 .groups = &((uint16_t []) {
1699 PINCTRL_GRP_ETHERNET3_0,
1700 PINCTRL_GRP_USB1_0,
1701 PINCTRL_GRP_SDIO0_2,
1702 PINCTRL_GRP_RESERVED,
1703 PINCTRL_GRP_RESERVED,
1704 PINCTRL_GRP_GPIO0_66,
1705 PINCTRL_GRP_CAN0_16,
1706 PINCTRL_GRP_I2C0_16,
1707 PINCTRL_GRP_SWDT0_10_CLK,
1708 PINCTRL_GRP_SPI0_5_SS1,
1709 PINCTRL_GRP_TTC2_8_CLK,
1710 PINCTRL_GRP_UART0_16,
1711 PINCTRL_GRP_TRACE0_2,
1712 PINCTRL_GRP_SDIO0_4BIT_2_0,
1713 PINCTRL_GRP_SDIO0_4BIT_2_1,
1714 PINCTRL_GRP_SDIO0_1BIT_2_0,
1715 PINCTRL_GRP_SDIO0_1BIT_2_1,
1716 PINCTRL_GRP_SDIO0_1BIT_2_2,
1717 PINCTRL_GRP_SDIO0_1BIT_2_3,
1718 PINCTRL_GRP_SDIO0_1BIT_2_4,
1719 PINCTRL_GRP_SDIO0_1BIT_2_5,
1720 PINCTRL_GRP_SDIO0_1BIT_2_6,
1721 PINCTRL_GRP_SDIO0_1BIT_2_7,
1722 END_OF_GROUPS,
1723 }),
1724 },
1725 [PINCTRL_PIN_67] = {
1726 .groups = &((uint16_t []) {
1727 PINCTRL_GRP_ETHERNET3_0,
1728 PINCTRL_GRP_USB1_0,
1729 PINCTRL_GRP_SDIO0_2,
1730 PINCTRL_GRP_RESERVED,
1731 PINCTRL_GRP_RESERVED,
1732 PINCTRL_GRP_GPIO0_67,
1733 PINCTRL_GRP_CAN0_16,
1734 PINCTRL_GRP_I2C0_16,
1735 PINCTRL_GRP_SWDT0_10_RST,
1736 PINCTRL_GRP_SPI0_5_SS0,
1737 PINCTRL_GRP_TTC2_8_WAV,
1738 PINCTRL_GRP_UART0_16,
1739 PINCTRL_GRP_TRACE0_2,
1740 PINCTRL_GRP_SDIO0_4BIT_2_0,
1741 PINCTRL_GRP_SDIO0_1BIT_2_0,
1742 END_OF_GROUPS,
1743 }),
1744 },
1745 [PINCTRL_PIN_68] = {
1746 .groups = &((uint16_t []) {
1747 PINCTRL_GRP_ETHERNET3_0,
1748 PINCTRL_GRP_USB1_0,
1749 PINCTRL_GRP_SDIO0_2,
1750 PINCTRL_GRP_RESERVED,
1751 PINCTRL_GRP_RESERVED,
1752 PINCTRL_GRP_GPIO0_68,
1753 PINCTRL_GRP_CAN1_17,
1754 PINCTRL_GRP_I2C1_17,
1755 PINCTRL_GRP_SWDT1_11_CLK,
1756 PINCTRL_GRP_SPI0_5,
1757 PINCTRL_GRP_TTC1_8_CLK,
1758 PINCTRL_GRP_UART1_17,
1759 PINCTRL_GRP_TRACE0_2,
1760 PINCTRL_GRP_SDIO0_4BIT_2_0,
1761 PINCTRL_GRP_SDIO0_1BIT_2_1,
1762 END_OF_GROUPS,
1763 }),
1764 },
1765 [PINCTRL_PIN_69] = {
1766 .groups = &((uint16_t []) {
1767 PINCTRL_GRP_ETHERNET3_0,
1768 PINCTRL_GRP_USB1_0,
1769 PINCTRL_GRP_SDIO0_2,
1770 PINCTRL_GRP_SDIO1_1_WP,
1771 PINCTRL_GRP_RESERVED,
1772 PINCTRL_GRP_GPIO0_69,
1773 PINCTRL_GRP_CAN1_17,
1774 PINCTRL_GRP_I2C1_17,
1775 PINCTRL_GRP_SWDT1_11_RST,
1776 PINCTRL_GRP_SPI0_5,
1777 PINCTRL_GRP_TTC1_8_WAV,
1778 PINCTRL_GRP_UART1_17,
1779 PINCTRL_GRP_TRACE0_2,
1780 PINCTRL_GRP_SDIO0_4BIT_2_0,
1781 PINCTRL_GRP_SDIO0_1BIT_2_2,
1782 END_OF_GROUPS,
1783 }),
1784 },
1785 [PINCTRL_PIN_70] = {
1786 .groups = &((uint16_t []) {
1787 PINCTRL_GRP_ETHERNET3_0,
1788 PINCTRL_GRP_USB1_0,
1789 PINCTRL_GRP_SDIO0_2,
1790 PINCTRL_GRP_SDIO1_1_PC,
1791 PINCTRL_GRP_RESERVED,
1792 PINCTRL_GRP_GPIO0_70,
1793 PINCTRL_GRP_CAN0_17,
1794 PINCTRL_GRP_I2C0_17,
1795 PINCTRL_GRP_SWDT0_11_CLK,
1796 PINCTRL_GRP_SPI1_5,
1797 PINCTRL_GRP_TTC0_8_CLK,
1798 PINCTRL_GRP_UART0_17,
1799 PINCTRL_GRP_RESERVED,
1800 PINCTRL_GRP_SDIO0_4BIT_2_0,
1801 PINCTRL_GRP_SDIO0_1BIT_2_3,
1802 END_OF_GROUPS,
1803 }),
1804 },
1805 [PINCTRL_PIN_71] = {
1806 .groups = &((uint16_t []) {
1807 PINCTRL_GRP_ETHERNET3_0,
1808 PINCTRL_GRP_USB1_0,
1809 PINCTRL_GRP_SDIO0_2,
1810 PINCTRL_GRP_SDIO1_4BIT_1_0,
1811 PINCTRL_GRP_RESERVED,
1812 PINCTRL_GRP_GPIO0_71,
1813 PINCTRL_GRP_CAN0_17,
1814 PINCTRL_GRP_I2C0_17,
1815 PINCTRL_GRP_SWDT0_11_RST,
1816 PINCTRL_GRP_SPI1_5_SS2,
1817 PINCTRL_GRP_TTC0_8_WAV,
1818 PINCTRL_GRP_UART0_17,
1819 PINCTRL_GRP_RESERVED,
1820 PINCTRL_GRP_SDIO0_2,
1821 PINCTRL_GRP_SDIO0_4BIT_2_1,
1822 PINCTRL_GRP_SDIO0_1BIT_2_4,
1823 PINCTRL_GRP_SDIO1_1BIT_1_0,
1824 END_OF_GROUPS,
1825 }),
1826 },
1827 [PINCTRL_PIN_72] = {
1828 .groups = &((uint16_t []) {
1829 PINCTRL_GRP_ETHERNET3_0,
1830 PINCTRL_GRP_USB1_0,
1831 PINCTRL_GRP_SDIO0_2,
1832 PINCTRL_GRP_SDIO1_4BIT_1_0,
1833 PINCTRL_GRP_RESERVED,
1834 PINCTRL_GRP_GPIO0_72,
1835 PINCTRL_GRP_CAN1_18,
1836 PINCTRL_GRP_I2C1_18,
1837 PINCTRL_GRP_SWDT1_12_CLK,
1838 PINCTRL_GRP_SPI1_5_SS1,
1839 PINCTRL_GRP_RESERVED,
1840 PINCTRL_GRP_UART1_18,
1841 PINCTRL_GRP_RESERVED,
1842 PINCTRL_GRP_SDIO0_4BIT_2_1,
1843 PINCTRL_GRP_SDIO0_1BIT_2_5,
1844 PINCTRL_GRP_SDIO1_1BIT_1_1,
1845 END_OF_GROUPS,
1846 }),
1847 },
1848 [PINCTRL_PIN_73] = {
1849 .groups = &((uint16_t []) {
1850 PINCTRL_GRP_ETHERNET3_0,
1851 PINCTRL_GRP_USB1_0,
1852 PINCTRL_GRP_SDIO0_2,
1853 PINCTRL_GRP_SDIO1_4BIT_1_0,
1854 PINCTRL_GRP_RESERVED,
1855 PINCTRL_GRP_GPIO0_73,
1856 PINCTRL_GRP_CAN1_18,
1857 PINCTRL_GRP_I2C1_18,
1858 PINCTRL_GRP_SWDT1_12_RST,
1859 PINCTRL_GRP_SPI1_5_SS0,
1860 PINCTRL_GRP_RESERVED,
1861 PINCTRL_GRP_UART1_18,
1862 PINCTRL_GRP_RESERVED,
1863 PINCTRL_GRP_SDIO0_4BIT_2_1,
1864 PINCTRL_GRP_SDIO0_1BIT_2_6,
1865 PINCTRL_GRP_SDIO1_1BIT_1_2,
1866 END_OF_GROUPS,
1867 }),
1868 },
1869 [PINCTRL_PIN_74] = {
1870 .groups = &((uint16_t []) {
1871 PINCTRL_GRP_ETHERNET3_0,
1872 PINCTRL_GRP_USB1_0,
1873 PINCTRL_GRP_SDIO0_2,
1874 PINCTRL_GRP_SDIO1_4BIT_1_0,
1875 PINCTRL_GRP_RESERVED,
1876 PINCTRL_GRP_GPIO0_74,
1877 PINCTRL_GRP_CAN0_18,
1878 PINCTRL_GRP_I2C0_18,
1879 PINCTRL_GRP_SWDT0_12_CLK,
1880 PINCTRL_GRP_SPI1_5,
1881 PINCTRL_GRP_RESERVED,
1882 PINCTRL_GRP_UART0_18,
1883 PINCTRL_GRP_RESERVED,
1884 PINCTRL_GRP_SDIO0_4BIT_2_1,
1885 PINCTRL_GRP_SDIO0_1BIT_2_7,
1886 PINCTRL_GRP_SDIO1_1BIT_1_3,
1887 END_OF_GROUPS,
1888 }),
1889 },
1890 [PINCTRL_PIN_75] = {
1891 .groups = &((uint16_t []) {
1892 PINCTRL_GRP_ETHERNET3_0,
1893 PINCTRL_GRP_USB1_0,
1894 PINCTRL_GRP_SDIO0_2_PC,
1895 PINCTRL_GRP_SDIO1_4BIT_1_0,
1896 PINCTRL_GRP_RESERVED,
1897 PINCTRL_GRP_GPIO0_75,
1898 PINCTRL_GRP_CAN0_18,
1899 PINCTRL_GRP_I2C0_18,
1900 PINCTRL_GRP_SWDT0_12_RST,
1901 PINCTRL_GRP_SPI1_5,
1902 PINCTRL_GRP_RESERVED,
1903 PINCTRL_GRP_UART0_18,
1904 PINCTRL_GRP_RESERVED,
1905 PINCTRL_GRP_SDIO1_1BIT_1_0,
1906 PINCTRL_GRP_SDIO1_1BIT_1_1,
1907 PINCTRL_GRP_SDIO1_1BIT_1_2,
1908 PINCTRL_GRP_SDIO1_1BIT_1_3,
1909 END_OF_GROUPS,
1910 }),
1911 },
1912 [PINCTRL_PIN_76] = {
1913 .groups = &((uint16_t []) {
1914 PINCTRL_GRP_RESERVED,
1915 PINCTRL_GRP_RESERVED,
1916 PINCTRL_GRP_SDIO0_2_WP,
1917 PINCTRL_GRP_SDIO1_4BIT_1_0,
1918 PINCTRL_GRP_RESERVED,
1919 PINCTRL_GRP_GPIO0_76,
1920 PINCTRL_GRP_CAN1_19,
1921 PINCTRL_GRP_I2C1_19,
1922 PINCTRL_GRP_MDIO0_0,
1923 PINCTRL_GRP_MDIO1_1,
1924 PINCTRL_GRP_MDIO2_0,
1925 PINCTRL_GRP_MDIO3_0,
1926 PINCTRL_GRP_RESERVED,
1927 PINCTRL_GRP_SDIO1_1BIT_1_0,
1928 PINCTRL_GRP_SDIO1_1BIT_1_1,
1929 PINCTRL_GRP_SDIO1_1BIT_1_2,
1930 PINCTRL_GRP_SDIO1_1BIT_1_3,
1931 END_OF_GROUPS,
1932 }),
1933 },
1934 [PINCTRL_PIN_77] = {
1935 .groups = &((uint16_t []) {
1936 PINCTRL_GRP_RESERVED,
1937 PINCTRL_GRP_RESERVED,
1938 PINCTRL_GRP_RESERVED,
1939 PINCTRL_GRP_SDIO1_1_CD,
1940 PINCTRL_GRP_RESERVED,
1941 PINCTRL_GRP_GPIO0_77,
1942 PINCTRL_GRP_CAN1_19,
1943 PINCTRL_GRP_I2C1_19,
1944 PINCTRL_GRP_MDIO0_0,
1945 PINCTRL_GRP_MDIO1_1,
1946 PINCTRL_GRP_MDIO2_0,
1947 PINCTRL_GRP_MDIO3_0,
1948 PINCTRL_GRP_RESERVED,
1949 END_OF_GROUPS,
1950 }),
1951 },
1952 };
1953
1954 /**
1955 * pm_api_pinctrl_get_num_pins() - PM call to request number of pins.
1956 * @npins: Number of pins.
1957 *
1958 * This function is used by master to get number of pins.
1959 *
1960 * Return: Returns success.
1961 *
1962 */
pm_api_pinctrl_get_num_pins(uint32_t * npins)1963 enum pm_ret_status pm_api_pinctrl_get_num_pins(uint32_t *npins)
1964 {
1965 *npins = MAX_PIN;
1966
1967 return PM_RET_SUCCESS;
1968 }
1969
1970 /**
1971 * pm_api_pinctrl_get_num_functions() - PM call to request number of functions.
1972 * @nfuncs: Number of functions.
1973 *
1974 * This function is used by master to get number of functions.
1975 *
1976 * Return: Returns success.
1977 *
1978 */
pm_api_pinctrl_get_num_functions(uint32_t * nfuncs)1979 enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs)
1980 {
1981 *nfuncs = MAX_FUNCTION;
1982
1983 return PM_RET_SUCCESS;
1984 }
1985
1986 /**
1987 * pm_api_pinctrl_get_num_func_groups() - PM call to request number of
1988 * function groups.
1989 * @fid: Function Id.
1990 * @ngroups: Number of function groups.
1991 *
1992 * This function is used by master to get number of function groups.
1993 *
1994 * Return: Returns success.
1995 *
1996 */
pm_api_pinctrl_get_num_func_groups(uint32_t fid,uint32_t * ngroups)1997 enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
1998 uint32_t *ngroups)
1999 {
2000 enum pm_ret_status status = PM_RET_SUCCESS;
2001
2002 if (fid >= (uint32_t)MAX_FUNCTION) {
2003 status = PM_RET_ERROR_ARGS;
2004 } else {
2005
2006 *ngroups = pinctrl_functions[fid].group_size;
2007 }
2008
2009 return status;
2010 }
2011
2012 /**
2013 * pm_api_pinctrl_get_function_name() - PM call to request a function name.
2014 * @fid: Function ID.
2015 * @name: Name of function (max 16 bytes).
2016 *
2017 * This function is used by master to get name of function specified
2018 * by given function ID.
2019 *
2020 */
pm_api_pinctrl_get_function_name(uint32_t fid,char * name)2021 void pm_api_pinctrl_get_function_name(uint32_t fid, char *name)
2022 {
2023 if (fid >= (uint32_t)MAX_FUNCTION) {
2024 (void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
2025 } else {
2026 (void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
2027 }
2028 }
2029
2030 /**
2031 * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function
2032 * groups of function Id.
2033 * @fid: Function ID.
2034 * @index: Index of next function groups.
2035 * @groups: Function groups.
2036 *
2037 * This function is used by master to get function groups specified
2038 * by given function Id. This API will return 6 function groups with
2039 * a single response. To get other function groups, master should call
2040 * same API in loop with new function groups index till error is returned.
2041 *
2042 * E.g First call should have index 0 which will return function groups
2043 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
2044 * function groups 6, 7, 8, 9, 10 and 11 and so on.
2045 *
2046 * Return: Returns status, either success or error+reason.
2047 *
2048 */
pm_api_pinctrl_get_function_groups(uint32_t fid,uint32_t index,uint16_t * groups)2049 enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid,
2050 uint32_t index,
2051 uint16_t *groups)
2052 {
2053 uint16_t grps;
2054 uint16_t end_of_grp_offset;
2055 uint16_t i;
2056 enum pm_ret_status status = PM_RET_SUCCESS;
2057
2058 if (fid >= (uint32_t)MAX_FUNCTION) {
2059 status = PM_RET_ERROR_ARGS;
2060 goto exit_label;
2061 }
2062
2063 (void)memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
2064
2065 grps = pinctrl_functions[fid].group_base;
2066 end_of_grp_offset = grps + pinctrl_functions[fid].group_size;
2067
2068 for (i = 0U; i < NUM_GROUPS_PER_RESP; i++) {
2069 if ((grps + index + i) >= end_of_grp_offset) {
2070 break;
2071 }
2072 groups[i] = (uint16_t)(grps + index + i);
2073 }
2074
2075 exit_label:
2076 return status;
2077 }
2078
2079 /**
2080 * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin
2081 * groups of pin.
2082 * @pin: Pin.
2083 * @index: Index of next pin groups.
2084 * @groups: pin groups.
2085 *
2086 * This function is used by master to get pin groups specified
2087 * by given pin Id. This API will return 6 pin groups with
2088 * a single response. To get other pin groups, master should call
2089 * same API in loop with new pin groups index till error is returned.
2090 *
2091 * E.g First call should have index 0 which will return pin groups
2092 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
2093 * pin groups 6, 7, 8, 9, 10 and 11 and so on.
2094 *
2095 * Return: Returns status, either success or error+reason.
2096 *
2097 */
pm_api_pinctrl_get_pin_groups(uint32_t pin,uint32_t index,uint16_t * groups)2098 enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin,
2099 uint32_t index,
2100 uint16_t *groups)
2101 {
2102 uint32_t i;
2103 const uint16_t *grps;
2104 enum pm_ret_status status = PM_RET_SUCCESS;
2105
2106 if (pin >= (uint32_t)MAX_PIN) {
2107 status = PM_RET_ERROR_ARGS;
2108 goto exit_label;
2109 }
2110
2111 (void)memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
2112
2113 grps = *zynqmp_pin_groups[pin].groups;
2114 if (grps == NULL) {
2115 status = PM_RET_SUCCESS;
2116 goto exit_label;
2117 }
2118
2119 /* Skip groups till index */
2120 for (i = 0; i < index; i++) {
2121 if (grps[i] == (uint16_t)END_OF_GROUPS) {
2122 status = PM_RET_SUCCESS;
2123 goto exit_label;
2124 }
2125 }
2126
2127 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
2128 groups[i] = grps[index + i];
2129 if (groups[i] == (uint16_t)END_OF_GROUPS) {
2130 break;
2131 }
2132 }
2133
2134 exit_label:
2135 return status;
2136 }
2137