1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `PSCI`_ as a runtime service. PSCI is the interface 13from normal world software to firmware implementing power management use-cases 14(for example, secondary CPU boot, hotplug and idle). Normal world software can 15access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction. 16The SMC instruction must be used as mandated by the SMC Calling Convention 17(`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the `Arm Confidential Compute 32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management 33 Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case SPMC_AT_EL3 is enabled, populate the BL32 image base, size and max 134 limit in the entry point information, since there is no platform function 135 to retrieve these in generic code. We choose ``arg2``, ``arg3`` and 136 ``arg4`` since the generic code uses ``arg1`` for stashing the SP manifest 137 size. The SPMC setup uses these arguments to update SP manifest with 138 actual SP's base address and it size. 139 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 140 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 141 from FW_CONFIG device tree. 142 143BL1 144~~~ 145 146This stage begins execution from the platform's reset vector at EL3. The reset 147address is platform dependent but it is usually located in a Trusted ROM area. 148The BL1 data section is copied to trusted SRAM at runtime. 149 150On the Arm development platforms, BL1 code starts execution from the reset 151vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 152to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 153 154The functionality implemented by this stage is as follows. 155 156Determination of boot path 157^^^^^^^^^^^^^^^^^^^^^^^^^^ 158 159Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 160boot and a cold boot. This is done using platform-specific mechanisms (see the 161``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 162of a warm boot, a CPU is expected to continue execution from a separate 163entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 164platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 165the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 166path as described in the following sections. 167 168This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 169:ref:`CPU Reset` for more information on the effect of the 170``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 171 172Architectural initialization 173^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 174 175BL1 performs minimal architectural initialization as follows. 176 177- Exception vectors 178 179 BL1 sets up simple exception vectors for both synchronous and asynchronous 180 exceptions. The default behavior upon receiving an exception is to populate 181 a status code in the general purpose register ``X0/R0`` and call the 182 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 183 status code is one of: 184 185 For AArch64: 186 187 :: 188 189 0x0 : Synchronous exception from Current EL with SP_EL0 190 0x1 : IRQ exception from Current EL with SP_EL0 191 0x2 : FIQ exception from Current EL with SP_EL0 192 0x3 : System Error exception from Current EL with SP_EL0 193 0x4 : Synchronous exception from Current EL with SP_ELx 194 0x5 : IRQ exception from Current EL with SP_ELx 195 0x6 : FIQ exception from Current EL with SP_ELx 196 0x7 : System Error exception from Current EL with SP_ELx 197 0x8 : Synchronous exception from Lower EL using aarch64 198 0x9 : IRQ exception from Lower EL using aarch64 199 0xa : FIQ exception from Lower EL using aarch64 200 0xb : System Error exception from Lower EL using aarch64 201 0xc : Synchronous exception from Lower EL using aarch32 202 0xd : IRQ exception from Lower EL using aarch32 203 0xe : FIQ exception from Lower EL using aarch32 204 0xf : System Error exception from Lower EL using aarch32 205 206 For AArch32: 207 208 :: 209 210 0x10 : User mode 211 0x11 : FIQ mode 212 0x12 : IRQ mode 213 0x13 : SVC mode 214 0x16 : Monitor mode 215 0x17 : Abort mode 216 0x1a : Hypervisor mode 217 0x1b : Undefined mode 218 0x1f : System mode 219 220 The ``plat_report_exception()`` implementation on the Arm FVP port programs 221 the Versatile Express System LED register in the following format to 222 indicate the occurrence of an unexpected exception: 223 224 :: 225 226 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 227 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 228 For AArch32 it is always 0x0 229 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 230 of the status code 231 232 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 233 CLCD window of the FVP. 234 235 BL1 does not expect to receive any exceptions other than the SMC exception. 236 For the latter, BL1 installs a simple stub. The stub expects to receive a 237 limited set of SMC types (determined by their function IDs in the general 238 purpose register ``X0/R0``): 239 240 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 241 to EL3 Runtime Software. 242 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 243 Design Guide are supported for AArch64 only. These SMCs are currently 244 not supported when BL1 is built for AArch32. 245 246 Any other SMC leads to an assertion failure. 247 248- CPU initialization 249 250 BL1 calls the ``reset_handler`` macro/function which in turn calls the CPU 251 specific reset handler function (see the section: "CPU specific operations 252 framework"). 253 254Platform initialization 255^^^^^^^^^^^^^^^^^^^^^^^ 256 257On Arm platforms, BL1 performs the following platform initializations: 258 259- Enable the Trusted Watchdog. 260- Initialize the console. 261- Configure the Interconnect to enable hardware coherency. 262- Enable the MMU and map the memory it needs to access. 263- Configure any required platform storage to load the next bootloader image 264 (BL2). 265- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 266 load it to the platform defined address and make it available to BL2 via 267 ``arg0``. 268- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 269 and NS-BL2U firmware update images. 270 271Firmware Update detection and execution 272^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 273 274After performing platform setup, BL1 common code calls 275``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 276required or to proceed with the normal boot process. If the platform code 277returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 278in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 279required and execution passes to the first image in the 280:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 281of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 282contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 283execution state of the next image. 284 285BL2 image load and execution 286^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 287 288In the normal boot flow, BL1 execution continues as follows: 289 290#. BL1 prints the following string from the primary CPU to indicate successful 291 execution of the BL1 stage: 292 293 :: 294 295 "Booting Trusted Firmware" 296 297#. BL1 loads a BL2 raw binary image from platform storage, at a 298 platform-specific base address. Prior to the load, BL1 invokes 299 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 300 use the image information. If the BL2 image file is not present or if 301 there is not enough free trusted SRAM the following error message is 302 printed: 303 304 :: 305 306 "Failed to load BL2 firmware." 307 308#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 309 for platforms to take further action after image load. This function must 310 populate the necessary arguments for BL2, which may also include the memory 311 layout. Further description of the memory layout can be found later 312 in this document. 313 314#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 315 Secure SVC mode (for AArch32), starting from its load address. 316 317BL2 318~~~ 319 320BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 321SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 322base address (more information can be found later in this document). 323The functionality implemented by BL2 is as follows. 324 325Architectural initialization 326^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 327 328For AArch64, BL2 performs the minimal architectural initialization required 329for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 330access to Floating Point and Advanced SIMD registers by setting the 331``CPACR.FPEN`` bits. 332 333For AArch32, the minimal architectural initialization required for subsequent 334stages of TF-A and normal world software is taken care of in BL1 as both BL1 335and BL2 execute at PL1. 336 337Platform initialization 338^^^^^^^^^^^^^^^^^^^^^^^ 339 340On Arm platforms, BL2 performs the following platform initializations: 341 342- Initialize the console. 343- Configure any required platform storage to allow loading further bootloader 344 images. 345- Enable the MMU and map the memory it needs to access. 346- Perform platform security setup to allow access to controlled components. 347- Reserve some memory for passing information to the next bootloader image 348 EL3 Runtime Software and populate it. 349- Define the extents of memory available for loading each subsequent 350 bootloader image. 351- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 352 then parse it. 353 354Image loading in BL2 355^^^^^^^^^^^^^^^^^^^^ 356 357BL2 generic code loads the images based on the list of loadable images 358provided by the platform. BL2 passes the list of executable images 359provided by the platform to the next handover BL image. 360 361The list of loadable images provided by the platform may also contain 362dynamic configuration files. The files are loaded and can be parsed as 363needed in the ``bl2_plat_handle_post_image_load()`` function. These 364configuration files can be passed to next Boot Loader stages as arguments 365by updating the corresponding entrypoint information in this function. 366 367SCP_BL2 (System Control Processor Firmware) image load 368^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 369 370Some systems have a separate System Control Processor (SCP) for power, clock, 371reset and system control. BL2 loads the optional SCP_BL2 image from platform 372storage into a platform-specific region of secure memory. The subsequent 373handling of SCP_BL2 is platform specific. For example, on the Juno Arm 374development platform port the image is transferred into SCP's internal memory 375using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 376memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 377for BL2 execution to continue. 378 379EL3 Runtime Software image load 380^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 381 382BL2 loads the EL3 Runtime Software image from platform storage into a platform- 383specific address in trusted SRAM. If there is not enough memory to load the 384image or image is missing it leads to an assertion failure. 385 386AArch64 BL32 (Secure-EL1 Payload) image load 387^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 388 389BL2 loads the optional BL32 image from platform storage into a platform- 390specific region of secure memory. The image executes in the secure world. BL2 391relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 392populates a platform-specific area of memory with the entrypoint/load-address 393of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 394for entry into BL32 is not determined by BL2, it is initialized by the 395Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 396managing interaction with BL32. This information is passed to BL31. 397 398BL33 (Non-trusted Firmware) image load 399^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 400 401BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 402platform storage into non-secure memory as defined by the platform. 403 404BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 405initialization is complete. Hence, BL2 populates a platform-specific area of 406memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 407normal world software image. The entrypoint is the load address of the BL33 408image. The ``SPSR`` is determined as specified in Section 5.13 of the 409`PSCI`_. This information is passed to the EL3 Runtime Software. 410 411AArch64 BL31 (EL3 Runtime Software) execution 412^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 413 414BL2 execution continues as follows: 415 416#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 417 BL31 entrypoint. The exception is handled by the SMC exception handler 418 installed by BL1. 419 420#. BL1 turns off the MMU and flushes the caches. It clears the 421 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 422 and invalidates the TLBs. 423 424#. BL1 passes control to BL31 at the specified entrypoint at EL3. 425 426Running BL2 at EL3 execution level 427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 428 429Some platforms have a non-TF-A Boot ROM that expects the next boot stage 430to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 431as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 432this waste, a special mode enables BL2 to execute at EL3, which allows 433a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 434when the build flag RESET_TO_BL2 is enabled. 435The main differences in this mode are: 436 437#. BL2 includes the reset code and the mailbox mechanism to differentiate 438 cold boot and warm boot. It runs at EL3 doing the arch 439 initialization required for EL3. 440 441#. BL2 does not receive the meminfo information from BL1 anymore. This 442 information can be passed by the Boot ROM or be internal to the 443 BL2 image. 444 445#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 446 instead of invoking the RUN_IMAGE SMC call. 447 448 449We assume 3 different types of BootROM support on the platform: 450 451#. The Boot ROM always jumps to the same address, for both cold 452 and warm boot. In this case, we will need to keep a resident part 453 of BL2 whose memory cannot be reclaimed by any other image. The 454 linker script defines the symbols __TEXT_RESIDENT_START__ and 455 __TEXT_RESIDENT_END__ that allows the platform to configure 456 correctly the memory map. 457#. The platform has some mechanism to indicate the jump address to the 458 Boot ROM. Platform code can then program the jump address with 459 psci_warmboot_entrypoint during cold boot. 460#. The platform has some mechanism to program the reset address using 461 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 462 program the reset address with psci_warmboot_entrypoint during 463 cold boot, bypassing the boot ROM for warm boot. 464 465In the last 2 cases, no part of BL2 needs to remain resident at 466runtime. In the first 2 cases, we expect the Boot ROM to be able to 467differentiate between warm and cold boot, to avoid loading BL2 again 468during warm boot. 469 470This functionality can be tested with FVP loading the image directly 471in memory and changing the address where the system jumps at reset. 472For example: 473 474 -C cluster0.cpu0.RVBAR=0x4022000 475 --data cluster0.cpu0=bl2.bin@0x4022000 476 477With this configuration, FVP is like a platform of the first case, 478where the Boot ROM jumps always to the same address. For simplification, 479BL32 is loaded in DRAM in this case, to avoid other images reclaiming 480BL2 memory. 481 482 483AArch64 BL31 484~~~~~~~~~~~~ 485 486The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 487EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 488loaded at a platform-specific base address (more information can be found later 489in this document). The functionality implemented by BL31 is as follows. 490 491Architectural initialization 492^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 493 494Currently, BL31 performs a similar architectural initialization to BL1 as 495far as system register settings are concerned. Since BL1 code resides in ROM, 496architectural initialization in BL31 allows override of any previous 497initialization done by BL1. 498 499BL31 initializes the per-CPU data framework, which provides a cache of 500frequently accessed per-CPU data optimised for fast, concurrent manipulation 501on different CPUs. This buffer includes pointers to per-CPU contexts, crash 502buffer, CPU reset and power down operations, PSCI data, platform data and so on. 503 504It then replaces the exception vectors populated by BL1 with its own. BL31 505exception vectors implement more elaborate support for handling SMCs since this 506is the only mechanism to access the runtime services implemented by BL31 (PSCI 507for example). BL31 checks each SMC for validity as specified by the 508`SMC Calling Convention`_ before passing control to the required SMC 509handler routine. 510 511BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 512counter, which is provided by the platform. 513 514Platform initialization 515^^^^^^^^^^^^^^^^^^^^^^^ 516 517BL31 performs detailed platform initialization, which enables normal world 518software to function correctly. 519 520On Arm platforms, this consists of the following: 521 522- Initialize the console. 523- Configure the Interconnect to enable hardware coherency. 524- Enable the MMU and map the memory it needs to access. 525- Initialize the generic interrupt controller. 526- Initialize the power controller device. 527- Detect the system topology. 528 529Runtime services initialization 530^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 531 532BL31 is responsible for initializing the runtime services. One of them is PSCI. 533 534As part of the PSCI initializations, BL31 detects the system topology. It also 535initializes the data structures that implement the state machine used to track 536the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 537``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 538that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 539initializes the locks that protect them. BL31 accesses the state of a CPU or 540cluster immediately after reset and before the data cache is enabled in the 541warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 542therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 543 544The runtime service framework and its initialization is described in more 545detail in the "EL3 runtime services framework" section below. 546 547Details about the status of the PSCI implementation are provided in the 548"Power State Coordination Interface" section below. 549 550AArch64 BL32 (Secure-EL1 Payload) image initialization 551^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 552 553If a BL32 image is present then there must be a matching Secure-EL1 Payload 554Dispatcher (SPD) service (see later for details). During initialization 555that service must register a function to carry out initialization of BL32 556once the runtime services are fully initialized. BL31 invokes such a 557registered function to initialize BL32 before running BL33. This initialization 558is not necessary for AArch32 SPs. 559 560Details on BL32 initialization and the SPD's role are described in the 561:ref:`firmware_design_sel1_spd` section below. 562 563BL33 (Non-trusted Firmware) execution 564^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 565 566EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 567world cold boot, ensuring that no secure state information finds its way into 568the non-secure execution state. EL3 Runtime Software uses the entrypoint 569information provided by BL2 to jump to the Non-trusted firmware image (BL33) 570at the highest available Exception Level (EL2 if available, otherwise EL1). 571 572Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 573~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 574 575Some platforms have existing implementations of Trusted Boot Firmware that 576would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 577firmware architecture it is important to provide a fully documented and stable 578interface between the Trusted Boot Firmware and BL31. 579 580Future changes to the BL31 interface will be done in a backwards compatible 581way, and this enables these firmware components to be independently enhanced/ 582updated to develop and exploit new functionality. 583 584Required CPU state when calling ``bl31_entrypoint()`` during cold boot 585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 586 587This function must only be called by the primary CPU. 588 589On entry to this function the calling primary CPU must be executing in AArch64 590EL3, little-endian data access, and all interrupt sources masked: 591 592:: 593 594 PSTATE.EL = 3 595 PSTATE.RW = 1 596 PSTATE.DAIF = 0xf 597 SCTLR_EL3.EE = 0 598 599X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 600platform code in BL31: 601 602:: 603 604 X0 : Reserved for common TF-A information 605 X1 : Platform specific information 606 607BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 608these will be zero filled prior to invoking platform setup code. 609 610Use of the X0 and X1 parameters 611''''''''''''''''''''''''''''''' 612 613The parameters are platform specific and passed from ``bl31_entrypoint()`` to 614``bl31_early_platform_setup()``. The value of these parameters is never directly 615used by the common BL31 code. 616 617Legacy platforms may still pass a ``bl31_params`` structure in ``X0``, while TL 618adopted platforms may use Transfer List; both are platform-specific. 619 620MMU, Data caches & Coherency 621'''''''''''''''''''''''''''' 622 623BL31 does not depend on the enabled state of the MMU, data caches or 624interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 625on entry, these should be enabled during ``bl31_plat_arch_setup()``. 626 627Data structures used in the BL31 cold boot interface 628'''''''''''''''''''''''''''''''''''''''''''''''''''' 629 630In the cold boot flow, ``entry_point_info`` is used to represent the execution 631state of an image; that is, the state of general purpose registers, PC, and 632SPSR. 633 634There are two variants of this structure, for AArch64: 635 636.. code:: c 637 638 typedef struct entry_point_info { 639 param_header_t h; 640 uintptr_t pc; 641 uint32_t spsr; 642 643 aapcs64_params_t args; 644 } 645 646and, AArch32: 647 648.. code:: c 649 650 typedef struct entry_point_info { 651 param_header_t h; 652 uintptr_t pc; 653 uint32_t spsr; 654 655 uintptr_t lr_svc; 656 aapcs32_params_t args; 657 } entry_point_info_t; 658 659These structures are designed to support compatibility and independent 660evolution of the structures and the firmware images. For example, a version of 661BL31 that can interpret the BL3x image information from different versions of 662BL2, a platform that uses an extended entry_point_info structure to convey 663additional register information to BL31, or a ELF image loader that can convey 664more details about the firmware images. 665 666To support these scenarios the structures are versioned and sized, which enables 667BL31 to detect which information is present and respond appropriately. The 668``param_header`` is defined to capture this information: 669 670.. code:: c 671 672 typedef struct param_header { 673 uint8_t type; /* type of the structure */ 674 uint8_t version; /* version of this structure */ 675 uint16_t size; /* size of this structure in bytes */ 676 uint32_t attr; /* attributes */ 677 } param_header_t; 678 679In `entry_point_info`, Bits 0 and 5 of ``attr`` field are used to encode the 680security state; in other words, whether the image is to be executed in Secure, 681Non-Secure, or Realm mode. 682 683Other structures using this format are ``image_info`` and ``bl31_params``. The 684code that allocates and populates these structures must set the header fields 685appropriately, the ``SET_PARAM_HEAD()`` macro is defined to simplify this 686action. 687 688Required CPU state for BL31 Warm boot initialization 689^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 690 691When requesting a CPU power-on, or suspending a running CPU, TF-A provides 692the platform power management code with a Warm boot initialization 693entry-point, to be invoked by the CPU immediately after the reset handler. 694On entry to the Warm boot initialization function the calling CPU must be in 695AArch64 EL3, little-endian data access and all interrupt sources masked: 696 697:: 698 699 PSTATE.EL = 3 700 PSTATE.RW = 1 701 PSTATE.DAIF = 0xf 702 SCTLR_EL3.EE = 0 703 704The PSCI implementation will initialize the processor state and ensure that the 705platform power management code is then invoked as required to initialize all 706necessary system, cluster and CPU resources. 707 708AArch32 EL3 Runtime Software entrypoint interface 709~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 710 711To enable this firmware architecture it is important to provide a fully 712documented and stable interface between the Trusted Boot Firmware and the 713AArch32 EL3 Runtime Software. 714 715Future changes to the entrypoint interface will be done in a backwards 716compatible way, and this enables these firmware components to be independently 717enhanced/updated to develop and exploit new functionality. 718 719Required CPU state when entering during cold boot 720^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 721 722This function must only be called by the primary CPU. 723 724On entry to this function the calling primary CPU must be executing in AArch32 725EL3, little-endian data access, and all interrupt sources masked: 726 727:: 728 729 PSTATE.AIF = 0x7 730 SCTLR.EE = 0 731 732R0 and R1 are used to pass information from the Trusted Boot Firmware to the 733platform code in AArch32 EL3 Runtime Software: 734 735:: 736 737 R0 : Reserved for common TF-A information 738 R1 : Platform specific information 739 740Use of the R0 and R1 parameters 741''''''''''''''''''''''''''''''' 742 743The parameters are platform specific and the convention is that ``R0`` conveys 744information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 745can be used for other platform specific purpose. This convention allows 746platforms which use TF-A's BL1 and BL2 images to transfer additional platform 747specific information from Secure Boot without conflicting with future 748evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 749 750The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 751information can be obtained in a platform defined manner, e.g. compiled into 752the AArch32 EL3 Runtime Software, or provided in a platform defined memory 753location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 754via the Cold boot Initialization parameters. This data may need to be cleaned 755out of the CPU caches if it is provided by an earlier boot stage and then 756accessed by AArch32 EL3 Runtime Software before the caches are enabled. 757 758When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 759``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 760Software platform code. 761 762MMU, Data caches & Coherency 763'''''''''''''''''''''''''''' 764 765AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 766data caches or interconnect coherency in its entrypoint. They must be explicitly 767enabled if required. 768 769Data structures used in cold boot interface 770''''''''''''''''''''''''''''''''''''''''''' 771 772The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 773of ``bl31_params``. The ``bl_params`` structure is based on the convention 774described in AArch64 BL31 cold boot interface section. 775 776Required CPU state for warm boot initialization 777^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 778 779When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 780Runtime Software must ensure execution of a warm boot initialization entrypoint. 781If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 782then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 783boot entrypoint by arranging for the BL1 platform function, 784plat_get_my_entrypoint(), to return a non-zero value. 785 786In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 787data access and all interrupt sources masked: 788 789:: 790 791 PSTATE.AIF = 0x7 792 SCTLR.EE = 0 793 794The warm boot entrypoint may be implemented by using TF-A 795``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 796the pre-requisites mentioned in the :ref:`Porting Guide`. 797 798EL3 runtime services framework 799------------------------------ 800 801Software executing in the non-secure state and in the secure state at exception 802levels lower than EL3 will request runtime services using the Secure Monitor 803Call (SMC) instruction. These requests will follow the convention described in 804the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 805identifiers to each SMC request and describes how arguments are passed and 806returned. 807 808The EL3 runtime services framework enables the development of services by 809different providers that can be easily integrated into final product firmware. 810The following sections describe the framework which facilitates the 811registration, initialization and use of runtime services in EL3 Runtime 812Software (BL31). 813 814The design of the runtime services depends heavily on the concepts and 815definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 816Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 817conventions. Please refer to that document for more detailed explanation of 818these terms. 819 820The following runtime services are expected to be implemented first. They have 821not all been instantiated in the current implementation. 822 823#. Standard service calls 824 825 This service is for management of the entire system. The Power State 826 Coordination Interface (`PSCI`_) is the first set of standard service calls 827 defined by Arm (see PSCI section later). 828 829#. Secure-EL1 Payload Dispatcher service 830 831 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 832 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 833 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 834 The Secure Monitor will make these world switches in response to SMCs. The 835 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 836 Application Call OEN ranges. 837 838 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 839 not defined by the `SMCCC`_ or any other standard. As a result, each 840 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 841 service - within TF-A this service is referred to as the Secure-EL1 Payload 842 Dispatcher (SPD). 843 844 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 845 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 846 :ref:`firmware_design_sel1_spd` section below. 847 848#. CPU implementation service 849 850 This service will provide an interface to CPU implementation specific 851 services for a given platform e.g. access to processor errata workarounds. 852 This service is currently unimplemented. 853 854Additional services for Arm Architecture, SiP and OEM calls can be implemented. 855Each implemented service handles a range of SMC function identifiers as 856described in the `SMCCC`_. 857 858Registration 859~~~~~~~~~~~~ 860 861A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 862the name of the service, the range of OENs covered, the type of service and 863initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 864This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 865the framework to find all service descriptors included into BL31. 866 867The specific service for a SMC Function is selected based on the OEN and call 868type of the Function ID, and the framework uses that information in the service 869descriptor to identify the handler for the SMC Call. 870 871The service descriptors do not include information to identify the precise set 872of SMC function identifiers supported by this service implementation, the 873security state from which such calls are valid nor the capability to support 87464-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 875to these aspects of a SMC call is the responsibility of the service 876implementation, the framework is focused on integration of services from 877different providers and minimizing the time taken by the framework before the 878service handler is invoked. 879 880Details of the parameters, requirements and behavior of the initialization and 881call handling functions are provided in the following sections. 882 883Initialization 884~~~~~~~~~~~~~~ 885 886``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 887framework running on the primary CPU during cold boot as part of the BL31 888initialization. This happens prior to initializing a Trusted OS and running 889Normal world boot firmware that might in turn use these services. 890Initialization involves validating each of the declared runtime service 891descriptors, calling the service initialization function and populating the 892index used for runtime lookup of the service. 893 894The BL31 linker script collects all of the declared service descriptors into a 895single array and defines symbols that allow the framework to locate and traverse 896the array, and determine its size. 897 898The framework does basic validation of each descriptor to halt firmware 899initialization if service declaration errors are detected. The framework does 900not check descriptors for the following error conditions, and may behave in an 901unpredictable manner under such scenarios: 902 903#. Overlapping OEN ranges 904#. Multiple descriptors for the same range of OENs and ``call_type`` 905#. Incorrect range of owning entity numbers for a given ``call_type`` 906 907Once validated, the service ``init()`` callback is invoked. This function carries 908out any essential EL3 initialization before servicing requests. The ``init()`` 909function is only invoked on the primary CPU during cold boot. If the service 910uses per-CPU data this must either be initialized for all CPUs during this call, 911or be done lazily when a CPU first issues an SMC call to that service. If 912``init()`` returns anything other than ``0``, this is treated as an initialization 913error and the service is ignored: this does not cause the firmware to halt. 914 915The OEN and call type fields present in the SMC Function ID cover a total of 916128 distinct services, but in practice a single descriptor can cover a range of 917OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 918service handler, the framework uses an array of 128 indices that map every 919distinct OEN/call-type combination either to one of the declared services or to 920indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 921populated for all of the OENs covered by a service after the service ``init()`` 922function has reported success. So a service that fails to initialize will never 923have it's ``handle()`` function invoked. 924 925The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 926Function ID call type and OEN onto a specific service handler in the 927``rt_svc_descs[]`` array. 928 929|Image 1| 930 931.. _handling-an-smc: 932 933Handling an SMC 934~~~~~~~~~~~~~~~ 935 936When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 937Function ID is passed in W0 from the lower exception level (as per the 938`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 939SMC Function which indicates the SMC64 calling convention: such calls are 940ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 941in R0/X0. 942 943Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 944Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 945resulting value might indicate a service that has no handler, in this case the 946framework will also report an Unknown SMC Function ID. Otherwise, the value is 947used as a further index into the ``rt_svc_descs[]`` array to locate the required 948service and handler. 949 950The service's ``handle()`` callback is provided with five of the SMC parameters 951directly, the others are saved into memory for retrieval (if needed) by the 952handler. The handler is also provided with an opaque ``handle`` for use with the 953supporting library for parameter retrieval, setting return values and context 954manipulation. The ``flags`` parameter indicates the security state of the caller 955and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 956up the execution stack for the handler, and invokes the services ``handle()`` 957function. 958 959On return from the handler the result registers are populated in X0-X7 as needed 960before restoring the stack and CPU state and returning from the original SMC. 961 962Exception Handling Framework 963---------------------------- 964 965Please refer to the :ref:`Exception Handling Framework` document. 966 967Power State Coordination Interface 968---------------------------------- 969 970TODO: Provide design walkthrough of PSCI implementation. 971 972The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 973mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 974`PSCI`_ are implemented. The table lists the PSCI v1.1 APIs and their support 975in generic code. 976 977An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 978requires the platform to export a part of the implementation. Hence the level 979of support of the mandatory APIs depends upon the support exported by the 980platform port as well. The Juno and FVP (all variants) platforms export all the 981required support. 982 983+-----------------------------+-------------+-------------------------------+ 984| PSCI v1.1 API | Supported | Comments | 985+=============================+=============+===============================+ 986| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 987+-----------------------------+-------------+-------------------------------+ 988| ``CPU_SUSPEND`` | Yes\* | | 989+-----------------------------+-------------+-------------------------------+ 990| ``CPU_OFF`` | Yes\* | | 991+-----------------------------+-------------+-------------------------------+ 992| ``CPU_ON`` | Yes\* | | 993+-----------------------------+-------------+-------------------------------+ 994| ``AFFINITY_INFO`` | Yes | | 995+-----------------------------+-------------+-------------------------------+ 996| ``MIGRATE`` | Yes\*\* | | 997+-----------------------------+-------------+-------------------------------+ 998| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 999+-----------------------------+-------------+-------------------------------+ 1000| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1001+-----------------------------+-------------+-------------------------------+ 1002| ``SYSTEM_OFF`` | Yes\* | | 1003+-----------------------------+-------------+-------------------------------+ 1004| ``SYSTEM_RESET`` | Yes\* | | 1005+-----------------------------+-------------+-------------------------------+ 1006| ``PSCI_FEATURES`` | Yes | | 1007+-----------------------------+-------------+-------------------------------+ 1008| ``CPU_FREEZE`` | No | | 1009+-----------------------------+-------------+-------------------------------+ 1010| ``CPU_DEFAULT_SUSPEND`` | No | | 1011+-----------------------------+-------------+-------------------------------+ 1012| ``NODE_HW_STATE`` | Yes\* | | 1013+-----------------------------+-------------+-------------------------------+ 1014| ``SYSTEM_SUSPEND`` | Yes\* | | 1015+-----------------------------+-------------+-------------------------------+ 1016| ``PSCI_SET_SUSPEND_MODE`` | No | | 1017+-----------------------------+-------------+-------------------------------+ 1018| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1019+-----------------------------+-------------+-------------------------------+ 1020| ``PSCI_STAT_COUNT`` | Yes\* | | 1021+-----------------------------+-------------+-------------------------------+ 1022| ``SYSTEM_RESET2`` | Yes\* | | 1023+-----------------------------+-------------+-------------------------------+ 1024| ``MEM_PROTECT`` | Yes\* | | 1025+-----------------------------+-------------+-------------------------------+ 1026| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1027+-----------------------------+-------------+-------------------------------+ 1028 1029\*Note : These PSCI APIs require platform power management hooks to be 1030registered with the generic PSCI code to be supported. 1031 1032\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1033hooks to be registered with the generic PSCI code to be supported. 1034 1035The PSCI implementation in TF-A is a library which can be integrated with 1036AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1037integrating the PSCI library for EL3 Runtime Software can be found 1038at :ref:`Porting Guide`. 1039 1040DSU driver 1041---------- 1042 1043Platforms that include a DSU (DynamIQ Shared Unit) can define 1044the ``USE_DSU_DRIVER`` build flag to enable the DSU driver. 1045This driver is responsible for configuring DSU-related powerdown 1046and power feature settings, enabling access to PMU registers at EL1 1047using ``dsu_driver_init()`` and for preserving the context of DSU 1048PMU system registers. 1049 1050To support the DSU driver, platforms must define the ``plat_dsu_data`` 1051structure. 1052 1053.. _firmware_design_sel1_spd: 1054 1055Secure-EL1 Payloads and Dispatchers 1056----------------------------------- 1057 1058On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1059the Trusted OS is coupled with a companion runtime service in the BL31 1060firmware. This service is responsible for the initialisation of the Trusted 1061OS and all communications with it. The Trusted OS is the BL32 stage of the 1062boot flow in TF-A. The firmware will attempt to locate, load and execute a 1063BL32 image. 1064 1065TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1066the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1067 1068TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1069Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1070production system using the Runtime Services Framework. On such a system, the 1071Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1072service. The TF-A build system expects that the dispatcher will define the 1073build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1074as a binary or to compile from source depending on whether the ``BL32`` build 1075option is specified or not. 1076 1077The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1078communication with the normal-world software running in EL1/EL2. Communication 1079is initiated by the normal-world software 1080 1081- either directly through a Fast SMC (as defined in the `SMCCC`_) 1082 1083- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1084 informs the TSPD about the requested power management operation. This allows 1085 the TSP to prepare for or respond to the power state change 1086 1087The TSPD service is responsible for. 1088 1089- Initializing the TSP 1090 1091- Routing requests and responses between the secure and the non-secure 1092 states during the two types of communications just described 1093 1094Initializing a BL32 Image 1095~~~~~~~~~~~~~~~~~~~~~~~~~ 1096 1097The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1098the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1099so. This is provided by: 1100 1101.. code:: c 1102 1103 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1104 1105which returns a reference to the ``entry_point_info`` structure corresponding to 1106the image which will be run in the specified security state. The SPD uses this 1107API to get entry point information for the SECURE image, BL32. 1108 1109In the absence of a BL32 image, BL31 passes control to the normal world 1110bootloader image (BL33). When the BL32 image is present, it is typical 1111that the SPD wants control to be passed to BL32 first and then later to BL33. 1112 1113To do this the SPD has to register a BL32 initialization function during 1114initialization of the SPD service. The BL32 initialization function has this 1115prototype: 1116 1117.. code:: c 1118 1119 int32_t init(void); 1120 1121and is registered using the ``bl31_register_bl32_init()`` function. 1122 1123TF-A supports two approaches for the SPD to pass control to BL32 before 1124returning through EL3 and running the non-trusted firmware (BL33): 1125 1126#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1127 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1128 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1129 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1130 1131 When the BL32 has completed initialization at Secure-EL1, it returns to 1132 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1133 receipt of this SMC, the SPD service handler should switch the CPU context 1134 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1135 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1136 the normal world firmware BL33. On return from the handler the framework 1137 will exit to EL2 and run BL33. 1138 1139#. The BL32 setup function registers an initialization function using 1140 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1141 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1142 entrypoint. 1143 1144 .. note:: 1145 The Test SPD service included with TF-A provides one implementation 1146 of such a mechanism. 1147 1148 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1149 SPD service handler invokes the synchronous call return mechanism to return 1150 to the BL32 initialization function. On return from this function, 1151 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1152 continue the boot process in the normal world. 1153 1154Exception handling in BL31 1155-------------------------- 1156 1157When exception occurs, PE must execute handler corresponding to exception. The 1158location in memory where the handler is stored is called the exception vector. 1159For ARM architecture, exception vectors are stored in a table, called the exception 1160vector table. 1161 1162Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base 1163of vector table. Refer to `AArch64 exception vector table`_ 1164 1165Current EL with SP_EL0 1166~~~~~~~~~~~~~~~~~~~~~~ 1167 1168- Sync exception : Not expected except for BRK instruction, its debugging tool which 1169 a programmer may place at specific points in a program, to check the state of 1170 processor flags at these points in the code. 1171 1172- IRQ/FIQ : Unexpected exception, panic 1173 1174- SError : "plat_handle_el3_ea", defaults to panic 1175 1176Current EL with SP_ELx 1177~~~~~~~~~~~~~~~~~~~~~~ 1178 1179- Sync exception : Unexpected exception, panic 1180 1181- IRQ/FIQ : Unexpected exception, panic 1182 1183- SError : "plat_handle_el3_ea" Except for special handling of lower EL's SError exception 1184 which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower 1185 EL's EA is routed to EL3 (FFH_SUPPORT=1). 1186 1187Lower EL Exceptions 1188~~~~~~~~~~~~~~~~~~~ 1189 1190Applies to all the exceptions in both AArch64/AArch32 mode of lower EL. 1191 1192Before handling any lower EL exception, we synchronize the errors at EL3 entry to ensure 1193that any errors pertaining to lower EL is isolated/identified. If we continue without 1194identifying these errors early on then these errors will trigger in EL3 (as SError from 1195current EL) any time after PSTATE.A is unmasked. This is wrong because the error originated 1196in lower EL but exception happened in EL3. 1197 1198To solve this problem, synchronize the errors at EL3 entry and check for any pending 1199errors (async EA). If there is no pending error then continue with original exception. 1200If there is a pending error then, handle them based on routing model of EA's. Refer to 1201:ref:`Reliability, Availability, and Serviceability (RAS) Extensions` for details about 1202routing models. 1203 1204- KFH : Reflect it back to lower EL using **reflect_pending_async_ea_to_lower_el()** 1205 1206- FFH : Handle the synchronized error first using **handle_pending_async_ea()** after 1207 that continue with original exception. It is the only scenario where EL3 is capable 1208 of doing nested exception handling. 1209 1210After synchronizing and handling lower EL SErrors, unmask EA (PSTATE.A) to ensure 1211that any further EA's caused by EL3 are caught. 1212 1213Crash Reporting in BL31 1214----------------------- 1215 1216BL31 implements a scheme for reporting the processor state when an unhandled 1217exception is encountered. The reporting mechanism attempts to preserve all the 1218register contents and report it via a dedicated UART (PL011 console). BL31 1219reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1220 1221A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1222the per-CPU pointer cache. The implementation attempts to minimise the memory 1223required for this feature. The file ``crash_reporting.S`` contains the 1224implementation for crash reporting. 1225 1226The sample crash output is shown below. 1227 1228:: 1229 1230 x0 = 0x000000002a4a0000 1231 x1 = 0x0000000000000001 1232 x2 = 0x0000000000000002 1233 x3 = 0x0000000000000003 1234 x4 = 0x0000000000000004 1235 x5 = 0x0000000000000005 1236 x6 = 0x0000000000000006 1237 x7 = 0x0000000000000007 1238 x8 = 0x0000000000000008 1239 x9 = 0x0000000000000009 1240 x10 = 0x0000000000000010 1241 x11 = 0x0000000000000011 1242 x12 = 0x0000000000000012 1243 x13 = 0x0000000000000013 1244 x14 = 0x0000000000000014 1245 x15 = 0x0000000000000015 1246 x16 = 0x0000000000000016 1247 x17 = 0x0000000000000017 1248 x18 = 0x0000000000000018 1249 x19 = 0x0000000000000019 1250 x20 = 0x0000000000000020 1251 x21 = 0x0000000000000021 1252 x22 = 0x0000000000000022 1253 x23 = 0x0000000000000023 1254 x24 = 0x0000000000000024 1255 x25 = 0x0000000000000025 1256 x26 = 0x0000000000000026 1257 x27 = 0x0000000000000027 1258 x28 = 0x0000000000000028 1259 x29 = 0x0000000000000029 1260 x30 = 0x0000000088000b78 1261 scr_el3 = 0x000000000003073d 1262 sctlr_el3 = 0x00000000b0cd183f 1263 cptr_el3 = 0x0000000000000000 1264 tcr_el3 = 0x000000008080351c 1265 daif = 0x00000000000002c0 1266 mair_el3 = 0x00000000004404ff 1267 spsr_el3 = 0x0000000060000349 1268 elr_el3 = 0x0000000088000114 1269 ttbr0_el3 = 0x0000000004018201 1270 esr_el3 = 0x00000000be000000 1271 far_el3 = 0x0000000000000000 1272 spsr_el1 = 0x0000000000000000 1273 elr_el1 = 0x0000000000000000 1274 spsr_abt = 0x0000000000000000 1275 spsr_und = 0x0000000000000000 1276 spsr_irq = 0x0000000000000000 1277 spsr_fiq = 0x0000000000000000 1278 sctlr_el1 = 0x0000000030d00800 1279 actlr_el1 = 0x0000000000000000 1280 cpacr_el1 = 0x0000000000000000 1281 csselr_el1 = 0x0000000000000000 1282 sp_el1 = 0x0000000000000000 1283 esr_el1 = 0x0000000000000000 1284 ttbr0_el1 = 0x0000000000000000 1285 ttbr1_el1 = 0x0000000000000000 1286 mair_el1 = 0x0000000000000000 1287 amair_el1 = 0x0000000000000000 1288 tcr_el1 = 0x0000000000000000 1289 tpidr_el1 = 0x0000000000000000 1290 tpidr_el0 = 0x0000000000000000 1291 tpidrro_el0 = 0x0000000000000000 1292 par_el1 = 0x0000000000000000 1293 mpidr_el1 = 0x0000000080000000 1294 afsr0_el1 = 0x0000000000000000 1295 afsr1_el1 = 0x0000000000000000 1296 contextidr_el1 = 0x0000000000000000 1297 vbar_el1 = 0x0000000000000000 1298 cntp_ctl_el0 = 0x0000000000000000 1299 cntp_cval_el0 = 0x0000000000000000 1300 cntv_ctl_el0 = 0x0000000000000000 1301 cntv_cval_el0 = 0x0000000000000000 1302 cntkctl_el1 = 0x0000000000000000 1303 sp_el0 = 0x0000000004014940 1304 isr_el1 = 0x0000000000000000 1305 dacr32_el2 = 0x0000000000000000 1306 ifsr32_el2 = 0x0000000000000000 1307 icc_hppir0_el1 = 0x00000000000003ff 1308 icc_hppir1_el1 = 0x00000000000003ff 1309 icc_ctlr_el3 = 0x0000000000080400 1310 gicd_ispendr regs (Offsets 0x200-0x278) 1311 Offset Value 1312 0x200: 0x0000000000000000 1313 0x208: 0x0000000000000000 1314 0x210: 0x0000000000000000 1315 0x218: 0x0000000000000000 1316 0x220: 0x0000000000000000 1317 0x228: 0x0000000000000000 1318 0x230: 0x0000000000000000 1319 0x238: 0x0000000000000000 1320 0x240: 0x0000000000000000 1321 0x248: 0x0000000000000000 1322 0x250: 0x0000000000000000 1323 0x258: 0x0000000000000000 1324 0x260: 0x0000000000000000 1325 0x268: 0x0000000000000000 1326 0x270: 0x0000000000000000 1327 0x278: 0x0000000000000000 1328 1329Guidelines for Reset Handlers 1330----------------------------- 1331 1332TF-A implements a framework that allows CPU and platform ports to perform 1333actions very early after a CPU is released from reset in both the cold and warm 1334boot paths. This is done by calling the ``reset_handler`` macro/function in both 1335the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1336handling functions. 1337 1338Details for implementing a CPU specific reset handler can be found in 1339:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a 1340platform specific reset handler can be found in the :ref:`Porting Guide` (see 1341the``plat_reset_handler()`` function). 1342 1343When adding functionality to a reset handler, keep in mind that if a different 1344reset handling behavior is required between the first and the subsequent 1345invocations of the reset handling code, this should be detected at runtime. 1346In other words, the reset handler should be able to detect whether an action has 1347already been performed and act as appropriate. Possible courses of actions are, 1348e.g. skip the action the second time, or undo/redo it. 1349 1350.. _configuring-secure-interrupts: 1351 1352Configuring secure interrupts 1353----------------------------- 1354 1355The GIC driver is responsible for performing initial configuration of secure 1356interrupts on the platform. To this end, the platform is expected to provide the 1357GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1358interrupt configuration during the driver initialisation. 1359 1360Secure interrupt configuration are specified in an array of secure interrupt 1361properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1362``interrupt_props`` member points to an array of interrupt properties. Each 1363element of the array specifies the interrupt number and its attributes 1364(priority, group, configuration). Each element of the array shall be populated 1365by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1366 1367- 13-bit interrupt number, 1368 1369- 8-bit interrupt priority, 1370 1371- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1372 ``INTR_TYPE_NS``), 1373 1374- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1375 ``GIC_INTR_CFG_EDGE``). 1376 1377.. _firmware_design_cpu_ops_fwk: 1378 1379CPU specific operations framework 1380--------------------------------- 1381 1382Certain aspects of the Armv8-A architecture are implementation defined, 1383that is, certain behaviours are not architecturally defined, but must be 1384defined and documented by individual processor implementations. TF-A 1385implements a framework which categorises the common implementation defined 1386behaviours and allows a processor to export its implementation of that 1387behaviour. The categories are: 1388 1389#. Processor specific reset sequence. 1390 1391#. Processor specific power down sequences. 1392 1393#. Processor specific register dumping as a part of crash reporting. 1394 1395#. Errata status reporting. 1396 1397Each of the above categories fulfils a different requirement. 1398 1399#. allows any processor specific initialization before the caches and MMU 1400 are turned on, like implementation of errata workarounds, entry into 1401 the intra-cluster coherency domain etc. 1402 1403#. allows each processor to implement the power down sequence mandated in 1404 its Technical Reference Manual (TRM). 1405 1406#. allows a processor to provide additional information to the developer 1407 in the event of a crash, for example Cortex-A53 has registers which 1408 can expose the data cache contents. 1409 1410#. allows a processor to define a function that inspects and reports the status 1411 of all errata workarounds on that processor. 1412 1413Please note that only 2. is mandated by the TRM. 1414 1415The CPU specific operations framework scales to accommodate a large number of 1416different CPUs during power down and reset handling. The platform can specify 1417any CPU optimization it wants to enable for each CPU. It can also specify 1418the CPU errata workarounds to be applied for each CPU type during reset 1419handling by defining CPU errata compile time macros. Details on these macros 1420can be found in the :ref:`Arm CPU Specific Build Macros` document. 1421 1422The CPU specific operations framework depends on the ``cpu_ops`` structure which 1423needs to be exported for each type of CPU in the platform. It is defined in 1424``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1425``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1426``cpu_reg_dump()``. 1427 1428The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1429suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1430exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1431configuration, these CPU specific files must be included in the build by 1432the platform makefile. The generic CPU specific operations framework code exists 1433in ``lib/cpus/aarch64/cpu_helpers.S``. 1434 1435CPU PCS 1436~~~~~~~ 1437 1438All assembly functions in CPU files are asked to follow a modified version of 1439the Procedure Call Standard (PCS) in their internals. This is done to ensure 1440calling these functions from outside the file doesn't unexpectedly corrupt 1441registers in the very early environment and to help the internals to be easier 1442to understand. Please see the :ref:`firmware_design_cpu_errata_implementation` 1443for any function specific restrictions. 1444 1445+--------------+---------------------------------+ 1446| register | use | 1447+==============+=================================+ 1448| x0 - x15 | scratch | 1449+--------------+---------------------------------+ 1450| x16, x17 | do not use (used by the linker) | 1451+--------------+---------------------------------+ 1452| x18 | do not use (platform register) | 1453+--------------+---------------------------------+ 1454| x19 - x28 | callee saved | 1455+--------------+---------------------------------+ 1456| x29, x30 | FP, LR | 1457+--------------+---------------------------------+ 1458 1459.. _firmware_design_cpu_specific_reset_handling: 1460 1461CPU specific Reset Handling 1462~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1463 1464After a reset, the state of the CPU when it calls generic reset handler is: 1465MMU turned off, both instruction and data caches turned off, not part 1466of any coherency domain and no stack. 1467 1468The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1469the platform to perform any system initialization required and any system 1470errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1471the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1472array and returns it. Note that only the part number and implementer fields 1473in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1474the returned ``cpu_ops`` is then invoked which executes the required reset 1475handling for that CPU and also any errata workarounds enabled by the platform. 1476 1477It should be defined using the ``cpu_reset_func_{start,end}`` macros and its 1478body may only clobber x0 to x14 with x14 being the cpu_rev parameter. The cpu 1479file should also include a call to ``cpu_reset_prologue`` at the start of the 1480file for errata to work correctly. 1481 1482CPU specific power down sequence 1483~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1484 1485During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1486entry is stored in per-CPU data by ``cpu_data_init_cpu_ops()`` so that it can be quickly 1487retrieved during power down sequences. 1488 1489Various CPU drivers register handlers to perform power down at certain power 1490levels for that specific CPU. The PSCI service, upon receiving a power down 1491request, determines the highest power level at which to execute power down 1492sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1493pick the right power down handler for the requested level. The function 1494retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1495retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1496requested power level is higher than what a CPU driver supports, the handler 1497registered for highest level is invoked. 1498 1499At runtime the platform hooks for power down are invoked by the PSCI service to 1500perform platform specific operations during a power down sequence, for example 1501turning off CCI coherency during a cluster power down. 1502 1503Newer CPUs include a feature called "powerdown abandon". The feature is based on 1504the observation that events like GIC wakeups have a high likelihood of happening 1505while the core is in the middle of its powerdown sequence (at ``wfi``). Older 1506cores will powerdown and immediately power back up when this happens. To save on 1507the work and latency involved, the newer cores will "give up" mid way through if 1508no context has been lost yet. This is possible as the powerdown operation is 1509lengthy and a large part of it does not lose context. 1510 1511To cater for this possibility, the powerdown hook will be called a second time 1512after a wakeup. The expectation is that the first call will operate as before, 1513while the second call will undo anything the first call did. This should be done 1514statelessly, for example by toggling the relevant bits. 1515 1516CPU specific register reporting during crash 1517~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1518 1519If the crash reporting is enabled in BL31, when a crash occurs, the crash 1520reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1521``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1522``cpu_ops`` is invoked, which then returns the CPU specific register values to 1523be reported and a pointer to the ASCII list of register names in a format 1524expected by the crash reporting framework. 1525 1526.. _firmware_design_cpu_errata_implementation: 1527 1528CPU errata implementation 1529~~~~~~~~~~~~~~~~~~~~~~~~~ 1530 1531Errata workarounds for CPUs supported in TF-A are applied during both cold and 1532warm boots, shortly after reset. Individual Errata workarounds are enabled as 1533build options. Some errata workarounds have potential run-time implications; 1534therefore some are enabled by default, others not. Platform ports shall 1535override build options to enable or disable errata as appropriate. The CPU 1536drivers take care of applying errata workarounds that are enabled and applicable 1537to a given CPU. 1538 1539Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form: 1540``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in 1541:ref:`arm_cpu_macros_errata_workarounds` on when it should apply. 1542 1543Errata framework 1544^^^^^^^^^^^^^^^^ 1545 1546The errata framework is a convention and a small library to allow errata to be 1547automatically discovered. It enables compliant errata to be automatically 1548applied and reported at runtime (either by status reporting or the errata ABI). 1549 1550To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that 1551declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things: 1552 1553#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>`` 1554 1555 It should check whether this erratum applies on this revision of this CPU. 1556 It will be called with the CPU revision as its first parameter (x0) and 1557 should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``. 1558 1559 It may only clobber x0 to x4. The rest should be treated as callee-saved. 1560 1561#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa`` 1562 1563 It should obtain the cpu revision (with ``cpu_get_rev_var``), call its 1564 revision checker, and perform the mitigation, should the erratum apply. 1565 1566 It may only clobber x0 to x8. The rest should be treated as callee-saved. 1567 1568#. Register itself to the framework 1569 1570 Do this with 1571 ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>`` 1572 where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described 1573 above. 1574 1575See the next section on how to do this easily. 1576 1577.. note:: 1578 1579 CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the 1580 ``erratum_id`` for the checker and the workaround functions become the 1581 ``number`` part of its name and the ``ERRATUM(<number>)`` part of the 1582 registration should instead be ``CVE(<year>, <number>)``. In the extremely 1583 unlikely scenario where a CVE and an erratum numbers clash, the CVE number 1584 should be prefixed with a zero. 1585 1586 Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``. 1587 1588.. note:: 1589 1590 AArch32 uses the legacy convention. The checker function has the format 1591 ``check_errata_<erratum_id>`` and the workaround has the format 1592 ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform 1593 letter and number name of the CPU. 1594 1595 For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``. 1596 1597Errata framework helpers 1598^^^^^^^^^^^^^^^^^^^^^^^^ 1599 1600Writing these errata involves lots of boilerplate and repetitive code. On 1601AArch64 there are helpers to omit most of this. They are located in 1602``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement 1603errata. Please see their comments on how to use them. 1604 1605The most common type of erratum workaround, one that just sets a "chicken" bit 1606in some arbitrary register, would have an implementation for the Cortex-A77, 1607erratum #1925769 like:: 1608 1609 workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 1610 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 1611 workaround_reset_end cortex_a77, ERRATUM(1925769) 1612 1613 check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 1614 1615Status reporting 1616^^^^^^^^^^^^^^^^ 1617 1618In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1619runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic 1620errata status reporting function. It will read the ``errata_entries`` list of 1621that cpu and will report whether each known erratum was applied and, if not, 1622whether it should have been. 1623 1624Reporting the status of errata workaround is for informational purpose only; it 1625has no functional significance. 1626 1627Memory layout of BL images 1628-------------------------- 1629 1630Each bootloader image can be divided in 2 parts: 1631 1632- the static contents of the image. These are data actually stored in the 1633 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1634 sections; 1635 1636- the run-time contents of the image. These are data that don't occupy any 1637 space in the binary on the disk. The ELF binary just contains some 1638 metadata indicating where these data will be stored at run-time and the 1639 corresponding sections need to be allocated and initialized at run-time. 1640 In the ELF terminology, they are called ``NOBITS`` sections. 1641 1642All PROGBITS sections are grouped together at the beginning of the image, 1643followed by all NOBITS sections. This is true for all TF-A images and it is 1644governed by the linker scripts. This ensures that the raw binary images are 1645as small as possible. If a NOBITS section was inserted in between PROGBITS 1646sections then the resulting binary file would contain zero bytes in place of 1647this NOBITS section, making the image unnecessarily bigger. Smaller images 1648allow faster loading from the FIP to the main memory. 1649 1650For BL31, a platform can specify an alternate location for NOBITS sections 1651(other than immediately following PROGBITS sections) by setting 1652``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1653``BL31_NOBITS_LIMIT``. 1654 1655Linker scripts and symbols 1656~~~~~~~~~~~~~~~~~~~~~~~~~~ 1657 1658Each bootloader stage image layout is described by its own linker script. The 1659linker scripts export some symbols into the program symbol table. Their values 1660correspond to particular addresses. TF-A code can refer to these symbols to 1661figure out the image memory layout. 1662 1663Linker symbols follow the following naming convention in TF-A. 1664 1665- ``__<SECTION>_START__`` 1666 1667 Start address of a given section named ``<SECTION>``. 1668 1669- ``__<SECTION>_END__`` 1670 1671 End address of a given section named ``<SECTION>``. If there is an alignment 1672 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1673 to the end address of the section's actual contents, rounded up to the right 1674 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1675 actual end address of the section's contents. 1676 1677- ``__<SECTION>_UNALIGNED_END__`` 1678 1679 End address of a given section named ``<SECTION>`` without any padding or 1680 rounding up due to some alignment constraint. 1681 1682- ``__<SECTION>_SIZE__`` 1683 1684 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1685 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1686 corresponds to the size of the section's actual contents, rounded up to the 1687 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1688 to know the actual size of the section's contents. 1689 1690- ``__<SECTION>_UNALIGNED_SIZE__`` 1691 1692 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1693 rounding up due to some alignment constraint. In other words, 1694 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1695 1696Some of the linker symbols are mandatory as TF-A code relies on them to be 1697defined. They are listed in the following subsections. Some of them must be 1698provided for each bootloader stage and some are specific to a given bootloader 1699stage. 1700 1701The linker scripts define some extra, optional symbols. They are not actually 1702used by any code but they help in understanding the bootloader images' memory 1703layout as they are easy to spot in the link map files. 1704 1705Common linker symbols 1706^^^^^^^^^^^^^^^^^^^^^ 1707 1708All BL images share the following requirements: 1709 1710- The BSS section must be zero-initialised before executing any C code. 1711- The coherent memory section (if enabled) must be zero-initialised as well. 1712- The MMU setup code needs to know the extents of the coherent and read-only 1713 memory regions to set the right memory attributes. When 1714 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1715 read-only memory region is divided between code and data. 1716 1717The following linker symbols are defined for this purpose: 1718 1719- ``__BSS_START__`` 1720- ``__BSS_SIZE__`` 1721- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1722- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1723- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1724- ``__RO_START__`` 1725- ``__RO_END__`` 1726- ``__TEXT_START__`` 1727- ``__TEXT_END_UNALIGNED__`` 1728- ``__TEXT_END__`` 1729- ``__RODATA_START__`` 1730- ``__RODATA_END_UNALIGNED__`` 1731- ``__RODATA_END__`` 1732 1733BL1's linker symbols 1734^^^^^^^^^^^^^^^^^^^^ 1735 1736BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1737it is entirely executed in place but it needs some read-write memory for its 1738mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1739relocated from ROM to RAM before executing any C code. 1740 1741The following additional linker symbols are defined for BL1: 1742 1743- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1744 and ``.data`` section in ROM. 1745- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1746 aligned on a 16-byte boundary. 1747- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1748 copied over. Must be aligned on a 16-byte boundary. 1749- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1750- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1751- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1752 1753How to choose the right base addresses for each bootloader stage image 1754~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1755 1756There is currently no support for dynamic image loading in TF-A. This means 1757that all bootloader images need to be linked against their ultimate runtime 1758locations and the base addresses of each image must be chosen carefully such 1759that images don't overlap each other in an undesired way. As the code grows, 1760the base addresses might need adjustments to cope with the new memory layout. 1761 1762The memory layout is completely specific to the platform and so there is no 1763general recipe for choosing the right base addresses for each bootloader image. 1764However, there are tools to aid in understanding the memory layout. These are 1765the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1766being the stage bootloader. They provide a detailed view of the memory usage of 1767each image. Among other useful information, they provide the end address of 1768each image. 1769 1770- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1771- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1772- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1773- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1774 1775For each bootloader image, the platform code must provide its start address 1776as well as a limit address that it must not overstep. The latter is used in the 1777linker scripts to check that the image doesn't grow past that address. If that 1778happens, the linker will issue a message similar to the following: 1779 1780:: 1781 1782 aarch64-none-elf-ld: BLx has exceeded its limit. 1783 1784Additionally, if the platform memory layout implies some image overlaying like 1785on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1786sections must not overstep. The platform code must provide those. 1787 1788TF-A does not provide any mechanism to verify at boot time that the memory 1789to load a new image is free to prevent overwriting a previously loaded image. 1790The platform must specify the memory available in the system for all the 1791relevant BL images to be loaded. 1792 1793For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1794return the region defined by the platform where BL1 intends to load BL2. The 1795``load_image()`` function performs bounds check for the image size based on the 1796base and maximum image size provided by the platforms. Platforms must take 1797this behaviour into account when defining the base/size for each of the images. 1798 1799Memory layout on Arm development platforms 1800^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1801 1802The following list describes the memory layout on the Arm development platforms: 1803 1804- A 4KB page of shared memory is used for communication between Trusted 1805 Firmware and the platform's power controller. This is located at the base of 1806 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1807 images is reduced by the size of the shared memory. 1808 1809 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1810 this is also used for the MHU payload when passing messages to and from the 1811 SCP. 1812 1813- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1814 and also the dynamic firmware configurations. 1815 1816- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1817 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1818 data are relocated to the top of Trusted SRAM at runtime. 1819 1820- BL2 is loaded below BL1 RW 1821 1822- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1823 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1824 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1825 remain valid only until execution reaches the EL3 Runtime Software entry 1826 point during a cold boot. 1827 1828- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1829 region and transferred to the SCP before being overwritten by EL3 Runtime 1830 Software. 1831 1832- BL32 (for AArch64) can be loaded in one of the following locations: 1833 1834 - Trusted SRAM 1835 - Trusted DRAM (FVP only) 1836 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1837 controller) 1838 1839 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1840 BL31. 1841 1842The location of the BL32 image will result in different memory maps. This is 1843illustrated for both FVP and Juno in the following diagrams, using the TSP as 1844an example. 1845 1846.. note:: 1847 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1848 layout of the other images in Trusted SRAM. 1849 1850CONFIG section in memory layouts shown below contains: 1851 1852:: 1853 1854 +--------------------+ 1855 |bl2_mem_params_descs| 1856 |--------------------| 1857 | fw_configs | 1858 +--------------------+ 1859 1860``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1861BL image during boot. 1862 1863``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1864 1865**FVP with TSP in Trusted SRAM with firmware configs :** 1866(These diagrams only cover the AArch64 case) 1867 1868:: 1869 1870 DRAM 1871 0xffffffff +----------+ 1872 | EL3 TZC | 1873 0xffe00000 |----------| (secure) 1874 | AP TZC | 1875 0xff000000 +----------+ 1876 : : 1877 0x82100000 |----------| 1878 |HW_CONFIG | 1879 0x82000000 |----------| (non-secure) 1880 | | 1881 0x80000000 +----------+ 1882 1883 Trusted DRAM 1884 0x08000000 +----------+ 1885 |HW_CONFIG | 1886 0x07f00000 |----------| 1887 : : 1888 | | 1889 0x06000000 +----------+ 1890 1891 Trusted SRAM 1892 0x04040000 +----------+ loaded by BL2 +----------------+ 1893 | BL1 (rw) | <<<<<<<<<<<<< | | 1894 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1895 | BL2 | <<<<<<<<<<<<< | | 1896 |----------| <<<<<<<<<<<<< |----------------| 1897 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1898 | | <<<<<<<<<<<<< |----------------| 1899 | | <<<<<<<<<<<<< | BL32 | 1900 0x04003000 +----------+ +----------------+ 1901 | CONFIG | 1902 0x04001000 +----------+ 1903 | Shared | 1904 0x04000000 +----------+ 1905 1906 Trusted ROM 1907 0x04000000 +----------+ 1908 | BL1 (ro) | 1909 0x00000000 +----------+ 1910 1911**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1912 1913:: 1914 1915 DRAM 1916 0xffffffff +--------------+ 1917 | EL3 TZC | 1918 0xffe00000 |--------------| (secure) 1919 | AP TZC | 1920 0xff000000 +--------------+ 1921 : : 1922 0x82100000 |--------------| 1923 | HW_CONFIG | 1924 0x82000000 |--------------| (non-secure) 1925 | | 1926 0x80000000 +--------------+ 1927 1928 Trusted DRAM 1929 0x08000000 +--------------+ 1930 | HW_CONFIG | 1931 0x07f00000 |--------------| 1932 : : 1933 | BL32 | 1934 0x06000000 +--------------+ 1935 1936 Trusted SRAM 1937 0x04040000 +--------------+ loaded by BL2 +----------------+ 1938 | BL1 (rw) | <<<<<<<<<<<<< | | 1939 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1940 | BL2 | <<<<<<<<<<<<< | | 1941 |--------------| <<<<<<<<<<<<< |----------------| 1942 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1943 | | +----------------+ 1944 0x04003000 +--------------+ 1945 | CONFIG | 1946 0x04001000 +--------------+ 1947 | Shared | 1948 0x04000000 +--------------+ 1949 1950 Trusted ROM 1951 0x04000000 +--------------+ 1952 | BL1 (ro) | 1953 0x00000000 +--------------+ 1954 1955**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1956 1957:: 1958 1959 DRAM 1960 0xffffffff +----------+ 1961 | EL3 TZC | 1962 0xffe00000 |----------| (secure) 1963 | AP TZC | 1964 | (BL32) | 1965 0xff000000 +----------+ 1966 | | 1967 0x82100000 |----------| 1968 |HW_CONFIG | 1969 0x82000000 |----------| (non-secure) 1970 | | 1971 0x80000000 +----------+ 1972 1973 Trusted DRAM 1974 0x08000000 +----------+ 1975 |HW_CONFIG | 1976 0x7f000000 |----------| 1977 : : 1978 | | 1979 0x06000000 +----------+ 1980 1981 Trusted SRAM 1982 0x04040000 +----------+ loaded by BL2 +----------------+ 1983 | BL1 (rw) | <<<<<<<<<<<<< | | 1984 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1985 | BL2 | <<<<<<<<<<<<< | | 1986 |----------| <<<<<<<<<<<<< |----------------| 1987 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1988 | | +----------------+ 1989 0x04003000 +----------+ 1990 | CONFIG | 1991 0x04001000 +----------+ 1992 | Shared | 1993 0x04000000 +----------+ 1994 1995 Trusted ROM 1996 0x04000000 +----------+ 1997 | BL1 (ro) | 1998 0x00000000 +----------+ 1999 2000**Juno with BL32 in Trusted SRAM :** 2001 2002:: 2003 2004 DRAM 2005 0xFFFFFFFF +----------+ 2006 | SCP TZC | 2007 0xFFE00000 |----------| 2008 | EL3 TZC | 2009 0xFFC00000 |----------| (secure) 2010 | AP TZC | 2011 0xFF000000 +----------+ 2012 | | 2013 : : (non-secure) 2014 | | 2015 0x80000000 +----------+ 2016 2017 2018 Flash0 2019 0x0C000000 +----------+ 2020 : : 2021 0x0BED0000 |----------| 2022 | BL1 (ro) | 2023 0x0BEC0000 |----------| 2024 : : 2025 0x08000000 +----------+ BL31 is loaded 2026 after SCP_BL2 has 2027 Trusted SRAM been sent to SCP 2028 0x04040000 +----------+ loaded by BL2 +----------------+ 2029 | BL1 (rw) | <<<<<<<<<<<<< | | 2030 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2031 | BL2 | <<<<<<<<<<<<< | | 2032 |----------| <<<<<<<<<<<<< |----------------| 2033 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2034 | | <<<<<<<<<<<<< |----------------| 2035 | | <<<<<<<<<<<<< | BL32 | 2036 | | +----------------+ 2037 | | 2038 0x04001000 +----------+ 2039 | MHU | 2040 0x04000000 +----------+ 2041 2042**Juno with BL32 in TZC-secured DRAM :** 2043 2044:: 2045 2046 DRAM 2047 0xFFFFFFFF +----------+ 2048 | SCP TZC | 2049 0xFFE00000 |----------| 2050 | EL3 TZC | 2051 0xFFC00000 |----------| (secure) 2052 | AP TZC | 2053 | (BL32) | 2054 0xFF000000 +----------+ 2055 | | 2056 : : (non-secure) 2057 | | 2058 0x80000000 +----------+ 2059 2060 Flash0 2061 0x0C000000 +----------+ 2062 : : 2063 0x0BED0000 |----------| 2064 | BL1 (ro) | 2065 0x0BEC0000 |----------| 2066 : : 2067 0x08000000 +----------+ BL31 is loaded 2068 after SCP_BL2 has 2069 Trusted SRAM been sent to SCP 2070 0x04040000 +----------+ loaded by BL2 +----------------+ 2071 | BL1 (rw) | <<<<<<<<<<<<< | | 2072 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2073 | BL2 | <<<<<<<<<<<<< | | 2074 |----------| <<<<<<<<<<<<< |----------------| 2075 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2076 | | +----------------+ 2077 0x04001000 +----------+ 2078 | MHU | 2079 0x04000000 +----------+ 2080 2081.. _firmware_design_fip: 2082 2083Firmware Image Package (FIP) 2084---------------------------- 2085 2086Using a Firmware Image Package (FIP) allows for packing bootloader images (and 2087potentially other payloads) into a single archive that can be loaded by TF-A 2088from non-volatile platform storage. A driver to load images from a FIP has 2089been added to the storage layer and allows a package to be read from supported 2090platform storage. A tool to create Firmware Image Packages is also provided 2091and described below. 2092 2093Firmware Image Package layout 2094~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2095 2096The FIP layout consists of a table of contents (ToC) followed by payload data. 2097The ToC itself has a header followed by one or more table entries. The ToC is 2098terminated by an end marker entry, and since the size of the ToC is 0 bytes, 2099the offset equals the total size of the FIP file. All ToC entries describe some 2100payload data that has been appended to the end of the binary package. With the 2101information provided in the ToC entry the corresponding payload data can be 2102retrieved. 2103 2104:: 2105 2106 ------------------ 2107 | ToC Header | 2108 |----------------| 2109 | ToC Entry 0 | 2110 |----------------| 2111 | ToC Entry 1 | 2112 |----------------| 2113 | ToC End Marker | 2114 |----------------| 2115 | | 2116 | Data 0 | 2117 | | 2118 |----------------| 2119 | | 2120 | Data 1 | 2121 | | 2122 ------------------ 2123 2124The ToC header and entry formats are described in the header file 2125``include/tools_share/firmware_image_package.h``. This file is used by both the 2126tool and TF-A. 2127 2128The ToC header has the following fields: 2129 2130:: 2131 2132 `name`: The name of the ToC. This is currently used to validate the header. 2133 `serial_number`: A non-zero number provided by the creation tool 2134 `flags`: Flags associated with this data. 2135 Bits 0-31: Reserved 2136 Bits 32-47: Platform defined 2137 Bits 48-63: Reserved 2138 2139A ToC entry has the following fields: 2140 2141:: 2142 2143 `uuid`: All files are referred to by a pre-defined Universally Unique 2144 IDentifier [UUID] . The UUIDs are defined in 2145 `include/tools_share/firmware_image_package.h`. The platform translates 2146 the requested image name into the corresponding UUID when accessing the 2147 package. 2148 `offset_address`: The offset address at which the corresponding payload data 2149 can be found. The offset is calculated from the ToC base address. 2150 `size`: The size of the corresponding payload data in bytes. 2151 `flags`: Flags associated with this entry. None are yet defined. 2152 2153Firmware Image Package creation tool 2154~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2155 2156The FIP creation tool can be used to pack specified images into a binary 2157package that can be loaded by TF-A from platform storage. The tool currently 2158only supports packing bootloader images. Additional image definitions can be 2159added to the tool as required. 2160 2161The tool can be found in ``tools/fiptool``. 2162 2163Loading from a Firmware Image Package (FIP) 2164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2165 2166The Firmware Image Package (FIP) driver can load images from a binary package on 2167non-volatile platform storage. For the Arm development platforms, this is 2168currently NOR FLASH. 2169 2170Bootloader images are loaded according to the platform policy as specified by 2171the function ``plat_get_image_source()``. For the Arm development platforms, this 2172means the platform will attempt to load images from a Firmware Image Package 2173located at the start of NOR FLASH0. 2174 2175The Arm development platforms' policy is to only allow loading of a known set of 2176images. The platform policy can be modified to allow additional images. 2177 2178Use of coherent memory in TF-A 2179------------------------------ 2180 2181There might be loss of coherency when physical memory with mismatched 2182shareability, cacheability and memory attributes is accessed by multiple CPUs 2183(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2184in TF-A during power up/down sequences when coherency, MMU and caches are 2185turned on/off incrementally. 2186 2187TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2188in the translation tables. The translation granule size in TF-A is 4KB. This 2189is the smallest possible size of the coherent memory region. 2190 2191By default, all data structures which are susceptible to accesses with 2192mismatched attributes from various CPUs are allocated in a coherent memory 2193region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2194region accesses are Outer Shareable, non-cacheable and they can be accessed with 2195the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2196at least an extra page of memory, TF-A is able to work around coherency issues 2197due to mismatched memory attributes. 2198 2199The alternative to the above approach is to allocate the susceptible data 2200structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2201approach requires the data structures to be designed so that it is possible to 2202work around the issue of mismatched memory attributes by performing software 2203cache maintenance on them. 2204 2205Disabling the use of coherent memory in TF-A 2206~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2207 2208It might be desirable to avoid the cost of allocating coherent memory on 2209platforms which are memory constrained. TF-A enables inclusion of coherent 2210memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2211This flag is enabled by default. It can be disabled to choose the second 2212approach described above. 2213 2214The below sections analyze the data structures allocated in the coherent memory 2215region and the changes required to allocate them in normal memory. 2216 2217Coherent memory usage in PSCI implementation 2218~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2219 2220The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2221tree information for state management of power domains. By default, this data 2222structure is allocated in the coherent memory region in TF-A because it can be 2223accessed by multiple CPUs, either with caches enabled or disabled. 2224 2225.. code:: c 2226 2227 typedef struct non_cpu_pwr_domain_node { 2228 /* 2229 * Index of the first CPU power domain node level 0 which has this node 2230 * as its parent. 2231 */ 2232 unsigned int cpu_start_idx; 2233 2234 /* 2235 * Number of CPU power domains which are siblings of the domain indexed 2236 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2237 * -> cpu_start_idx + ncpus' have this node as their parent. 2238 */ 2239 unsigned int ncpus; 2240 2241 /* 2242 * Index of the parent power domain node. 2243 */ 2244 unsigned int parent_node; 2245 2246 plat_local_state_t local_state; 2247 2248 unsigned char level; 2249 2250 /* For indexing the psci_lock array*/ 2251 unsigned char lock_index; 2252 } non_cpu_pd_node_t; 2253 2254In order to move this data structure to normal memory, the use of each of its 2255fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2256``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2257them from coherent memory involves only doing a clean and invalidate of the 2258cache lines after these fields are written. 2259 2260The field ``local_state`` can be concurrently accessed by multiple CPUs in 2261different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2262mutual exclusion to this field and a clean and invalidate is needed after it 2263is written. 2264 2265Bakery lock data 2266~~~~~~~~~~~~~~~~ 2267 2268The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2269and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2270defined as follows: 2271 2272.. code:: c 2273 2274 typedef struct bakery_lock { 2275 /* 2276 * The lock_data is a bit-field of 2 members: 2277 * Bit[0] : choosing. This field is set when the CPU is 2278 * choosing its bakery number. 2279 * Bits[1 - 15] : number. This is the bakery number allocated. 2280 */ 2281 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2282 } bakery_lock_t; 2283 2284It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2285fields can be read by all CPUs but only written to by the owning CPU. 2286 2287Depending upon the data cache line size, the per-CPU fields of the 2288``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2289These per-CPU fields can be read and written during lock contention by multiple 2290CPUs with mismatched memory attributes. Since these fields are a part of the 2291lock implementation, they do not have access to any other locking primitive to 2292safeguard against the resulting coherency issues. As a result, simple software 2293cache maintenance is not enough to allocate them in coherent memory. Consider 2294the following example. 2295 2296CPU0 updates its per-CPU field with data cache enabled. This write updates a 2297local cache line which contains a copy of the fields for other CPUs as well. Now 2298CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2299disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2300its field in any other cache line in the system. This operation will invalidate 2301the update made by CPU0 as well. 2302 2303To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2304has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2305algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2306for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2307needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2308for other cores by using the total size allocated for the bakery_lock section 2309and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2310perform software cache maintenance on the lock data structure without running 2311into coherency issues associated with mismatched attributes. 2312 2313The bakery lock data structure ``bakery_info_t`` is defined for use when 2314``USE_COHERENT_MEM`` is disabled as follows: 2315 2316.. code:: c 2317 2318 typedef struct bakery_info { 2319 /* 2320 * The lock_data is a bit-field of 2 members: 2321 * Bit[0] : choosing. This field is set when the CPU is 2322 * choosing its bakery number. 2323 * Bits[1 - 15] : number. This is the bakery number allocated. 2324 */ 2325 volatile uint16_t lock_data; 2326 } bakery_info_t; 2327 2328The ``bakery_info_t`` represents a single per-CPU field of one lock and 2329the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2330system represents the complete bakery lock. The view in memory for a system 2331with n bakery locks are: 2332 2333:: 2334 2335 .bakery_lock section start 2336 |----------------| 2337 | `bakery_info_t`| <-- Lock_0 per-CPU field 2338 | Lock_0 | for CPU0 2339 |----------------| 2340 | `bakery_info_t`| <-- Lock_1 per-CPU field 2341 | Lock_1 | for CPU0 2342 |----------------| 2343 | .... | 2344 |----------------| 2345 | `bakery_info_t`| <-- Lock_N per-CPU field 2346 | Lock_N | for CPU0 2347 ------------------ 2348 | XXXXX | 2349 | Padding to | 2350 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2351 | Granule | continuous memory for remaining CPUs. 2352 ------------------ 2353 | `bakery_info_t`| <-- Lock_0 per-CPU field 2354 | Lock_0 | for CPU1 2355 |----------------| 2356 | `bakery_info_t`| <-- Lock_1 per-CPU field 2357 | Lock_1 | for CPU1 2358 |----------------| 2359 | .... | 2360 |----------------| 2361 | `bakery_info_t`| <-- Lock_N per-CPU field 2362 | Lock_N | for CPU1 2363 ------------------ 2364 | XXXXX | 2365 | Padding to | 2366 | next Cache WB | 2367 | Granule | 2368 ------------------ 2369 2370Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2371operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2372``.bakery_lock`` section need to be fetched and appropriate cache operations need 2373to be performed for each access. 2374 2375On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2376driver (``arm_lock``). 2377 2378Non Functional Impact of removing coherent memory 2379~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2380 2381Removal of the coherent memory region leads to the additional software overhead 2382of performing cache maintenance for the affected data structures. However, since 2383the memory where the data structures are allocated is cacheable, the overhead is 2384mostly mitigated by an increase in performance. 2385 2386There is however a performance impact for bakery locks, due to: 2387 2388- Additional cache maintenance operations, and 2389- Multiple cache line reads for each lock operation, since the bakery locks 2390 for each CPU are distributed across different cache lines. 2391 2392The implementation has been optimized to minimize this additional overhead. 2393Measurements indicate that when bakery locks are allocated in Normal memory, the 2394minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2395in Device memory the same is 2 micro seconds. The measurements were done on the 2396Juno Arm development platform. 2397 2398As mentioned earlier, almost a page of memory can be saved by disabling 2399``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2400whether coherent memory should be used. If a platform disables 2401``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2402optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2403:ref:`Porting Guide`). Refer to the reference platform code for examples. 2404 2405Isolating code and read-only data on separate memory pages 2406---------------------------------------------------------- 2407 2408In the Armv8-A VMSA, translation table entries include fields that define the 2409properties of the target memory region, such as its access permissions. The 2410smallest unit of memory that can be addressed by a translation table entry is 2411a memory page. Therefore, if software needs to set different permissions on two 2412memory regions then it needs to map them using different memory pages. 2413 2414The default memory layout for each BL image is as follows: 2415 2416:: 2417 2418 | ... | 2419 +-------------------+ 2420 | Read-write data | 2421 +-------------------+ Page boundary 2422 | <Padding> | 2423 +-------------------+ 2424 | Exception vectors | 2425 +-------------------+ 2 KB boundary 2426 | <Padding> | 2427 +-------------------+ 2428 | Read-only data | 2429 +-------------------+ 2430 | Code | 2431 +-------------------+ BLx_BASE 2432 2433.. note:: 2434 The 2KB alignment for the exception vectors is an architectural 2435 requirement. 2436 2437The read-write data start on a new memory page so that they can be mapped with 2438read-write permissions, whereas the code and read-only data below are configured 2439as read-only. 2440 2441However, the read-only data are not aligned on a page boundary. They are 2442contiguous to the code. Therefore, the end of the code section and the beginning 2443of the read-only data one might share a memory page. This forces both to be 2444mapped with the same memory attributes. As the code needs to be executable, this 2445means that the read-only data stored on the same memory page as the code are 2446executable as well. This could potentially be exploited as part of a security 2447attack. 2448 2449TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2450read-only data on separate memory pages. This in turn allows independent control 2451of the access permissions for the code and read-only data. In this case, 2452platform code gets a finer-grained view of the image layout and can 2453appropriately map the code region as executable and the read-only data as 2454execute-never. 2455 2456This has an impact on memory footprint, as padding bytes need to be introduced 2457between the code and read-only data to ensure the segregation of the two. To 2458limit the memory cost, this flag also changes the memory layout such that the 2459code and exception vectors are now contiguous, like so: 2460 2461:: 2462 2463 | ... | 2464 +-------------------+ 2465 | Read-write data | 2466 +-------------------+ Page boundary 2467 | <Padding> | 2468 +-------------------+ 2469 | Read-only data | 2470 +-------------------+ Page boundary 2471 | <Padding> | 2472 +-------------------+ 2473 | Exception vectors | 2474 +-------------------+ 2 KB boundary 2475 | <Padding> | 2476 +-------------------+ 2477 | Code | 2478 +-------------------+ BLx_BASE 2479 2480With this more condensed memory layout, the separation of read-only data will 2481add zero or one page to the memory footprint of each BL image. Each platform 2482should consider the trade-off between memory footprint and security. 2483 2484This build flag is disabled by default, minimising memory footprint. On Arm 2485platforms, it is enabled. 2486 2487Publish and Subscribe Framework 2488------------------------------- 2489 2490The Publish and Subscribe Framework allows EL3 components to define and publish 2491events, to which other EL3 components can subscribe. 2492 2493The following macros are provided by the framework: 2494 2495- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2496 the event name, which must be a valid C identifier. All calls to 2497 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2498 ``pubsub_events.h``. 2499 2500- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2501 subscribed handlers and calling them in turn. The handlers will be passed the 2502 parameter ``arg``. The expected use-case is to broadcast an event. 2503 2504- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2505 ``NULL`` is passed to subscribed handlers. 2506 2507- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2508 subscribe to ``event``. The handler will be executed whenever the ``event`` 2509 is published. 2510 2511- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2512 subscribed for ``event``. ``subscriber`` must be a local variable of type 2513 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2514 iteration. This macro can be used for those patterns that none of the 2515 ``PUBLISH_EVENT_*()`` macros cover. 2516 2517Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2518result in build error. Subscribing to an undefined event however won't. 2519 2520Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2521signature: 2522 2523.. code:: c 2524 2525 typedef void* (*pubsub_cb_t)(const void *arg); 2526 2527There may be arbitrary number of handlers registered to the same event. The 2528order in which subscribed handlers are notified when that event is published is 2529not defined. Subscribed handlers may be executed in any order; handlers should 2530not assume any relative ordering amongst them. 2531 2532Publishing an event on a PE will result in subscribed handlers executing on that 2533PE only; it won't cause handlers to execute on a different PE. 2534 2535Note that publishing an event on a PE blocks until all the subscribed handlers 2536finish executing on the PE. 2537 2538TF-A generic code publishes and subscribes to some events within. Platform 2539ports are discouraged from subscribing to them. These events may be withdrawn, 2540renamed, or have their semantics altered in the future. Platforms may however 2541register, publish, and subscribe to platform-specific events. 2542 2543Publish and Subscribe Example 2544~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2545 2546A publisher that wants to publish event ``foo`` would: 2547 2548- Define the event ``foo`` in the ``pubsub_events.h``. 2549 2550 .. code:: c 2551 2552 REGISTER_PUBSUB_EVENT(foo); 2553 2554- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2555 publish the event at the appropriate path and time of execution. 2556 2557A subscriber that wants to subscribe to event ``foo`` published above would 2558implement: 2559 2560.. code:: c 2561 2562 void *foo_handler(const void *arg) 2563 { 2564 void *result; 2565 2566 /* Do handling ... */ 2567 2568 return result; 2569 } 2570 2571 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2572 2573 2574Reclaiming the BL31 initialization code 2575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2576 2577A significant amount of the code used for the initialization of BL31 is never 2578needed again after boot time. In order to reduce the runtime memory 2579footprint, the memory used for this code can be reclaimed after initialization 2580has finished and be used for runtime data. 2581 2582The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2583with a ``.text.init.*`` attribute which can be filtered and placed suitably 2584within the BL image for later reclamation by the platform. The platform can 2585specify the filter and the memory region for this init section in BL31 via the 2586plat.ld.S linker script. For example, on the FVP, this section is placed 2587overlapping the secondary CPU stacks so that after the cold boot is done, this 2588memory can be reclaimed for the stacks. The init memory section is initially 2589mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2590completed, the FVP changes the attributes of this section to ``RW``, 2591``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2592are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2593section section can be reclaimed for any data which is accessed after cold 2594boot initialization and it is upto the platform to make the decision. 2595 2596Please note that this will disable inlining for any functions with the __init 2597attribute. 2598 2599.. _firmware_design_pmf: 2600 2601Performance Measurement Framework 2602--------------------------------- 2603 2604The Performance Measurement Framework (PMF) facilitates collection of 2605timestamps by registered services and provides interfaces to retrieve them 2606from within TF-A. A platform can choose to expose appropriate SMCs to 2607retrieve these collected timestamps. 2608 2609By default, the global physical counter is used for the timestamp 2610value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2611timestamps captured by other CPUs. 2612 2613Timestamp identifier format 2614~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2615 2616A PMF timestamp is uniquely identified across the system via the 2617timestamp ID or ``tid``. The ``tid`` is composed as follows: 2618 2619:: 2620 2621 Bits 0-7: The local timestamp identifier. 2622 Bits 8-9: Reserved. 2623 Bits 10-15: The service identifier. 2624 Bits 16-31: Reserved. 2625 2626#. The service identifier. Each PMF service is identified by a 2627 service name and a service identifier. Both the service name and 2628 identifier are unique within the system as a whole. 2629 2630#. The local timestamp identifier. This identifier is unique within a given 2631 service. 2632 2633Registering a PMF service 2634~~~~~~~~~~~~~~~~~~~~~~~~~ 2635 2636To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2637is used. The arguments required are the service name, the service ID, 2638the total number of local timestamps to be captured and a set of flags. 2639 2640The ``flags`` field can be specified as a bitwise-OR of the following values: 2641 2642:: 2643 2644 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2645 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2646 2647The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2648timestamps in a PMF specific linker section at build time. 2649Additionally, it defines necessary functions to capture and 2650retrieve a particular timestamp for the given service at runtime. 2651 2652The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2653from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2654``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2655accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2656macro but additionally supports retrieving timestamps using SMCs. 2657 2658Capturing a timestamp 2659~~~~~~~~~~~~~~~~~~~~~ 2660 2661PMF timestamps are stored in a per-service timestamp region. On a 2662system with multiple CPUs, each timestamp is captured and stored 2663in a per-CPU cache line aligned memory region. 2664 2665Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2666used to capture a timestamp at the location where it is used. The macro 2667takes the service name, a local timestamp identifier and a flag as arguments. 2668 2669The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2670instructs PMF to do cache maintenance following the capture. Cache 2671maintenance is required if any of the service's timestamps are captured 2672with data cache disabled. 2673 2674To capture a timestamp in assembly code, the caller should use 2675``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2676calculate the address of where the timestamp would be stored. The 2677caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2678and store it at the determined address for later retrieval. 2679 2680Retrieving a timestamp 2681~~~~~~~~~~~~~~~~~~~~~~ 2682 2683From within TF-A, timestamps for individual CPUs can be retrieved using either 2684``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2685These macros accept the CPU's MPIDR value, or its ordinal position 2686respectively. 2687 2688From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2689into ``pmf_smc_handler()``. 2690 2691:: 2692 2693 Interface : pmf_smc_handler() 2694 Argument : unsigned int smc_fid, u_register_t x1, 2695 u_register_t x2, u_register_t x3, 2696 u_register_t x4, void *cookie, 2697 void *handle, u_register_t flags 2698 Return : uintptr_t 2699 2700 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2701 when the caller of the SMC is running in AArch32 mode 2702 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2703 x1: Timestamp identifier. 2704 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2705 This can be the `mpidr` of a different core to the one initiating 2706 the SMC. In that case, service specific cache maintenance may be 2707 required to ensure the updated copy of the timestamp is returned. 2708 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2709 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2710 cache invalidate before reading the timestamp. This ensures 2711 an updated copy is returned. 2712 2713The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2714in this implementation. 2715 2716PMF code structure 2717~~~~~~~~~~~~~~~~~~ 2718 2719#. ``pmf_main.c`` consists of core functions that implement service registration, 2720 initialization, storing, dumping and retrieving timestamps. 2721 2722#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2723 2724#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2725 2726#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2727 assembly code. 2728 2729#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2730 2731Armv8-A Architecture Extensions 2732------------------------------- 2733 2734TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2735section lists the usage of Architecture Extensions, and build flags 2736controlling them. 2737 2738Build options 2739~~~~~~~~~~~~~ 2740 2741``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` 2742 2743These build options serve dual purpose 2744 2745- Determine the architecture extension support in TF-A build: All the mandatory 2746 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included 2747 and unconditionally enabled by TF-A build system. 2748 2749- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility 2750 this will try to come up with an appropriate -march value to be passed to compiler 2751 by probing the compiler and checking what's supported by the compiler and what's best 2752 that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used 2753 directly and compiler probing will be skipped. Use ``ARM_ARCH_FEATURE`` to provide a 2754 list of optional features that can be relied upon. 2755 2756The build system requires that the platform provides a valid numeric value based on 2757CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. 2758Subsequent Arm Architecture versions also support extensions which were introduced 2759in previous versions. 2760 2761.. seealso:: :ref:`Build Options` 2762 2763For details on the Architecture Extension and available features, please refer 2764to the respective Architecture Extension Supplement. 2765 2766Armv8.1-A 2767~~~~~~~~~ 2768 2769This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2770``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2771 2772- By default, a load-/store-exclusive instruction pair is used to implement 2773 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2774 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2775 Notice this instruction is only available in AArch64 execution state, so 2776 the option is only available to AArch64 builds. 2777 2778Armv8.2-A 2779~~~~~~~~~ 2780 2781- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2782 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2783 Processing Elements in the same Inner Shareable domain use the same 2784 translation table entries for a given stage of translation for a particular 2785 translation regime. 2786 2787Armv8.3-A 2788~~~~~~~~~ 2789 2790- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2791 the Non-secure world so that lower ELs are allowed to use them without 2792 causing a trap to EL3. 2793 2794 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2795 must be set to 1. This will add all pointer authentication system registers 2796 to the context that is saved when doing a world switch. 2797 2798 The TF-A itself has support for pointer authentication at runtime 2799 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2800 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2801 BL2, BL31, and the TSP if it is used. 2802 2803 Note that Pointer Authentication is enabled for Non-secure world irrespective 2804 of the value of these build flags if the CPU supports it. 2805 2806 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2807 enabling PAuth is lower because the compiler will use the optimized 2808 PAuth instructions rather than the backwards-compatible ones. 2809 2810Armv8.5-A 2811~~~~~~~~~ 2812 2813- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2814 option set to 1. This option defaults to 0. 2815 2816- Memory Tagging Extension feature has few variants but not all of them require 2817 enablement from EL3 to be used at lower EL. e.g. Memory tagging only at 2818 EL0(MTE) does not require EL3 configuration however memory tagging at 2819 EL2/EL1 (MTE2) does require EL3 enablement and we need to set this option 2820 ``ENABLE_FEAT_MTE2`` to 1. This option defaults to 0. 2821 2822Armv7-A 2823~~~~~~~ 2824 2825This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2826 2827There are several Armv7-A extensions available. Obviously the TrustZone 2828extension is mandatory to support the TF-A bootloader and runtime services. 2829 2830Platform implementing an Armv7-A system can to define from its target 2831Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2832``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2833Cortex-A15 target. 2834 2835Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2836Note that using neon at runtime has constraints on non secure world context. 2837TF-A does not yet provide VFP context management. 2838 2839Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2840the toolchain target architecture directive. 2841 2842Platform may choose to not define straight the toolchain target architecture 2843directive by defining ``MARCH_DIRECTIVE``. 2844I.e: 2845 2846.. code:: make 2847 2848 MARCH_DIRECTIVE := -march=armv7-a 2849 2850Code Structure 2851-------------- 2852 2853TF-A code is logically divided between the three boot loader stages mentioned 2854in the previous sections. The code is also divided into the following 2855categories (present as directories in the source code): 2856 2857- **Platform specific.** Choice of architecture specific code depends upon 2858 the platform. 2859- **Common code.** This is platform and architecture agnostic code. 2860- **Library code.** This code comprises of functionality commonly used by all 2861 other code. The PSCI implementation and other EL3 runtime frameworks reside 2862 as Library components. 2863- **Stage specific.** Code specific to a boot stage. 2864- **Drivers.** 2865- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2866 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2867 2868Each boot loader stage uses code from one or more of the above mentioned 2869categories. Based upon the above, the code layout looks like this: 2870 2871:: 2872 2873 Directory Used by BL1? Used by BL2? Used by BL31? 2874 bl1 Yes No No 2875 bl2 No Yes No 2876 bl31 No No Yes 2877 plat Yes Yes Yes 2878 drivers Yes No Yes 2879 common Yes Yes Yes 2880 lib Yes Yes Yes 2881 services No No Yes 2882 2883The build system provides a non configurable build option IMAGE_BLx for each 2884boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2885defined by the build system. This enables TF-A to compile certain code only 2886for specific boot loader stages 2887 2888All assembler files have the ``.S`` extension. The linker source files for each 2889boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2890linker scripts which have the extension ``.ld``. 2891 2892FDTs provide a description of the hardware platform and are used by the Linux 2893kernel at boot time. These can be found in the ``fdts`` directory. 2894 2895.. rubric:: References 2896 2897- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2898 2899- `PSCI`_ 2900 2901- `SMC Calling Convention`_ 2902 2903- :ref:`Interrupt Management Framework` 2904 2905-------------- 2906 2907*Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved.* 2908 2909.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2910.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 2911.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2912.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2913.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest 2914.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2915.. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table 2916 2917.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2918
