1 /*
2 * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <platform_def.h>
9
10 #include <common/debug.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gic.h>
13 #include <drivers/arm/gicv3.h>
14 #include <lib/utils.h>
15 #include <plat/arm/common/plat_arm.h>
16 #include <plat/common/platform.h>
17
18 #if USE_GIC_DRIVER != 3
19 #error "This file should only be used with USE_GIC_DRIVER=3"
20 #endif
21
22 #pragma weak gic_cpuif_enable
23 #pragma weak gic_cpuif_disable
24
25 /* The GICv3 driver only needs to be initialized in EL3 */
26 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
27
28 /* List of zero terminated GICR frame addresses which CPUs will probe */
29 static const uintptr_t *gicr_frames = NULL;
30
31 static const interrupt_prop_t arm_interrupt_props[] = {
32 #ifdef PLAT_ARM_G1S_IRQ_PROPS
33 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
34 #endif
35 #ifdef PLAT_ARM_G0_IRQ_PROPS
36 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0),
37 #endif
38 #if ENABLE_FEAT_RAS && FFH_SUPPORT
39 INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0,
40 GIC_INTR_CFG_LEVEL)
41 #endif
42 };
43
44 /*
45 * We save and restore the GICv3 context on system suspend. Allocate the
46 * data in the designated EL3 Secure carve-out memory. The `used` attribute
47 * is used to prevent the compiler from removing the gicv3 contexts.
48 */
49 static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used;
50 static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used;
51
52 /* Define accessor function to get reference to the GICv3 context */
53 DEFINE_LOAD_SYM_ADDR(rdist_ctx)
DEFINE_LOAD_SYM_ADDR(dist_ctx)54 DEFINE_LOAD_SYM_ADDR(dist_ctx)
55
56 /*
57 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
58 * to core position.
59 *
60 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
61 * values read from GICR_TYPER don't have an MT field. To reuse the same
62 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
63 * that read from GICR_TYPER.
64 *
65 * Assumptions:
66 *
67 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
68 * - No CPUs implemented in the system use affinity level 3.
69 */
70 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
71 {
72 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
73 return plat_arm_calc_core_pos(mpidr);
74 }
75
76 gicv3_driver_data_t gic_data __unused = {
77 .gicd_base = PLAT_ARM_GICD_BASE,
78 /* unused for USE_GIC_DRIVER=3. Use gic_set_gicr_frames(), passing a ptr
79 * to an array with 2 values - the frame's base and a NULL pointer */
80 .gicr_base = 0U,
81 .interrupt_props = arm_interrupt_props,
82 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
83 .rdistif_num = PLATFORM_CORE_COUNT,
84 .rdistif_base_addrs = rdistif_base_addrs,
85 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
86 };
87
88 /*
89 * Initialises the gicr_frames array. It contains a NULL terminated list of
90 * non-contiguous blocks of GICR frames (located at uneven offsets). Most
91 * platforms will have one such block, except multichip configurations, which
92 * will usually have multiple.
93 */
gic_set_gicr_frames(const uintptr_t * plat_gicr_frames)94 void gic_set_gicr_frames(const uintptr_t *plat_gicr_frames)
95 {
96 assert(plat_gicr_frames != NULL);
97 gicr_frames = plat_gicr_frames;
98 }
99
100 /******************************************************************************
101 * ARM common helper to initialize the GIC. Only invoked by BL31. The platform
102 * should have already done any prerequisites.
103 *****************************************************************************/
gic_init(unsigned int cpu_idx)104 void __init gic_init(unsigned int cpu_idx)
105 {
106 gicv3_driver_init(&gic_data);
107 gicv3_distif_init();
108 }
109
110 /******************************************************************************
111 * ARM common helper to enable the GIC CPU interface
112 *****************************************************************************/
gic_cpuif_enable(unsigned int cpu_idx)113 void gic_cpuif_enable(unsigned int cpu_idx)
114 {
115 gicv3_cpuif_enable(cpu_idx);
116 }
117
118 /******************************************************************************
119 * ARM common helper to disable the GIC CPU interface
120 *****************************************************************************/
gic_cpuif_disable(unsigned int cpu_idx)121 void gic_cpuif_disable(unsigned int cpu_idx)
122 {
123 gicv3_cpuif_disable(cpu_idx);
124 }
125
126 /******************************************************************************
127 * ARM common helper function to iterate over all GICR frames and discover the
128 * corresponding per-cpu redistributor frame as well as initialize the
129 * corresponding interface in GICv3.
130 *****************************************************************************/
gic_pcpu_init(unsigned int cpu_idx)131 void gic_pcpu_init(unsigned int cpu_idx)
132 {
133 /* to guard against an empty array */
134 int result = -1;
135 const uintptr_t *frame = gicr_frames;
136
137 /* did the platform initialise the array with gic_set_gicr_frames() */
138 assert(gicr_frames != NULL);
139
140 #if __aarch64__
141 plat_gic_pre_pcpu_init(cpu_idx);
142 #endif
143
144 while (*frame != 0U) {
145 result = gicv3_rdistif_probe(*frame);
146
147 if (result == 0)
148 break;
149
150 frame++;
151 }
152
153 if (result == -1) {
154 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
155 panic();
156 }
157 gicv3_rdistif_init(cpu_idx);
158 }
159
160 /******************************************************************************
161 * ARM common helpers to power GIC redistributor interface
162 *****************************************************************************/
gic_pcpu_off(unsigned int cpu_idx)163 void gic_pcpu_off(unsigned int cpu_idx)
164 {
165 gicv3_rdistif_off(cpu_idx);
166 }
167
168 /******************************************************************************
169 * Common helper to save & restore the GICv3 on resume from system suspend. It
170 * is the platform's responsibility to call these.
171 *****************************************************************************/
gic_save(void)172 void gic_save(void)
173 {
174 gicv3_redist_ctx_t * const rdist_context =
175 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
176 gicv3_dist_ctx_t * const dist_context =
177 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
178
179 /*
180 * If an ITS is available, save its context before
181 * the Redistributor using:
182 * gicv3_its_save_disable(gits_base, &its_ctx[i])
183 * Additionally, an implementation-defined sequence may
184 * be required to save the whole ITS state.
185 */
186
187 /*
188 * Save the GIC Redistributors and ITS contexts before the
189 * Distributor context. As we only handle SYSTEM SUSPEND API,
190 * we only need to save the context of the CPU that is issuing
191 * the SYSTEM SUSPEND call, i.e. the current CPU.
192 */
193 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
194
195 /* Save the GIC Distributor context */
196 gicv3_distif_save(dist_context);
197
198 /*
199 * From here, all the components of the GIC can be safely powered down
200 * as long as there is an alternate way to handle wakeup interrupt
201 * sources.
202 */
203 }
204
gic_resume(void)205 void gic_resume(void)
206 {
207 const gicv3_redist_ctx_t *rdist_context =
208 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
209 const gicv3_dist_ctx_t *dist_context =
210 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
211
212 /* Restore the GIC Distributor context */
213 gicv3_distif_init_restore(dist_context);
214
215 /*
216 * Restore the GIC Redistributor and ITS contexts after the
217 * Distributor context. As we only handle SYSTEM SUSPEND API,
218 * we only need to restore the context of the CPU that issued
219 * the SYSTEM SUSPEND call.
220 */
221 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
222
223 /*
224 * If an ITS is available, restore its context after
225 * the Redistributor using:
226 * gicv3_its_restore(gits_base, &its_ctx[i])
227 * An implementation-defined sequence may be required to
228 * restore the whole ITS state. The ITS must also be
229 * re-enabled after this sequence has been executed.
230 */
231 }
232