1 /*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/debug.h>
10 #include <common/desc_image_load.h>
11 #include <drivers/arm/sp804_delay_timer.h>
12 #include <fvp_pas_def.h>
13 #include <lib/fconf/fconf.h>
14 #include <lib/fconf/fconf_dyn_cfg_getter.h>
15 #if TRANSFER_LIST
16 #include <transfer_list.h>
17 #endif
18
19 #include <plat/arm/common/plat_arm.h>
20 #include <plat/common/platform.h>
21 #include <platform_def.h>
22
23 #include "fvp_private.h"
24
25 #if ENABLE_FEAT_RME
26 /*
27 * The GPT library might modify the gpt regions structure to optimize
28 * the layout, so the array cannot be constant.
29 */
30 static pas_region_t pas_regions[] = {
31 ARM_PAS_KERNEL,
32 ARM_PAS_SECURE,
33 #if ENABLE_RMM
34 ARM_PAS_REALM,
35 #endif
36 ARM_PAS_EL3_DRAM,
37 #ifdef ARM_PAS_GPTS
38 ARM_PAS_GPTS,
39 #endif
40 ARM_PAS_KERNEL_1,
41 ARM_PAS_PCI_MEM_1,
42 ARM_PAS_PCI_MEM_2
43 };
44
45 static const arm_gpt_info_t arm_gpt_info = {
46 .pas_region_base = pas_regions,
47 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
48 .l0_base = ARM_L0_GPT_BASE,
49 .l1_base = ARM_L1_GPT_BASE,
50 .l0_size = ARM_L0_GPT_SIZE,
51 .l1_size = ARM_L1_GPT_SIZE,
52 .pps = GPCCR_PPS_1TB,
53 .pgs = GPCCR_PGS_4K
54 };
55 #endif /* ENABLE_FEAT_RME */
56
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)57 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
58 {
59 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
60
61 /* Initialize the platform config for future decision making */
62 fvp_config_setup();
63
64 #if RESET_TO_BL2
65 /*
66 * Initialize Interconnect for this cluster during cold boot.
67 * No need for locks as no other CPU is active.
68 */
69 fvp_interconnect_init();
70
71 /* Enable coherency in Interconnect for the primary CPU's cluster. */
72 fvp_interconnect_enable();
73 #endif
74 }
75
bl2_platform_setup(void)76 void bl2_platform_setup(void)
77 {
78 arm_bl2_platform_setup();
79
80 /* Initialize System level generic or SP804 timer */
81 fvp_timer_init();
82 }
83
84 #if ENABLE_FEAT_RME
plat_arm_get_gpt_info(void)85 const arm_gpt_info_t *plat_arm_get_gpt_info(void)
86 {
87 return &arm_gpt_info;
88 }
89 #endif /* ENABLE_FEAT_RME */
90
91 /*******************************************************************************
92 * This function returns the list of executable images
93 ******************************************************************************/
plat_get_next_bl_params(void)94 struct bl_params *plat_get_next_bl_params(void)
95 {
96 struct bl_params *arm_bl_params;
97 bl_mem_params_node_t *param_node __unused;
98 const struct dyn_cfg_dtb_info_t *fw_config_info __unused;
99 const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
100 entry_point_info_t *ep __unused;
101 uint32_t next_exe_img_id __unused;
102 uintptr_t fw_config_base __unused;
103
104 arm_bl_params = arm_get_next_bl_params();
105
106 #if __aarch64__
107 /* Get BL31 image node */
108 param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
109 #else /* aarch32 */
110 /* Get SP_MIN image node */
111 param_node = get_bl_mem_params_node(BL32_IMAGE_ID);
112 #endif /* __aarch64__ */
113 assert(param_node != NULL);
114
115 #if TRANSFER_LIST
116 arm_bl_params->head = ¶m_node->params_node_mem;
117 arm_bl_params->head->ep_info = ¶m_node->ep_info;
118 arm_bl_params->head->image_id = param_node->image_id;
119
120 arm_bl2_setup_next_ep_info(param_node);
121 #elif (!RESET_TO_BL2 || ARM_FW_CONFIG_LOAD_ENABLE) && !EL3_PAYLOAD_BASE
122 fw_config_base = 0UL;
123
124 /* Update the next image's ep info with the FW config address */
125 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
126 assert(fw_config_info != NULL);
127
128 fw_config_base = fw_config_info->config_addr;
129 assert(fw_config_base != 0UL);
130
131 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base;
132 #endif /* TRANSFER_LIST */
133
134 return arm_bl_params;
135 }
136
bl2_plat_handle_post_image_load(unsigned int image_id)137 int bl2_plat_handle_post_image_load(unsigned int image_id)
138 {
139 #if ((!RESET_TO_BL2 || ARM_FW_CONFIG_LOAD_ENABLE) && !EL3_PAYLOAD_BASE && \
140 !TRANSFER_LIST)
141 if (image_id == HW_CONFIG_ID) {
142 const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
143 struct transfer_list_entry *te __unused;
144 bl_mem_params_node_t *param_node __unused;
145
146 param_node = get_bl_mem_params_node(image_id);
147 assert(param_node != NULL);
148
149 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
150 assert(hw_config_info != NULL);
151
152 memcpy((void *)hw_config_info->secondary_config_addr,
153 (void *)hw_config_info->config_addr,
154 (size_t)param_node->image_info.image_size);
155
156 /*
157 * Ensure HW-config device tree is committed to memory, as the HW-Config
158 * might be used without cache and MMU enabled at BL33.
159 */
160 flush_dcache_range(hw_config_info->secondary_config_addr,
161 param_node->image_info.image_size);
162 }
163 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/
164
165 return arm_bl2_plat_handle_post_image_load(image_id);
166 }
167
plat_get_hw_dt_base(void)168 uintptr_t plat_get_hw_dt_base(void)
169 {
170 const struct dyn_cfg_dtb_info_t *hw_config_info;
171
172 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
173 if (hw_config_info == NULL) {
174 return 0U;
175 }
176
177 return hw_config_info->secondary_config_addr;
178 }
179