1 /*
2 * Copyright 2024-2026 NXP
3 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <errno.h>
9
10 #include <common/debug.h>
11 #include <common/desc_image_load.h>
12 #include <drivers/generic_delay_timer.h>
13 #include <imx_usdhc.h>
14 #include <lib/mmio.h>
15 #include <lib/utils.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17 #include <plat/common/platform.h>
18 #include <plat_console.h>
19 #include <s32cc-clk-drv.h>
20
21 #include <ddr_init.h>
22
23 #include <plat_io_storage.h>
24 #include <s32cc-bl-common.h>
25 #include <s32cc-ncore.h>
26 #include <tbbr_img_def.h>
27
28 #define SIUL20_BASE UL(0x4009C000)
29 #define SIUL2_PC09_MSCR UL(0x4009C2E4)
30 #define SIUL2_PC10_MSCR UL(0x4009C2E8)
31 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40)
32
33 #define LIN0_TX_MSCR_CFG U(0x00214001)
34 #define LIN0_RX_MSCR_CFG U(0x00094000)
35 #define LIN0_RX_IMCR_CFG U(0x00000002)
36
plat_get_bl_image_load_info(void)37 struct bl_load_info *plat_get_bl_image_load_info(void)
38 {
39 return get_bl_load_info_from_mem_params_desc();
40 }
41
plat_get_next_bl_params(void)42 struct bl_params *plat_get_next_bl_params(void)
43 {
44 return get_next_bl_params_from_mem_params_desc();
45 }
46
plat_flush_next_bl_params(void)47 void plat_flush_next_bl_params(void)
48 {
49 flush_bl_params_desc();
50 }
51
bl2_platform_setup(void)52 void bl2_platform_setup(void)
53 {
54 int ret;
55
56 ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE,
57 S32G_FIP_SIZE,
58 MT_MEMORY | MT_RW | MT_SECURE);
59 if (ret != 0) {
60 panic();
61 }
62 }
63
s32g_mmap_siul2(void)64 static int s32g_mmap_siul2(void)
65 {
66 return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE,
67 MT_DEVICE | MT_RW | MT_SECURE);
68 }
69
plat_ddr_mmap_setup(void)70 int plat_ddr_mmap_setup(void)
71 {
72 int ret;
73
74 ret = mmap_add_dynamic_region(DDR_PHY_BASE_ADDR, DDR_PHY_BASE_ADDR,
75 DDR_PHY_SIZE, MT_DEVICE | MT_RW);
76 if (ret != 0) {
77 return ret;
78 }
79
80 return mmap_add_dynamic_region(GPR_BASE_PAGE_ADDR, GPR_BASE_PAGE_ADDR,
81 GPR_SIZE, MT_DEVICE | MT_RW);
82 }
83
linflex_config_pinctrl(void)84 static void linflex_config_pinctrl(void)
85 {
86 /* set PC09 - MSCR[41] - for UART0 TXD */
87 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG);
88 /* set PC10 - MSCR[42] - for UART0 RXD */
89 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG);
90 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */
91 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
92 }
93
init_s32g_usdhc(void)94 static void init_s32g_usdhc(void)
95 {
96 static struct mmc_device_info sd_device_info = {
97 .mmc_dev_type = MMC_IS_SD_HC,
98 .ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4,
99 };
100 imx_usdhc_params_t params;
101
102 zeromem(¶ms, sizeof(imx_usdhc_params_t));
103
104 params.reg_base = S32G_USDHC_BASE;
105 params.clk_rate = 25000000;
106 params.bus_width = MMC_BUS_WIDTH_4;
107 params.flags = MMC_FLAG_SD_CMD6;
108
109 imx_usdhc_init(¶ms, &sd_device_info);
110 }
111
plat_s32_mmc_setup(void)112 static void plat_s32_mmc_setup(void)
113 {
114 init_s32g_usdhc();
115 }
116
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)117 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
118 u_register_t arg2, u_register_t arg3)
119 {
120 int ret;
121
122 /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which
123 * we have manually set during early BL2 boot.
124 */
125 ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU);
126
127 ncore_init();
128 ncore_caiu_online(A53_CLUSTER0_CAIU);
129
130 ret = s32cc_init_core_clocks();
131 if (ret != 0) {
132 panic();
133 }
134
135 ret = s32cc_bl_mmu_setup();
136 if (ret != 0) {
137 panic();
138 }
139
140 ret = s32cc_init_early_clks();
141 if (ret != 0) {
142 panic();
143 }
144
145 ret = s32g_mmap_siul2();
146 if (ret != 0) {
147 panic();
148 }
149
150 generic_delay_timer_init();
151
152 /* Configure the generic timer frequency to ensure proper operation
153 * of the architectural timer in BL2.
154 */
155 write_cntfrq_el0(plat_get_syscnt_freq2());
156
157 linflex_config_pinctrl();
158 console_s32g2_register();
159
160 plat_s32_mmc_setup();
161
162 plat_s32g2_io_setup();
163 }
164
bl2_plat_handle_post_image_load(unsigned int image_id)165 int bl2_plat_handle_post_image_load(unsigned int image_id)
166 {
167 const bl_mem_params_node_t *bl_mem_params;
168
169 bl_mem_params = get_bl_mem_params_node(DDR_FW_IMAGE_ID);
170
171 if (image_id == DDR_FW_IMAGE_ID) {
172 if (ddr_init(bl_mem_params->image_info.image_base) != 0U) {
173 ERROR("Failed to configure the DDR subsystem\n");
174 panic();
175 }
176 }
177 return 0;
178 }
179
bl2_plat_arch_setup(void)180 void bl2_plat_arch_setup(void)
181 {
182 }
183
bl2_plat_handle_pre_image_load(unsigned int image_id)184 int bl2_plat_handle_pre_image_load(unsigned int image_id)
185 {
186 const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id);
187 const struct image_info *img_info;
188 size_t size;
189
190 if (desc == NULL) {
191 return -EINVAL;
192 }
193
194 if (image_id == DDR_FW_IMAGE_ID) {
195 return 0;
196 }
197
198 img_info = &desc->image_info;
199
200 if ((img_info == NULL) || (img_info->image_max_size == 0U)) {
201 return -EINVAL;
202 }
203
204 size = page_align(img_info->image_max_size, UP);
205
206 return mmap_add_dynamic_region(img_info->image_base,
207 img_info->image_base,
208 size,
209 MT_MEMORY | MT_RW | MT_SECURE);
210 }
211