1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25 #include "mp_precomp.h"
26 #include "../phydm_precomp.h"
27
28 #if (RTL8822B_SUPPORT == 1)
phydm_dynamic_switch_htstf_mumimo_8822b(struct dm_struct * dm)29 void phydm_dynamic_switch_htstf_mumimo_8822b(struct dm_struct *dm)
30 {
31 u8 rssi_l2h = 40, rssi_h2l = 35;
32
33 /*@if Pin > -60dBm, enable HT-STF gain controller, otherwise, if rssi < -65dBm, disable the controller*/
34
35 if (dm->rssi_min >= rssi_l2h)
36 odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x1);
37 else if (dm->rssi_min < rssi_h2l)
38 odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x0);
39 }
40
phydm_dynamic_parameters_ota(struct dm_struct * dm)41 void phydm_dynamic_parameters_ota(struct dm_struct *dm)
42 {
43 u8 rssi_l2h = 40, rssi_h2l = 35;
44
45 /* PD TH modify due to enlarge MF windows size */
46 odm_set_bb_reg(dm, 0x838, 0xf0, 0x6);
47
48 if ((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_20)) {
49 if (dm->rssi_min >= rssi_l2h) {
50 /*@if (dm->bhtstfdisabled == false)*/
51 odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x1);
52
53 odm_set_bb_reg(dm, R_0x98c, 0x7fc0000, 0x0);
54 odm_set_bb_reg(dm, R_0x818, 0x7000000, 0x1);
55 odm_set_bb_reg(dm, R_0xc04, BIT(18), 0x0);
56 odm_set_bb_reg(dm, R_0xe04, BIT(18), 0x0);
57 if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) {
58 odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0x444);
59 odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0x4444aaaa);
60 } else if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B) {
61 odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0x444);
62 odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0x444444aa);
63 }
64 } else if (dm->rssi_min < rssi_h2l) {
65 /*@if (dm->bhtstfdisabled == true)*/
66 odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x0);
67
68 odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
69 odm_set_bb_reg(dm, R_0x818, 0x7000000, 0x4);
70 odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
71 odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
72 odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0xaaa);
73 odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0xaaaaaaaa);
74 }
75 } else {
76 #if 0
77 //odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x0);
78 #endif
79 odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
80 odm_set_bb_reg(dm, R_0x818, 0x7000000, 0x4);
81 odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
82 odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
83 odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0xaaa);
84 odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0xaaaaaaaa);
85 }
86 }
87
88 static void
_set_tx_a_cali_value(struct dm_struct * dm,enum rf_path rf_path,u8 offset,u8 tx_a_bias_offset)89 _set_tx_a_cali_value(
90 struct dm_struct *dm,
91 enum rf_path rf_path,
92 u8 offset,
93 u8 tx_a_bias_offset)
94 {
95 u32 modi_tx_a_value = 0;
96 u8 tmp1_byte = 0;
97 boolean is_minus = false;
98 u8 comp_value = 0;
99
100 switch (offset) {
101 case 0x0:
102 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10124);
103 break;
104 case 0x1:
105 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10524);
106 break;
107 case 0x2:
108 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10924);
109 break;
110 case 0x3:
111 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10D24);
112 break;
113 case 0x4:
114 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30164);
115 break;
116 case 0x5:
117 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30564);
118 break;
119 case 0x6:
120 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30964);
121 break;
122 case 0x7:
123 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30D64);
124 break;
125 case 0x8:
126 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50195);
127 break;
128 case 0x9:
129 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50595);
130 break;
131 case 0xa:
132 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50995);
133 break;
134 case 0xb:
135 odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50D95);
136 break;
137 default:
138 PHYDM_DBG(dm, ODM_COMP_API, "Invalid TxA band offset...\n");
139 return;
140 }
141
142 /* @Get TxA value */
143 modi_tx_a_value = odm_get_rf_reg(dm, rf_path, RF_0x61, 0xFFFFF);
144 tmp1_byte = (u8)modi_tx_a_value & (BIT(3) | BIT(2) | BIT(1) | BIT(0));
145
146 /* @check how much need to calibration */
147 switch (tx_a_bias_offset) {
148 case 0xF6:
149 is_minus = true;
150 comp_value = 3;
151 break;
152
153 case 0xF4:
154 is_minus = true;
155 comp_value = 2;
156 break;
157
158 case 0xF2:
159 is_minus = true;
160 comp_value = 1;
161 break;
162
163 case 0xF3:
164 is_minus = false;
165 comp_value = 1;
166 break;
167
168 case 0xF5:
169 is_minus = false;
170 comp_value = 2;
171 break;
172
173 case 0xF7:
174 is_minus = false;
175 comp_value = 3;
176 break;
177
178 case 0xF9:
179 is_minus = false;
180 comp_value = 4;
181 break;
182
183 /* @do nothing case */
184 case 0xF0:
185 default:
186 PHYDM_DBG(dm, ODM_COMP_API,
187 "No need to do TxA bias current calibration\n");
188 return;
189 }
190
191 /* @calc correct value to calibrate */
192 if (is_minus) {
193 if (tmp1_byte >= comp_value)
194 tmp1_byte -= comp_value;
195 #if 0
196 //modi_tx_a_value += tmp1_byte;
197 #endif
198 else
199 tmp1_byte = 0;
200 } else {
201 tmp1_byte += comp_value;
202 if (tmp1_byte >= 7)
203 tmp1_byte = 7;
204 }
205
206 /* Write back to RF reg */
207 odm_set_rf_reg(dm, rf_path, RF_0x30, 0xFFFF, (offset << 12 | (modi_tx_a_value & 0xFF0) | tmp1_byte));
208 }
209
210 static void
_txa_bias_cali_4_each_path(struct dm_struct * dm,u8 rf_path,u8 efuse_value)211 _txa_bias_cali_4_each_path(
212 struct dm_struct *dm,
213 u8 rf_path,
214 u8 efuse_value)
215 {
216 /* switch on set TxA bias */
217 odm_set_rf_reg(dm, rf_path, RF_0xef, 0xFFFFF, 0x200);
218
219 /* Set 12 sets of TxA value */
220 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x0, efuse_value);
221 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x1, efuse_value);
222 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x2, efuse_value);
223 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x3, efuse_value);
224 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x4, efuse_value);
225 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x5, efuse_value);
226 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x6, efuse_value);
227 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x7, efuse_value);
228 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x8, efuse_value);
229 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x9, efuse_value);
230 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xa, efuse_value);
231 _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xb, efuse_value);
232
233 /* switch off set TxA bias */
234 odm_set_rf_reg(dm, rf_path, RF_0xef, 0xFFFFF, 0x0);
235 }
236
237 /* @for 8822B PCIE D-cut patch only */
238 /* Normal driver and MP driver need this patch */
239
phydm_txcurrentcalibration(struct dm_struct * dm)240 void phydm_txcurrentcalibration(struct dm_struct *dm)
241 {
242 u8 efuse0x3D8, efuse0x3D7;
243 u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0;
244
245 if (!(dm->support_ic_type & ODM_RTL8822B))
246 return;
247
248 PHYDM_DBG(dm, ODM_COMP_API,
249 "8822b 5g tx current calibration 0x3d7=0x%X 0x3d8=0x%X\n",
250 dm->efuse0x3d7, dm->efuse0x3d8);
251
252 /* save original 0x18 value */
253 orig_rf0x18_path_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xFFFFF);
254 orig_rf0x18_path_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18, 0xFFFFF);
255
256 /* @define efuse content */
257 efuse0x3D8 = dm->efuse0x3d8;
258 efuse0x3D7 = dm->efuse0x3d7;
259
260 /* @check efuse content to judge whether need to calibration or not */
261 if (efuse0x3D7 == 0xFF) {
262 PHYDM_DBG(dm, ODM_COMP_API,
263 "efuse content 0x3D7 == 0xFF, No need to do TxA cali\n");
264 return;
265 }
266
267 /* write RF register for calibration */
268 _txa_bias_cali_4_each_path(dm, RF_PATH_A, efuse0x3D7);
269 _txa_bias_cali_4_each_path(dm, RF_PATH_B, efuse0x3D8);
270
271 /* restore original 0x18 value */
272 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xFFFFF, orig_rf0x18_path_a);
273 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xFFFFF, orig_rf0x18_path_b);
274 }
275
phydm_1rcca_setting(struct dm_struct * dm,boolean enable_1rcca)276 void phydm_1rcca_setting(struct dm_struct *dm, boolean enable_1rcca)
277 {
278 u32 reg_32;
279
280 reg_32 = odm_get_bb_reg(dm, R_0xa04, 0x0f000000);
281
282 /* @Enable or disable 1RCCA setting accrodding to the control from driver */
283 if (enable_1rcca) {
284 if (reg_32 == 0x0)
285 /* @CCK path-a */
286 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x13);
287 else if (reg_32 == 0x5)
288 /* @CCK path-b */
289 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x23);
290 } else {
291 if (dm->valid_path_set == BB_PATH_A) {
292 /* @disable 1RCCA */
293 /* @CCK default is at path-a */
294 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x31);
295 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0);
296 } else if (dm->valid_path_set == BB_PATH_B) {
297 /* @disable 1RCCA */
298 /* @CCK default is at path-a */
299 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x32);
300 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5);
301 } else {
302 /* @disable 1RCCA */
303 /* @CCK default is at path-a */
304 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x33);
305 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0);
306 }
307 }
308 }
309
phydm_dynamic_select_cck_path_8822b(struct dm_struct * dm)310 void phydm_dynamic_select_cck_path_8822b(struct dm_struct *dm)
311 {
312 struct phydm_fa_struct *fa_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
313 struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b;
314
315 if (dm->ap_total_num > 10) {
316 if (drp_8822b->path_judge & BIT(2))
317 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0); /*@fix CCK Path A if AP nums > 10*/
318 return;
319 }
320
321 if (drp_8822b->path_judge & BIT(2))
322 return;
323
324 PHYDM_DBG(dm, ODM_PHY_CONFIG,
325 "phydm 8822b cck rx path selection start\n");
326
327 if (drp_8822b->path_judge & BB_PATH_A) {
328 drp_8822b->path_a_cck_fa = (u16)fa_cnt->cnt_cck_fail;
329 drp_8822b->path_judge &= ~BB_PATH_A;
330 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@change to path B collect CCKFA*/
331 } else if (drp_8822b->path_judge & BB_PATH_B) {
332 drp_8822b->path_b_cck_fa = (u16)fa_cnt->cnt_cck_fail;
333 drp_8822b->path_judge &= ~BB_PATH_B;
334
335 if (drp_8822b->path_a_cck_fa <= drp_8822b->path_b_cck_fa)
336 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0); /*@FA A<=B choose A*/
337 else
338 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@FA B>A choose B*/
339
340 drp_8822b->path_judge |= BIT(2); /*@it means we have already choosed cck rx path*/
341 }
342
343 PHYDM_DBG(dm, ODM_PHY_CONFIG, "path_a_fa = %d, path_b_fa = %d\n",
344 drp_8822b->path_a_cck_fa, drp_8822b->path_b_cck_fa);
345 }
346
phydm_somlrxhp_setting(struct dm_struct * dm,boolean switch_soml)347 void phydm_somlrxhp_setting(struct dm_struct *dm, boolean switch_soml)
348 {
349 if (switch_soml) {
350 odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd90a0000);
351 /* @Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */
352 } else {
353 odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0x090a0000);
354 }
355
356 /* @Dynamic RxHP setting with SoML on/off apply on all RFE type */
357 if (!switch_soml && (dm->rfe_type == 1 || dm->rfe_type == 6 || dm->rfe_type == 7 || dm->rfe_type == 9)) {
358 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
359 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
360 }
361
362 if (*dm->channel <= 14) {
363 if (switch_soml && (!(dm->rfe_type == 3 || dm->rfe_type == 5 || dm->rfe_type == 8 || dm->rfe_type == 17))) {
364 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
365 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
366 }
367 } else if (*dm->channel > 35) {
368 if (switch_soml) {
369 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
370 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
371 }
372 }
373 /* @for 8822B RXHP H2L, since always L will cause DFS FRD */
374 if (dm->is_dfs_band) {
375 odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29035612);
376 odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
377 }
378 #if 0
379 if (!(dm->rfe_type == 1 || dm->rfe_type == 6 || dm->rfe_type == 7 || dm->rfe_type == 9)) {
380 if (*dm->channel <= 14) {
381 /* TFBGA iFEM SoML on/off with RxHP always high-to-low */
382 if (switch_soml == true && (!(dm->rfe_type == 3 || dm->rfe_type == 5))) {
383 if (switch_soml == true) {
384 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
385 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
386 odm_set_bb_reg(dm, R_0xc04, (BIT(21) | (BIT(18))), 0x0);
387 odm_set_bb_reg(dm, R_0xe04, (BIT(21) | (BIT(18))), 0x0);
388 } else {
389 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108492);
390 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
391 }
392 }
393 } else if (*dm->channel > 35) {
394 if (switch_soml == true) {
395 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
396 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
397 odm_set_bb_reg(dm, R_0xc04, (BIT(21) | (BIT(18))), 0x0);
398 odm_set_bb_reg(dm, R_0xe04, (BIT(21) | (BIT(18))), 0x0);
399 } else {
400 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108492);
401 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
402 }
403 }
404 PHYDM_DBG(dm, ODM_COMP_API,
405 "Dynamic RxHP control with SoML is enable !!\n");
406 }
407 #endif
408 }
409
phydm_config_tx2path_8822b(struct dm_struct * dm,enum wireless_set wireless_mode,boolean is_tx2_path)410 void phydm_config_tx2path_8822b(struct dm_struct *dm,
411 enum wireless_set wireless_mode,
412 boolean is_tx2_path)
413 {
414 if (wireless_mode == WIRELESS_CCK) {
415 if (is_tx2_path)
416 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
417 else
418 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
419 } else {
420 if (is_tx2_path)
421 odm_set_bb_reg(dm, R_0x93c, 0xf00000, 0x3);
422 else
423 odm_set_bb_reg(dm, R_0x93c, 0xf00000, 0x1);
424 }
425 }
426
427 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_dynamic_ant_weighting_8822b(void * dm_void)428 void phydm_dynamic_ant_weighting_8822b(void *dm_void)
429 {
430 struct dm_struct *dm = (struct dm_struct *)dm_void;
431 u8 rssi_l2h = 43, rssi_h2l = 37;
432 u8 reg_8;
433
434 if (dm->is_disable_dym_ant_weighting)
435 return;
436 #ifdef CONFIG_MCC_DM
437 if (dm->is_stop_dym_ant_weighting)
438 return;
439 #endif
440 if (*dm->channel <= 14) {
441 if (dm->rssi_min >= rssi_l2h) {
442 odm_set_bb_reg(dm, R_0x98c, 0x7fc0000, 0x0);
443
444 /*@equal weighting*/
445 reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
446 PHYDM_DBG(dm, ODM_COMP_API,
447 "Equal weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
448 dm->rssi_min, reg_8);
449 } else if (dm->rssi_min <= rssi_h2l) {
450 odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
451
452 /*@fix sec_min_wgt = 1/2*/
453 reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
454 PHYDM_DBG(dm, ODM_COMP_API,
455 "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
456 dm->rssi_min, reg_8);
457 }
458 } else {
459 odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
460
461 reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
462 PHYDM_DBG(dm, ODM_COMP_API,
463 "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
464 dm->rssi_min, reg_8);
465 /*@fix sec_min_wgt = 1/2*/
466 }
467 }
468 #endif
469
470
471 #ifdef CONFIG_DYNAMIC_BYPASS
472 void
phydm_pw_sat_8822b(struct dm_struct * dm,u8 rssi_value)473 phydm_pw_sat_8822b(
474 struct dm_struct *dm,
475 u8 rssi_value
476 )
477 {
478 u8 ret=2;
479
480 if (dm->rfe_type != 2)
481 return;
482
483 /* check */
484 ret = odm_get_bb_reg(dm, 0xcb0, BIT(9));
485
486 /* apply on eFEM type*/
487 if (rssi_value >= 75) {
488 if (*dm->p_channel > 35) {
489 if (ret == 0) {
490 PHYDM_DBG(dm, ODM_PHY_CONFIG,
491 ("Already in bypass mode setting\n"));
492 return;
493 }
494 odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x8108000);
495 odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
496 odm_set_bb_reg(dm, 0x840, BIT(12), 0x1);
497 odm_set_bb_reg(dm, 0x810, (BIT(24)|BIT(25)), 0x2);
498 odm_set_bb_reg(dm, 0x814, BIT(0), 0x1);
499 odm_set_bb_reg(dm, 0x844, BIT(24), 0x1);
500
501 odm_set_bb_reg(dm, 0x830, MASKDWORD, 0x79a0eaaa);
502 odm_set_bb_reg(dm, 0xe58, BIT(20), 0x1);
503
504 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
505 0x177717);
506 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
507 0x177717);
508 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x77);
509 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x77);
510
511 PHYDM_DBG(dm, ODM_PHY_CONFIG,
512 ("External-fem turn off !!\n"));
513
514 phydm_rxagc_switch_8822b(dm, true);
515 }
516 } else if (rssi_value <= 55) {
517 if (*dm->p_channel > 35) {
518 if (ret == 1) {
519 PHYDM_DBG(dm, ODM_PHY_CONFIG,
520 ("Not in bypass mode setting\n"));
521 return;
522 }
523 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
524 0x177517);
525 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
526 0x177517);
527 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
528 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
529
530 PHYDM_DBG(dm, ODM_PHY_CONFIG,
531 ("External-fem turn on !!rssi =%d\n", rssi_value));
532
533 phydm_rxagc_switch_8822b(dm, false);
534 }
535 }
536 }
537 #endif
538
phydm_hwsetting_8822b(struct dm_struct * dm)539 void phydm_hwsetting_8822b(struct dm_struct *dm)
540 {
541 struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b;
542 u8 set_result_nbi = PHYDM_SET_NO_NEED;
543
544 if ((dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B)) {
545 phydm_dynamic_parameters_ota(dm);
546 } else {
547 if (!dm->bhtstfdisabled)
548 phydm_dynamic_switch_htstf_mumimo_8822b(dm);
549 else
550 PHYDM_DBG(dm, ODM_PHY_CONFIG,
551 "Default HT-STF gain control setting\n");
552 }
553
554 phydm_dynamic_ant_weighting(dm);
555
556 if (dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) {
557 /* PD TH modify due to enlarge MF windows size */
558 odm_set_bb_reg(dm, 0x838, 0xf0, 0x6);
559
560 if (dm->rssi_min <= 20)
561 phydm_somlrxhp_setting(dm, false);
562 else if (dm->rssi_min >= 25)
563 phydm_somlrxhp_setting(dm, true);
564 }
565
566 if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING_CCK_PATH) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_CCK_PATH)) {
567 if (dm->is_linked)
568 phydm_dynamic_select_cck_path_8822b(dm);
569 else
570 drp_8822b->path_judge |= ((~BIT(2)) | BB_PATH_A | BB_PATH_B);
571 }
572
573 if (dm->p_advance_ota & PHYDM_LENOVO_OTA_SETTING_NBI_CSI) {
574 if ((*dm->band_width == CHANNEL_WIDTH_80) && (*dm->channel == 157)) {
575 set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5760, PHYDM_DONT_CARE);
576 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Enable NBI\n");
577 }
578 }
579 }
580
581 #endif /* RTL8822B_SUPPORT == 1 */
582