1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19
20 #include "mp_precomp.h"
21 #include "phydm_precomp.h"
22
23 void
phydm_rx_statistic_cal(struct PHY_DM_STRUCT * p_phydm,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo)24 phydm_rx_statistic_cal(
25 struct PHY_DM_STRUCT *p_phydm,
26 u8 *p_phy_status,
27 struct phydm_perpkt_info_struct *p_pktinfo
28 )
29 {
30 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
31 struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status;
32 #endif
33 u8 date_rate = (p_pktinfo->data_rate & 0x7f);
34
35 if (date_rate <= ODM_RATE54M) {
36
37 p_phydm->phy_dbg_info.num_qry_legacy_pkt[date_rate]++;
38 /**/
39 } else if (date_rate <= ODM_RATEMCS31) {
40
41 p_phydm->phy_dbg_info.num_qry_ht_pkt[date_rate - ODM_RATEMCS0]++;
42 p_phydm->phy_dbg_info.ht_pkt_not_zero = true;
43
44 }
45 #if ODM_IC_11AC_SERIES_SUPPORT
46 else if (date_rate <= ODM_RATEVHTSS4MCS9) {
47
48 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
49 if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63) && (p_phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE)) {
50
51 p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++;
52 if (p_pktinfo->ppdu_cnt < 4) {
53 p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7);
54 p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
55 }
56 } else
57 #endif
58 {
59 p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++;
60 p_phydm->phy_dbg_info.vht_pkt_not_zero = true;
61 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
62 if (p_pktinfo->ppdu_cnt < 4) {
63 p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate;
64 p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
65 }
66 #endif
67 }
68 }
69 #endif
70 }
71
72 void
phydm_reset_phystatus_avg(struct PHY_DM_STRUCT * p_dm)73 phydm_reset_phystatus_avg(
74 struct PHY_DM_STRUCT *p_dm
75 )
76 {
77 struct phydm_phystatus_avg *p_dbg_avg = &(p_dm->phy_dbg_info.phystatus_statistic_avg);
78
79 odm_memory_set(p_dm, &(p_dbg_avg->rssi_cck_avg), 0, sizeof(struct phydm_phystatus_avg));
80 }
81
82 void
phydm_reset_phystatus_statistic(struct PHY_DM_STRUCT * p_dm)83 phydm_reset_phystatus_statistic(
84 struct PHY_DM_STRUCT *p_dm
85 )
86 {
87 struct phydm_phystatus_statistic *p_dbg_statistic = &(p_dm->phy_dbg_info.phystatus_statistic_info);
88
89 odm_memory_set(p_dm, &(p_dbg_statistic->rssi_cck_sum), 0, sizeof(struct phydm_phystatus_statistic));
90 }
91
92 void
phydm_avg_phystatus_index(struct PHY_DM_STRUCT * p_dm,struct phydm_phyinfo_struct * p_phy_info,struct phydm_perpkt_info_struct * p_pktinfo)93 phydm_avg_phystatus_index(
94 struct PHY_DM_STRUCT *p_dm,
95 struct phydm_phyinfo_struct *p_phy_info,
96 struct phydm_perpkt_info_struct *p_pktinfo
97 )
98 {
99 u8 rate_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
100 struct phydm_phystatus_statistic *p_dbg_statistic = &(p_dm->phy_dbg_info.phystatus_statistic_info);
101
102 if (p_pktinfo->data_rate <= ODM_RATE11M) {
103
104 /*RSSI*/
105 p_dbg_statistic->rssi_cck_sum += p_phy_info->rx_mimo_signal_strength[0];
106 p_dbg_statistic->rssi_cck_cnt++;
107 } else if (p_pktinfo->data_rate <= ODM_RATE54M) {
108
109 /*evm*/
110 p_dbg_statistic->evm_ofdm_sum += p_phy_info->rx_mimo_evm_dbm[0];
111
112 /*SNR*/
113 p_dbg_statistic->snr_ofdm_sum += p_phy_info->rx_snr[0];
114
115 /*RSSI*/
116 p_dbg_statistic->rssi_ofdm_sum += p_phy_info->rx_mimo_signal_strength[0];
117 p_dbg_statistic->rssi_ofdm_cnt++;
118 } else if (rate_ss == 1) {
119
120 /*evm*/
121 p_dbg_statistic->evm_1ss_sum += p_phy_info->rx_mimo_evm_dbm[0];
122
123 /*SNR*/
124 p_dbg_statistic->snr_1ss_sum += p_phy_info->rx_snr[0];
125
126 p_dbg_statistic->rssi_1ss_sum += p_phy_info->rx_mimo_signal_strength[0];
127 p_dbg_statistic->rssi_1ss_cnt++;
128 } else if (rate_ss == 2) {
129 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
130 /*evm*/
131 p_dbg_statistic->evm_2ss_sum[0] += p_phy_info->rx_mimo_evm_dbm[0];
132 p_dbg_statistic->evm_2ss_sum[1] += p_phy_info->rx_mimo_evm_dbm[1];
133
134 /*SNR*/
135 p_dbg_statistic->snr_2ss_sum[0] += p_phy_info->rx_snr[0];
136 p_dbg_statistic->snr_2ss_sum[1] += p_phy_info->rx_snr[1];
137
138 /*RSSI*/
139 p_dbg_statistic->rssi_2ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0];
140 p_dbg_statistic->rssi_2ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1];
141 p_dbg_statistic->rssi_2ss_cnt++;
142 #endif
143 } else if (rate_ss == 3) {
144 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
145 /*evm*/
146 p_dbg_statistic->evm_3ss_sum[0] += p_phy_info->rx_mimo_evm_dbm[0];
147 p_dbg_statistic->evm_3ss_sum[1] += p_phy_info->rx_mimo_evm_dbm[1];
148 p_dbg_statistic->evm_3ss_sum[2] += p_phy_info->rx_mimo_evm_dbm[2];
149
150 /*SNR*/
151 p_dbg_statistic->snr_3ss_sum[0] += p_phy_info->rx_snr[0];
152 p_dbg_statistic->snr_3ss_sum[1] += p_phy_info->rx_snr[1];
153 p_dbg_statistic->snr_3ss_sum[2] += p_phy_info->rx_snr[2];
154
155 /*RSSI*/
156 p_dbg_statistic->rssi_3ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0];
157 p_dbg_statistic->rssi_3ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1];
158 p_dbg_statistic->rssi_3ss_sum[2] += p_phy_info->rx_mimo_signal_strength[2];
159 p_dbg_statistic->rssi_3ss_cnt++;
160 #endif
161 } else if (rate_ss == 4) {
162 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
163 /*evm*/
164 p_dbg_statistic->evm_4ss_sum[0] += p_phy_info->rx_mimo_evm_dbm[0];
165 p_dbg_statistic->evm_4ss_sum[1] += p_phy_info->rx_mimo_evm_dbm[1];
166 p_dbg_statistic->evm_4ss_sum[2] += p_phy_info->rx_mimo_evm_dbm[2];
167 p_dbg_statistic->evm_4ss_sum[3] += p_phy_info->rx_mimo_evm_dbm[3];
168
169 /*SNR*/
170 p_dbg_statistic->snr_4ss_sum[0] += p_phy_info->rx_snr[0];
171 p_dbg_statistic->snr_4ss_sum[1] += p_phy_info->rx_snr[1];
172 p_dbg_statistic->snr_4ss_sum[2] += p_phy_info->rx_snr[2];
173 p_dbg_statistic->snr_4ss_sum[3] += p_phy_info->rx_snr[3];
174
175 /*RSSI*/
176 p_dbg_statistic->rssi_4ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0];
177 p_dbg_statistic->rssi_4ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1];
178 p_dbg_statistic->rssi_4ss_sum[2] += p_phy_info->rx_mimo_signal_strength[2];
179 p_dbg_statistic->rssi_4ss_sum[3] += p_phy_info->rx_mimo_signal_strength[3];
180 p_dbg_statistic->rssi_4ss_cnt++;
181 #endif
182 }
183 }
184
phydm_get_signal_quality(struct phydm_phyinfo_struct * p_phy_info,struct PHY_DM_STRUCT * p_dm,struct _phy_status_rpt_8192cd * p_phy_sta_rpt)185 u8 phydm_get_signal_quality(
186 struct phydm_phyinfo_struct *p_phy_info,
187 struct PHY_DM_STRUCT *p_dm,
188 struct _phy_status_rpt_8192cd *p_phy_sta_rpt
189 )
190 {
191 u8 SQ_rpt;
192 u8 result = 0;
193
194 if (p_phy_info->rx_pwdb_all > 40 && !p_dm->is_in_hct_test)
195 result = 100;
196 else {
197 SQ_rpt = p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all;
198
199 if (SQ_rpt > 64)
200 result = 0;
201 else if (SQ_rpt < 20)
202 result = 100;
203 else
204 result = ((64 - SQ_rpt) * 100) / 44;
205
206 }
207
208 return result;
209 }
210
211 u8
phydm_query_rx_pwr_percentage(s8 ant_power)212 phydm_query_rx_pwr_percentage(
213 s8 ant_power
214 )
215 {
216 if ((ant_power <= -100) || (ant_power >= 20))
217 return 0;
218 else if (ant_power >= 0)
219 return 100;
220 else
221 return 100 + ant_power;
222 }
223
224
225 s32
phydm_signal_scale_mapping_92c_series(struct PHY_DM_STRUCT * p_dm,s32 curr_sig)226 phydm_signal_scale_mapping_92c_series(
227 struct PHY_DM_STRUCT *p_dm,
228 s32 curr_sig
229 )
230 {
231 s32 ret_sig = 0;
232 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
233 if (p_dm->support_interface == ODM_ITRF_PCIE) {
234 /* step 1. Scale mapping. */
235 if (curr_sig >= 61 && curr_sig <= 100)
236 ret_sig = 90 + ((curr_sig - 60) / 4);
237 else if (curr_sig >= 41 && curr_sig <= 60)
238 ret_sig = 78 + ((curr_sig - 40) / 2);
239 else if (curr_sig >= 31 && curr_sig <= 40)
240 ret_sig = 66 + (curr_sig - 30);
241 else if (curr_sig >= 21 && curr_sig <= 30)
242 ret_sig = 54 + (curr_sig - 20);
243 else if (curr_sig >= 5 && curr_sig <= 20)
244 ret_sig = 42 + (((curr_sig - 5) * 2) / 3);
245 else if (curr_sig == 4)
246 ret_sig = 36;
247 else if (curr_sig == 3)
248 ret_sig = 27;
249 else if (curr_sig == 2)
250 ret_sig = 18;
251 else if (curr_sig == 1)
252 ret_sig = 9;
253 else
254 ret_sig = curr_sig;
255 }
256 #endif
257
258 #if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
259 if ((p_dm->support_interface == ODM_ITRF_USB) || (p_dm->support_interface == ODM_ITRF_SDIO)) {
260 if (curr_sig >= 51 && curr_sig <= 100)
261 ret_sig = 100;
262 else if (curr_sig >= 41 && curr_sig <= 50)
263 ret_sig = 80 + ((curr_sig - 40) * 2);
264 else if (curr_sig >= 31 && curr_sig <= 40)
265 ret_sig = 66 + (curr_sig - 30);
266 else if (curr_sig >= 21 && curr_sig <= 30)
267 ret_sig = 54 + (curr_sig - 20);
268 else if (curr_sig >= 10 && curr_sig <= 20)
269 ret_sig = 42 + (((curr_sig - 10) * 2) / 3);
270 else if (curr_sig >= 5 && curr_sig <= 9)
271 ret_sig = 22 + (((curr_sig - 5) * 3) / 2);
272 else if (curr_sig >= 1 && curr_sig <= 4)
273 ret_sig = 6 + (((curr_sig - 1) * 3) / 2);
274 else
275 ret_sig = curr_sig;
276 }
277
278 #endif
279 return ret_sig;
280 }
281
282 s32
phydm_signal_scale_mapping(struct PHY_DM_STRUCT * p_dm,s32 curr_sig)283 phydm_signal_scale_mapping(
284 struct PHY_DM_STRUCT *p_dm,
285 s32 curr_sig
286 )
287 {
288 #ifdef CONFIG_SIGNAL_SCALE_MAPPING
289 return phydm_signal_scale_mapping_92c_series(p_dm, curr_sig);
290 #else
291 return curr_sig;
292 #endif
293
294 }
295
296 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
phydm_sq_patch_rt_cid_819x_lenovo(struct PHY_DM_STRUCT * p_dm,u8 is_cck_rate,u8 PWDB_ALL,u8 path,u8 RSSI)297 static u8 phydm_sq_patch_rt_cid_819x_lenovo(
298 struct PHY_DM_STRUCT *p_dm,
299 u8 is_cck_rate,
300 u8 PWDB_ALL,
301 u8 path,
302 u8 RSSI
303 )
304 {
305 u8 SQ = 0;
306
307 if (is_cck_rate) {
308
309 if (IS_HARDWARE_TYPE_8192E(p_dm->adapter)) {
310
311 /* */
312 /* <Roger_Notes> Expected signal strength and bars indication at Lenovo lab. 2013.04.11 */
313 /* 802.11n, 802.11b, 802.11g only at channel 6 */
314 /* */
315 /* Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) */
316 /* 50 5 -49 */
317 /* 55 5 -49 */
318 /* 60 5 -50 */
319 /* 65 5 -51 */
320 /* 70 5 -52 */
321 /* 75 5 -54 */
322 /* 80 5 -55 */
323 /* 85 4 -60 */
324 /* 90 3 -63 */
325 /* 95 3 -65 */
326 /* 100 2 -67 */
327 /* 102 2 -67 */
328 /* 104 1 -70 */
329 /* */
330
331 if (PWDB_ALL >= 50)
332 SQ = 100;
333 else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
334 SQ = 80;
335 else if (PWDB_ALL >= 31 && PWDB_ALL < 35)
336 SQ = 60;
337 else if (PWDB_ALL >= 22 && PWDB_ALL < 31)
338 SQ = 40;
339 else if (PWDB_ALL >= 18 && PWDB_ALL < 22)
340 SQ = 20;
341 else
342 SQ = 10;
343 } else {
344 if (PWDB_ALL >= 50)
345 SQ = 100;
346 else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
347 SQ = 80;
348 else if (PWDB_ALL >= 22 && PWDB_ALL < 35)
349 SQ = 60;
350 else if (PWDB_ALL >= 18 && PWDB_ALL < 22)
351 SQ = 40;
352 else
353 SQ = 10;
354 }
355
356 } else {
357 /* OFDM rate */
358
359 if (IS_HARDWARE_TYPE_8192E(p_dm->adapter)) {
360 if (RSSI >= 45)
361 SQ = 100;
362 else if (RSSI >= 22 && RSSI < 45)
363 SQ = 80;
364 else if (RSSI >= 18 && RSSI < 22)
365 SQ = 40;
366 else
367 SQ = 20;
368 } else {
369 if (RSSI >= 45)
370 SQ = 100;
371 else if (RSSI >= 22 && RSSI < 45)
372 SQ = 80;
373 else if (RSSI >= 18 && RSSI < 22)
374 SQ = 40;
375 else
376 SQ = 20;
377 }
378 }
379
380 RT_TRACE(COMP_DBG, DBG_TRACE, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ));
381
382
383 return SQ;
384 }
385
phydm_sq_patch_rt_cid_819x_acer(struct PHY_DM_STRUCT * p_dm,u8 is_cck_rate,u8 PWDB_ALL,u8 path,u8 RSSI)386 static u8 phydm_sq_patch_rt_cid_819x_acer(
387 struct PHY_DM_STRUCT *p_dm,
388 u8 is_cck_rate,
389 u8 PWDB_ALL,
390 u8 path,
391 u8 RSSI
392 )
393 {
394 u8 SQ = 0;
395
396 if (is_cck_rate) {
397
398 RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n"));
399
400 #if OS_WIN_FROM_WIN8(OS_VERSION)
401
402 if (PWDB_ALL >= 50)
403 SQ = 100;
404 else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
405 SQ = 80;
406 else if (PWDB_ALL >= 30 && PWDB_ALL < 35)
407 SQ = 60;
408 else if (PWDB_ALL >= 25 && PWDB_ALL < 30)
409 SQ = 40;
410 else if (PWDB_ALL >= 20 && PWDB_ALL < 25)
411 SQ = 20;
412 else
413 SQ = 10;
414 #else
415 if (PWDB_ALL >= 50)
416 SQ = 100;
417 else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
418 SQ = 80;
419 else if (PWDB_ALL >= 30 && PWDB_ALL < 35)
420 SQ = 60;
421 else if (PWDB_ALL >= 25 && PWDB_ALL < 30)
422 SQ = 40;
423 else if (PWDB_ALL >= 20 && PWDB_ALL < 25)
424 SQ = 20;
425 else
426 SQ = 10;
427
428 if (PWDB_ALL == 0) /* Abnormal case, do not indicate the value above 20 on Win7 */
429 SQ = 20;
430 #endif
431
432
433
434 } else {
435 /* OFDM rate */
436
437 if (IS_HARDWARE_TYPE_8192E(p_dm->adapter)) {
438 if (RSSI >= 45)
439 SQ = 100;
440 else if (RSSI >= 22 && RSSI < 45)
441 SQ = 80;
442 else if (RSSI >= 18 && RSSI < 22)
443 SQ = 40;
444 else
445 SQ = 20;
446 } else {
447 if (RSSI >= 35)
448 SQ = 100;
449 else if (RSSI >= 30 && RSSI < 35)
450 SQ = 80;
451 else if (RSSI >= 25 && RSSI < 30)
452 SQ = 40;
453 else
454 SQ = 20;
455 }
456 }
457
458 RT_TRACE(COMP_DBG, DBG_LOUD, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ));
459
460
461 return SQ;
462 }
463 #endif
464
465 static u8
phydm_evm_db_to_percentage(s8 value)466 phydm_evm_db_to_percentage(
467 s8 value
468 )
469 {
470 /* */
471 /* -33dB~0dB to 0%~99% */
472 /* */
473 s8 ret_val;
474
475 ret_val = value;
476 ret_val /= 2;
477
478 /*dbg_print("value=%d\n", value);*/
479 /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/
480 #ifdef ODM_EVM_ENHANCE_ANTDIV
481 if (ret_val >= 0)
482 ret_val = 0;
483
484 if (ret_val <= -40)
485 ret_val = -40;
486
487 ret_val = 0 - ret_val;
488 ret_val *= 3;
489 #else
490 if (ret_val >= 0)
491 ret_val = 0;
492
493 if (ret_val <= -33)
494 ret_val = -33;
495
496 ret_val = 0 - ret_val;
497 ret_val *= 3;
498
499 if (ret_val == 99)
500 ret_val = 100;
501 #endif
502
503 return (u8)ret_val;
504 }
505
506 static u8
phydm_evm_dbm_jaguar_series(s8 value)507 phydm_evm_dbm_jaguar_series(
508 s8 value
509 )
510 {
511 s8 ret_val = value;
512
513 /* -33dB~0dB to 33dB ~ 0dB */
514 if (ret_val == -128)
515 ret_val = 127;
516 else if (ret_val < 0)
517 ret_val = 0 - ret_val;
518
519 ret_val = ret_val >> 1;
520 return (u8)ret_val;
521 }
522
523 static s16
phydm_cfo(s8 value)524 phydm_cfo(
525 s8 value
526 )
527 {
528 s16 ret_val;
529
530 if (value < 0) {
531 ret_val = 0 - value;
532 ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */
533 ret_val = ret_val | BIT(12); /* set bit12 as 1 for negative cfo */
534 } else {
535 ret_val = value;
536 ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */
537 }
538 return ret_val;
539 }
540
541 s8
phydm_cck_rssi_convert(struct PHY_DM_STRUCT * p_dm,u16 lna_idx,u8 vga_idx)542 phydm_cck_rssi_convert(
543 struct PHY_DM_STRUCT *p_dm,
544 u16 lna_idx,
545 u8 vga_idx
546 )
547 {
548 return (p_dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));
549 }
550
551 void
phydm_get_cck_rssi_table_from_reg(struct PHY_DM_STRUCT * p_dm)552 phydm_get_cck_rssi_table_from_reg(
553 struct PHY_DM_STRUCT *p_dm
554 )
555 {
556 u8 used_lna_idx_tmp;
557 u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd; /*example: {-53, -43, -33, -27, -19, -13, -3, 1}*/ /*{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/
558 u8 i;
559
560 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("CCK LNA Gain table init\n"));
561
562 if (!(p_dm->support_ic_type & (ODM_RTL8197F)))
563 return;
564
565 reg_0xa80 = odm_get_bb_reg(p_dm, 0xa80, 0xFFFF);
566 reg_0xabc = odm_get_bb_reg(p_dm, 0xabc, MASKDWORD);
567
568 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("reg_0xa80 = 0x%x\n", reg_0xa80));
569 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("reg_0xabc = 0x%x\n", reg_0xabc));
570
571 for (i = 0; i <= 3; i++) {
572 used_lna_idx_tmp = (u8)((reg_0xa80 >> (4*i)) & 0x7);
573 p_dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)((reg_0xabc >> (8*i)) & 0xff);
574 }
575
576 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n",
577 p_dm->cck_lna_gain_table[0],
578 p_dm->cck_lna_gain_table[1],
579 p_dm->cck_lna_gain_table[2],
580 p_dm->cck_lna_gain_table[3],
581 p_dm->cck_lna_gain_table[4],
582 p_dm->cck_lna_gain_table[5],
583 p_dm->cck_lna_gain_table[6],
584 p_dm->cck_lna_gain_table[7]));
585
586 }
587
588 u8
phydm_rate_to_num_ss(struct PHY_DM_STRUCT * p_dm,u8 data_rate)589 phydm_rate_to_num_ss(
590 struct PHY_DM_STRUCT *p_dm,
591 u8 data_rate
592 )
593 {
594 u8 num_ss = 1;
595
596 if (data_rate <= ODM_RATE54M)
597 num_ss = 1;
598 else if (data_rate <= ODM_RATEMCS31)
599 num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
600 else if (data_rate <= ODM_RATEVHTSS1MCS9)
601 num_ss = 1;
602 else if (data_rate <= ODM_RATEVHTSS2MCS9)
603 num_ss = 2;
604 else if (data_rate <= ODM_RATEVHTSS3MCS9)
605 num_ss = 3;
606 else if (data_rate <= ODM_RATEVHTSS4MCS9)
607 num_ss = 4;
608
609 return num_ss;
610 }
611
612
613
614 #if (RTL8703B_SUPPORT == 1)
615 s8
phydm_cck_rssi_8703B(u16 LNA_idx,u8 VGA_idx)616 phydm_cck_rssi_8703B(
617 u16 LNA_idx,
618 u8 VGA_idx
619 )
620 {
621 s8 rx_pwr_all = 0x00;
622
623 switch (LNA_idx) {
624 case 0xf:
625 rx_pwr_all = -48 - (2 * VGA_idx);
626 break;
627 case 0xb:
628 rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/
629 break;
630 case 0xa:
631 rx_pwr_all = -36 - (2 * VGA_idx);
632 break;
633 case 8:
634 rx_pwr_all = -32 - (2 * VGA_idx);
635 break;
636 case 7:
637 rx_pwr_all = -19 - (2 * VGA_idx);
638 break;
639 case 4:
640 rx_pwr_all = -6 - (2 * VGA_idx);
641 break;
642 case 0:
643 rx_pwr_all = -2 - (2 * VGA_idx);
644 break;
645 default:
646 /*rx_pwr_all = -53+(2*(31-VGA_idx));*/
647 /*dbg_print("wrong LNA index\n");*/
648 break;
649
650 }
651 return rx_pwr_all;
652 }
653 #endif
654
655 #if (RTL8195A_SUPPORT == 1)
656 s8
phydm_cck_rssi_8195a(struct PHY_DM_STRUCT * p_dm,u16 LNA_idx,u8 VGA_idx)657 phydm_cck_rssi_8195a(
658 struct PHY_DM_STRUCT *p_dm,
659 u16 LNA_idx,
660 u8 VGA_idx
661 )
662 {
663 s8 rx_pwr_all = 0;
664 s8 lna_gain = 0;
665 s8 lna_gain_table_0[8] = {0, -8, -15, -22, -29, -36, -45, -54};
666 s8 lna_gain_table_1[8] = {0, -8, -15, -22, -29, -36, -45, -54};/*use 8195A to calibrate this table. 2016.06.24, Dino*/
667
668 if (p_dm->cck_agc_report_type == 0)
669 lna_gain = lna_gain_table_0[LNA_idx];
670 else
671 lna_gain = lna_gain_table_1[LNA_idx];
672
673 rx_pwr_all = lna_gain - (2 * VGA_idx);
674
675 return rx_pwr_all;
676 }
677 #endif
678
679 #if (RTL8192E_SUPPORT == 1)
680 s8
phydm_cck_rssi_8192e(struct PHY_DM_STRUCT * p_dm,u16 LNA_idx,u8 VGA_idx)681 phydm_cck_rssi_8192e(
682 struct PHY_DM_STRUCT *p_dm,
683 u16 LNA_idx,
684 u8 VGA_idx
685 )
686 {
687 s8 rx_pwr_all = 0;
688 s8 lna_gain = 0;
689 s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44};
690 s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/
691
692 if (p_dm->cck_agc_report_type == 0)
693 lna_gain = lna_gain_table_0[LNA_idx];
694 else
695 lna_gain = lna_gain_table_1[LNA_idx];
696
697 rx_pwr_all = lna_gain - (2 * VGA_idx);
698
699 return rx_pwr_all;
700 }
701 #endif
702
703 #if (RTL8188E_SUPPORT == 1)
704 s8
phydm_cck_rssi_8188e(struct PHY_DM_STRUCT * p_dm,u16 LNA_idx,u8 VGA_idx)705 phydm_cck_rssi_8188e(
706 struct PHY_DM_STRUCT *p_dm,
707 u16 LNA_idx,
708 u8 VGA_idx
709 )
710 {
711 s8 rx_pwr_all = 0;
712 s8 lna_gain = 0;
713 s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/
714 s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/
715
716 if (p_dm->cut_version >= ODM_CUT_I) /*SMIC*/
717 lna_gain = lna_gain_table_0[LNA_idx];
718 else /*TSMC*/
719 lna_gain = lna_gain_table_1[LNA_idx];
720
721 rx_pwr_all = lna_gain - (2 * VGA_idx);
722
723 return rx_pwr_all;
724 }
725 #endif
726
727 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
728 void
phydm_rx_phy_status92c_series_parsing(struct PHY_DM_STRUCT * p_dm,struct phydm_phyinfo_struct * p_phy_info,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo)729 phydm_rx_phy_status92c_series_parsing(
730 struct PHY_DM_STRUCT *p_dm,
731 struct phydm_phyinfo_struct *p_phy_info,
732 u8 *p_phy_status,
733 struct phydm_perpkt_info_struct *p_pktinfo
734 )
735 {
736 u8 i, max_spatial_stream;
737 s8 rx_pwr[4], rx_pwr_all = 0;
738 u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT;
739 u8 RSSI, total_rssi = 0;
740 boolean is_cck_rate = false;
741 u8 rf_rx_num = 0;
742 u8 LNA_idx = 0;
743 u8 VGA_idx = 0;
744 u8 cck_agc_rpt;
745 u8 num_ss;
746 u8 stream_rxevm_tmp = 0;
747 struct _phy_status_rpt_8192cd *p_phy_sta_rpt = (struct _phy_status_rpt_8192cd *)p_phy_status;
748
749 is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
750 p_dm->rate_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
751
752 if (p_pktinfo->is_to_self)
753 p_dm->curr_station_id = p_pktinfo->station_id;
754
755 p_phy_info->rx_mimo_signal_quality[RF_PATH_A] = -1;
756 p_phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
757
758
759 if (is_cck_rate) {
760 p_dm->phy_dbg_info.num_qry_phy_status_cck++;
761 cck_agc_rpt = p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a;
762
763 if (p_dm->support_ic_type & (ODM_RTL8703B)) {
764
765 #if (RTL8703B_SUPPORT == 1)
766 if (p_dm->cck_agc_report_type == 1) { /*4 bit LNA*/
767
768 u8 cck_agc_rpt_b = (p_phy_sta_rpt->cck_rpt_b_ofdm_cfosho_b & BIT(7)) ? 1 : 0;
769
770 LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5);
771 VGA_idx = (cck_agc_rpt & 0x1F);
772
773 rx_pwr_all = phydm_cck_rssi_8703B(LNA_idx, VGA_idx);
774 }
775 #endif
776 } else { /*3 bit LNA*/
777
778 LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
779 VGA_idx = (cck_agc_rpt & 0x1F);
780
781 if (p_dm->support_ic_type & (ODM_RTL8188E)) {
782
783 #if (RTL8188E_SUPPORT == 1)
784 rx_pwr_all = phydm_cck_rssi_8188e(p_dm, LNA_idx, VGA_idx);
785 /**/
786 #endif
787 }
788 #if (RTL8192E_SUPPORT == 1)
789 else if (p_dm->support_ic_type & (ODM_RTL8192E)) {
790
791 rx_pwr_all = phydm_cck_rssi_8192e(p_dm, LNA_idx, VGA_idx);
792 /**/
793 }
794 #endif
795 #if (RTL8723B_SUPPORT == 1)
796 else if (p_dm->support_ic_type & (ODM_RTL8723B)) {
797
798 rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx);
799 /**/
800 }
801 #endif
802 #if (RTL8188F_SUPPORT == 1)
803 else if (p_dm->support_ic_type & (ODM_RTL8188F)) {
804
805 rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx);
806 /**/
807 }
808 #endif
809 #if (RTL8195A_SUPPORT == 1)
810 else if (p_dm->support_ic_type & (ODM_RTL8195A)) {
811
812 rx_pwr_all = phydm_cck_rssi_8195a(LNA_idx, VGA_idx);
813 /**/
814 }
815 #endif
816 }
817
818 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
819 p_dm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all));
820
821 if (p_dm->board_type & ODM_BOARD_EXT_LNA)
822 rx_pwr_all -= p_dm->ext_lna_gain;
823
824 PWDB_ALL = phydm_query_rx_pwr_percentage(rx_pwr_all);
825
826 if (p_pktinfo->is_to_self) {
827 p_dm->cck_lna_idx = LNA_idx;
828 p_dm->cck_vga_idx = VGA_idx;
829 }
830 p_phy_info->rx_pwdb_all = PWDB_ALL;
831
832 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
833 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL;
834 p_phy_info->recv_signal_power = rx_pwr_all;
835 #endif
836
837 /* (3) Get Signal Quality (EVM) */
838
839
840 {
841 u8 SQ;
842 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
843 if (p_dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
844 SQ = phydm_sq_patch_rt_cid_819x_lenovo(p_dm, is_cck_rate, PWDB_ALL, 0, 0);
845 else if (p_dm->iot_table.win_patch_id == RT_CID_819X_ACER)
846 SQ = phydm_sq_patch_rt_cid_819x_acer(p_dm, is_cck_rate, PWDB_ALL, 0, 0);
847 else
848 #endif
849 SQ = phydm_get_signal_quality(p_phy_info, p_dm, p_phy_sta_rpt);
850
851 /* dbg_print("cck SQ = %d\n", SQ); */
852 p_phy_info->signal_quality = SQ;
853 p_phy_info->rx_mimo_signal_quality[RF_PATH_A] = SQ;
854 p_phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
855 }
856
857 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
858 if (i == 0)
859 p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL;
860 else
861 p_phy_info->rx_mimo_signal_strength[1] = 0;
862 }
863 } else { /* 2 is OFDM rate */
864 p_dm->phy_dbg_info.num_qry_phy_status_ofdm++;
865
866 /* */
867 /* (1)Get RSSI for HT rate */
868 /* */
869
870 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
871 /* 2008/01/30 MH we will judge RF RX path now. */
872 if (p_dm->rf_path_rx_enable & BIT(i))
873 rf_rx_num++;
874 /* else */
875 /* continue; */
876
877 rx_pwr[i] = ((p_phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) - 110;
878
879 if (p_pktinfo->is_to_self) {
880 p_dm->ofdm_agc_idx[i] = (p_phy_sta_rpt->path_agc[i].gain & 0x3F);
881 /**/
882 }
883
884 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
885 p_phy_info->rx_pwr[i] = rx_pwr[i];
886 #endif
887
888 /* Translate DBM to percentage. */
889 RSSI = phydm_query_rx_pwr_percentage(rx_pwr[i]);
890 total_rssi += RSSI;
891 /* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */
892
893 p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI;
894
895 /* Get Rx snr value in DB */
896 p_phy_info->rx_snr[i] = p_dm->phy_dbg_info.rx_snr_db[i] = (s8)(p_phy_sta_rpt->path_rxsnr[i] / 2);
897
898 /* Record Signal Strength for next packet */
899
900 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
901 if (i == RF_PATH_A) {
902 if (p_dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
903 p_phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_lenovo(p_dm, is_cck_rate, PWDB_ALL, i, RSSI);
904 } else if (p_dm->iot_table.win_patch_id == RT_CID_819X_ACER)
905 p_phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(p_dm, is_cck_rate, PWDB_ALL, 0, RSSI);
906 }
907 #endif
908 }
909
910
911 /* */
912 /* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */
913 /* */
914 rx_pwr_all = (((p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110;
915
916 PWDB_ALL_BT = PWDB_ALL = phydm_query_rx_pwr_percentage(rx_pwr_all);
917
918
919 p_phy_info->rx_pwdb_all = PWDB_ALL;
920 /* PHYDM_DBG(p_dm,DBG_RSSI_MNTR, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */
921 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
922 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT;
923 p_phy_info->rx_power = rx_pwr_all;
924 p_phy_info->recv_signal_power = rx_pwr_all;
925 #endif
926
927 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
928 if (p_dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
929 /* do nothing */
930 } else if (p_dm->iot_table.win_patch_id == RT_CID_819X_ACER) {
931 /* do nothing */
932 } else
933 #endif
934 {
935 /* (3)EVM of HT rate */
936
937 if (p_pktinfo->data_rate >= ODM_RATEMCS8 && p_pktinfo->data_rate <= ODM_RATEMCS15)
938 max_spatial_stream = 2; /* both spatial stream make sense */
939 else
940 max_spatial_stream = 1; /* only spatial stream 1 makes sense */
941
942 for (i = 0; i < max_spatial_stream; i++) {
943 /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
944 /* fill most significant bit to "zero" when doing shifting operation which may change a negative */
945 /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
946 EVM = phydm_evm_db_to_percentage((p_phy_sta_rpt->stream_rxevm[i])); /* dbm */
947
948 /* GET_RX_STATUS_DESC_RX_MCS(p_desc), p_drv_info->rxevm[i], "%", EVM)); */
949
950 if (i == RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
951 p_phy_info->signal_quality = (u8)(EVM & 0xff);
952
953 p_phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
954
955 if (p_phy_sta_rpt->stream_rxevm[i] < 0)
956 stream_rxevm_tmp = (u8)(0 - (p_phy_sta_rpt->stream_rxevm[i]));
957
958 if (stream_rxevm_tmp == 64)
959 stream_rxevm_tmp = 0;
960
961 p_phy_info->rx_mimo_evm_dbm[i] = stream_rxevm_tmp;
962
963 }
964 }
965
966 num_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
967 odm_parsing_cfo(p_dm, p_pktinfo, p_phy_sta_rpt->path_cfotail, num_ss);
968
969 }
970 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
971 /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
972 /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
973 if (is_cck_rate) {
974 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
975 /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */
976 p_phy_info->signal_strength = SignalScaleProc(p_dm->adapter, PWDB_ALL, true, true);
977 #else
978 p_phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(p_dm, PWDB_ALL));/*PWDB_ALL;*/
979 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
980 } else {
981 if (rf_rx_num != 0) {
982 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
983 /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */
984 p_phy_info->signal_strength = SignalScaleProc(p_dm->adapter, (total_rssi /= rf_rx_num), true, false);
985 #else
986 p_phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(p_dm, total_rssi /= rf_rx_num));
987 #endif
988 }
989 }
990 #endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/
991
992 /* dbg_print("is_cck_rate = %d, p_phy_info->rx_pwdb_all = %d, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", */
993 /* is_cck_rate, p_phy_info->rx_pwdb_all, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a); */
994
995 /* For 92C/92D HW (Hybrid) Antenna Diversity */
996 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
997 /* For 88E HW Antenna Diversity */
998 p_dm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->ant_sel;
999 p_dm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->ant_sel_b;
1000 p_dm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antsel_rx_keep_2;
1001 #endif
1002
1003 if (p_pktinfo->is_packet_match_bssid) {
1004 phydm_avg_phystatus_index(p_dm, p_phy_info, p_pktinfo);
1005 phydm_rx_statistic_cal(p_dm, p_phy_status, p_pktinfo);
1006 }
1007
1008 }
1009 #endif
1010
1011 #if ODM_IC_11AC_SERIES_SUPPORT
1012
1013 void
phydm_rx_phy_bw_jaguar_series_parsing(struct phydm_phyinfo_struct * p_phy_info,struct phydm_perpkt_info_struct * p_pktinfo,struct _phy_status_rpt_8812 * p_phy_sta_rpt)1014 phydm_rx_phy_bw_jaguar_series_parsing(
1015 struct phydm_phyinfo_struct *p_phy_info,
1016 struct phydm_perpkt_info_struct *p_pktinfo,
1017 struct _phy_status_rpt_8812 *p_phy_sta_rpt
1018 )
1019 {
1020
1021 if (p_pktinfo->data_rate <= ODM_RATE54M) {
1022 switch (p_phy_sta_rpt->r_RFMOD) {
1023 case 1:
1024 if (p_phy_sta_rpt->sub_chnl == 0)
1025 p_phy_info->band_width = 1;
1026 else
1027 p_phy_info->band_width = 0;
1028 break;
1029
1030 case 2:
1031 if (p_phy_sta_rpt->sub_chnl == 0)
1032 p_phy_info->band_width = 2;
1033 else if (p_phy_sta_rpt->sub_chnl == 9 || p_phy_sta_rpt->sub_chnl == 10)
1034 p_phy_info->band_width = 1;
1035 else
1036 p_phy_info->band_width = 0;
1037 break;
1038
1039 default:
1040 case 0:
1041 p_phy_info->band_width = 0;
1042 break;
1043 }
1044 }
1045
1046 }
1047
1048 void
phydm_rx_phy_status_jaguar_series_parsing(struct PHY_DM_STRUCT * p_dm,struct phydm_phyinfo_struct * p_phy_info,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo)1049 phydm_rx_phy_status_jaguar_series_parsing(
1050 struct PHY_DM_STRUCT *p_dm,
1051 struct phydm_phyinfo_struct *p_phy_info,
1052 u8 *p_phy_status,
1053 struct phydm_perpkt_info_struct *p_pktinfo
1054 )
1055 {
1056 u8 i, max_spatial_stream;
1057 s8 rx_pwr[4], rx_pwr_all = 0;
1058 u8 EVM = 0, evm_dbm, PWDB_ALL = 0, PWDB_ALL_BT;
1059 u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0;
1060 u8 is_cck_rate = 0;
1061 u8 rf_rx_num = 0;
1062 u8 cck_highpwr = 0;
1063 u8 LNA_idx, VGA_idx;
1064 struct _phy_status_rpt_8812 *p_phy_sta_rpt = (struct _phy_status_rpt_8812 *)p_phy_status;
1065 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1066 u8 num_ss;
1067
1068 phydm_rx_phy_bw_jaguar_series_parsing(p_phy_info, p_pktinfo, p_phy_sta_rpt);
1069
1070 is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
1071 p_dm->rate_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
1072
1073 if (p_pktinfo->is_to_self)
1074 p_dm->curr_station_id = p_pktinfo->station_id;
1075 else
1076 p_dm->curr_station_id = 0xff;
1077
1078 p_phy_info->rx_mimo_signal_quality[RF_PATH_A] = -1;
1079 p_phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
1080 p_phy_info->rx_mimo_signal_quality[RF_PATH_C] = -1;
1081 p_phy_info->rx_mimo_signal_quality[RF_PATH_D] = -1;
1082
1083 if (is_cck_rate) {
1084 u8 cck_agc_rpt;
1085
1086 p_dm->phy_dbg_info.num_qry_phy_status_cck++;
1087
1088 /*(1)Hardware does not provide RSSI for CCK*/
1089 /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/
1090
1091 /*if(p_hal_data->e_rf_power_state == e_rf_on)*/
1092 cck_highpwr = p_dm->is_cck_high_power;
1093 /*else*/
1094 /*cck_highpwr = false;*/
1095
1096 cck_agc_rpt = p_phy_sta_rpt->cfosho[0];
1097 LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
1098 VGA_idx = (cck_agc_rpt & 0x1F);
1099
1100 if (p_dm->support_ic_type == ODM_RTL8812) {
1101 switch (LNA_idx) {
1102 case 7:
1103 if (VGA_idx <= 27)
1104 rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/
1105 else
1106 rx_pwr_all = -100;
1107 break;
1108 case 6:
1109 rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/
1110 break;
1111 case 5:
1112 rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/
1113 break;
1114 case 4:
1115 rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/
1116 break;
1117 case 3:
1118 /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/
1119 rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/
1120 break;
1121 case 2:
1122 if (cck_highpwr)
1123 rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/
1124 else
1125 rx_pwr_all = -6 + 2 * (5 - VGA_idx);
1126 break;
1127 case 1:
1128 rx_pwr_all = 8 - 2 * VGA_idx;
1129 break;
1130 case 0:
1131 rx_pwr_all = 14 - 2 * VGA_idx;
1132 break;
1133 default:
1134 /*dbg_print("CCK Exception default\n");*/
1135 break;
1136 }
1137 rx_pwr_all += 6;
1138 PWDB_ALL = phydm_query_rx_pwr_percentage(rx_pwr_all);
1139
1140 if (cck_highpwr == false) {
1141 if (PWDB_ALL >= 80)
1142 PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80;
1143 else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20))
1144 PWDB_ALL += 3;
1145 if (PWDB_ALL > 100)
1146 PWDB_ALL = 100;
1147 }
1148 } else if (p_dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
1149 s8 pout = -6;
1150
1151 switch (LNA_idx) {
1152 case 5:
1153 rx_pwr_all = pout - 32 - (2 * VGA_idx);
1154 break;
1155 case 4:
1156 rx_pwr_all = pout - 24 - (2 * VGA_idx);
1157 break;
1158 case 2:
1159 rx_pwr_all = pout - 11 - (2 * VGA_idx);
1160 break;
1161 case 1:
1162 rx_pwr_all = pout + 5 - (2 * VGA_idx);
1163 break;
1164 case 0:
1165 rx_pwr_all = pout + 21 - (2 * VGA_idx);
1166 break;
1167 }
1168 PWDB_ALL = phydm_query_rx_pwr_percentage(rx_pwr_all);
1169 } else if (p_dm->support_ic_type == ODM_RTL8814A || p_dm->support_ic_type == ODM_RTL8822B) {
1170 s8 pout = -6;
1171
1172 switch (LNA_idx) {
1173 /*CCK only use LNA: 2, 3, 5, 7*/
1174 case 7:
1175 rx_pwr_all = pout - 32 - (2 * VGA_idx);
1176 break;
1177 case 5:
1178 rx_pwr_all = pout - 22 - (2 * VGA_idx);
1179 break;
1180 case 3:
1181 rx_pwr_all = pout - 2 - (2 * VGA_idx);
1182 break;
1183 case 2:
1184 rx_pwr_all = pout + 5 - (2 * VGA_idx);
1185 break;
1186 /*case 6:*/
1187 /*rx_pwr_all = pout -26 - (2*VGA_idx);*/
1188 /*break;*/
1189 /*case 4:*/
1190 /*rx_pwr_all = pout - 8 - (2*VGA_idx);*/
1191 /*break;*/
1192 /*case 1:*/
1193 /*rx_pwr_all = pout + 21 - (2*VGA_idx);*/
1194 /*break;*/
1195 /*case 0:*/
1196 /*rx_pwr_all = pout + 10 - (2*VGA_idx);*/
1197 /* break; */
1198 default:
1199 /* dbg_print("CCK Exception default\n"); */
1200 break;
1201 }
1202 PWDB_ALL = phydm_query_rx_pwr_percentage(rx_pwr_all);
1203 }
1204
1205 p_dm->cck_lna_idx = LNA_idx;
1206 p_dm->cck_vga_idx = VGA_idx;
1207 p_phy_info->rx_pwdb_all = PWDB_ALL;
1208 /* if(p_pktinfo->station_id == 0) */
1209 /* { */
1210 /* dbg_print("CCK: LNA_idx = %d, VGA_idx = %d, p_phy_info->rx_pwdb_all = %d\n", */
1211 /* LNA_idx, VGA_idx, p_phy_info->rx_pwdb_all); */
1212 /* } */
1213 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1214 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL;
1215 p_phy_info->recv_signal_power = rx_pwr_all;
1216 #endif
1217 /*(3) Get Signal Quality (EVM)*/
1218 /*if (p_pktinfo->is_packet_match_bssid)*/
1219 {
1220 u8 SQ, SQ_rpt;
1221
1222 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1223 if (p_dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
1224 SQ = phydm_sq_patch_rt_cid_819x_lenovo(p_dm, is_cck_rate, PWDB_ALL, 0, 0);
1225 else
1226 #endif
1227 if (p_phy_info->rx_pwdb_all > 40 && !p_dm->is_in_hct_test)
1228 SQ = 100;
1229 else {
1230 SQ_rpt = p_phy_sta_rpt->pwdb_all;
1231
1232 if (SQ_rpt > 64)
1233 SQ = 0;
1234 else if (SQ_rpt < 20)
1235 SQ = 100;
1236 else
1237 SQ = ((64 - SQ_rpt) * 100) / 44;
1238 }
1239
1240 /* dbg_print("cck SQ = %d\n", SQ); */
1241 p_phy_info->signal_quality = SQ;
1242 p_phy_info->rx_mimo_signal_quality[RF_PATH_A] = SQ;
1243 }
1244
1245 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1246 if (i == 0)
1247 p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL;
1248 else
1249 p_phy_info->rx_mimo_signal_strength[i] = 0;
1250 }
1251 } else {
1252 /*is OFDM rate*/
1253 p_dm_fat_table->hw_antsw_occur = p_phy_sta_rpt->hw_antsw_occur;
1254
1255 p_dm->phy_dbg_info.num_qry_phy_status_ofdm++;
1256
1257 /*(1)Get RSSI for OFDM rate*/
1258
1259 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1260 /*2008/01/30 MH we will judge RF RX path now.*/
1261 /* dbg_print("p_dm->rf_path_rx_enable = %x\n", p_dm->rf_path_rx_enable); */
1262 if (p_dm->rf_path_rx_enable & BIT(i))
1263 rf_rx_num++;
1264 /* else */
1265 /* continue; */
1266 /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/
1267 /* if((p_dm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!p_dm->is_mp_chip)) */
1268 if (i < RF_PATH_C) {
1269 rx_pwr[i] = (p_phy_sta_rpt->gain_trsw[i] & 0x7F) - 110;
1270
1271 if (p_pktinfo->is_to_self)
1272 p_dm->ofdm_agc_idx[i] = p_phy_sta_rpt->gain_trsw[i];
1273
1274 } else
1275 rx_pwr[i] = (p_phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110;
1276 /* else */
1277 /*rx_pwr[i] = ((p_phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/
1278
1279 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1280 p_phy_info->rx_pwr[i] = rx_pwr[i];
1281 #endif
1282
1283 /* Translate DBM to percentage. */
1284 RSSI = phydm_query_rx_pwr_percentage(rx_pwr[i]);
1285
1286 /*total_rssi += RSSI;*/
1287 /*Get the best two RSSI*/
1288 if (RSSI > best_rssi && RSSI > second_rssi) {
1289 second_rssi = best_rssi;
1290 best_rssi = RSSI;
1291 } else if (RSSI > second_rssi && RSSI <= best_rssi)
1292 second_rssi = RSSI;
1293
1294 /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/
1295
1296 p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI;
1297
1298
1299 /*Get Rx snr value in DB*/
1300 if (i < RF_PATH_C)
1301 p_phy_info->rx_snr[i] = p_dm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2;
1302 else if (p_dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))
1303 p_phy_info->rx_snr[i] = p_dm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->csi_current[i - 2] / 2;
1304
1305 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
1306 /*(2) CFO_short & CFO_tail*/
1307 if (i < RF_PATH_C) {
1308 p_phy_info->cfo_short[i] = phydm_cfo((p_phy_sta_rpt->cfosho[i]));
1309 p_phy_info->cfo_tail[i] = phydm_cfo((p_phy_sta_rpt->cfotail[i]));
1310 }
1311 #endif
1312 /* Record Signal Strength for next packet */
1313 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1314 if (p_pktinfo->is_packet_match_bssid && (i == RF_PATH_A)) {
1315 if (p_dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
1316 p_phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_lenovo(p_dm, is_cck_rate, PWDB_ALL, i, RSSI);
1317 }
1318 }
1319 #endif
1320 }
1321
1322 /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/
1323
1324 /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/
1325 if ((p_dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!p_dm->is_mp_chip))
1326 rx_pwr_all = (p_phy_sta_rpt->pwdb_all & 0x7f) - 110;
1327 else
1328 rx_pwr_all = (((p_phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/
1329
1330 PWDB_ALL_BT = PWDB_ALL = phydm_query_rx_pwr_percentage(rx_pwr_all);
1331
1332 p_phy_info->rx_pwdb_all = PWDB_ALL;
1333 /*PHYDM_DBG(p_dm,DBG_RSSI_MNTR, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all));*/
1334 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1335 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT;
1336 p_phy_info->rx_power = rx_pwr_all;
1337 p_phy_info->recv_signal_power = rx_pwr_all;
1338 #endif
1339
1340 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1341 if (p_dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
1342 /*do nothing*/
1343 } else
1344 #endif
1345 {
1346 /*(4)EVM of OFDM rate*/
1347
1348 if ((p_pktinfo->data_rate >= ODM_RATEMCS8) &&
1349 (p_pktinfo->data_rate <= ODM_RATEMCS15))
1350 max_spatial_stream = 2;
1351 else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) &&
1352 (p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9))
1353 max_spatial_stream = 2;
1354 else if ((p_pktinfo->data_rate >= ODM_RATEMCS16) &&
1355 (p_pktinfo->data_rate <= ODM_RATEMCS23))
1356 max_spatial_stream = 3;
1357 else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) &&
1358 (p_pktinfo->data_rate <= ODM_RATEVHTSS3MCS9))
1359 max_spatial_stream = 3;
1360 else
1361 max_spatial_stream = 1;
1362
1363 /*if (p_pktinfo->is_packet_match_bssid) */
1364 {
1365 /*dbg_print("p_pktinfo->data_rate = %d\n", p_pktinfo->data_rate);*/
1366
1367 for (i = 0; i < max_spatial_stream; i++) {
1368 /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/
1369 /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/
1370 /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/
1371
1372 if (p_pktinfo->data_rate >= ODM_RATE6M && p_pktinfo->data_rate <= ODM_RATE54M) {
1373 if (i == RF_PATH_A) {
1374 EVM = phydm_evm_db_to_percentage((p_phy_sta_rpt->sigevm)); /*dbm*/
1375 EVM += 20;
1376 if (EVM > 100)
1377 EVM = 100;
1378 }
1379 } else {
1380 if (i < RF_PATH_C) {
1381 if (p_phy_sta_rpt->rxevm[i] == -128)
1382 p_phy_sta_rpt->rxevm[i] = -25;
1383 EVM = phydm_evm_db_to_percentage((p_phy_sta_rpt->rxevm[i])); /*dbm*/
1384 } else {
1385 if (p_phy_sta_rpt->rxevm_cd[i - 2] == -128)
1386 p_phy_sta_rpt->rxevm_cd[i - 2] = -25;
1387 EVM = phydm_evm_db_to_percentage((p_phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/
1388 }
1389 }
1390
1391 if (i < RF_PATH_C)
1392 evm_dbm = phydm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm[i]);
1393 else
1394 evm_dbm = phydm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm_cd[i - 2]);
1395 /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/
1396 /*p_pktinfo->data_rate, p_phy_sta_rpt->rxevm[i], "%", EVM));*/
1397
1398 {
1399 if (i == RF_PATH_A) {
1400 /*Fill value in RFD, Get the first spatial stream only*/
1401 p_phy_info->signal_quality = EVM;
1402 }
1403 p_phy_info->rx_mimo_signal_quality[i] = EVM;
1404 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
1405 p_phy_info->rx_mimo_evm_dbm[i] = evm_dbm;
1406 #endif
1407 }
1408 }
1409 }
1410 }
1411
1412 num_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
1413 odm_parsing_cfo(p_dm, p_pktinfo, p_phy_sta_rpt->cfotail, num_ss);
1414
1415 }
1416 /* dbg_print("is_cck_rate= %d, p_phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, p_phy_info->signal_strength, PWDB_ALL, rf_rx_num); */
1417
1418 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1419 /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/
1420 /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/
1421 if (is_cck_rate) {
1422 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1423 /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/
1424 p_phy_info->signal_strength = SignalScaleProc(p_dm->adapter, PWDB_ALL, false, true);
1425 #else
1426 p_phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(p_dm, PWDB_ALL));/*PWDB_ALL;*/
1427 #endif
1428 } else {
1429 if (rf_rx_num != 0) {
1430 /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/
1431 if (rf_rx_num == 1)
1432 avg_rssi = best_rssi;
1433 else
1434 avg_rssi = (best_rssi + second_rssi) / 2;
1435 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1436 /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/
1437 p_phy_info->signal_strength = SignalScaleProc(p_dm->adapter, avg_rssi, false, false);
1438 #else
1439 p_phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(p_dm, avg_rssi));
1440 #endif
1441 }
1442 }
1443 #endif
1444 p_dm->rx_pwdb_ave = p_dm->rx_pwdb_ave + p_phy_info->rx_pwdb_all;
1445
1446 p_dm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_anta;
1447 p_dm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_antb;
1448 p_dm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_antc;
1449 p_dm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd;
1450
1451 if (p_pktinfo->is_packet_match_bssid) {
1452 phydm_avg_phystatus_index(p_dm, p_phy_info, p_pktinfo);
1453 phydm_rx_statistic_cal(p_dm, p_phy_status, p_pktinfo);
1454 }
1455 /*PHYDM_DBG(p_dm, DBG_ANT_DIV, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/
1456
1457
1458 /* dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/
1459 /* p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/
1460 /* dbg_print("----------------------------\n");*/
1461 /* dbg_print("p_pktinfo->station_id=%d, p_pktinfo->data_rate=0x%x\n",p_pktinfo->station_id, p_pktinfo->data_rate);*/
1462 /* dbg_print("p_phy_sta_rpt->r_RFMOD = %d\n", p_phy_sta_rpt->r_RFMOD);*/
1463 /* dbg_print("p_phy_sta_rpt->gain_trsw[0]=0x%x, p_phy_sta_rpt->gain_trsw[1]=0x%x\n",*/
1464 /* p_phy_sta_rpt->gain_trsw[0],p_phy_sta_rpt->gain_trsw[1]);*/
1465 /* dbg_print("p_phy_sta_rpt->gain_trsw[2]=0x%x, p_phy_sta_rpt->gain_trsw[3]=0x%x\n",*/
1466 /* p_phy_sta_rpt->gain_trsw_cd[0],p_phy_sta_rpt->gain_trsw_cd[1]);*/
1467 /* dbg_print("p_phy_sta_rpt->pwdb_all = 0x%x, p_phy_info->rx_pwdb_all = %d\n", p_phy_sta_rpt->pwdb_all, p_phy_info->rx_pwdb_all);*/
1468 /* dbg_print("p_phy_sta_rpt->cfotail[i] = 0x%x, p_phy_sta_rpt->CFO_tail[i] = 0x%x\n", p_phy_sta_rpt->cfotail[0], p_phy_sta_rpt->cfotail[1]);*/
1469 /* dbg_print("p_phy_sta_rpt->rxevm[0] = %d, p_phy_sta_rpt->rxevm[1] = %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1]);*/
1470 /* dbg_print("p_phy_sta_rpt->rxevm[2] = %d, p_phy_sta_rpt->rxevm[3] = %d\n", p_phy_sta_rpt->rxevm_cd[0], p_phy_sta_rpt->rxevm_cd[1]);*/
1471 /* dbg_print("p_phy_info->rx_mimo_signal_strength[0]=%d, p_phy_info->rx_mimo_signal_strength[1]=%d, rx_pwdb_all=%d\n",*/
1472 /* p_phy_info->rx_mimo_signal_strength[0], p_phy_info->rx_mimo_signal_strength[1], p_phy_info->rx_pwdb_all);*/
1473 /* dbg_print("p_phy_info->rx_mimo_signal_strength[2]=%d, p_phy_info->rx_mimo_signal_strength[3]=%d\n",*/
1474 /* p_phy_info->rx_mimo_signal_strength[2], p_phy_info->rx_mimo_signal_strength[3]);*/
1475 /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[0]=%d, p_phy_info->rx_mimo_signal_quality[1]=%d\n",*/
1476 /* p_phy_info->rx_mimo_signal_quality[0], p_phy_info->rx_mimo_signal_quality[1]);*/
1477 /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[2]=%d, p_phy_info->rx_mimo_signal_quality[3]=%d\n",*/
1478 /* p_phy_info->rx_mimo_signal_quality[2], p_phy_info->rx_mimo_signal_quality[3]);*/
1479
1480 }
1481
1482 #endif
1483
1484 void
phydm_reset_rssi_for_dm(struct PHY_DM_STRUCT * p_dm,u8 station_id)1485 phydm_reset_rssi_for_dm(
1486 struct PHY_DM_STRUCT *p_dm,
1487 u8 station_id
1488 )
1489 {
1490 struct cmn_sta_info *p_sta;
1491 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1492 struct _ADAPTER *adapter = p_dm->adapter;
1493 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
1494 #endif
1495 p_sta = p_dm->p_phydm_sta_info[station_id];
1496
1497 if (!is_sta_active(p_sta)) {
1498 /**/
1499 return;
1500 }
1501 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("Reset RSSI for macid = (( %d ))\n", station_id));
1502
1503
1504 p_sta->rssi_stat.rssi_cck = -1;
1505 p_sta->rssi_stat.rssi_ofdm = -1;
1506 p_sta->rssi_stat.rssi = -1;
1507 p_sta->rssi_stat.ofdm_pkt_cnt = 0;
1508 p_sta->rssi_stat.cck_pkt_cnt = 0;
1509 p_sta->rssi_stat.cck_sum_power = 0;
1510 p_sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
1511 p_sta->rssi_stat.packet_map = 0;
1512 p_sta->rssi_stat.valid_bit = 0;
1513
1514 /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/
1515 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1516 p_sta->dm_ctrl = p_sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
1517 if (station_id == 0) {
1518
1519 p_hal_data->UndecoratedSmoothedPWDB = -1;
1520 /**/
1521 }
1522 #endif
1523
1524 }
1525
1526 void
phydm_process_rssi_for_dm(struct PHY_DM_STRUCT * p_dm,struct phydm_phyinfo_struct * p_phy_info,struct phydm_perpkt_info_struct * p_pktinfo)1527 phydm_process_rssi_for_dm(
1528 struct PHY_DM_STRUCT *p_dm,
1529 struct phydm_phyinfo_struct *p_phy_info,
1530 struct phydm_perpkt_info_struct *p_pktinfo
1531 )
1532 {
1533
1534 s32 rssi_ave;
1535 s8 undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm;
1536 u8 i, is_cck_rate = 0;
1537 u8 RSSI_max, RSSI_min;
1538 u32 weighting = 0;
1539 u8 send_rssi_2_fw = 0;
1540 struct cmn_sta_info *p_sta;
1541 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1542 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1543 struct _ADAPTER *adapter = p_dm->adapter;
1544 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
1545 #endif
1546
1547 if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
1548 return;
1549
1550 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
1551 odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(p_dm, p_phy_info, p_pktinfo);
1552 #endif
1553
1554 p_sta = p_dm->p_phydm_sta_info[p_pktinfo->station_id];
1555
1556 if (!is_sta_active(p_sta)) {
1557 return;
1558 /**/
1559 }
1560
1561 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1562 if ((p_dm->support_ability & ODM_BB_ANT_DIV) &&
1563 (p_dm_fat_table->enable_ctrl_frame_antdiv)
1564 ) {
1565 if (p_pktinfo->is_packet_match_bssid)
1566 p_dm->data_frame_num++;
1567
1568 if ((p_dm_fat_table->use_ctrl_frame_antdiv)) {
1569 if (!p_pktinfo->is_to_self)/*data frame + CTRL frame*/
1570 return;
1571 } else {
1572 if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/
1573 return;
1574 }
1575 } else
1576 #endif
1577 {
1578 if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/
1579 return;
1580 }
1581
1582 if (p_pktinfo->is_packet_beacon)
1583 p_dm->phy_dbg_info.num_qry_beacon_pkt++;
1584
1585 is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
1586 p_dm->rx_rate = p_pktinfo->data_rate;
1587
1588 /* --------------Statistic for antenna/path diversity------------------ */
1589 if (p_dm->support_ability & ODM_BB_ANT_DIV) {
1590 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
1591 odm_process_rssi_for_ant_div(p_dm, p_phy_info, p_pktinfo);
1592 #endif
1593 }
1594 #if (defined(CONFIG_PATH_DIVERSITY))
1595 else if (p_dm->support_ability & ODM_BB_PATH_DIV)
1596 phydm_process_rssi_for_path_div(p_dm, p_phy_info, p_pktinfo);
1597 #endif
1598 /* -----------------Smart Antenna Debug Message------------------ */
1599
1600 undecorated_smoothed_cck = p_sta->rssi_stat.rssi_cck;
1601 undecorated_smoothed_ofdm = p_sta->rssi_stat.rssi_ofdm;
1602 undecorated_smoothed_pwdb = p_sta->rssi_stat.rssi;
1603
1604 if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) {
1605
1606 if (!is_cck_rate) { /* ofdm rate */
1607 #if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)
1608 if (p_dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) {
1609 u8 RX_count = 0;
1610 u32 RSSI_linear = 0;
1611
1612 if (p_dm->rx_ant_status & BB_PATH_A) {
1613 p_dm->RSSI_A = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
1614 RX_count++;
1615 RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[RF_PATH_A]);
1616 } else
1617 p_dm->RSSI_A = 0;
1618
1619 if (p_dm->rx_ant_status & BB_PATH_B) {
1620 p_dm->RSSI_B = p_phy_info->rx_mimo_signal_strength[RF_PATH_B];
1621 RX_count++;
1622 RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[RF_PATH_B]);
1623 } else
1624 p_dm->RSSI_B = 0;
1625
1626 if (p_dm->rx_ant_status & BB_PATH_C) {
1627 p_dm->RSSI_C = p_phy_info->rx_mimo_signal_strength[RF_PATH_C];
1628 RX_count++;
1629 RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[RF_PATH_C]);
1630 } else
1631 p_dm->RSSI_C = 0;
1632
1633 if (p_dm->rx_ant_status & BB_PATH_D) {
1634 p_dm->RSSI_D = p_phy_info->rx_mimo_signal_strength[RF_PATH_D];
1635 RX_count++;
1636 RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[RF_PATH_D]);
1637 } else
1638 p_dm->RSSI_D = 0;
1639
1640 /* Calculate average RSSI */
1641 switch (RX_count) {
1642 case 2:
1643 RSSI_linear = (RSSI_linear >> 1);
1644 break;
1645 case 3:
1646 RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */
1647 break;
1648 case 4:
1649 RSSI_linear = (RSSI_linear >> 2);
1650 break;
1651 }
1652 rssi_ave = odm_convert_to_db(RSSI_linear);
1653 } else
1654 #endif
1655 {
1656 if (p_phy_info->rx_mimo_signal_strength[RF_PATH_B] == 0) {
1657 rssi_ave = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
1658 p_dm->RSSI_A = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
1659 p_dm->RSSI_B = 0;
1660 } else {
1661 /*dbg_print("p_rfd->status.rx_mimo_signal_strength[0] = %d, p_rfd->status.rx_mimo_signal_strength[1] = %d\n",*/
1662 /*p_rfd->status.rx_mimo_signal_strength[0], p_rfd->status.rx_mimo_signal_strength[1]);*/
1663 p_dm->RSSI_A = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
1664 p_dm->RSSI_B = p_phy_info->rx_mimo_signal_strength[RF_PATH_B];
1665
1666 if (p_phy_info->rx_mimo_signal_strength[RF_PATH_A] > p_phy_info->rx_mimo_signal_strength[RF_PATH_B]) {
1667 RSSI_max = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
1668 RSSI_min = p_phy_info->rx_mimo_signal_strength[RF_PATH_B];
1669 } else {
1670 RSSI_max = p_phy_info->rx_mimo_signal_strength[RF_PATH_B];
1671 RSSI_min = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
1672 }
1673 if ((RSSI_max - RSSI_min) < 3)
1674 rssi_ave = RSSI_max;
1675 else if ((RSSI_max - RSSI_min) < 6)
1676 rssi_ave = RSSI_max - 1;
1677 else if ((RSSI_max - RSSI_min) < 10)
1678 rssi_ave = RSSI_max - 2;
1679 else
1680 rssi_ave = RSSI_max - 3;
1681 }
1682 }
1683
1684 /* 1 Process OFDM RSSI */
1685 if (undecorated_smoothed_ofdm <= 0) { /* initialize */
1686 undecorated_smoothed_ofdm = (s8)p_phy_info->rx_pwdb_all;
1687 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm));
1688 } else {
1689 if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) {
1690 undecorated_smoothed_ofdm =
1691 (s8)((((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) +
1692 (rssi_ave)) / (RX_SMOOTH_FACTOR));
1693 undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1;
1694 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm));
1695 } else {
1696 undecorated_smoothed_ofdm =
1697 (s8)((((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) +
1698 (rssi_ave)) / (RX_SMOOTH_FACTOR));
1699 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm));
1700 }
1701 }
1702 if (p_sta->rssi_stat.ofdm_pkt_cnt != 64) {
1703 i = 63;
1704 p_sta->rssi_stat.ofdm_pkt_cnt -= (u8)(((p_sta->rssi_stat.packet_map >> i) & BIT(0)) - 1);
1705 }
1706 p_sta->rssi_stat.packet_map = (p_sta->rssi_stat.packet_map << 1) | BIT(0);
1707
1708 } else {
1709 rssi_ave = p_phy_info->rx_pwdb_all;
1710 p_dm->RSSI_A = (u8) p_phy_info->rx_pwdb_all;
1711 p_dm->RSSI_B = 0xFF;
1712 p_dm->RSSI_C = 0xFF;
1713 p_dm->RSSI_D = 0xFF;
1714
1715 if (p_sta->rssi_stat.cck_pkt_cnt <= 63)
1716 p_sta->rssi_stat.cck_pkt_cnt++;
1717
1718 /* 1 Process CCK RSSI */
1719 if (undecorated_smoothed_cck <= 0) { /* initialize */
1720 undecorated_smoothed_cck = (s8)p_phy_info->rx_pwdb_all;
1721 p_sta->rssi_stat.cck_sum_power = (u16)p_phy_info->rx_pwdb_all ; /*reset*/
1722 p_sta->rssi_stat.cck_pkt_cnt = 1; /*reset*/
1723 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("CCK_INIT: (( %d ))\n", undecorated_smoothed_cck));
1724 } else if (p_sta->rssi_stat.cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {
1725
1726 p_sta->rssi_stat.cck_sum_power = p_sta->rssi_stat.cck_sum_power + (u16)p_phy_info->rx_pwdb_all;
1727 undecorated_smoothed_cck = p_sta->rssi_stat.cck_sum_power / p_sta->rssi_stat.cck_pkt_cnt;
1728
1729 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n",
1730 undecorated_smoothed_cck, p_sta->rssi_stat.cck_sum_power, p_sta->rssi_stat.cck_pkt_cnt));
1731 } else {
1732 if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) {
1733 undecorated_smoothed_cck =
1734 (s8)((((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) +
1735 (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR));
1736 undecorated_smoothed_cck = undecorated_smoothed_cck + 1;
1737 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("CCK_1: (( %d ))\n", undecorated_smoothed_cck));
1738 } else {
1739 undecorated_smoothed_cck =
1740 (s8)((((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) +
1741 (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR));
1742 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("CCK_2: (( %d ))\n", undecorated_smoothed_cck));
1743 }
1744 }
1745 i = 63;
1746 p_sta->rssi_stat.ofdm_pkt_cnt -= (u8)((p_sta->rssi_stat.packet_map >> i) & BIT(0));
1747 p_sta->rssi_stat.packet_map = p_sta->rssi_stat.packet_map << 1;
1748 }
1749
1750 /* if(p_entry) */
1751 {
1752 /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
1753 if (p_sta->rssi_stat.ofdm_pkt_cnt == 64) { /* speed up when all packets are OFDM*/
1754 undecorated_smoothed_pwdb = undecorated_smoothed_ofdm;
1755 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("PWDB_0[%d] = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck));
1756 } else {
1757 if (p_sta->rssi_stat.valid_bit < 64)
1758 p_sta->rssi_stat.valid_bit++;
1759
1760 if (p_sta->rssi_stat.valid_bit == 64) {
1761 weighting = ((p_sta->rssi_stat.ofdm_pkt_cnt) > 4) ? 64 : (p_sta->rssi_stat.ofdm_pkt_cnt << 4);
1762 undecorated_smoothed_pwdb = (s8)((weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6);
1763 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, weighting));
1764 } else {
1765 if (p_sta->rssi_stat.valid_bit != 0)
1766 undecorated_smoothed_pwdb =
1767 (p_sta->rssi_stat.ofdm_pkt_cnt * undecorated_smoothed_ofdm + (p_sta->rssi_stat.valid_bit - p_sta->rssi_stat.ofdm_pkt_cnt) * undecorated_smoothed_cck) / p_sta->rssi_stat.valid_bit;
1768 else
1769 undecorated_smoothed_pwdb = 0;
1770
1771 PHYDM_DBG(p_dm, DBG_RSSI_MNTR, ("PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n",
1772 p_pktinfo->station_id, undecorated_smoothed_cck, p_sta->rssi_stat.ofdm_pkt_cnt, p_sta->rssi_stat.valid_bit));
1773 }
1774 }
1775
1776
1777 if ((p_sta->rssi_stat.ofdm_pkt_cnt >= 1 || p_sta->rssi_stat.cck_pkt_cnt >= 5) && (p_sta->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) {
1778
1779 send_rssi_2_fw = 1;
1780 p_sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND;
1781 }
1782
1783 p_sta->rssi_stat.rssi_cck = undecorated_smoothed_cck;
1784 p_sta->rssi_stat.rssi_ofdm = undecorated_smoothed_ofdm;
1785 p_sta->rssi_stat.rssi = undecorated_smoothed_pwdb;
1786
1787
1788
1789 if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
1790
1791 if (p_sta->rssi_stat.ofdm_pkt_cnt != 0)
1792 p_sta->rssi_stat.rssi = undecorated_smoothed_ofdm;
1793
1794 PHYDM_DBG(p_dm, DBG_RSSI_MNTR,
1795 ("[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n",
1796 undecorated_smoothed_pwdb, p_sta->rssi_stat.ofdm_pkt_cnt, p_sta->rssi_stat.cck_pkt_cnt));
1797
1798 }
1799
1800
1801 /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/
1802 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1803
1804 if (p_pktinfo->station_id == 0) {
1805 /**/
1806 p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb;
1807 }
1808 #endif
1809
1810 /* dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting); */
1811 /* dbg_print("undecorated_smoothed_ofdm=%d, undecorated_smoothed_pwdb=%d, undecorated_smoothed_cck=%d\n", */
1812 /* undecorated_smoothed_ofdm, undecorated_smoothed_pwdb, undecorated_smoothed_cck); */
1813
1814 }
1815
1816 }
1817 }
1818
1819 /*
1820 * Endianness before calling this API
1821 * */
1822
1823 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
1824 /* For 8822B only!! need to move to FW finally */
1825 /*==============================================*/
1826
1827 boolean
phydm_query_is_mu_api(struct PHY_DM_STRUCT * p_phydm,u8 ppdu_idx,u8 * p_data_rate,u8 * p_gid)1828 phydm_query_is_mu_api(
1829 struct PHY_DM_STRUCT *p_phydm,
1830 u8 ppdu_idx,
1831 u8 *p_data_rate,
1832 u8 *p_gid
1833 )
1834 {
1835 u8 data_rate = 0, gid = 0;
1836 boolean is_mu = false;
1837
1838 data_rate = p_phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
1839 gid = p_phydm->phy_dbg_info.gid_num[ppdu_idx];
1840
1841 if (data_rate & BIT(7)) {
1842 is_mu = true;
1843 data_rate = data_rate & ~(BIT(7));
1844 } else
1845 is_mu = false;
1846
1847 *p_data_rate = data_rate;
1848 *p_gid = gid;
1849
1850 return is_mu;
1851
1852 }
1853
1854 void
phydm_reset_phy_info(struct PHY_DM_STRUCT * p_phydm,struct phydm_phyinfo_struct * p_phy_info)1855 phydm_reset_phy_info(
1856 struct PHY_DM_STRUCT *p_phydm,
1857 struct phydm_phyinfo_struct *p_phy_info
1858 )
1859 {
1860 p_phy_info->rx_pwdb_all = 0;
1861 p_phy_info->signal_quality = 0;
1862 p_phy_info->band_width = 0;
1863 p_phy_info->rx_count = 0;
1864 odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_quality, 0, 4);
1865 odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_strength, 0, 4);
1866 odm_memory_set(p_phydm, p_phy_info->rx_snr, 0, 4);
1867
1868 p_phy_info->rx_power = -110;
1869 p_phy_info->recv_signal_power = -110;
1870 p_phy_info->bt_rx_rssi_percentage = 0;
1871 p_phy_info->signal_strength = 0;
1872 p_phy_info->channel = 0;
1873 p_phy_info->is_mu_packet = 0;
1874 p_phy_info->is_beamformed = 0;
1875 p_phy_info->rxsc = 0;
1876 odm_memory_set(p_phydm, p_phy_info->rx_pwr, -110, 4);
1877 /*odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4);*/
1878 odm_memory_set(p_phydm, p_phy_info->cfo_short, 0, 8);
1879 odm_memory_set(p_phydm, p_phy_info->cfo_tail, 0, 8);
1880
1881 odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4);
1882 }
1883
1884 void
phydm_set_per_path_phy_info(u8 rx_path,s8 rx_pwr,s8 rx_evm,s8 cfo_tail,s8 rx_snr,struct phydm_phyinfo_struct * p_phy_info)1885 phydm_set_per_path_phy_info(
1886 u8 rx_path,
1887 s8 rx_pwr,
1888 s8 rx_evm,
1889 s8 cfo_tail,
1890 s8 rx_snr,
1891 struct phydm_phyinfo_struct *p_phy_info
1892 )
1893 {
1894 u8 evm_dbm = 0;
1895 u8 evm_percentage = 0;
1896
1897 /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
1898
1899 if (rx_evm < 0) {
1900 /* Calculate EVM in dBm */
1901 evm_dbm = ((u8)(0 - rx_evm) >> 1);
1902
1903 /* Calculate EVM in percentage */
1904 if (evm_dbm >= 34)
1905 evm_percentage = 100;
1906 else
1907 evm_percentage = (evm_dbm << 1) + (evm_dbm);
1908 }
1909
1910 p_phy_info->rx_pwr[rx_path] = rx_pwr;
1911
1912 /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/
1913 p_phy_info->cfo_tail[rx_path] = cfo_tail;
1914 p_phy_info->cfo_tail[rx_path] = ((p_phy_info->cfo_tail[rx_path] << 5) + (p_phy_info->cfo_tail[rx_path] << 2) +
1915 (p_phy_info->cfo_tail[rx_path] << 1) + (p_phy_info->cfo_tail[rx_path])) >> 9;
1916
1917 if (evm_dbm == 64)
1918 evm_dbm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/
1919
1920 p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
1921
1922 p_phy_info->rx_mimo_signal_strength[rx_path] = phydm_query_rx_pwr_percentage(rx_pwr);
1923 p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
1924 p_phy_info->rx_snr[rx_path] = rx_snr >> 1;
1925
1926 #if 0
1927 /* if (p_pktinfo->is_packet_match_bssid) */
1928 {
1929 dbg_print("path (%d)--------\n", rx_path);
1930 dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]);
1931 dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]);
1932 dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]);
1933 }
1934 #endif
1935 }
1936
1937 void
phydm_set_common_phy_info(s8 rx_power,u8 channel,boolean is_beamformed,boolean is_mu_packet,u8 bandwidth,u8 signal_quality,u8 rxsc,struct phydm_phyinfo_struct * p_phy_info)1938 phydm_set_common_phy_info(
1939 s8 rx_power,
1940 u8 channel,
1941 boolean is_beamformed,
1942 boolean is_mu_packet,
1943 u8 bandwidth,
1944 u8 signal_quality,
1945 u8 rxsc,
1946 struct phydm_phyinfo_struct *p_phy_info
1947 )
1948 {
1949 p_phy_info->rx_power = rx_power; /* RSSI in dB */
1950 p_phy_info->recv_signal_power = rx_power; /* RSSI in dB */
1951 p_phy_info->channel = channel; /* channel number */
1952 p_phy_info->is_beamformed = is_beamformed; /* apply BF */
1953 p_phy_info->is_mu_packet = is_mu_packet; /* MU packet */
1954 p_phy_info->rxsc = rxsc;
1955
1956 p_phy_info->rx_pwdb_all = phydm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */
1957 p_phy_info->signal_quality = signal_quality; /* signal quality */
1958 p_phy_info->band_width = bandwidth; /* bandwidth */
1959
1960 #if 0
1961 /* if (p_pktinfo->is_packet_match_bssid) */
1962 {
1963 dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power);
1964 dbg_print("signal_quality = %d\n", p_phy_info->signal_quality);
1965 dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1);
1966 dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth);
1967 }
1968 #endif
1969 }
1970
1971 void
phydm_get_rx_phy_status_type0(struct PHY_DM_STRUCT * p_dm,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo,struct phydm_phyinfo_struct * p_phy_info)1972 phydm_get_rx_phy_status_type0(
1973 struct PHY_DM_STRUCT *p_dm,
1974 u8 *p_phy_status,
1975 struct phydm_perpkt_info_struct *p_pktinfo,
1976 struct phydm_phyinfo_struct *p_phy_info
1977 )
1978 {
1979 /* type 0 is used for cck packet */
1980 struct _phy_status_rpt_jaguar2_type0 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type0 *)p_phy_status;
1981 u8 SQ = 0;
1982 s8 rx_power = p_phy_sta_rpt->pwdb - 110;
1983
1984
1985 if (p_dm->support_ic_type & ODM_RTL8723D) {
1986 #if (RTL8723D_SUPPORT == 1)
1987 rx_power = p_phy_sta_rpt->pwdb - 97;
1988 #endif
1989 }
1990 /*#if (RTL8710B_SUPPORT == 1)*/
1991 /*if (p_dm->support_ic_type & ODM_RTL8710B)*/
1992 /*rx_power = p_phy_sta_rpt->pwdb - 97;*/
1993 /*#endif*/
1994
1995 #if (RTL8821C_SUPPORT == 1)
1996 else if (p_dm->support_ic_type & ODM_RTL8821C) {
1997 if (p_phy_sta_rpt->pwdb >= -57)
1998 rx_power = p_phy_sta_rpt->pwdb - 100;
1999 else
2000 rx_power = p_phy_sta_rpt->pwdb - 102;
2001 }
2002 #endif
2003
2004 if (p_pktinfo->is_to_self) {
2005 p_dm->ofdm_agc_idx[0] = p_phy_sta_rpt->pwdb;
2006 p_dm->ofdm_agc_idx[1] = 0;
2007 p_dm->ofdm_agc_idx[2] = 0;
2008 p_dm->ofdm_agc_idx[3] = 0;
2009 }
2010
2011
2012 /* Calculate Signal Quality*/
2013 if (p_pktinfo->is_packet_match_bssid) {
2014 if (p_phy_sta_rpt->signal_quality >= 64)
2015 SQ = 0;
2016 else if (p_phy_sta_rpt->signal_quality <= 20)
2017 SQ = 100;
2018 else {
2019 /* mapping to 2~99% */
2020 SQ = 64 - p_phy_sta_rpt->signal_quality;
2021 SQ = ((SQ << 3) + SQ) >> 2;
2022 }
2023 }
2024
2025 /* Modify CCK PWDB if old AGC */
2026 if (p_dm->cck_new_agc == false) {
2027
2028 #if (RTL8197F_SUPPORT == 1)
2029 if (p_dm->support_ic_type & ODM_RTL8197F)
2030 rx_power = phydm_cck_rssi_convert(p_dm, p_phy_sta_rpt->lna_l, p_phy_sta_rpt->vga);
2031 else
2032 #endif
2033 {
2034 u8 lna_idx, vga_idx;
2035
2036 lna_idx = ((p_phy_sta_rpt->lna_h << 3) | p_phy_sta_rpt->lna_l);
2037 vga_idx = p_phy_sta_rpt->vga;
2038
2039 #if (RTL8723D_SUPPORT == 1)
2040 if (p_dm->support_ic_type & ODM_RTL8723D)
2041 rx_power = odm_cckrssi_8723d(lna_idx, vga_idx);
2042 #endif
2043
2044 #if (RTL8710B_SUPPORT == 1)
2045 if (p_dm->support_ic_type & ODM_RTL8710B)
2046 rx_power = odm_cckrssi_8710b(lna_idx, vga_idx);
2047 #endif
2048
2049 #if (RTL8822B_SUPPORT == 1)
2050 /* Need to do !! */
2051 /*if (p_dm->support_ic_type & ODM_RTL8822B) */
2052 /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/
2053 #endif
2054 }
2055
2056 }
2057
2058 /* Confirm CCK RSSI */
2059 #if (RTL8197F_SUPPORT == 1)
2060 if (p_dm->support_ic_type & ODM_RTL8197F) {
2061 u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */
2062 u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */
2063
2064 if ((p_phy_sta_rpt->bb_power < bb_pwr_th_l) || (p_phy_sta_rpt->bb_power > bb_pwr_th_h))
2065 rx_power = 0; /* Error RSSI for CCK ; set 100*/
2066 }
2067 #endif
2068
2069 /* Update CCK packet counter */
2070 p_dm->phy_dbg_info.num_qry_phy_status_cck++;
2071
2072 /*CCK no STBC and LDPC*/
2073 p_dm->phy_dbg_info.is_ldpc_pkt = false;
2074 p_dm->phy_dbg_info.is_stbc_pkt = false;
2075
2076 /* Update Common information */
2077 phydm_set_common_phy_info(rx_power, p_phy_sta_rpt->channel, false,
2078 false, CHANNEL_WIDTH_20, SQ, p_phy_sta_rpt->rxsc, p_phy_info);
2079
2080 /* Update CCK pwdb */
2081 phydm_set_per_path_phy_info(RF_PATH_A, rx_power, 0, 0, 0, p_phy_info); /* Update per-path information */
2082
2083 p_dm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a;
2084 p_dm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b;
2085 p_dm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c;
2086 p_dm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d;
2087 #if 0
2088 /* if (p_pktinfo->is_packet_match_bssid) */
2089 {
2090 dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw);
2091 dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc);
2092 dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power);
2093 dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality);
2094 dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d);
2095 dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2);
2096 dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5);
2097 dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8);
2098 }
2099 #endif
2100 }
2101
2102 void
phydm_get_rx_phy_status_type1(struct PHY_DM_STRUCT * p_dm,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo,struct phydm_phyinfo_struct * p_phy_info)2103 phydm_get_rx_phy_status_type1(
2104 struct PHY_DM_STRUCT *p_dm,
2105 u8 *p_phy_status,
2106 struct phydm_perpkt_info_struct *p_pktinfo,
2107 struct phydm_phyinfo_struct *p_phy_info
2108 )
2109 {
2110 /* type 1 is used for ofdm packet */
2111
2112 struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status;
2113 s8 rx_pwr_db = -120;
2114 u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
2115 boolean is_mu;
2116 u8 num_ss;
2117
2118 /* Update OFDM packet counter */
2119 p_dm->phy_dbg_info.num_qry_phy_status_ofdm++;
2120
2121 /* Update per-path information */
2122 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
2123 if (p_dm->rx_ant_status & BIT(i)) {
2124 s8 rx_path_pwr_db;
2125
2126 /* RX path counter */
2127 rx_count++;
2128
2129 /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */
2130 /* EVM report is reported by stream, not path */
2131 rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */
2132
2133 if (p_pktinfo->is_to_self)
2134 p_dm->ofdm_agc_idx[i] = p_phy_sta_rpt->pwdb[i];
2135
2136 phydm_set_per_path_phy_info(i, rx_path_pwr_db, p_phy_sta_rpt->rxevm[rx_count - 1],
2137 p_phy_sta_rpt->cfo_tail[i], p_phy_sta_rpt->rxsnr[i], p_phy_info);
2138
2139 /* search maximum pwdb */
2140 if (rx_path_pwr_db > rx_pwr_db)
2141 rx_pwr_db = rx_path_pwr_db;
2142 }
2143 }
2144
2145 /* mapping RX counter from 1~4 to 0~3 */
2146 if (rx_count > 0)
2147 p_phy_info->rx_count = rx_count - 1;
2148
2149 /* Check if MU packet or not */
2150 if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) {
2151 is_mu = true;
2152 p_dm->phy_dbg_info.num_qry_mu_pkt++;
2153 } else
2154 is_mu = false;
2155
2156 /* count BF packet */
2157 p_dm->phy_dbg_info.num_qry_bf_pkt = p_dm->phy_dbg_info.num_qry_bf_pkt + p_phy_sta_rpt->beamformed;
2158
2159 /*STBC or LDPC pkt*/
2160 p_dm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc;
2161 p_dm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc;
2162
2163 /* Check sub-channel */
2164 if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0))
2165 rxsc = p_phy_sta_rpt->l_rxsc;
2166 else
2167 rxsc = p_phy_sta_rpt->ht_rxsc;
2168
2169 /* Check RX bandwidth */
2170 if (p_dm->support_ic_type & ODM_RTL8822B) {
2171 if ((rxsc >= 1) && (rxsc <= 8))
2172 bw = CHANNEL_WIDTH_20;
2173 else if ((rxsc >= 9) && (rxsc <= 12))
2174 bw = CHANNEL_WIDTH_40;
2175 else if (rxsc >= 13)
2176 bw = CHANNEL_WIDTH_80;
2177 else
2178 bw = p_phy_sta_rpt->rf_mode;
2179 } else if (p_dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {
2180 if (p_phy_sta_rpt->rf_mode == 0)
2181 bw = CHANNEL_WIDTH_20;
2182 else if ((rxsc == 1) || (rxsc == 2))
2183 bw = CHANNEL_WIDTH_20;
2184 else
2185 bw = CHANNEL_WIDTH_40;
2186 }
2187
2188 /* Update packet information */
2189 phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed,
2190 is_mu, bw, p_phy_info->rx_mimo_signal_quality[0], rxsc, p_phy_info);
2191
2192 num_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
2193
2194 odm_parsing_cfo(p_dm, p_pktinfo, p_phy_sta_rpt->cfo_tail, num_ss);
2195 p_dm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a;
2196 p_dm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b;
2197 p_dm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c;
2198 p_dm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d;
2199
2200 #if 0
2201 if (p_pktinfo->is_packet_match_bssid) {
2202
2203 dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc, p_phy_sta_rpt->rf_mode);
2204 dbg_print("Antidx A = %d, B = %d, C = %d, D = %d\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d);
2205 dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]);
2206 dbg_print("EVM A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1], p_phy_sta_rpt->rxevm[2], p_phy_sta_rpt->rxevm[3]);
2207 dbg_print("SNR A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxsnr[0], p_phy_sta_rpt->rxsnr[1], p_phy_sta_rpt->rxsnr[2], p_phy_sta_rpt->rxsnr[3]);
2208 dbg_print("CFO A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->cfo_tail[0], p_phy_sta_rpt->cfo_tail[1], p_phy_sta_rpt->cfo_tail[2], p_phy_sta_rpt->cfo_tail[3]);
2209 dbg_print("paid = %d, gid = %d, length = %d\n", (p_phy_sta_rpt->paid + (p_phy_sta_rpt->paid_msb<<8)), p_phy_sta_rpt->gid, p_phy_sta_rpt->lsig_length);
2210 dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu);
2211 dbg_print("NBI: %d, pos: %d\n", p_phy_sta_rpt->nb_intf_flag, (p_phy_sta_rpt->intf_pos + (p_phy_sta_rpt->intf_pos_msb<<8)));
2212 dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5);
2213
2214 }
2215
2216 dbg_print("phydm_get_rx_phy_status_type1 p_pktinfo->is_packet_match_bssid = %d\n", p_pktinfo->is_packet_match_bssid);
2217 dbg_print("p_pktinfo->data_rate = 0x%x\n", p_pktinfo->data_rate);
2218 #endif
2219 }
2220
2221 void
phydm_get_rx_phy_status_type2(struct PHY_DM_STRUCT * p_dm,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo,struct phydm_phyinfo_struct * p_phy_info)2222 phydm_get_rx_phy_status_type2(
2223 struct PHY_DM_STRUCT *p_dm,
2224 u8 *p_phy_status,
2225 struct phydm_perpkt_info_struct *p_pktinfo,
2226 struct phydm_phyinfo_struct *p_phy_info
2227 )
2228 {
2229 struct _phy_status_rpt_jaguar2_type2 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type2 *)p_phy_status;
2230 s8 rx_pwr_db = -120;
2231 u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
2232
2233 /* Update OFDM packet counter */
2234 p_dm->phy_dbg_info.num_qry_phy_status_ofdm++;
2235
2236 /* Update per-path information */
2237 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
2238 if (p_dm->rx_ant_status & BIT(i)) {
2239 s8 rx_path_pwr_db;
2240
2241 /* RX path counter */
2242 rx_count++;
2243
2244 /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */
2245 #if (RTL8197F_SUPPORT == 1)
2246 if ((p_dm->support_ic_type & ODM_RTL8197F) && (p_phy_sta_rpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/
2247
2248 if (i == RF_PATH_A) {
2249 rx_path_pwr_db = (p_phy_sta_rpt->gain_a) << 1;
2250 rx_path_pwr_db = rx_path_pwr_db - 110;
2251 } else if (i == RF_PATH_B) {
2252 rx_path_pwr_db = (p_phy_sta_rpt->gain_b) << 1;
2253 rx_path_pwr_db = rx_path_pwr_db - 110;
2254 } else
2255 rx_path_pwr_db = 0;
2256 } else
2257 #endif
2258 rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */
2259
2260 phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, p_phy_info);
2261
2262 /* search maximum pwdb */
2263 if (rx_path_pwr_db > rx_pwr_db)
2264 rx_pwr_db = rx_path_pwr_db;
2265 }
2266 }
2267
2268 /* mapping RX counter from 1~4 to 0~3 */
2269 if (rx_count > 0)
2270 p_phy_info->rx_count = rx_count - 1;
2271
2272 /* Check RX sub-channel */
2273 if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0))
2274 rxsc = p_phy_sta_rpt->l_rxsc;
2275 else
2276 rxsc = p_phy_sta_rpt->ht_rxsc;
2277
2278 /*STBC or LDPC pkt*/
2279 p_dm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc;
2280 p_dm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc;
2281
2282 /* Check RX bandwidth */
2283 /* the BW information of sc=0 is useless, because there is no information of RF mode*/
2284
2285 if (p_dm->support_ic_type & ODM_RTL8822B) {
2286 if ((rxsc >= 1) && (rxsc <= 8))
2287 bw = CHANNEL_WIDTH_20;
2288 else if ((rxsc >= 9) && (rxsc <= 12))
2289 bw = CHANNEL_WIDTH_40;
2290 else if (rxsc >= 13)
2291 bw = CHANNEL_WIDTH_80;
2292 else
2293 bw = CHANNEL_WIDTH_20;
2294 } else if (p_dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */
2295 if (rxsc == 3)
2296 bw = CHANNEL_WIDTH_40;
2297 else if ((rxsc == 1) || (rxsc == 2))
2298 bw = CHANNEL_WIDTH_20;
2299 else
2300 bw = CHANNEL_WIDTH_20;
2301 }
2302
2303 /* Update packet information */
2304 phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed,
2305 false, bw, 0, rxsc, p_phy_info);
2306
2307 #if 0
2308 /* if (p_pktinfo->is_packet_match_bssid) */
2309 {
2310 dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc);
2311 dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]);
2312 dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d);
2313 dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d);
2314 dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d);
2315 dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d);
2316 dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]);
2317 dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]);
2318 dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu);
2319 dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count);
2320 dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map);
2321 dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4);
2322 dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7);
2323 }
2324 #endif
2325 }
2326
2327 void
phydm_get_rx_phy_status_type5(u8 * p_phy_status)2328 phydm_get_rx_phy_status_type5(
2329 u8 *p_phy_status
2330 )
2331 {
2332 /*
2333 dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0));
2334 dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4));
2335 dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8));
2336 dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12));
2337 dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16));
2338 dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20));
2339 dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24));
2340 */
2341 }
2342
2343 void
phydm_process_rssi_for_dm_new_type(struct PHY_DM_STRUCT * p_dm,struct phydm_phyinfo_struct * p_phy_info,struct phydm_perpkt_info_struct * p_pktinfo)2344 phydm_process_rssi_for_dm_new_type(
2345 struct PHY_DM_STRUCT *p_dm,
2346 struct phydm_phyinfo_struct *p_phy_info,
2347 struct phydm_perpkt_info_struct *p_pktinfo
2348 )
2349 {
2350 s32 undecorated_smoothed_pwdb, accumulate_pwdb;
2351 u32 rssi_ave, rssi_linear = 0;
2352 u8 i;
2353 struct cmn_sta_info *p_sta;
2354 u8 scaling_factor = 4;
2355 u8 is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
2356
2357 if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
2358 return;
2359
2360 p_sta = p_dm->p_phydm_sta_info[p_pktinfo->station_id];
2361
2362 if (!is_sta_active(p_sta))
2363 return;
2364
2365 if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/
2366 return;
2367
2368 if (p_pktinfo->is_packet_beacon)
2369 p_dm->phy_dbg_info.num_qry_beacon_pkt++;
2370
2371 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2372 if (p_dm->support_ability & ODM_BB_ANT_DIV)
2373 odm_process_rssi_for_ant_div(p_dm, p_phy_info, p_pktinfo);
2374 #endif
2375
2376 #ifdef CONFIG_DYNAMIC_RX_PATH
2377 phydm_process_phy_status_for_dynamic_rx_path(p_dm, p_phy_info, p_pktinfo);
2378 #endif
2379
2380 if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) {
2381
2382 p_dm->rx_rate = p_pktinfo->data_rate;
2383 undecorated_smoothed_pwdb = p_sta->rssi_stat.rssi;
2384 accumulate_pwdb = p_dm->accumulate_pwdb[p_pktinfo->station_id];
2385 p_dm->RSSI_A = p_phy_info->rx_mimo_signal_strength[RF_PATH_A];
2386 p_dm->RSSI_B = p_phy_info->rx_mimo_signal_strength[RF_PATH_B];
2387 p_dm->RSSI_C = p_phy_info->rx_mimo_signal_strength[RF_PATH_C];
2388 p_dm->RSSI_D = p_phy_info->rx_mimo_signal_strength[RF_PATH_D];
2389
2390 for (i = RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
2391 if (p_phy_info->rx_mimo_signal_strength[i] != 0)
2392 rssi_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[i]);
2393 }
2394
2395 switch (p_phy_info->rx_count + 1) {
2396 case 2:
2397 rssi_linear = (rssi_linear >> 1);
2398 break;
2399 case 3:
2400 rssi_linear = ((rssi_linear) + (rssi_linear << 1) + (rssi_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */
2401 break;
2402 case 4:
2403 rssi_linear = (rssi_linear >> 2);
2404 break;
2405 }
2406 rssi_ave = odm_convert_to_db(rssi_linear);
2407
2408 if (undecorated_smoothed_pwdb <= 0) {
2409 accumulate_pwdb = (p_phy_info->rx_pwdb_all << scaling_factor);
2410 undecorated_smoothed_pwdb = p_phy_info->rx_pwdb_all;
2411 } else {
2412 accumulate_pwdb = accumulate_pwdb - (accumulate_pwdb >> scaling_factor) + rssi_ave;
2413 undecorated_smoothed_pwdb = (accumulate_pwdb + (1 << (scaling_factor - 1))) >> scaling_factor;
2414 }
2415
2416 p_sta->rssi_stat.rssi = (s8)undecorated_smoothed_pwdb;
2417
2418 if (is_cck_rate)
2419 p_sta->rssi_stat.rssi_cck = (s8)rssi_ave;
2420 else
2421 p_sta->rssi_stat.rssi_ofdm = (s8)rssi_ave;
2422
2423
2424 p_dm->accumulate_pwdb[p_pktinfo->station_id] = accumulate_pwdb;
2425
2426 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2427 if (p_pktinfo->station_id == 0) {
2428 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm->adapter);
2429
2430 p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb;
2431 }
2432 #endif
2433 }
2434 }
2435
2436 void
phydm_rx_phy_status_new_type(void * p_dm_void,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo,struct phydm_phyinfo_struct * p_phy_info)2437 phydm_rx_phy_status_new_type(
2438 void *p_dm_void,
2439 u8 *p_phy_status,
2440 struct phydm_perpkt_info_struct *p_pktinfo,
2441 struct phydm_phyinfo_struct *p_phy_info
2442 )
2443 {
2444 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2445 #ifdef PHYDM_PHYSTAUS_SMP_MODE
2446 struct pkt_process_info *p_pkt_process = &(p_dm->pkt_proc_struct);
2447 #endif
2448 u8 phy_status_type = (*p_phy_status & 0xf);
2449
2450 #ifdef PHYDM_PHYSTAUS_SMP_MODE
2451 if (p_pkt_process->phystatus_smp_mode_en && phy_status_type != 0) {
2452
2453 if (p_pkt_process->pre_ppdu_cnt == p_pktinfo->ppdu_cnt)
2454 return;
2455
2456 p_pkt_process->pre_ppdu_cnt = p_pktinfo->ppdu_cnt;
2457 }
2458 #endif
2459
2460 /*dbg_print("phydm_rx_phy_status_new_type================> (page: %d)\n", phy_status_type);*/
2461
2462 /* Memory reset */
2463 phydm_reset_phy_info(p_dm, p_phy_info);
2464 p_dm->rate_ss = phydm_rate_to_num_ss(p_dm, p_pktinfo->data_rate);
2465
2466 /* Phy status parsing */
2467 switch (phy_status_type) {
2468 case 0: /*CCK*/
2469 phydm_get_rx_phy_status_type0(p_dm, p_phy_status, p_pktinfo, p_phy_info);
2470 break;
2471 case 1:
2472 phydm_get_rx_phy_status_type1(p_dm, p_phy_status, p_pktinfo, p_phy_info);
2473 break;
2474 case 2:
2475 phydm_get_rx_phy_status_type2(p_dm, p_phy_status, p_pktinfo, p_phy_info);
2476 break;
2477 #if 0
2478 case 5:
2479 phydm_get_rx_phy_status_type5(p_phy_status);
2480 return;
2481 #endif
2482 default:
2483 return;
2484 }
2485
2486 if (p_pktinfo->is_packet_match_bssid) {
2487 phydm_avg_phystatus_index(p_dm, p_phy_info, p_pktinfo);
2488 phydm_rx_statistic_cal(p_dm, p_phy_status, p_pktinfo);
2489 }
2490
2491 /* Update signal strength to UI, and p_phy_info->rx_pwdb_all is the maximum RSSI of all path */
2492 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2493 p_phy_info->signal_strength = SignalScaleProc(p_dm->adapter, p_phy_info->rx_pwdb_all, false, false);
2494 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2495 p_phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(p_dm, p_phy_info->rx_pwdb_all));
2496 #endif
2497
2498
2499
2500 }
2501 /*==============================================*/
2502 #endif
2503
2504 void
odm_phy_status_query(struct PHY_DM_STRUCT * p_dm,struct phydm_phyinfo_struct * p_phy_info,u8 * p_phy_status,struct phydm_perpkt_info_struct * p_pktinfo)2505 odm_phy_status_query(
2506 struct PHY_DM_STRUCT *p_dm,
2507 struct phydm_phyinfo_struct *p_phy_info,
2508 u8 *p_phy_status,
2509 struct phydm_perpkt_info_struct *p_pktinfo
2510 )
2511 {
2512
2513 if (p_dm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) {
2514 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
2515 phydm_rx_phy_status_new_type(p_dm, p_phy_status, p_pktinfo, p_phy_info);
2516 phydm_process_rssi_for_dm_new_type(p_dm, p_phy_info, p_pktinfo);
2517 #endif
2518 } else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
2519 #if ODM_IC_11AC_SERIES_SUPPORT
2520 phydm_rx_phy_status_jaguar_series_parsing(p_dm, p_phy_info, p_phy_status, p_pktinfo);
2521 phydm_process_rssi_for_dm(p_dm, p_phy_info, p_pktinfo);
2522 #endif
2523 } else if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
2524 #if ODM_IC_11N_SERIES_SUPPORT
2525 phydm_rx_phy_status92c_series_parsing(p_dm, p_phy_info, p_phy_status, p_pktinfo);
2526 phydm_process_rssi_for_dm(p_dm, p_phy_info, p_pktinfo);
2527 #endif
2528 }
2529 }
2530
2531 void
phydm_rx_phy_status_init(void * p_dm_void)2532 phydm_rx_phy_status_init(
2533 void *p_dm_void
2534 )
2535 {
2536 #ifdef PHYDM_PHYSTAUS_SMP_MODE
2537 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2538 struct pkt_process_info *p_pkt_process = &(p_dm->pkt_proc_struct);
2539
2540 if (p_dm->support_ic_type == ODM_RTL8822B) {
2541
2542 p_pkt_process->phystatus_smp_mode_en = 1;
2543 p_pkt_process->pre_ppdu_cnt = 0xff;
2544
2545 odm_set_mac_reg(p_dm, 0x60f, BIT(7), 1); /*phystatus sampling mode enable*/
2546
2547 odm_set_bb_reg(p_dm, 0x9e4, 0x3ff, 0x0); /*First update timming*/
2548 odm_set_bb_reg(p_dm, 0x9e4, 0xfc00, 0x0); /*Update Sampling time*/
2549 }
2550 #endif
2551 }
2552