1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19 #include "mp_precomp.h"
20 #include "phydm_precomp.h"
21
22 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
23 #if WPP_SOFTWARE_TRACE
24 #include "PhyDM_Adaptivity.tmh"
25 #endif
26 #endif
27
28 void
phydm_dig_up_bound_lmt_en(void * p_dm_void)29 phydm_dig_up_bound_lmt_en(
30 void *p_dm_void
31 )
32 {
33 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
34 struct phydm_adaptivity_struct *p_adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
35
36 if (!(p_dm->support_ability & ODM_BB_ADAPTIVITY) ||
37 (p_dm->adaptivity_flag == false) ||
38 (!p_dm->is_linked) ||
39 (p_dm->adaptivity_enable == false)
40 ) {
41 p_adaptivity->igi_up_bound_lmt_cnt = 0;
42 p_adaptivity->igi_lmt_en = false;
43 return;
44 }
45
46 if (p_dm->total_tp > 1) {
47 p_adaptivity->igi_lmt_en = true;
48 p_adaptivity->igi_up_bound_lmt_cnt = p_adaptivity->igi_up_bound_lmt_val;
49 PHYDM_DBG(p_dm, DBG_ADPTVTY,
50 ("TP >1, Start limit IGI upper bound\n"));
51 } else {
52 if (p_adaptivity->igi_up_bound_lmt_cnt == 0)
53 p_adaptivity->igi_lmt_en = false;
54 else
55 p_adaptivity->igi_up_bound_lmt_cnt--;
56 }
57
58 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("IGI_lmt_cnt = %d\n", p_adaptivity->igi_up_bound_lmt_cnt));
59 }
60
61 void
phydm_check_adaptivity(void * p_dm_void)62 phydm_check_adaptivity(
63 void *p_dm_void
64 )
65 {
66 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
67 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
68
69 if (!(p_dm->support_ability & ODM_BB_ADAPTIVITY)) {
70 p_dm->adaptivity_enable = false;
71 return;
72 }
73
74 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
75 if (p_dm->ap_total_num > adaptivity->ap_num_th) {
76 p_dm->adaptivity_enable = false;
77 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th));
78 return;
79 }
80 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
81 if (adaptivity->dynamic_link_adaptivity) {
82 if (p_dm->is_linked && adaptivity->is_check == false) {
83 phydm_check_environment(p_dm);
84 } else if (!p_dm->is_linked)
85 adaptivity->is_check = false;
86
87 return;
88 }
89 #endif
90
91 p_dm->adaptivity_enable = true;
92 }
93
94 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
95 boolean
phydm_check_channel_plan(void * p_dm_void)96 phydm_check_channel_plan(
97 void *p_dm_void
98 )
99 {
100 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
101 struct _ADAPTER *p_adapter = p_dm->adapter;
102 PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo);
103
104 if (p_mgnt_info->RegEnableAdaptivity == 2) {
105 if (p_dm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/
106 if ((*p_dm->p_band_type == ODM_BAND_5G) &&
107 !(p_dm->odm_regulation_5g == REGULATION_ETSI || p_dm->odm_regulation_5g == REGULATION_WW)) {
108 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("adaptivity skip 5G domain code : %d\n", p_dm->odm_regulation_5g));
109 p_dm->adaptivity_enable = false;
110 return true;
111 } else if ((*p_dm->p_band_type == ODM_BAND_2_4G) &&
112 !(p_dm->odm_regulation_2_4g == REGULATION_ETSI || p_dm->odm_regulation_2_4g == REGULATION_WW)) {
113 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("adaptivity skip 2.4G domain code : %d\n", p_dm->odm_regulation_2_4g));
114 p_dm->adaptivity_enable = false;
115 return true;
116
117 } else if ((*p_dm->p_band_type != ODM_BAND_2_4G) && (*p_dm->p_band_type != ODM_BAND_5G)) {
118 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("adaptivity neither 2G nor 5G band, return\n"));
119 p_dm->adaptivity_enable = false;
120 return true;
121 }
122 } else {
123 if ((*p_dm->p_band_type == ODM_BAND_5G) &&
124 !(p_dm->odm_regulation_5g == REGULATION_MKK || p_dm->odm_regulation_5g == REGULATION_WW)) {
125 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("CarrierSense skip 5G domain code : %d\n", p_dm->odm_regulation_5g));
126 p_dm->adaptivity_enable = false;
127 return true;
128 }
129
130 else if ((*p_dm->p_band_type == ODM_BAND_2_4G) &&
131 !(p_dm->odm_regulation_2_4g == REGULATION_MKK || p_dm->odm_regulation_2_4g == REGULATION_WW)) {
132 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("CarrierSense skip 2.4G domain code : %d\n", p_dm->odm_regulation_2_4g));
133 p_dm->adaptivity_enable = false;
134 return true;
135
136 } else if ((*p_dm->p_band_type != ODM_BAND_2_4G) && (*p_dm->p_band_type != ODM_BAND_5G)) {
137 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("CarrierSense neither 2G nor 5G band, return\n"));
138 p_dm->adaptivity_enable = false;
139 return true;
140 }
141 }
142 }
143
144 return false;
145
146 }
147 #endif
148
149 void
phydm_set_edcca_threshold(void * p_dm_void,s8 H2L,s8 L2H)150 phydm_set_edcca_threshold(
151 void *p_dm_void,
152 s8 H2L,
153 s8 L2H
154 )
155 {
156 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
157
158 if (p_dm->support_ic_type & ODM_IC_11N_SERIES)
159 odm_set_bb_reg(p_dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16));
160 #if (RTL8195A_SUPPORT == 0)
161 else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES)
162 odm_set_bb_reg(p_dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8));
163 #endif
164
165 }
166
167 void
phydm_set_lna(void * p_dm_void,enum phydm_set_lna type)168 phydm_set_lna(
169 void *p_dm_void,
170 enum phydm_set_lna type
171 )
172 {
173 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
174
175 if (p_dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
176 if (type == phydm_disable_lna) {
177 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
178 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
179 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f);
180 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/
181 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
182 if (p_dm->rf_type > RF_1T1R) {
183 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x1);
184 odm_set_rf_reg(p_dm, RF_PATH_B, 0x30, 0xfffff, 0x18000);
185 odm_set_rf_reg(p_dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f);
186 odm_set_rf_reg(p_dm, RF_PATH_B, 0x32, 0xfffff, 0x37f82);
187 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x0);
188 }
189 } else if (type == phydm_enable_lna) {
190 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
191 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
192 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f);
193 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/
194 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
195 if (p_dm->rf_type > RF_1T1R) {
196 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x1);
197 odm_set_rf_reg(p_dm, RF_PATH_B, 0x30, 0xfffff, 0x18000);
198 odm_set_rf_reg(p_dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f);
199 odm_set_rf_reg(p_dm, RF_PATH_B, 0x32, 0xfffff, 0x77f82);
200 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x0);
201 }
202 }
203 } else if (p_dm->support_ic_type & ODM_RTL8723B) {
204 if (type == phydm_disable_lna) {
205 /*S0*/
206 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
207 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
208 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x0001f);
209 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/
210 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
211 /*S1*/
212 odm_set_rf_reg(p_dm, RF_PATH_A, 0xed, 0x00020, 0x1);
213 odm_set_rf_reg(p_dm, RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/
214 odm_set_rf_reg(p_dm, RF_PATH_A, 0xed, 0x00020, 0x0);
215 } else if (type == phydm_enable_lna) {
216 /*S0*/
217 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
218 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
219 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x0001f);
220 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/
221 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
222 /*S1*/
223 odm_set_rf_reg(p_dm, RF_PATH_A, 0xed, 0x00020, 0x1);
224 odm_set_rf_reg(p_dm, RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/
225 odm_set_rf_reg(p_dm, RF_PATH_A, 0xed, 0x00020, 0x0);
226 }
227
228 } else if (p_dm->support_ic_type & ODM_RTL8812) {
229 if (type == phydm_disable_lna) {
230 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
231 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
232 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
233 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
234 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
235 if (p_dm->rf_type > RF_1T1R) {
236 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x1);
237 odm_set_rf_reg(p_dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
238 odm_set_rf_reg(p_dm, RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
239 odm_set_rf_reg(p_dm, RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
240 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x0);
241 }
242 } else if (type == phydm_enable_lna) {
243 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
244 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
245 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
246 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
247 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
248 if (p_dm->rf_type > RF_1T1R) {
249 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x1);
250 odm_set_rf_reg(p_dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
251 odm_set_rf_reg(p_dm, RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
252 odm_set_rf_reg(p_dm, RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
253 odm_set_rf_reg(p_dm, RF_PATH_B, 0xef, 0x80000, 0x0);
254 }
255 }
256 } else if (p_dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
257 if (type == phydm_disable_lna) {
258 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
259 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
260 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f);
261 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
262 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
263 } else if (type == phydm_enable_lna) {
264 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x1);
265 odm_set_rf_reg(p_dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
266 odm_set_rf_reg(p_dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f);
267 odm_set_rf_reg(p_dm, RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
268 odm_set_rf_reg(p_dm, RF_PATH_A, 0xef, 0x80000, 0x0);
269 }
270 }
271 }
272
273
274
275 void
phydm_set_trx_mux(void * p_dm_void,enum phydm_trx_mux_type tx_mode,enum phydm_trx_mux_type rx_mode)276 phydm_set_trx_mux(
277 void *p_dm_void,
278 enum phydm_trx_mux_type tx_mode,
279 enum phydm_trx_mux_type rx_mode
280 )
281 {
282 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
283
284 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
285 odm_set_bb_reg(p_dm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
286 odm_set_bb_reg(p_dm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
287 if (p_dm->rf_type > RF_1T1R) {
288 odm_set_bb_reg(p_dm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
289 odm_set_bb_reg(p_dm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
290 }
291 }
292 #if (RTL8195A_SUPPORT == 0)
293 else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
294 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
295 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
296 if (p_dm->rf_type > RF_1T1R) {
297 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
298 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
299 }
300 }
301 #endif
302
303 }
304
305 void
phydm_mac_edcca_state(void * p_dm_void,enum phydm_mac_edcca_type state)306 phydm_mac_edcca_state(
307 void *p_dm_void,
308 enum phydm_mac_edcca_type state
309 )
310 {
311 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
312 if (state == phydm_ignore_edcca) {
313 odm_set_mac_reg(p_dm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/
314 /* odm_set_mac_reg(p_dm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/
315 } else { /*don't set MAC ignore EDCCA signal*/
316 odm_set_mac_reg(p_dm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/
317 /* odm_set_mac_reg(p_dm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */
318 }
319 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("EDCCA enable state = %d\n", state));
320
321 }
322
323 void
phydm_check_environment(void * p_dm_void)324 phydm_check_environment(
325 void *p_dm_void
326 )
327 {
328 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
329 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
330 boolean is_clean_environment = false;
331
332 is_clean_environment = phydm_cal_nhm_cnt(p_dm);
333
334 if (is_clean_environment == true) {
335 p_dm->th_l2h_ini = adaptivity->th_l2h_ini_backup; /*adaptivity mode*/
336 p_dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
337
338 p_dm->adaptivity_enable = true;
339 } else {
340 p_dm->th_l2h_ini = p_dm->th_l2h_ini_mode2; /*mode2*/
341 p_dm->th_edcca_hl_diff = p_dm->th_edcca_hl_diff_mode2;
342
343 p_dm->adaptivity_enable = false;
344 }
345
346 adaptivity->is_check = true;
347
348 }
349
350 void
phydm_search_pwdb_lower_bound(void * p_dm_void)351 phydm_search_pwdb_lower_bound(
352 void *p_dm_void
353 )
354 {
355 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
356 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
357 u32 value32 = 0, reg_value32 = 0;
358 u8 cnt, try_count = 0;
359 u8 tx_edcca1 = 0;
360 boolean is_adjust = true;
361 s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
362 s8 diff;
363 u8 IGI = adaptivity->igi_base + 30 + (u8)p_dm->th_l2h_ini - (u8)p_dm->th_edcca_hl_diff;
364
365 if (p_dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
366 phydm_set_lna(p_dm, phydm_disable_lna);
367
368 diff = igi_target - (s8)IGI;
369 th_l2h_dmc = p_dm->th_l2h_ini + diff;
370 if (th_l2h_dmc > 10)
371 th_l2h_dmc = 10;
372
373 th_h2l_dmc = th_l2h_dmc - p_dm->th_edcca_hl_diff;
374 phydm_set_edcca_threshold(p_dm, th_h2l_dmc, th_l2h_dmc);
375 ODM_delay_ms(30);
376
377 while (is_adjust) {
378
379 /*check CCA status*/
380 if (phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/
381 reg_value32 = phydm_get_bb_dbg_port_value(p_dm);
382
383 while (reg_value32 & BIT(3) && try_count < 3) {
384 ODM_delay_ms(3);
385 try_count = try_count + 1;
386 reg_value32 = phydm_get_bb_dbg_port_value(p_dm);
387 }
388 phydm_release_bb_dbg_port(p_dm);
389 try_count = 0;
390 }
391
392 /*count EDCCA signal = 1 times*/
393 for (cnt = 0; cnt < 20; cnt++) {
394
395 if (phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) {
396 value32 = phydm_get_bb_dbg_port_value(p_dm);
397 phydm_release_bb_dbg_port(p_dm);
398 }
399
400 if (value32 & BIT(30) && (p_dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)))
401 tx_edcca1 = tx_edcca1 + 1;
402 else if (value32 & BIT(29))
403 tx_edcca1 = tx_edcca1 + 1;
404 }
405
406 if (tx_edcca1 > 1) {
407 IGI = IGI - 1;
408 th_l2h_dmc = th_l2h_dmc + 1;
409 if (th_l2h_dmc > 10)
410 th_l2h_dmc = 10;
411
412 th_h2l_dmc = th_l2h_dmc - p_dm->th_edcca_hl_diff;
413 phydm_set_edcca_threshold(p_dm, th_h2l_dmc, th_l2h_dmc);
414 tx_edcca1 = 0;
415 if (th_l2h_dmc == 10)
416 is_adjust = false;
417
418 } else
419 is_adjust = false;
420
421 }
422
423 adaptivity->adapt_igi_up = IGI - p_dm->dc_backoff;
424 adaptivity->h2l_lb = th_h2l_dmc + p_dm->dc_backoff;
425 adaptivity->l2h_lb = th_l2h_dmc + p_dm->dc_backoff;
426
427 if (p_dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
428 phydm_set_lna(p_dm, phydm_enable_lna);
429
430 phydm_set_edcca_threshold(p_dm, 0x7f, 0x7f); /*resume to no link state*/
431 }
432
433 boolean
phydm_re_search_condition(void * p_dm_void)434 phydm_re_search_condition(
435 void *p_dm_void
436 )
437 {
438 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
439 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
440 u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + p_dm->dc_backoff;
441 /*s8 TH_L2H_dmc, IGI_target = 0x32;*/
442 /*s8 diff;*/
443
444 /*TH_L2H_dmc = 10;*/
445
446 /*diff = TH_L2H_dmc - p_dm->TH_L2H_ini;*/
447 /*lowest_IGI_upper = IGI_target - diff;*/
448 /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/
449
450 if (adaptivity_igi_upper <= 0x26)
451 return true;
452 else
453 return false;
454 }
455
456 void
phydm_adaptivity_info_init(void * p_dm_void,enum phydm_adapinfo_e cmn_info,u32 value)457 phydm_adaptivity_info_init(
458 void *p_dm_void,
459 enum phydm_adapinfo_e cmn_info,
460 u32 value
461 )
462 {
463 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
464 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
465
466 switch (cmn_info) {
467 case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
468 p_dm->carrier_sense_enable = (boolean)value;
469 break;
470
471 case PHYDM_ADAPINFO_DCBACKOFF:
472 p_dm->dc_backoff = (u8)value;
473 break;
474
475 case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
476 adaptivity->dynamic_link_adaptivity = (boolean)value;
477 break;
478
479 case PHYDM_ADAPINFO_TH_L2H_INI:
480 p_dm->th_l2h_ini = (s8)value;
481 break;
482
483 case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
484 p_dm->th_edcca_hl_diff = (s8)value;
485 break;
486
487 case PHYDM_ADAPINFO_AP_NUM_TH:
488 adaptivity->ap_num_th = (u8)value;
489 break;
490
491 default:
492 break;
493
494 }
495
496 }
497
498 void
phydm_adaptivity_init(void * p_dm_void)499 phydm_adaptivity_init(
500 void *p_dm_void
501 )
502 {
503 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
504 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
505 s8 igi_target = 0x32;
506 /*struct phydm_dig_struct* p_dig_t = &p_dm->dm_dig_table;*/
507
508 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
509
510 if (p_dm->carrier_sense_enable == false) {
511 if (p_dm->th_l2h_ini == 0)
512 phydm_set_l2h_th_ini(p_dm);
513 } else
514 p_dm->th_l2h_ini = 0xa;
515
516 if (p_dm->th_edcca_hl_diff == 0)
517 p_dm->th_edcca_hl_diff = 7;
518 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
519 if (p_dm->wifi_test == true || *(p_dm->p_mp_mode) == true)
520 #else
521 if ((p_dm->wifi_test & RT_WIFI_LOGO) == true)
522 #endif
523 p_dm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
524 else
525 p_dm->edcca_enable = true;
526
527 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
528 struct rtl8192cd_priv *priv = p_dm->priv;
529
530 if (p_dm->carrier_sense_enable) {
531 p_dm->th_l2h_ini = 0xa;
532 p_dm->th_edcca_hl_diff = 7;
533 } else {
534 p_dm->th_l2h_ini = p_dm->TH_L2H_default; /*set by mib*/
535 p_dm->th_edcca_hl_diff = p_dm->th_edcca_hl_diff_default;
536 }
537
538 if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
539 adaptivity->dynamic_link_adaptivity = true;
540 else
541 adaptivity->dynamic_link_adaptivity = false;
542
543 #endif
544
545 adaptivity->adapt_igi_up = 0;
546 p_dm->adaptivity_enable = false; /*use this flag to decide enable or disable*/
547
548 p_dm->th_l2h_ini_mode2 = 20;
549 p_dm->th_edcca_hl_diff_mode2 = 8;
550 adaptivity->debug_mode = false;
551 adaptivity->th_l2h_ini_backup = p_dm->th_l2h_ini;
552 adaptivity->th_edcca_hl_diff_backup = p_dm->th_edcca_hl_diff;
553
554 adaptivity->igi_base = 0x32;
555 adaptivity->igi_target = 0x1c;
556 adaptivity->h2l_lb = 0;
557 adaptivity->l2h_lb = 0;
558 adaptivity->is_check = false;
559 adaptivity->adajust_igi_level = 0;
560 adaptivity->is_stop_edcca = false;
561 adaptivity->backup_h2l = 0;
562 adaptivity->backup_l2h = 0;
563 adaptivity->adaptivity_dbg_port = (p_dm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209;
564
565 phydm_mac_edcca_state(p_dm, phydm_dont_ignore_edcca);
566
567 if (p_dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
568 /*odm_set_bb_reg(p_dm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT(11) | BIT(10), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
569 if (p_dm->support_ic_type & ODM_RTL8197F) {
570 odm_set_bb_reg(p_dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/
571 odm_set_bb_reg(p_dm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT(26), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
572 odm_set_bb_reg(p_dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
573 } else
574 odm_set_bb_reg(p_dm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT(20), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
575 }
576 #if (RTL8195A_SUPPORT == 0)
577 if (p_dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/
578 /*odm_set_bb_reg(p_dm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT(29) | BIT(28), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
579 odm_set_bb_reg(p_dm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT(28), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
580 }
581
582 if (!(p_dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
583 phydm_search_pwdb_lower_bound(p_dm);
584 if (phydm_re_search_condition(p_dm))
585 phydm_search_pwdb_lower_bound(p_dm);
586 } else
587 phydm_set_edcca_threshold(p_dm, 0x7f, 0x7f); /*resume to no link state*/
588 #endif
589 /*forgetting factor setting*/
590 phydm_set_forgetting_factor(p_dm);
591
592 /*pwdb mode setting with 0: mean, 1:max*/
593 phydm_set_pwdb_mode(p_dm);
594
595 /*we need to consider PwdB upper bound for 8814 later IC*/
596 adaptivity->adajust_igi_level = (u8)((p_dm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
597
598 /*Check this later on Windows*/
599 /*phydm_set_edcca_threshold_api(p_dm, p_dig_t->cur_ig_value);*/
600
601 p_dm->adaptivity_flag = (p_dm->support_ic_type & ODM_IC_GAIN_IDX_EDCCA) ? false : true;
602
603 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
604 adaptivity->igi_up_bound_lmt_val = 180;
605 #else
606 adaptivity->igi_up_bound_lmt_val = 90;
607 #endif
608 adaptivity->igi_up_bound_lmt_cnt = 0;
609 adaptivity->igi_lmt_en = false;
610
611 }
612
613
614 void
phydm_adaptivity(void * p_dm_void)615 phydm_adaptivity(
616 void *p_dm_void
617 )
618 {
619 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
620 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
621 u8 igi = p_dig_t->cur_ig_value;
622 s8 th_l2h_dmc, th_h2l_dmc;
623 s8 diff = 0, igi_target = 0x32;
624 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
625 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
626 struct _ADAPTER *p_adapter = p_dm->adapter;
627 u32 is_fw_current_in_ps_mode = false;
628 u8 disable_ap_adapt_setting;
629
630 p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode));
631
632 /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
633 if (is_fw_current_in_ps_mode)
634 return;
635 #endif
636
637 if ((p_dm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) {
638 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("Disable EDCCA!!!\n"));
639 return;
640 }
641
642 phydm_check_adaptivity(p_dm); /*Check adaptivity enable*/
643 phydm_dig_up_bound_lmt_en(p_dm);
644
645 if ((!(p_dm->support_ability & ODM_BB_ADAPTIVITY)) && adaptivity->debug_mode == false) {
646 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("adaptivity disable, enable EDCCA mode!!!\n"));
647 p_dm->th_l2h_ini = p_dm->th_l2h_ini_mode2;
648 p_dm->th_edcca_hl_diff = p_dm->th_edcca_hl_diff_mode2;
649 }
650 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
651 else if (adaptivity->debug_mode == false) {
652 disable_ap_adapt_setting = false;
653 if (p_dm->p_soft_ap_mode != NULL) {
654 if (*(p_dm->p_soft_ap_mode) != 0 && (p_dm->soft_ap_special_setting & BIT(0)))
655 disable_ap_adapt_setting = true;
656 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("p_dm->soft_ap_special_setting = %x, *(p_dm->p_soft_ap_mode) = %d, disable_ap_adapt_setting = %d\n", p_dm->soft_ap_special_setting, *(p_dm->p_soft_ap_mode), disable_ap_adapt_setting));
657 }
658 if (phydm_check_channel_plan(p_dm) || (p_dm->ap_total_num > adaptivity->ap_num_th) || disable_ap_adapt_setting) {
659 p_dm->th_l2h_ini = p_dm->th_l2h_ini_mode2;
660 p_dm->th_edcca_hl_diff = p_dm->th_edcca_hl_diff_mode2;
661 } else {
662 p_dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
663 p_dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
664 }
665 }
666 #endif
667 else if (adaptivity->debug_mode == true) {
668 p_dm->th_l2h_ini = adaptivity->th_l2h_ini_debug;
669 p_dm->th_edcca_hl_diff = 7;
670 adaptivity->adajust_igi_level = (u8)((p_dm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
671 }
672 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("odm_Adaptivity() =====>\n"));
673 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
674 adaptivity->igi_base, p_dm->th_l2h_ini, p_dm->th_edcca_hl_diff));
675 #if (RTL8195A_SUPPORT == 0)
676 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
677 /*fix AC series when enable EDCCA hang issue*/
678 odm_set_bb_reg(p_dm, 0x800, BIT(10), 1); /*ADC_mask disable*/
679 odm_set_bb_reg(p_dm, 0x800, BIT(10), 0); /*ADC_mask enable*/
680 }
681 #endif
682
683 igi_target = adaptivity->igi_base;
684 adaptivity->igi_target = (u8) igi_target;
685
686 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d\n",
687 (*p_dm->p_band_width == CHANNEL_WIDTH_80) ? "80M" : ((*p_dm->p_band_width == CHANNEL_WIDTH_40) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity));
688 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
689 adaptivity->adajust_igi_level, p_dm->adaptivity_flag, p_dm->adaptivity_enable));
690
691 if ((adaptivity->dynamic_link_adaptivity == true) && (!p_dm->is_linked) && (p_dm->adaptivity_enable == false)) {
692 phydm_set_edcca_threshold(p_dm, 0x7f, 0x7f);
693 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
694 return;
695 }
696
697 if (p_dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
698 if ((adaptivity->adajust_igi_level > igi) && (p_dm->adaptivity_enable == true))
699 diff = adaptivity->adajust_igi_level - igi;
700 else if (p_dm->adaptivity_enable == false)
701 diff = 0x3e - igi;
702
703 th_l2h_dmc = p_dm->th_l2h_ini - diff + igi_target;
704 th_h2l_dmc = th_l2h_dmc - p_dm->th_edcca_hl_diff;
705 }
706 #if (RTL8195A_SUPPORT == 0)
707 else {
708 diff = igi_target - (s8)igi;
709 th_l2h_dmc = p_dm->th_l2h_ini + diff;
710 if (th_l2h_dmc > 10 && (p_dm->adaptivity_enable == true))
711 th_l2h_dmc = 10;
712
713 th_h2l_dmc = th_l2h_dmc - p_dm->th_edcca_hl_diff;
714
715 /*replace lower bound to prevent EDCCA always equal 1*/
716 if (th_h2l_dmc < adaptivity->h2l_lb)
717 th_h2l_dmc = adaptivity->h2l_lb;
718 if (th_l2h_dmc < adaptivity->l2h_lb)
719 th_l2h_dmc = adaptivity->l2h_lb;
720 }
721 #endif
722 adaptivity->th_l2h = th_l2h_dmc;
723 adaptivity->th_h2l = th_h2l_dmc;
724 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi, th_l2h_dmc, th_h2l_dmc));
725 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", adaptivity->adapt_igi_up, adaptivity->h2l_lb, adaptivity->l2h_lb));
726 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("debug_mode = %d\n", adaptivity->debug_mode));
727 phydm_set_edcca_threshold(p_dm, th_h2l_dmc, th_l2h_dmc);
728
729 if (p_dm->adaptivity_enable == true)
730 odm_set_mac_reg(p_dm, REG_RD_CTRL, BIT(11), 1);
731
732 return;
733 }
734
735 /*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
736 void
phydm_pause_edcca(void * p_dm_void,boolean is_pasue_edcca)737 phydm_pause_edcca(
738 void *p_dm_void,
739 boolean is_pasue_edcca
740 )
741 {
742 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
743 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
744 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
745 u8 IGI = p_dig_t->cur_ig_value;
746 s8 diff = 0;
747
748 if (is_pasue_edcca) {
749 adaptivity->is_stop_edcca = true;
750
751 if (p_dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
752 if (adaptivity->adajust_igi_level > IGI)
753 diff = adaptivity->adajust_igi_level - IGI;
754
755 adaptivity->backup_l2h = p_dm->th_l2h_ini - diff + adaptivity->igi_target;
756 adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm->th_edcca_hl_diff;
757 }
758 #if (RTL8195A_SUPPORT == 0)
759 else {
760 diff = adaptivity->igi_target - (s8)IGI;
761 adaptivity->backup_l2h = p_dm->th_l2h_ini + diff;
762 if (adaptivity->backup_l2h > 10)
763 adaptivity->backup_l2h = 10;
764
765 adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm->th_edcca_hl_diff;
766
767 /*replace lower bound to prevent EDCCA always equal 1*/
768 if (adaptivity->backup_h2l < adaptivity->h2l_lb)
769 adaptivity->backup_h2l = adaptivity->h2l_lb;
770 if (adaptivity->backup_l2h < adaptivity->l2h_lb)
771 adaptivity->backup_l2h = adaptivity->l2h_lb;
772 }
773 #endif
774 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI));
775
776 /*Disable EDCCA*/
777 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
778 if (odm_is_work_item_scheduled(&(adaptivity->phydm_pause_edcca_work_item)) == false)
779 odm_schedule_work_item(&(adaptivity->phydm_pause_edcca_work_item));
780 #else
781 phydm_pause_edcca_work_item_callback(p_dm);
782 #endif
783
784 } else {
785
786 adaptivity->is_stop_edcca = false;
787 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI));
788 /*Resume EDCCA*/
789 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
790 if (odm_is_work_item_scheduled(&(adaptivity->phydm_resume_edcca_work_item)) == false)
791 odm_schedule_work_item(&(adaptivity->phydm_resume_edcca_work_item));
792 #else
793 phydm_resume_edcca_work_item_callback(p_dm);
794 #endif
795
796 }
797
798 }
799
800
801 void
phydm_pause_edcca_work_item_callback(struct _ADAPTER * adapter)802 phydm_pause_edcca_work_item_callback(
803 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
804 struct _ADAPTER *adapter
805 #else
806 void *p_dm_void
807 #endif
808 )
809 {
810 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
811 PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
812 struct PHY_DM_STRUCT *p_dm = &p_hal_data->DM_OutSrc;
813 #else
814 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
815 #endif
816
817 if (p_dm->support_ic_type & ODM_IC_11N_SERIES)
818 odm_set_bb_reg(p_dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
819 #if (RTL8195A_SUPPORT == 0)
820 else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES)
821 odm_set_bb_reg(p_dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8));
822 #endif
823
824 }
825
826 void
phydm_resume_edcca_work_item_callback(struct _ADAPTER * adapter)827 phydm_resume_edcca_work_item_callback(
828 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
829 struct _ADAPTER *adapter
830 #else
831 void *p_dm_void
832 #endif
833 )
834 {
835 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
836 PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
837 struct PHY_DM_STRUCT *p_dm = &p_hal_data->DM_OutSrc;
838 #else
839 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
840 #endif
841 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
842
843 if (p_dm->support_ic_type & ODM_IC_11N_SERIES)
844 odm_set_bb_reg(p_dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16));
845 #if (RTL8195A_SUPPORT == 0)
846 else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES)
847 odm_set_bb_reg(p_dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8));
848 #endif
849
850 }
851
852
853 void
phydm_set_edcca_threshold_api(void * p_dm_void,u8 IGI)854 phydm_set_edcca_threshold_api(
855 void *p_dm_void,
856 u8 IGI
857 )
858 {
859 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
860 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
861 s8 th_l2h_dmc, th_h2l_dmc;
862 s8 diff = 0, igi_target = 0x32;
863
864 if (p_dm->support_ability & ODM_BB_ADAPTIVITY) {
865 if (p_dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
866 if (adaptivity->adajust_igi_level > IGI)
867 diff = adaptivity->adajust_igi_level - IGI;
868
869 th_l2h_dmc = p_dm->th_l2h_ini - diff + igi_target;
870 th_h2l_dmc = th_l2h_dmc - p_dm->th_edcca_hl_diff;
871 }
872 #if (RTL8195A_SUPPORT == 0)
873 else {
874 diff = igi_target - (s8)IGI;
875 th_l2h_dmc = p_dm->th_l2h_ini + diff;
876 if (th_l2h_dmc > 10)
877 th_l2h_dmc = 10;
878
879 th_h2l_dmc = th_l2h_dmc - p_dm->th_edcca_hl_diff;
880
881 /*replace lower bound to prevent EDCCA always equal 1*/
882 if (th_h2l_dmc < adaptivity->h2l_lb)
883 th_h2l_dmc = adaptivity->h2l_lb;
884 if (th_l2h_dmc < adaptivity->l2h_lb)
885 th_l2h_dmc = adaptivity->l2h_lb;
886 }
887 #endif
888 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc));
889 PHYDM_DBG(p_dm, DBG_ADPTVTY, ("API :adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", adaptivity->adapt_igi_up, adaptivity->h2l_lb, adaptivity->l2h_lb));
890
891 phydm_set_edcca_threshold(p_dm, th_h2l_dmc, th_l2h_dmc);
892 }
893 }
894
895 void
phydm_adaptivity_debug(void * p_dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)896 phydm_adaptivity_debug(
897 void *p_dm_void,
898 u32 *const dm_value,
899 u32 *_used,
900 char *output,
901 u32 *_out_len
902 )
903 {
904 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
905 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
906 u32 used = *_used;
907 u32 out_len = *_out_len;
908 u32 reg_value32;
909 s8 h2l_diff = 0;
910
911 if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
912 PHYDM_SNPRINTF((output + used, out_len - used, "Adaptivity Debug Mode ===>\n"));
913 adaptivity->debug_mode = true;
914 adaptivity->th_l2h_ini_debug = (s8)dm_value[1];
915 PHYDM_SNPRINTF((output + used, out_len - used, "th_l2h_ini_debug = %d\n", adaptivity->th_l2h_ini_debug));
916 } else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
917 PHYDM_SNPRINTF((output + used, out_len - used, "===> Adaptivity Resume\n"));
918 adaptivity->debug_mode = false;
919 } else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) {
920 PHYDM_SNPRINTF((output + used, out_len - used, "EDCCA Threshold Pause\n"));
921 p_dm->edcca_enable = false;
922 } else if (dm_value[0] == PHYDM_EDCCA_RESUME) {
923 PHYDM_SNPRINTF((output + used, out_len - used, "EDCCA Resume\n"));
924 p_dm->edcca_enable = true;
925 } else if (dm_value[0] == PHYDM_ADAPT_MSG) {
926 PHYDM_SNPRINTF((output + used, out_len - used, "debug_mode = %s, th_l2h_ini = %d\n", (adaptivity->debug_mode ? "TRUE" : "FALSE"), p_dm->th_l2h_ini));
927 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
928 reg_value32 = odm_get_bb_reg(p_dm, 0xc4c, MASKDWORD);
929 h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x00ff0000 & reg_value32)>>16);
930 }
931 #if (RTL8195A_SUPPORT == 0)
932 else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
933 reg_value32 = odm_get_bb_reg(p_dm, 0x8a4, MASKDWORD);
934 h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x0000ff00 & reg_value32)>>8);
935 }
936 #endif
937 if (h2l_diff == 7)
938 PHYDM_SNPRINTF((output + used, out_len - used, "adaptivity is enabled\n"));
939 else
940 PHYDM_SNPRINTF((output + used, out_len - used, "adaptivity is disabled\n"));
941 }
942 *_used = used;
943 *_out_len = out_len;
944 }
945
946 void
phydm_set_l2h_th_ini(void * p_dm_void)947 phydm_set_l2h_th_ini(
948 void *p_dm_void
949 )
950 {
951 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
952
953 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
954 if (p_dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
955 p_dm->th_l2h_ini = 0xf2;
956 else
957 p_dm->th_l2h_ini = 0xef;
958 } else
959 p_dm->th_l2h_ini = 0xf5;
960 }
961
962 void
phydm_set_forgetting_factor(void * p_dm_void)963 phydm_set_forgetting_factor(
964 void *p_dm_void
965 )
966 {
967 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
968
969 if (p_dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
970 odm_set_bb_reg(p_dm, 0x8a0, BIT(1) | BIT(0), 0);
971 }
972
973 void
phydm_set_pwdb_mode(void * p_dm_void)974 phydm_set_pwdb_mode(
975 void *p_dm_void
976 )
977 {
978 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
979
980 if (p_dm->support_ability & ODM_BB_ADAPTIVITY) {
981 if (p_dm->support_ic_type & ODM_RTL8822B)
982 odm_set_bb_reg(p_dm, 0x8dc, BIT(5), 0x1);
983 else if (p_dm->support_ic_type & ODM_RTL8197F)
984 odm_set_bb_reg(p_dm, 0xce8, BIT(13), 0x1);
985 } else {
986 if (p_dm->support_ic_type & ODM_RTL8822B)
987 odm_set_bb_reg(p_dm, 0x8dc, BIT(5), 0x0);
988 else if (p_dm->support_ic_type & ODM_RTL8197F)
989 odm_set_bb_reg(p_dm, 0xce8, BIT(13), 0x0);
990 }
991 }
992
993 void
phydm_set_edcca_val(void * p_dm_void,u32 * val_buf,u8 val_len)994 phydm_set_edcca_val(
995 void *p_dm_void,
996 u32 *val_buf,
997 u8 val_len
998 )
999 {
1000 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1001
1002 if (val_len != 2) {
1003 PHYDM_DBG(p_dm, ODM_COMP_API, ("[Error][adaptivity]Need val_len = 2\n"));
1004 return;
1005 }
1006 if (p_dm->pause_ability & BIT(F13_ADPTVTY))
1007 p_dm->adaptivity.is_stop_edcca = true;
1008 else
1009 p_dm->adaptivity.is_stop_edcca = false;
1010
1011 phydm_set_edcca_threshold(p_dm, (s8)val_buf[1], (s8)val_buf[0]);
1012 }
1013