1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 //============================================================
22 // include files
23 //============================================================
24 #include "mp_precomp.h"
25 #include "phydm_precomp.h"
26
27 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
28 #if WPP_SOFTWARE_TRACE
29 #include "PhyDM_Adaptivity.tmh"
30 #endif
31 #endif
32
33
34 VOID
Phydm_CheckAdaptivity(IN PVOID pDM_VOID)35 Phydm_CheckAdaptivity(
36 IN PVOID pDM_VOID
37 )
38 {
39 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
40 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
41
42 if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
43 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
44 if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {
45 pDM_Odm->Adaptivity_enable = FALSE;
46 pDM_Odm->adaptivity_flag = FALSE;
47 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));
48 } else
49 #endif
50 {
51 if (Adaptivity->DynamicLinkAdaptivity || Adaptivity->AcsForAdaptivity) {
52 if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {
53 Phydm_NHMCounterStatistics(pDM_Odm);
54 Phydm_CheckEnvironment(pDM_Odm);
55 } else if (!pDM_Odm->bLinked)
56 Adaptivity->bCheck = FALSE;
57 } else {
58 pDM_Odm->Adaptivity_enable = TRUE;
59
60 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
61 pDM_Odm->adaptivity_flag = FALSE;
62 else
63 pDM_Odm->adaptivity_flag = TRUE;
64 }
65 }
66 } else {
67 pDM_Odm->Adaptivity_enable = FALSE;
68 pDM_Odm->adaptivity_flag = FALSE;
69 }
70
71
72
73 }
74
75 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
76 BOOLEAN
Phydm_CheckChannelPlan(IN PVOID pDM_VOID)77 Phydm_CheckChannelPlan(
78 IN PVOID pDM_VOID
79 )
80 {
81 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
82 PADAPTER pAdapter = pDM_Odm->Adapter;
83 PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
84
85 if (pMgntInfo->RegEnableAdaptivity == 2) {
86 if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/
87 if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
88 !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
89 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
90 pDM_Odm->Adaptivity_enable = FALSE;
91 pDM_Odm->adaptivity_flag = FALSE;
92 return TRUE;
93 } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
94 !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
95 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
96 pDM_Odm->Adaptivity_enable = FALSE;
97 pDM_Odm->adaptivity_flag = FALSE;
98 return TRUE;
99
100 } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
101 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
102 pDM_Odm->Adaptivity_enable = FALSE;
103 pDM_Odm->adaptivity_flag = FALSE;
104 return TRUE;
105 }
106 } else {
107 if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
108 !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
109 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
110 pDM_Odm->Adaptivity_enable = FALSE;
111 pDM_Odm->adaptivity_flag = FALSE;
112 return TRUE;
113 }
114
115 else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
116 !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
117 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
118 pDM_Odm->Adaptivity_enable = FALSE;
119 pDM_Odm->adaptivity_flag = FALSE;
120 return TRUE;
121
122 } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
123 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
124 pDM_Odm->Adaptivity_enable = FALSE;
125 pDM_Odm->adaptivity_flag = FALSE;
126 return TRUE;
127 }
128 }
129 }
130
131 return FALSE;
132
133 }
134 #endif
135
136 VOID
Phydm_NHMCounterStatisticsInit(IN PVOID pDM_VOID)137 Phydm_NHMCounterStatisticsInit(
138 IN PVOID pDM_VOID
139 )
140 {
141 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
142
143 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
144 /*PHY parameters initialize for n series*/
145 ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+ 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
146 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/
147 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
148 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
149 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/
150 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
151 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/
152 }
153 #if (RTL8195A_SUPPORT == 0)
154 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
155 /*PHY parameters initialize for ac series*/
156 ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+ 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
157 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/
158 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
159 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
160 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/
161 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
162 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/
163
164 }
165 #endif
166 }
167
168 VOID
Phydm_NHMCounterStatistics(IN PVOID pDM_VOID)169 Phydm_NHMCounterStatistics(
170 IN PVOID pDM_VOID
171 )
172 {
173 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
174
175 if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
176 return;
177
178 /*Get NHM report*/
179 Phydm_GetNHMCounterStatistics(pDM_Odm);
180
181 /*Reset NHM counter*/
182 Phydm_NHMCounterStatisticsReset(pDM_Odm);
183 }
184
185 VOID
Phydm_GetNHMCounterStatistics(IN PVOID pDM_VOID)186 Phydm_GetNHMCounterStatistics(
187 IN PVOID pDM_VOID
188 )
189 {
190 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
191 u4Byte value32 = 0;
192 #if (RTL8195A_SUPPORT == 0)
193 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
194 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
195 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
196 #endif
197 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
198
199 pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
200 pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);
201
202 }
203
204 VOID
Phydm_NHMCounterStatisticsReset(IN PVOID pDM_VOID)205 Phydm_NHMCounterStatisticsReset(
206 IN PVOID pDM_VOID
207 )
208 {
209 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
210
211 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
212 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
213 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
214 }
215 #if (RTL8195A_SUPPORT == 0)
216 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
217 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
218 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
219 }
220
221 #endif
222
223 }
224
225 VOID
Phydm_SetEDCCAThreshold(IN PVOID pDM_VOID,IN s1Byte H2L,IN s1Byte L2H)226 Phydm_SetEDCCAThreshold(
227 IN PVOID pDM_VOID,
228 IN s1Byte H2L,
229 IN s1Byte L2H
230 )
231 {
232 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
233
234 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
235 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16));
236 #if (RTL8195A_SUPPORT == 0)
237 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
238 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8));
239 #endif
240
241 }
242
243 VOID
Phydm_SetLNA(IN PVOID pDM_VOID,IN PhyDM_set_LNA type)244 Phydm_SetLNA(
245 IN PVOID pDM_VOID,
246 IN PhyDM_set_LNA type
247 )
248 {
249 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
250
251 if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) {
252 if (type == PhyDM_disable_LNA) {
253 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
254 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
255 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
256 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/
257 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
258 if (pDM_Odm->RFType > ODM_1T1R) {
259 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
260 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
261 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
262 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);
263 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
264 }
265 } else if (type == PhyDM_enable_LNA) {
266 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
267 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
268 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
269 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/
270 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
271 if (pDM_Odm->RFType > ODM_1T1R) {
272 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
273 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
274 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
275 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);
276 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
277 }
278 }
279 } else if (pDM_Odm->SupportICType & ODM_RTL8723B) {
280 if (type == PhyDM_disable_LNA) {
281 /*S0*/
282 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
283 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
284 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
285 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/
286 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
287 /*S1*/
288 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
289 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/
290 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
291 } else if (type == PhyDM_enable_LNA) {
292 /*S0*/
293 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
294 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
295 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
296 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/
297 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
298 /*S1*/
299 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
300 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/
301 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
302 }
303
304 } else if (pDM_Odm->SupportICType & ODM_RTL8812) {
305 if (type == PhyDM_disable_LNA) {
306 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
307 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
308 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
309 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
310 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
311 if (pDM_Odm->RFType > ODM_1T1R) {
312 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
313 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
314 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
315 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
316 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
317 }
318 } else if (type == PhyDM_enable_LNA) {
319 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
320 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
321 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
322 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
323 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
324 if (pDM_Odm->RFType > ODM_1T1R) {
325 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
326 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
327 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
328 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
329 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
330 }
331 }
332 } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) {
333 if (type == PhyDM_disable_LNA) {
334 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
335 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
336 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
337 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
338 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
339 } else if (type == PhyDM_enable_LNA) {
340 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
341 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
342 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
343 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
344 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
345 }
346 }
347 }
348
349
350
351 VOID
Phydm_SetTRxMux(IN PVOID pDM_VOID,IN PhyDM_Trx_MUX_Type txMode,IN PhyDM_Trx_MUX_Type rxMode)352 Phydm_SetTRxMux(
353 IN PVOID pDM_VOID,
354 IN PhyDM_Trx_MUX_Type txMode,
355 IN PhyDM_Trx_MUX_Type rxMode
356 )
357 {
358 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
359
360 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
361 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
362 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
363 if (pDM_Odm->RFType > ODM_1T1R) {
364 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
365 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
366 }
367 }
368 #if (RTL8195A_SUPPORT == 0)
369 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
370 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
371 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
372 if (pDM_Odm->RFType > ODM_1T1R) {
373 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
374 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
375 }
376 }
377 #endif
378
379 }
380
381 VOID
Phydm_MACEDCCAState(IN PVOID pDM_VOID,IN PhyDM_MACEDCCA_Type State)382 Phydm_MACEDCCAState(
383 IN PVOID pDM_VOID,
384 IN PhyDM_MACEDCCA_Type State
385 )
386 {
387 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
388 if (State == PhyDM_IGNORE_EDCCA) {
389 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/
390 /* ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); *//*reg524[11]=0*/
391 } else { /*don't set MAC ignore EDCCA signal*/
392 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/
393 /* ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); *//*reg524[11]=1 */
394 }
395 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));
396
397 }
398
399 BOOLEAN
Phydm_CalNHMcnt(IN PVOID pDM_VOID)400 Phydm_CalNHMcnt(
401 IN PVOID pDM_VOID
402 )
403 {
404 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
405 u2Byte Base = 0;
406
407 Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
408
409 if (Base != 0) {
410 pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
411 pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
412 }
413 if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
414 return TRUE; /*clean environment*/
415 else
416 return FALSE; /*noisy environment*/
417
418 }
419
420
421 VOID
Phydm_CheckEnvironment(IN PVOID pDM_VOID)422 Phydm_CheckEnvironment(
423 IN PVOID pDM_VOID
424 )
425 {
426 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
427 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
428 BOOLEAN isCleanEnvironment = FALSE;
429 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
430 prtl8192cd_priv priv = pDM_Odm->priv;
431 #endif
432
433 if (Adaptivity->bFirstLink == TRUE) {
434 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
435 pDM_Odm->adaptivity_flag = FALSE;
436 else
437 pDM_Odm->adaptivity_flag = TRUE;
438
439 Adaptivity->bFirstLink = FALSE;
440 return;
441 } else {
442 if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/
443 Adaptivity->NHMWait++;
444 Phydm_NHMCounterStatistics(pDM_Odm);
445 return;
446 } else {
447 Phydm_NHMCounterStatistics(pDM_Odm);
448 isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
449 if (isCleanEnvironment == TRUE) {
450 pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/
451 pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
452
453 pDM_Odm->Adaptivity_enable = TRUE;
454
455 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
456 pDM_Odm->adaptivity_flag = FALSE;
457 else
458 pDM_Odm->adaptivity_flag = TRUE;
459 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
460 priv->pshare->rf_ft_var.isCleanEnvironment = TRUE;
461 #endif
462 } else {
463 if (!Adaptivity->AcsForAdaptivity) {
464 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/
465 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
466
467 pDM_Odm->adaptivity_flag = FALSE;
468 pDM_Odm->Adaptivity_enable = FALSE;
469 }
470 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
471 priv->pshare->rf_ft_var.isCleanEnvironment = FALSE;
472 #endif
473 }
474 Adaptivity->NHMWait = 0;
475 Adaptivity->bFirstLink = TRUE;
476 Adaptivity->bCheck = TRUE;
477 }
478
479 }
480
481
482 }
483
484 VOID
Phydm_SearchPwdBLowerBound(IN PVOID pDM_VOID)485 Phydm_SearchPwdBLowerBound(
486 IN PVOID pDM_VOID
487 )
488 {
489 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
490 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
491 u4Byte value32 = 0;
492 u1Byte cnt;
493 u1Byte txEdcca1 = 0, txEdcca0 = 0;
494 BOOLEAN bAdjust = TRUE;
495 s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
496 s1Byte Diff;
497 u1Byte IGI = Adaptivity->IGI_Base + 30 + (u1Byte)pDM_Odm->TH_L2H_ini - (u1Byte)pDM_Odm->TH_EDCCA_HL_diff;
498
499 if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
500 Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA);
501 else {
502 Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
503 odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
504 }
505
506 Diff = IGI_target - (s1Byte)IGI;
507 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
508 if (TH_L2H_dmc > 10)
509 TH_L2H_dmc = 10;
510 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
511
512 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
513 ODM_delay_ms(5);
514
515 while (bAdjust) {
516 for (cnt = 0; cnt < 20; cnt++) {
517 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
518 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);
519 #if (RTL8195A_SUPPORT == 0)
520 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
521 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);
522 #endif
523 if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E)))
524 txEdcca1 = txEdcca1 + 1;
525 else if (value32 & BIT29)
526 txEdcca1 = txEdcca1 + 1;
527 else
528 txEdcca0 = txEdcca0 + 1;
529 }
530
531 if (txEdcca1 > 1) {
532 IGI = IGI - 1;
533 TH_L2H_dmc = TH_L2H_dmc + 1;
534 if (TH_L2H_dmc > 10)
535 TH_L2H_dmc = 10;
536 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
537
538 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
539 if (TH_L2H_dmc == 10) {
540 bAdjust = FALSE;
541 Adaptivity->H2L_lb = TH_H2L_dmc;
542 Adaptivity->L2H_lb = TH_L2H_dmc;
543 pDM_Odm->Adaptivity_IGI_upper = IGI;
544 }
545
546 txEdcca1 = 0;
547 txEdcca0 = 0;
548
549 } else {
550 bAdjust = FALSE;
551 Adaptivity->H2L_lb = TH_H2L_dmc;
552 Adaptivity->L2H_lb = TH_L2H_dmc;
553 pDM_Odm->Adaptivity_IGI_upper = IGI;
554 txEdcca1 = 0;
555 txEdcca0 = 0;
556 }
557 }
558
559 pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;
560 Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;
561 Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;
562
563 if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
564 Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA);
565 else {
566 Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
567 odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
568 }
569
570 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/
571 }
572
573 BOOLEAN
phydm_reSearchCondition(IN PVOID pDM_VOID)574 phydm_reSearchCondition(
575 IN PVOID pDM_VOID
576 )
577 {
578 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
579 /*PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);*/
580 u1Byte Adaptivity_IGI_upper;
581 /*s1Byte TH_L2H_dmc, IGI_target = 0x32;*/
582 /*s1Byte Diff;*/
583
584 Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + pDM_Odm->DCbackoff;
585
586 /*TH_L2H_dmc = 10;*/
587
588 /*Diff = TH_L2H_dmc - pDM_Odm->TH_L2H_ini;*/
589 /*lowest_IGI_upper = IGI_target - Diff;*/
590
591 /*if ((Adaptivity_IGI_upper - lowest_IGI_upper) <= 5)*/
592 if (Adaptivity_IGI_upper <= 0x26)
593 return TRUE;
594 else
595 return FALSE;
596
597 }
598
599 VOID
phydm_adaptivityInfoInit(IN PVOID pDM_VOID,IN PHYDM_ADAPINFO_E CmnInfo,IN u4Byte Value)600 phydm_adaptivityInfoInit(
601 IN PVOID pDM_VOID,
602 IN PHYDM_ADAPINFO_E CmnInfo,
603 IN u4Byte Value
604 )
605 {
606 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
607 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
608
609 switch (CmnInfo) {
610 case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
611 pDM_Odm->Carrier_Sense_enable = (BOOLEAN)Value;
612 break;
613
614 case PHYDM_ADAPINFO_DCBACKOFF:
615 pDM_Odm->DCbackoff = (u1Byte)Value;
616 break;
617
618 case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
619 Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)Value;
620 break;
621
622 case PHYDM_ADAPINFO_TH_L2H_INI:
623 pDM_Odm->TH_L2H_ini = (s1Byte)Value;
624 break;
625
626 case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
627 pDM_Odm->TH_EDCCA_HL_diff = (s1Byte)Value;
628 break;
629
630 case PHYDM_ADAPINFO_AP_NUM_TH:
631 Adaptivity->APNumTH = (u1Byte)Value;
632 break;
633
634 default:
635 break;
636
637 }
638
639 }
640
641
642
643 VOID
Phydm_AdaptivityInit(IN PVOID pDM_VOID)644 Phydm_AdaptivityInit(
645 IN PVOID pDM_VOID
646 )
647 {
648 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
649 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
650 s1Byte IGItarget = 0x32;
651 /*pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;*/
652
653 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
654
655 if (pDM_Odm->Carrier_Sense_enable == FALSE) {
656 if (pDM_Odm->TH_L2H_ini == 0)
657 pDM_Odm->TH_L2H_ini = 0xf5;
658 } else
659 pDM_Odm->TH_L2H_ini = 0xa;
660
661 if (pDM_Odm->TH_EDCCA_HL_diff == 0)
662 pDM_Odm->TH_EDCCA_HL_diff = 7;
663 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))
664 if (pDM_Odm->WIFITest == TRUE || pDM_Odm->mp_mode == TRUE)
665 #else
666 if ((pDM_Odm->WIFITest & RT_WIFI_LOGO) == TRUE)
667 #endif
668 pDM_Odm->EDCCA_enable = FALSE; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
669 else
670 pDM_Odm->EDCCA_enable = TRUE;
671
672 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
673 prtl8192cd_priv priv = pDM_Odm->priv;
674
675 if (pDM_Odm->Carrier_Sense_enable) {
676 pDM_Odm->TH_L2H_ini = 0xa;
677 pDM_Odm->TH_EDCCA_HL_diff = 7;
678 } else {
679 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_default; /*set by mib*/
680 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_default;
681 }
682
683 if (priv->pshare->rf_ft_var.adaptivity_enable == 3)
684 Adaptivity->AcsForAdaptivity = TRUE;
685 else
686 Adaptivity->AcsForAdaptivity = FALSE;
687
688 if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
689 Adaptivity->DynamicLinkAdaptivity = TRUE;
690 else
691 Adaptivity->DynamicLinkAdaptivity = FALSE;
692
693 priv->pshare->rf_ft_var.isCleanEnvironment = FALSE;
694
695 #endif
696
697 pDM_Odm->Adaptivity_IGI_upper = 0;
698 pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/
699
700 pDM_Odm->TH_L2H_ini_mode2 = 20;
701 pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
702 Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
703 Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;
704
705 Adaptivity->IGI_Base = 0x32;
706 Adaptivity->IGI_target = 0x1c;
707 Adaptivity->H2L_lb = 0;
708 Adaptivity->L2H_lb = 0;
709 Adaptivity->NHMWait = 0;
710 Adaptivity->bCheck = FALSE;
711 Adaptivity->bFirstLink = TRUE;
712 Adaptivity->AdajustIGILevel = 0;
713 Adaptivity->bStopEDCCA = FALSE;
714 Adaptivity->backupH2L = 0;
715 Adaptivity->backupL2H = 0;
716
717 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
718
719 /*Search pwdB lower bound*/
720 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
721 ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
722 #if (RTL8195A_SUPPORT == 0)
723 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
724 ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
725 #endif
726
727 if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) {
728 /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
729 if (pDM_Odm->SupportICType & ODM_RTL8197F) {
730 ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x1); /*set to page B1*/
731 ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_97F, BIT27 | BIT26, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
732 ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x0);
733 } else
734 ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
735 }
736 #if (RTL8195A_SUPPORT == 0)
737 if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/
738 /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
739 ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
740 }
741
742 if (!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
743 Phydm_SearchPwdBLowerBound(pDM_Odm);
744 if (phydm_reSearchCondition(pDM_Odm))
745 Phydm_SearchPwdBLowerBound(pDM_Odm);
746 }
747 #endif
748
749 /*we need to consider PwdB upper bound for 8814 later IC*/
750 Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/
751
752 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel));
753
754 /*Check this later on Windows*/
755 /*phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);*/
756
757 }
758
759
760 VOID
Phydm_Adaptivity(IN PVOID pDM_VOID,IN u1Byte IGI)761 Phydm_Adaptivity(
762 IN PVOID pDM_VOID,
763 IN u1Byte IGI
764 )
765 {
766 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
767 s1Byte TH_L2H_dmc, TH_H2L_dmc;
768 s1Byte Diff = 0, IGI_target;
769 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
770 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
771 PADAPTER pAdapter = pDM_Odm->Adapter;
772 BOOLEAN bFwCurrentInPSMode = FALSE;
773
774 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
775
776 /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
777 if (bFwCurrentInPSMode)
778 return;
779 #endif
780
781 if ((pDM_Odm->EDCCA_enable == FALSE) || (Adaptivity->bStopEDCCA == TRUE)) {
782 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));
783 return;
784 }
785
786 if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {
787 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));
788 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
789 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
790 }
791 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
792 else{
793 if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) {
794 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
795 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
796 } else {
797 pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup;
798 pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
799 }
800 }
801 #endif
802
803 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));
804 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",
805 Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
806 #if (RTL8195A_SUPPORT == 0)
807 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
808 /*fix AC series when enable EDCCA hang issue*/
809 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/
810 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/
811 }
812 #endif
813 if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/
814 IGI_target = Adaptivity->IGI_Base;
815 else if (*pDM_Odm->pBandWidth == ODM_BW40M)
816 IGI_target = Adaptivity->IGI_Base + 2;
817 #if (RTL8195A_SUPPORT == 0)
818 else if (*pDM_Odm->pBandWidth == ODM_BW80M)
819 IGI_target = Adaptivity->IGI_Base + 2;
820 #endif
821 else
822 IGI_target = Adaptivity->IGI_Base;
823 Adaptivity->IGI_target = (u1Byte) IGI_target;
824
825 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d, AcsForAdaptivity = %d\n",
826 (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity, Adaptivity->AcsForAdaptivity));
827 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",
828 pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));
829
830 if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {
831 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
832 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
833 return;
834 }
835
836 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
837 if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE))
838 Diff = Adaptivity->AdajustIGILevel - IGI;
839
840 TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;
841 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
842 }
843 #if (RTL8195A_SUPPORT == 0)
844 else {
845 Diff = IGI_target - (s1Byte)IGI;
846 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
847 if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE))
848 TH_L2H_dmc = 10;
849
850 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
851
852 /*replace lower bound to prevent EDCCA always equal 1*/
853 if (TH_H2L_dmc < Adaptivity->H2L_lb)
854 TH_H2L_dmc = Adaptivity->H2L_lb;
855 if (TH_L2H_dmc < Adaptivity->L2H_lb)
856 TH_L2H_dmc = Adaptivity->L2H_lb;
857 }
858 #endif
859 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
860 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));
861
862 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
863
864 if (pDM_Odm->Adaptivity_enable == TRUE)
865 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);
866
867 return;
868 }
869
870
871 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
872
873 VOID
Phydm_AdaptivityBSOD(IN PVOID pDM_VOID)874 Phydm_AdaptivityBSOD(
875 IN PVOID pDM_VOID
876 )
877 {
878 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
879 PADAPTER pAdapter = pDM_Odm->Adapter;
880 PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
881 u1Byte count = 0;
882 u4Byte u4Value;
883
884 /*
885 1. turn off RF (TRX Mux in standby mode)
886 2. H2C mac id drop
887 3. ignore EDCCA
888 4. wait for clear FIFO
889 5. don't ignore EDCCA
890 6. turn on RF (TRX Mux in TRx mdoe)
891 7. H2C mac id resume
892 */
893
894 RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
895
896 pAdapter->dropPktByMacIdCnt++;
897 pMgntInfo->bDropPktInProgress = TRUE;
898
899 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));
900 RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));
901 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
902 RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
903
904 /*Standby mode*/
905 Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
906 ODM_Write_DIG(pDM_Odm, 0x20);
907
908 /*H2C mac id drop*/
909 MacIdIndicateDisconnect(pAdapter);
910
911 /*Ignore EDCCA*/
912 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
913
914 delay_ms(50);
915 count = 5;
916
917 /*Resume EDCCA*/
918 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
919
920 /*Turn on TRx mode*/
921 Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
922 ODM_Write_DIG(pDM_Odm, 0x20);
923
924 /*Resume H2C macid*/
925 MacIdRecoverMediaStatus(pAdapter);
926
927 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
928 RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
929
930 pMgntInfo->bDropPktInProgress = FALSE;
931 RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));
932
933 }
934
935 #endif
936
937 /*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
938 VOID
phydm_pauseEDCCA(IN PVOID pDM_VOID,IN BOOLEAN bPasueEDCCA)939 phydm_pauseEDCCA(
940 IN PVOID pDM_VOID,
941 IN BOOLEAN bPasueEDCCA
942 )
943 {
944 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
945 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
946 pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
947 u1Byte IGI = pDM_DigTable->CurIGValue;
948 s1Byte Diff = 0;
949
950 if (bPasueEDCCA) {
951 Adaptivity->bStopEDCCA = TRUE;
952
953 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
954 if (Adaptivity->AdajustIGILevel > IGI)
955 Diff = Adaptivity->AdajustIGILevel - IGI;
956
957 Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini - Diff + Adaptivity->IGI_target;
958 Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff;
959 }
960 #if (RTL8195A_SUPPORT == 0)
961 else {
962 Diff = Adaptivity->IGI_target - (s1Byte)IGI;
963 Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini + Diff;
964 if (Adaptivity->backupL2H > 10)
965 Adaptivity->backupL2H = 10;
966
967 Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff;
968
969 /*replace lower bound to prevent EDCCA always equal 1*/
970 if (Adaptivity->backupH2L < Adaptivity->H2L_lb)
971 Adaptivity->backupH2L = Adaptivity->H2L_lb;
972 if (Adaptivity->backupL2H < Adaptivity->L2H_lb)
973 Adaptivity->backupL2H = Adaptivity->L2H_lb;
974 }
975 #endif
976 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI));
977
978 /*Disable EDCCA*/
979 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
980 if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_pauseEDCCAWorkItem)) == FALSE)
981 PlatformScheduleWorkItem(&(Adaptivity->phydm_pauseEDCCAWorkItem));
982 #else
983 phydm_pauseEDCCA_WorkItemCallback(pDM_Odm);
984 #endif
985
986 } else {
987
988 Adaptivity->bStopEDCCA = FALSE;
989 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI));
990 /*Resume EDCCA*/
991 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
992 if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_resumeEDCCAWorkItem)) == FALSE)
993 PlatformScheduleWorkItem(&(Adaptivity->phydm_resumeEDCCAWorkItem));
994 #else
995 phydm_resumeEDCCA_WorkItemCallback(pDM_Odm);
996 #endif
997
998 }
999
1000 }
1001
1002
1003 VOID
phydm_pauseEDCCA_WorkItemCallback(IN PADAPTER Adapter)1004 phydm_pauseEDCCA_WorkItemCallback(
1005 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1006 IN PADAPTER Adapter
1007 #else
1008 IN PVOID pDM_VOID
1009 #endif
1010 )
1011 {
1012 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1013 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1014 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1015 #else
1016 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1017 #endif
1018
1019 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1020 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)(0x7f|0x7f<<16));
1021 #if (RTL8195A_SUPPORT == 0)
1022 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1023 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)(0x7f|0x7f<<8));
1024 #endif
1025
1026 }
1027
1028 VOID
phydm_resumeEDCCA_WorkItemCallback(IN PADAPTER Adapter)1029 phydm_resumeEDCCA_WorkItemCallback(
1030 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1031 IN PADAPTER Adapter
1032 #else
1033 IN PVOID pDM_VOID
1034 #endif
1035 )
1036 {
1037 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1038 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1039 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1040 #else
1041 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1042 #endif
1043 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
1044
1045 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1046 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<16));
1047 #if (RTL8195A_SUPPORT == 0)
1048 else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1049 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<8));
1050 #endif
1051
1052 }
1053
1054
1055 VOID
phydm_setEDCCAThresholdAPI(IN PVOID pDM_VOID,IN u1Byte IGI)1056 phydm_setEDCCAThresholdAPI(
1057 IN PVOID pDM_VOID,
1058 IN u1Byte IGI
1059 )
1060 {
1061 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1062 PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
1063 s1Byte TH_L2H_dmc, TH_H2L_dmc;
1064 s1Byte Diff = 0, IGI_target = 0x32;
1065
1066 if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
1067 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
1068 if (Adaptivity->AdajustIGILevel > IGI)
1069 Diff = Adaptivity->AdajustIGILevel - IGI;
1070
1071 TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;
1072 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
1073 }
1074 #if (RTL8195A_SUPPORT == 0)
1075 else {
1076 Diff = IGI_target - (s1Byte)IGI;
1077 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
1078 if (TH_L2H_dmc > 10)
1079 TH_L2H_dmc = 10;
1080
1081 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
1082
1083 /*replace lower bound to prevent EDCCA always equal 1*/
1084 if (TH_H2L_dmc < Adaptivity->H2L_lb)
1085 TH_H2L_dmc = Adaptivity->H2L_lb;
1086 if (TH_L2H_dmc < Adaptivity->L2H_lb)
1087 TH_L2H_dmc = Adaptivity->L2H_lb;
1088 }
1089 #endif
1090 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
1091 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));
1092
1093 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
1094 }
1095
1096 }
1097
1098