1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19
20 #include "mp_precomp.h"
21 #include "phydm_precomp.h"
22
23
24 void
phydm_init_trx_antenna_setting(void * p_dm_void)25 phydm_init_trx_antenna_setting(
26 void *p_dm_void
27 )
28 {
29 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
30
31 if (p_dm->support_ic_type & (ODM_RTL8814A)) {
32 u8 rx_ant = 0, tx_ant = 0;
33
34 rx_ant = (u8)odm_get_bb_reg(p_dm, ODM_REG(BB_RX_PATH, p_dm), ODM_BIT(BB_RX_PATH, p_dm));
35 tx_ant = (u8)odm_get_bb_reg(p_dm, ODM_REG(BB_TX_PATH, p_dm), ODM_BIT(BB_TX_PATH, p_dm));
36 p_dm->tx_ant_status = (tx_ant & 0xf);
37 p_dm->rx_ant_status = (rx_ant & 0xf);
38 } else if (p_dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */
39 p_dm->tx_ant_status = 0x1;
40 p_dm->rx_ant_status = 0x1;
41
42 }
43 }
44
45 void
phydm_config_ofdm_tx_path(void * p_dm_void,u32 path)46 phydm_config_ofdm_tx_path(
47 void *p_dm_void,
48 u32 path
49 )
50 {
51 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
52 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
53 u8 ofdm_tx_path = 0x33;
54 #endif
55
56 #if (RTL8192E_SUPPORT == 1)
57 if (p_dm->support_ic_type & (ODM_RTL8192E)) {
58
59 if (path == BB_PATH_A) {
60 odm_set_bb_reg(p_dm, 0x90c, MASKDWORD, 0x81121111);
61 /**/
62 } else if (path == BB_PATH_B) {
63 odm_set_bb_reg(p_dm, 0x90c, MASKDWORD, 0x82221222);
64 /**/
65 } else if (path == BB_PATH_AB) {
66 odm_set_bb_reg(p_dm, 0x90c, MASKDWORD, 0x83321333);
67 /**/
68 }
69
70
71 }
72 #endif
73
74 #if (RTL8812A_SUPPORT == 1)
75 if (p_dm->support_ic_type & (ODM_RTL8812)) {
76
77 if (path == BB_PATH_A) {
78 ofdm_tx_path = 0x11;
79 /**/
80 } else if (path == BB_PATH_B) {
81 ofdm_tx_path = 0x22;
82 /**/
83 } else if (path == BB_PATH_AB) {
84 ofdm_tx_path = 0x33;
85 /**/
86 }
87
88 odm_set_bb_reg(p_dm, 0x80c, 0xff00, ofdm_tx_path);
89 }
90 #endif
91 }
92
93 void
phydm_config_ofdm_rx_path(void * p_dm_void,u32 path)94 phydm_config_ofdm_rx_path(
95 void *p_dm_void,
96 u32 path
97 )
98 {
99 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
100 u8 ofdm_rx_path = 0;
101
102
103 if (p_dm->support_ic_type & (ODM_RTL8192E)) {
104 #if (RTL8192E_SUPPORT == 1)
105 if (path == BB_PATH_A) {
106 ofdm_rx_path = 1;
107 /**/
108 } else if (path == BB_PATH_B) {
109 ofdm_rx_path = 2;
110 /**/
111 } else if (path == BB_PATH_AB) {
112 ofdm_rx_path = 3;
113 /**/
114 }
115
116 odm_set_bb_reg(p_dm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path));
117 odm_set_bb_reg(p_dm, 0xD04, 0xf, ofdm_rx_path);
118 #endif
119 }
120 #if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
121 else if (p_dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
122
123 if (path == BB_PATH_A) {
124 ofdm_rx_path = 1;
125 /**/
126 } else if (path == BB_PATH_B) {
127 ofdm_rx_path = 2;
128 /**/
129 } else if (path == BB_PATH_AB) {
130 ofdm_rx_path = 3;
131 /**/
132 }
133
134 odm_set_bb_reg(p_dm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path));
135 }
136 #endif
137 }
138
139 void
phydm_config_cck_rx_antenna_init(void * p_dm_void)140 phydm_config_cck_rx_antenna_init(
141 void *p_dm_void
142 )
143 {
144 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
145
146 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
147 /*CCK 2R CCA parameters*/
148 odm_set_bb_reg(p_dm, 0xa00, BIT(15), 0x0); /*Disable antenna diversity*/
149 odm_set_bb_reg(p_dm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/
150 odm_set_bb_reg(p_dm, 0xa74, BIT(8), 0); /*RX path diversity enable*/
151 odm_set_bb_reg(p_dm, 0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
152 odm_set_bb_reg(p_dm, 0xa20, (BIT(5) | BIT(4)), 1); /*MBC weighting*/
153
154 if (p_dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
155 odm_set_bb_reg(p_dm, 0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
156 /**/
157 } else if (p_dm->support_ic_type & ODM_RTL8814A) {
158 odm_set_bb_reg(p_dm, 0xa84, BIT(28), 1); /*2R CCA only*/
159 /**/
160 }
161 #endif
162 }
163
164 void
phydm_config_cck_rx_path(void * p_dm_void,enum bb_path path)165 phydm_config_cck_rx_path(
166 void *p_dm_void,
167 enum bb_path path
168 )
169 {
170 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
171 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
172 u8 path_div_select = 0;
173 u8 cck_path[2] = {0};
174 u8 en_2R_path = 0;
175 u8 en_2R_mrc = 0;
176 u8 i = 0, j =0;
177 u8 num_enable_path = 0;
178 u8 cck_mrc_max_path = 2;
179
180 for (i = 0; i < 4; i++) {
181 if (path & BIT(i)) { /*ex: PHYDM_ABCD*/
182 num_enable_path++;
183 cck_path[j] = i;
184 j++;
185 }
186 if (num_enable_path >= cck_mrc_max_path)
187 break;
188 }
189
190 if (num_enable_path > 1) {
191 path_div_select = 1;
192 en_2R_path = 1;
193 en_2R_mrc = 1;
194 } else {
195 path_div_select = 0;
196 en_2R_path = 0;
197 en_2R_mrc = 0;
198 }
199
200 odm_set_bb_reg(p_dm, 0xa04, (BIT(27) | BIT(26)), cck_path[0]); /*CCK_1 input signal path*/
201 odm_set_bb_reg(p_dm, 0xa04, (BIT(25) | BIT(24)), cck_path[1]); /*CCK_2 input signal path*/
202 odm_set_bb_reg(p_dm, 0xa74, BIT(8), path_div_select); /*enable Rx path diversity*/
203 odm_set_bb_reg(p_dm, 0xa2c, BIT(18), en_2R_path); /*enable 2R Rx path*/
204 odm_set_bb_reg(p_dm, 0xa2c, BIT(22), en_2R_mrc); /*enable 2R MRC*/
205
206 #endif
207 }
208
209 void
phydm_config_trx_path(void * p_dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)210 phydm_config_trx_path(
211 void *p_dm_void,
212 u32 *const dm_value,
213 u32 *_used,
214 char *output,
215 u32 *_out_len
216 )
217 {
218 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
219 u32 used = *_used;
220 u32 out_len = *_out_len;
221
222 /* CCK */
223 if (dm_value[0] == 0) {
224
225 if (dm_value[1] == 1) { /*TX*/
226 if (dm_value[2] == 1)
227 odm_set_bb_reg(p_dm, 0xa04, 0xf0000000, 0x8);
228 else if (dm_value[2] == 2)
229 odm_set_bb_reg(p_dm, 0xa04, 0xf0000000, 0x4);
230 else if (dm_value[2] == 3)
231 odm_set_bb_reg(p_dm, 0xa04, 0xf0000000, 0xc);
232 } else if (dm_value[1] == 2) { /*RX*/
233
234 phydm_config_cck_rx_antenna_init(p_dm);
235
236 if (dm_value[2] == 1)
237 phydm_config_cck_rx_path(p_dm, BB_PATH_A);
238 else if (dm_value[2] == 2)
239 phydm_config_cck_rx_path(p_dm, BB_PATH_B);
240 else if (dm_value[2] == 3) {
241 phydm_config_cck_rx_path(p_dm, BB_PATH_AB);
242 }
243 }
244 }
245 /* OFDM */
246 else if (dm_value[0] == 1) {
247
248 if (dm_value[1] == 1) { /*TX*/
249 phydm_config_ofdm_tx_path(p_dm, dm_value[2]);
250 /**/
251 } else if (dm_value[1] == 2) { /*RX*/
252 phydm_config_ofdm_rx_path(p_dm, dm_value[2]);
253 /**/
254 }
255 }
256
257 PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
258 (dm_value[0] == 1) ? "OFDM" : "CCK",
259 (dm_value[1] == 1) ? "TX" : "RX",
260 (dm_value[2] & 0x1) ? "A" : "",
261 (dm_value[2] & 0x2) ? "B" : "",
262 (dm_value[2] & 0x4) ? "C" : "",
263 (dm_value[2] & 0x8) ? "D" : ""
264 ));
265
266 }
267
268 void
phydm_stop_3_wire(void * p_dm_void,u8 set_type)269 phydm_stop_3_wire(
270 void *p_dm_void,
271 u8 set_type
272 )
273 {
274 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
275
276 if (set_type == PHYDM_SET) {
277
278 /*[Stop 3-wires]*/
279 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
280 odm_set_bb_reg(p_dm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */
281 odm_set_bb_reg(p_dm, 0xe00, 0xf, 0x4);/* hardware 3-wire off */
282 } else {
283 odm_set_bb_reg(p_dm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
284 }
285
286 } else { /*if (set_type == PHYDM_REVERT)*/
287
288 /*[Start 3-wires]*/
289 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
290 odm_set_bb_reg(p_dm, 0xc00, 0xf, 0x7);/* hardware 3-wire on */
291 odm_set_bb_reg(p_dm, 0xe00, 0xf, 0x7);/* hardware 3-wire on */
292 } else {
293 odm_set_bb_reg(p_dm, 0x88c, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
294 }
295 }
296 }
297
298 u8
phydm_stop_ic_trx(void * p_dm_void,u8 set_type)299 phydm_stop_ic_trx(
300 void *p_dm_void,
301 u8 set_type
302 )
303 {
304 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
305 struct phydm_api_stuc *p_api = &(p_dm->api_table);
306 u32 i;
307 u8 trx_idle_success = false;
308 u32 dbg_port_value = 0;
309
310 if (set_type == PHYDM_SET) {
311 /*[Stop TRX]---------------------------------------------------------------------*/
312 if (phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_3, 0x0) == false) /*set debug port to 0x0*/
313 return PHYDM_SET_FAIL;
314
315 for (i = 0; i<10000; i++) {
316 dbg_port_value = phydm_get_bb_dbg_port_value(p_dm);
317 if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ {
318 PHYDM_DBG(p_dm, ODM_COMP_API, ("PSD wait for ((%d)) times\n", i));
319
320 trx_idle_success = true;
321 break;
322 }
323 }
324 phydm_release_bb_dbg_port(p_dm);
325
326 if (trx_idle_success) {
327
328 p_api->tx_queue_bitmap = (u8)odm_get_bb_reg(p_dm, 0x520, 0xff0000);
329
330 odm_set_bb_reg(p_dm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/
331
332 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
333 odm_set_bb_reg(p_dm, 0x808, BIT(28), 0); /*disable CCK block*/
334 odm_set_bb_reg(p_dm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/
335 } else {
336 /*TBD*/
337 odm_set_bb_reg(p_dm, 0x800, BIT(24), 0); /* disable whole CCK block */
338
339
340 p_api->rx_iqc_reg_1 = odm_get_bb_reg(p_dm, 0xc14, MASKDWORD);
341 p_api->rx_iqc_reg_2 = odm_get_bb_reg(p_dm, 0xc1c, MASKDWORD);
342
343 odm_set_bb_reg(p_dm, 0xc14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
344 odm_set_bb_reg(p_dm, 0xc1c, MASKDWORD, 0x0);
345 }
346
347 } else {
348 return PHYDM_SET_FAIL;
349 }
350
351 return PHYDM_SET_SUCCESS;
352
353 } else { /*if (set_type == PHYDM_REVERT)*/
354
355 odm_set_bb_reg(p_dm, 0x520, 0xff0000, (u32)(p_api->tx_queue_bitmap)); /*Release all TX queue*/
356
357 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
358 odm_set_bb_reg(p_dm, 0x808, BIT(28), 1); /*enable CCK block*/
359 odm_set_bb_reg(p_dm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/
360 } else {
361 /*TBD*/
362 odm_set_bb_reg(p_dm, 0x800, BIT(24), 1); /* enable whole CCK block */
363
364 odm_set_bb_reg(p_dm, 0xc14, MASKDWORD, p_api->rx_iqc_reg_1); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
365 odm_set_bb_reg(p_dm, 0xc1c, MASKDWORD, p_api->rx_iqc_reg_2);
366 }
367
368 return PHYDM_SET_SUCCESS;
369 }
370
371 }
372
373 void
phydm_set_ext_switch(void * p_dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)374 phydm_set_ext_switch(
375 void *p_dm_void,
376 u32 *const dm_value,
377 u32 *_used,
378 char *output,
379 u32 *_out_len
380 )
381 {
382 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
383 u32 ext_ant_switch = dm_value[0];
384
385 #if (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
386 if (p_dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
387
388 /*Output Pin Settings*/
389 odm_set_mac_reg(p_dm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/
390 odm_set_mac_reg(p_dm, 0x4C, BIT(24), 1); /*by WLAN control*/
391
392 odm_set_bb_reg(p_dm, 0xCB4, 0xFF, 77); /*DPDT_N = 1b'0*/ /*DPDT_P = 1b'0*/
393
394 if (ext_ant_switch == MAIN_ANT) {
395 odm_set_bb_reg(p_dm, 0xCB4, (BIT(29) | BIT(28)), 1);
396 PHYDM_DBG(p_dm, ODM_COMP_API, ("***8821A set ant switch = 2b'01 (Main)\n"));
397 } else if (ext_ant_switch == AUX_ANT) {
398 odm_set_bb_reg(p_dm, 0xCB4, BIT(29) | BIT(28), 2);
399 PHYDM_DBG(p_dm, ODM_COMP_API, ("***8821A set ant switch = 2b'10 (Aux)\n"));
400 }
401 }
402 #endif
403 }
404
405 void
phydm_csi_mask_enable(void * p_dm_void,u32 enable)406 phydm_csi_mask_enable(
407 void *p_dm_void,
408 u32 enable
409 )
410 {
411 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
412 u32 reg_value = 0;
413
414 reg_value = (enable == FUNC_ENABLE) ? 1 : 0;
415
416 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
417
418 odm_set_bb_reg(p_dm, 0xD2C, BIT(28), reg_value);
419 PHYDM_DBG(p_dm, ODM_COMP_API, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value));
420
421 } else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
422
423 odm_set_bb_reg(p_dm, 0x874, BIT(0), reg_value);
424 PHYDM_DBG(p_dm, ODM_COMP_API, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value));
425 }
426
427 }
428
429 void
phydm_clean_all_csi_mask(void * p_dm_void)430 phydm_clean_all_csi_mask(
431 void *p_dm_void
432 )
433 {
434 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
435
436 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
437
438 odm_set_bb_reg(p_dm, 0xD40, MASKDWORD, 0);
439 odm_set_bb_reg(p_dm, 0xD44, MASKDWORD, 0);
440 odm_set_bb_reg(p_dm, 0xD48, MASKDWORD, 0);
441 odm_set_bb_reg(p_dm, 0xD4c, MASKDWORD, 0);
442
443 } else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
444
445 odm_set_bb_reg(p_dm, 0x880, MASKDWORD, 0);
446 odm_set_bb_reg(p_dm, 0x884, MASKDWORD, 0);
447 odm_set_bb_reg(p_dm, 0x888, MASKDWORD, 0);
448 odm_set_bb_reg(p_dm, 0x88c, MASKDWORD, 0);
449 odm_set_bb_reg(p_dm, 0x890, MASKDWORD, 0);
450 odm_set_bb_reg(p_dm, 0x894, MASKDWORD, 0);
451 odm_set_bb_reg(p_dm, 0x898, MASKDWORD, 0);
452 odm_set_bb_reg(p_dm, 0x89c, MASKDWORD, 0);
453 }
454 }
455
456 void
phydm_set_csi_mask_reg(void * p_dm_void,u32 tone_idx_tmp,u8 tone_direction)457 phydm_set_csi_mask_reg(
458 void *p_dm_void,
459 u32 tone_idx_tmp,
460 u8 tone_direction
461 )
462 {
463 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
464 u8 byte_offset, bit_offset;
465 u32 target_reg;
466 u8 reg_tmp_value;
467 u32 tone_num = 64;
468 u32 tone_num_shift = 0;
469 u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
470
471 /* calculate real tone idx*/
472 if ((tone_idx_tmp % 10) >= 5)
473 tone_idx_tmp += 10;
474
475 tone_idx_tmp = (tone_idx_tmp / 10);
476
477 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
478
479 tone_num = 64;
480 csi_mask_reg_p = 0xD40;
481 csi_mask_reg_n = 0xD48;
482
483 } else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
484
485 tone_num = 128;
486 csi_mask_reg_p = 0x880;
487 csi_mask_reg_n = 0x890;
488 }
489
490 if (tone_direction == FREQ_POSITIVE) {
491
492 if (tone_idx_tmp >= (tone_num - 1))
493 tone_idx_tmp = (tone_num - 1);
494
495 byte_offset = (u8)(tone_idx_tmp >> 3);
496 bit_offset = (u8)(tone_idx_tmp & 0x7);
497 target_reg = csi_mask_reg_p + byte_offset;
498
499 } else {
500 tone_num_shift = tone_num;
501
502 if (tone_idx_tmp >= tone_num)
503 tone_idx_tmp = tone_num;
504
505 tone_idx_tmp = tone_num - tone_idx_tmp;
506
507 byte_offset = (u8)(tone_idx_tmp >> 3);
508 bit_offset = (u8)(tone_idx_tmp & 0x7);
509 target_reg = csi_mask_reg_n + byte_offset;
510 }
511
512 reg_tmp_value = odm_read_1byte(p_dm, target_reg);
513 PHYDM_DBG(p_dm, ODM_COMP_API, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
514 reg_tmp_value |= BIT(bit_offset);
515 odm_write_1byte(p_dm, target_reg, reg_tmp_value);
516 PHYDM_DBG(p_dm, ODM_COMP_API, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
517 }
518
519 void
phydm_set_nbi_reg(void * p_dm_void,u32 tone_idx_tmp,u32 bw)520 phydm_set_nbi_reg(
521 void *p_dm_void,
522 u32 tone_idx_tmp,
523 u32 bw
524 )
525 {
526 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
527 u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/
528 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/
529 485, 505, 525, 555, 585, 615, 635
530 }; /*21~27*/
531
532 u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/
533 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/
534 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/
535 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/
536 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/
537 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275
538 }; /*51~59*/
539
540 u32 reg_idx = 0;
541 u32 i;
542 u8 nbi_table_idx = FFT_128_TYPE;
543
544 if (p_dm->support_ic_type & ODM_IC_11N_SERIES)
545
546 nbi_table_idx = FFT_128_TYPE;
547 else if (p_dm->support_ic_type & ODM_IC_11AC_1_SERIES)
548
549 nbi_table_idx = FFT_256_TYPE;
550 else if (p_dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
551
552 if (bw == 80)
553 nbi_table_idx = FFT_256_TYPE;
554 else /*20M, 40M*/
555 nbi_table_idx = FFT_128_TYPE;
556 }
557
558 if (nbi_table_idx == FFT_128_TYPE) {
559
560 for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
561 if (tone_idx_tmp < nbi_table_128[i]) {
562 reg_idx = i + 1;
563 break;
564 }
565 }
566
567 } else if (nbi_table_idx == FFT_256_TYPE) {
568
569 for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
570 if (tone_idx_tmp < nbi_table_256[i]) {
571 reg_idx = i + 1;
572 break;
573 }
574 }
575 }
576
577 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
578 odm_set_bb_reg(p_dm, 0xc40, 0x1f000000, reg_idx);
579 PHYDM_DBG(p_dm, ODM_COMP_API, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx));
580 /**/
581 } else {
582 odm_set_bb_reg(p_dm, 0x87c, 0xfc000, reg_idx);
583 PHYDM_DBG(p_dm, ODM_COMP_API, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx));
584 /**/
585 }
586 }
587
588
589 void
phydm_nbi_enable(void * p_dm_void,u32 enable)590 phydm_nbi_enable(
591 void *p_dm_void,
592 u32 enable
593 )
594 {
595 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
596 u32 reg_value = 0;
597
598 reg_value = (enable == FUNC_ENABLE) ? 1 : 0;
599
600 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
601
602 odm_set_bb_reg(p_dm, 0xc40, BIT(9), reg_value);
603 PHYDM_DBG(p_dm, ODM_COMP_API, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value));
604
605 } else if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
606
607 if (p_dm->support_ic_type & (ODM_RTL8822B|ODM_RTL8821C)) {
608 odm_set_bb_reg(p_dm, 0x87c, BIT(13), reg_value);
609 odm_set_bb_reg(p_dm, 0xc20, BIT(28), reg_value);
610 if (p_dm->rf_type > RF_1T1R)
611 odm_set_bb_reg(p_dm, 0xe20, BIT(28), reg_value);
612 } else
613 odm_set_bb_reg(p_dm, 0x87c, BIT(13), reg_value);
614 PHYDM_DBG(p_dm, ODM_COMP_API, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value));
615 }
616 }
617
618 u8
phydm_calculate_fc(void * p_dm_void,u32 channel,u32 bw,u32 second_ch,u32 * fc_in)619 phydm_calculate_fc(
620 void *p_dm_void,
621 u32 channel,
622 u32 bw,
623 u32 second_ch,
624 u32 *fc_in
625 )
626 {
627 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
628 u32 fc = *fc_in;
629 u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173};
630 u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165};
631 u32 *p_start_ch = &(start_ch_per_40m[0]);
632 u32 num_start_channel = NUM_START_CH_40M;
633 u32 channel_offset = 0;
634 u32 i;
635
636 /*2.4G*/
637 if (channel <= 14 && channel > 0) {
638
639 if (bw == 80)
640 return PHYDM_SET_FAIL;
641
642 fc = 2412 + (channel - 1) * 5;
643
644 if (bw == 40 && (second_ch == PHYDM_ABOVE)) {
645
646 if (channel >= 10) {
647 PHYDM_DBG(p_dm, ODM_COMP_API, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch));
648 return PHYDM_SET_FAIL;
649 }
650 fc += 10;
651 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
652
653 if (channel <= 2) {
654 PHYDM_DBG(p_dm, ODM_COMP_API, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch));
655 return PHYDM_SET_FAIL;
656 }
657 fc -= 10;
658 }
659 }
660 /*5G*/
661 else if (channel >= 36 && channel <= 177) {
662
663 if (bw != 20) {
664
665 if (bw == 40) {
666 num_start_channel = NUM_START_CH_40M;
667 p_start_ch = &(start_ch_per_40m[0]);
668 channel_offset = CH_OFFSET_40M;
669 } else if (bw == 80) {
670 num_start_channel = NUM_START_CH_80M;
671 p_start_ch = &(start_ch_per_80m[0]);
672 channel_offset = CH_OFFSET_80M;
673 }
674
675 for (i = 0; i < (num_start_channel - 1); i++) {
676
677 if (channel < p_start_ch[i + 1]) {
678 channel = p_start_ch[i] + channel_offset;
679 break;
680 }
681 }
682 PHYDM_DBG(p_dm, ODM_COMP_API, ("Mod_CH = ((%d))\n", channel));
683 }
684
685 fc = 5180 + (channel - 36) * 5;
686
687 } else {
688 PHYDM_DBG(p_dm, ODM_COMP_API, ("CH = ((%d)) Error setting\n", channel));
689 return PHYDM_SET_FAIL;
690 }
691
692 *fc_in = fc;
693
694 return PHYDM_SET_SUCCESS;
695 }
696
697
698 u8
phydm_calculate_intf_distance(void * p_dm_void,u32 bw,u32 fc,u32 f_interference,u32 * p_tone_idx_tmp_in)699 phydm_calculate_intf_distance(
700 void *p_dm_void,
701 u32 bw,
702 u32 fc,
703 u32 f_interference,
704 u32 *p_tone_idx_tmp_in
705 )
706 {
707 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
708 u32 bw_up, bw_low;
709 u32 int_distance;
710 u32 tone_idx_tmp;
711 u8 set_result = PHYDM_SET_NO_NEED;
712
713 bw_up = fc + bw / 2;
714 bw_low = fc - bw / 2;
715
716 PHYDM_DBG(p_dm, ODM_COMP_API, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference));
717
718 if ((f_interference >= bw_low) && (f_interference <= bw_up)) {
719
720 int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc);
721 tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */
722 PHYDM_DBG(p_dm, ODM_COMP_API, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10)));
723 *p_tone_idx_tmp_in = tone_idx_tmp;
724 set_result = PHYDM_SET_SUCCESS;
725 }
726
727 return set_result;
728
729 }
730
731
732 u8
phydm_csi_mask_setting(void * p_dm_void,u32 enable,u32 channel,u32 bw,u32 f_interference,u32 second_ch)733 phydm_csi_mask_setting(
734 void *p_dm_void,
735 u32 enable,
736 u32 channel,
737 u32 bw,
738 u32 f_interference,
739 u32 second_ch
740 )
741 {
742 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
743 u32 fc = 2412;
744 u8 tone_direction;
745 u32 tone_idx_tmp;
746 u8 set_result = PHYDM_SET_SUCCESS;
747
748 if (enable == FUNC_DISABLE) {
749 set_result = PHYDM_SET_SUCCESS;
750 phydm_clean_all_csi_mask(p_dm);
751
752 } else {
753
754 PHYDM_DBG(p_dm, ODM_COMP_API, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
755 channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")));
756
757 /*calculate fc*/
758 if (phydm_calculate_fc(p_dm, channel, bw, second_ch, &fc) == PHYDM_SET_FAIL)
759 set_result = PHYDM_SET_FAIL;
760
761 else {
762 /*calculate interference distance*/
763 if (phydm_calculate_intf_distance(p_dm, bw, fc, f_interference, &tone_idx_tmp) == PHYDM_SET_SUCCESS) {
764
765 tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE;
766 phydm_set_csi_mask_reg(p_dm, tone_idx_tmp, tone_direction);
767 set_result = PHYDM_SET_SUCCESS;
768 } else
769 set_result = PHYDM_SET_NO_NEED;
770 }
771 }
772
773 if (set_result == PHYDM_SET_SUCCESS)
774 phydm_csi_mask_enable(p_dm, enable);
775 else
776 phydm_csi_mask_enable(p_dm, FUNC_DISABLE);
777
778 return set_result;
779 }
780
781 u8
phydm_nbi_setting(void * p_dm_void,u32 enable,u32 channel,u32 bw,u32 f_interference,u32 second_ch)782 phydm_nbi_setting(
783 void *p_dm_void,
784 u32 enable,
785 u32 channel,
786 u32 bw,
787 u32 f_interference,
788 u32 second_ch
789 )
790 {
791 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
792 u32 fc = 2412;
793 u32 tone_idx_tmp;
794 u8 set_result = PHYDM_SET_SUCCESS;
795
796 if (enable == FUNC_DISABLE)
797 set_result = PHYDM_SET_SUCCESS;
798
799 else {
800
801 PHYDM_DBG(p_dm, ODM_COMP_API, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
802 channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")));
803
804 /*calculate fc*/
805 if (phydm_calculate_fc(p_dm, channel, bw, second_ch, &fc) == PHYDM_SET_FAIL)
806 set_result = PHYDM_SET_FAIL;
807
808 else {
809 /*calculate interference distance*/
810 if (phydm_calculate_intf_distance(p_dm, bw, fc, f_interference, &tone_idx_tmp) == PHYDM_SET_SUCCESS) {
811
812 phydm_set_nbi_reg(p_dm, tone_idx_tmp, bw);
813 set_result = PHYDM_SET_SUCCESS;
814 } else
815 set_result = PHYDM_SET_NO_NEED;
816 }
817 }
818
819 if (set_result == PHYDM_SET_SUCCESS)
820 phydm_nbi_enable(p_dm, enable);
821 else
822 phydm_nbi_enable(p_dm, FUNC_DISABLE);
823
824 return set_result;
825 }
826
827 void
phydm_api_debug(void * p_dm_void,u32 function_map,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)828 phydm_api_debug(
829 void *p_dm_void,
830 u32 function_map,
831 u32 *const dm_value,
832 u32 *_used,
833 char *output,
834 u32 *_out_len
835 )
836 {
837 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
838 u32 used = *_used;
839 u32 out_len = *_out_len;
840 u32 channel = dm_value[1];
841 u32 bw = dm_value[2];
842 u32 f_interference = dm_value[3];
843 u32 second_ch = dm_value[4];
844 u8 set_result = 0;
845
846 /*PHYDM_API_NBI*/
847 /*-------------------------------------------------------------------------------------------------------------------------------*/
848 if (function_map == PHYDM_API_NBI) {
849
850 if (dm_value[0] == 100) {
851
852 PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"));
853 return;
854
855 } else if (dm_value[0] == FUNC_ENABLE) {
856
857 PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
858 channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L")));
859 set_result = phydm_nbi_setting(p_dm, FUNC_ENABLE, channel, bw, f_interference, second_ch);
860
861 } else if (dm_value[0] == FUNC_DISABLE) {
862
863 PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n"));
864 set_result = phydm_nbi_setting(p_dm, FUNC_DISABLE, channel, bw, f_interference, second_ch);
865
866 } else
867
868 set_result = PHYDM_SET_FAIL;
869 PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == PHYDM_SET_SUCCESS) ? "Success" : ((set_result == PHYDM_SET_NO_NEED) ? "No need" : "Error")));
870
871 }
872
873 /*PHYDM_CSI_MASK*/
874 /*-------------------------------------------------------------------------------------------------------------------------------*/
875 else if (function_map == PHYDM_API_CSI_MASK) {
876
877 if (dm_value[0] == 100) {
878
879 PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"));
880 return;
881
882 } else if (dm_value[0] == FUNC_ENABLE) {
883
884 PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
885 channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L")));
886 set_result = phydm_csi_mask_setting(p_dm, FUNC_ENABLE, channel, bw, f_interference, second_ch);
887
888 } else if (dm_value[0] == FUNC_DISABLE) {
889
890 PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n"));
891 set_result = phydm_csi_mask_setting(p_dm, FUNC_DISABLE, channel, bw, f_interference, second_ch);
892
893 } else
894
895 set_result = PHYDM_SET_FAIL;
896 PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == PHYDM_SET_SUCCESS) ? "Success" : ((set_result == PHYDM_SET_NO_NEED) ? "No need" : "Error")));
897 }
898 *_used = used;
899 *_out_len = out_len;
900 }
901
902 void
phydm_stop_ck320(void * p_dm_void,u8 enable)903 phydm_stop_ck320(
904 void *p_dm_void,
905 u8 enable
906 ) {
907 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
908 u32 reg_value = (enable == true) ? 1 : 0;
909
910 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
911 odm_set_bb_reg(p_dm, 0x8b4, BIT(6), reg_value);
912 /**/
913 } else {
914
915 if (p_dm->support_ic_type & ODM_IC_N_2SS) { /*N-2SS*/
916 odm_set_bb_reg(p_dm, 0x87c, BIT(29), reg_value);
917 /**/
918 } else { /*N-1SS*/
919 odm_set_bb_reg(p_dm, 0x87c, BIT(31), reg_value);
920 /**/
921 }
922 }
923 }
924
925 #ifdef PHYDM_COMMON_API_SUPPORT
926 boolean
phydm_api_set_txagc(void * p_dm_void,u32 power_index,enum rf_path path,u8 hw_rate,boolean is_single_rate)927 phydm_api_set_txagc(
928 void *p_dm_void,
929 u32 power_index,
930 enum rf_path path,
931 u8 hw_rate,
932 boolean is_single_rate
933 )
934 {
935 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
936 boolean ret = false;
937 u8 i;
938
939 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
940 if (p_dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
941 if (is_single_rate) {
942
943 #if (RTL8822B_SUPPORT == 1)
944 if (p_dm->support_ic_type == ODM_RTL8822B)
945 ret = phydm_write_txagc_1byte_8822b(p_dm, power_index, path, hw_rate);
946 #endif
947
948 #if (RTL8821C_SUPPORT == 1)
949 if (p_dm->support_ic_type == ODM_RTL8821C)
950 ret = phydm_write_txagc_1byte_8821c(p_dm, power_index, path, hw_rate);
951 #endif
952
953 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
954 set_current_tx_agc(p_dm->priv, path, hw_rate, (u8)power_index);
955 #endif
956
957 } else {
958
959 #if (RTL8822B_SUPPORT == 1)
960 if (p_dm->support_ic_type == ODM_RTL8822B)
961 ret = config_phydm_write_txagc_8822b(p_dm, power_index, path, hw_rate);
962 #endif
963
964 #if (RTL8821C_SUPPORT == 1)
965 if (p_dm->support_ic_type == ODM_RTL8821C)
966 ret = config_phydm_write_txagc_8821c(p_dm, power_index, path, hw_rate);
967 #endif
968
969 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
970 for (i = 0; i < 4; i++)
971 set_current_tx_agc(p_dm->priv, path, (hw_rate + i), (u8)power_index);
972 #endif
973 }
974 }
975 #endif
976
977
978 #if (RTL8197F_SUPPORT == 1)
979 if (p_dm->support_ic_type & ODM_RTL8197F)
980 ret = config_phydm_write_txagc_8197f(p_dm, power_index, path, hw_rate);
981 #endif
982
983 return ret;
984 }
985
986 u8
phydm_api_get_txagc(void * p_dm_void,enum rf_path path,u8 hw_rate)987 phydm_api_get_txagc(
988 void *p_dm_void,
989 enum rf_path path,
990 u8 hw_rate
991 )
992 {
993 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
994 u8 ret = 0;
995
996 #if (RTL8822B_SUPPORT == 1)
997 if (p_dm->support_ic_type & ODM_RTL8822B)
998 ret = config_phydm_read_txagc_8822b(p_dm, path, hw_rate);
999 #endif
1000
1001 #if (RTL8197F_SUPPORT == 1)
1002 if (p_dm->support_ic_type & ODM_RTL8197F)
1003 ret = config_phydm_read_txagc_8197f(p_dm, path, hw_rate);
1004 #endif
1005
1006 #if (RTL8821C_SUPPORT == 1)
1007 if (p_dm->support_ic_type & ODM_RTL8821C)
1008 ret = config_phydm_read_txagc_8821c(p_dm, path, hw_rate);
1009 #endif
1010
1011 return ret;
1012 }
1013
1014
1015 boolean
phydm_api_switch_bw_channel(void * p_dm_void,u8 central_ch,u8 primary_ch_idx,enum channel_width bandwidth)1016 phydm_api_switch_bw_channel(
1017 void *p_dm_void,
1018 u8 central_ch,
1019 u8 primary_ch_idx,
1020 enum channel_width bandwidth
1021 )
1022 {
1023 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1024 boolean ret = false;
1025
1026 #if (RTL8822B_SUPPORT == 1)
1027 if (p_dm->support_ic_type & ODM_RTL8822B)
1028 ret = config_phydm_switch_channel_bw_8822b(p_dm, central_ch, primary_ch_idx, bandwidth);
1029 #endif
1030
1031 #if (RTL8197F_SUPPORT == 1)
1032 if (p_dm->support_ic_type & ODM_RTL8197F)
1033 ret = config_phydm_switch_channel_bw_8197f(p_dm, central_ch, primary_ch_idx, bandwidth);
1034 #endif
1035
1036 #if (RTL8821C_SUPPORT == 1)
1037 if (p_dm->support_ic_type & ODM_RTL8821C)
1038 ret = config_phydm_switch_channel_bw_8821c(p_dm, central_ch, primary_ch_idx, bandwidth);
1039 #endif
1040
1041 return ret;
1042 }
1043
1044 boolean
phydm_api_trx_mode(void * p_dm_void,enum bb_path tx_path,enum bb_path rx_path,boolean is_tx2_path)1045 phydm_api_trx_mode(
1046 void *p_dm_void,
1047 enum bb_path tx_path,
1048 enum bb_path rx_path,
1049 boolean is_tx2_path
1050 )
1051 {
1052 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1053 boolean ret = false;
1054
1055 #if (RTL8822B_SUPPORT == 1)
1056 if (p_dm->support_ic_type & ODM_RTL8822B)
1057 ret = config_phydm_trx_mode_8822b(p_dm, tx_path, rx_path, is_tx2_path);
1058 #endif
1059
1060 #if (RTL8197F_SUPPORT == 1)
1061 if (p_dm->support_ic_type & ODM_RTL8197F)
1062 ret = config_phydm_trx_mode_8197f(p_dm, tx_path, rx_path, is_tx2_path);
1063 #endif
1064
1065 return ret;
1066 }
1067 #endif
1068
1069
1070 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1071 void
phydm_normal_driver_rx_sniffer(struct PHY_DM_STRUCT * p_dm,u8 * p_desc,PRT_RFD_STATUS p_rt_rfd_status,u8 * p_drv_info,u8 phy_status)1072 phydm_normal_driver_rx_sniffer(
1073 struct PHY_DM_STRUCT *p_dm,
1074 u8 *p_desc,
1075 PRT_RFD_STATUS p_rt_rfd_status,
1076 u8 *p_drv_info,
1077 u8 phy_status
1078 )
1079 {
1080 #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
1081 u32 *p_msg;
1082 u16 seq_num;
1083 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1084
1085 if (p_rt_rfd_status->packet_report_type != NORMAL_RX)
1086 return;
1087
1088 if (!p_dm->is_linked) {
1089 if (p_rt_rfd_status->is_hw_error)
1090 return;
1091 }
1092
1093 if (!(p_dm_fat_table->fat_state == FAT_TRAINING_STATE))
1094 return;
1095
1096 if (phy_status == true) {
1097
1098 if ((p_dm->rx_pkt_type == type_block_ack) || (p_dm->rx_pkt_type == type_rts) || (p_dm->rx_pkt_type == type_cts))
1099 seq_num = 0;
1100 else
1101 seq_num = p_rt_rfd_status->seq_num;
1102
1103 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
1104 seq_num,
1105 /*p_rt_rfd_status->mac_id,*/
1106 ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"),
1107 p_rt_rfd_status->data_rate,
1108 p_rt_rfd_status->length,
1109 ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")),
1110 ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC")));
1111
1112 if (p_dm->rx_pkt_type == type_asoc_req) {
1113 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "AS_REQ"));
1114 /**/
1115 } else if (p_dm->rx_pkt_type == type_asoc_rsp) {
1116 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "AS_RSP"));
1117 /**/
1118 } else if (p_dm->rx_pkt_type == type_probe_req) {
1119 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "PR_REQ"));
1120 /**/
1121 } else if (p_dm->rx_pkt_type == type_probe_rsp) {
1122 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "PR_RSP"));
1123 /**/
1124 } else if (p_dm->rx_pkt_type == type_deauth) {
1125 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "DEAUTH"));
1126 /**/
1127 } else if (p_dm->rx_pkt_type == type_beacon) {
1128 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "BEACON"));
1129 /**/
1130 } else if (p_dm->rx_pkt_type == type_block_ack_req) {
1131 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "BA_REQ"));
1132 /**/
1133 } else if (p_dm->rx_pkt_type == type_rts) {
1134 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "__RTS_"));
1135 /**/
1136 } else if (p_dm->rx_pkt_type == type_cts) {
1137 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "__CTS_"));
1138 /**/
1139 } else if (p_dm->rx_pkt_type == type_ack) {
1140 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "__ACK_"));
1141 /**/
1142 } else if (p_dm->rx_pkt_type == type_block_ack) {
1143 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "__BA__"));
1144 /**/
1145 } else if (p_dm->rx_pkt_type == type_data) {
1146 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "_DATA_"));
1147 /**/
1148 } else if (p_dm->rx_pkt_type == type_data_ack) {
1149 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "Data_Ack"));
1150 /**/
1151 } else if (p_dm->rx_pkt_type == type_qos_data) {
1152 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [%s]", "QoS_Data"));
1153 /**/
1154 } else {
1155 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [0x%x]", p_dm->rx_pkt_type));
1156 /**/
1157 }
1158
1159 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , [RSSI=%d,%d,%d,%d ]",
1160 p_dm->RSSI_A,
1161 p_dm->RSSI_B,
1162 p_dm->RSSI_C,
1163 p_dm->RSSI_D));
1164
1165 p_msg = (u32 *)p_drv_info;
1166
1167 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
1168 p_msg[6], p_msg[5], p_msg[4], p_msg[3], p_msg[2], p_msg[1], p_msg[1]));
1169 } else {
1170
1171 PHYDM_DBG_F(p_dm, ODM_COMP_SNIFFER, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
1172 p_rt_rfd_status->seq_num,
1173 /*p_rt_rfd_status->mac_id,*/
1174 ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"),
1175 p_rt_rfd_status->data_rate,
1176 p_rt_rfd_status->length,
1177 ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")),
1178 ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC")));
1179 }
1180
1181
1182 #endif
1183 }
1184 #endif
1185
1186