1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 #include "mp_precomp.h"
22 #include "../phydm_precomp.h"
23
24 #if (RTL8822B_SUPPORT == 1)
25
26 /* ======================================================================== */
27 /* These following functions can be used for PHY DM only*/
28
29 u4Byte reg82c_8822b;
30 u4Byte reg838_8822b;
31 u4Byte reg830_8822b;
32 u4Byte reg83c_8822b;
33 u4Byte rega20_8822b;
34 u4Byte rega24_8822b;
35 u4Byte rega28_8822b;
36 ODM_BW_E bw_8822b;
37 u1Byte central_ch_8822b;
38
39 u4Byte cca_ifem_ccut[12][4] = {
40 /*20M*/
41 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
42 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
43 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
44 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
45 /*40M*/
46 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
47 {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/
48 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
49 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
50 /*80M*/
51 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
52 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
53 {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/
54 {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/
55 u4Byte cca_efem_ccut[12][4] = {
56 /*20M*/
57 {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
58 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
59 {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
60 {0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/
61 /*40M*/
62 {0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/
63 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
64 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
65 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
66 /*80M*/
67 {0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/
68 {0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/
69 {0x76666641, 0x76666641, 0x76666641, 0x76666641}, /*Reg838*/
70 {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/
71 u4Byte cca_ifem_ccut_RFTType5[12][4] = {
72 /*20M*/
73 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
74 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
75 {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
76 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
77 /*40M*/
78 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
79 {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/
80 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
81 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
82 /*80M*/
83 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
84 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
85 {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
86 {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/
87 u4Byte cca_ifem_ccut_RFTType3[12][4] = {
88 /*20M*/
89 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
90 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
91 {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
92 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
93 /*40M*/
94 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
95 {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/
96 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
97 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
98 /*80M*/
99 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
100 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
101 {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
102 {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/
103
104 BOOLEAN
phydm_rfe_8822b(IN PDM_ODM_T pDM_Odm,IN u1Byte channel)105 phydm_rfe_8822b(
106 IN PDM_ODM_T pDM_Odm,
107 IN u1Byte channel
108 )
109 {
110 if (pDM_Odm->RFEType == 4) {
111
112 /*TRSW = trsw_forced_BT ? 0x804[0] : (0xCB8[2] ? 0xCB8[0] : trsw_lut); trsw_lut = TXON*/
113 /*TRSWB = trsw_forced_BT ? (~0x804[0]) : (0xCB8[2] ? 0xCB8[1] : trswb_lut); trswb_lut = TXON*/
114 /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */
115 /*ODM_SetBBReg(pDM_Odm, 0x804, (BIT1|BIT0), 0x0);*/
116 /* Default setting is in PHY parameters */
117
118 if (channel <= 14) {
119 /* signal source */
120 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774);
121 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774);
122 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57);
123 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57);
124
125 /* inverse or not */
126 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8);
127 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x2);
128 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8);
129 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x2);
130
131 /* antenna switch table */
132 if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) {
133 /* 2TX or 2RX */
134 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf050);
135 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf050);
136 } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) {
137 /* TXA+RXA or TXB+RXB */
138 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf055);
139 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf055);
140 } else {
141 /* TXB+RXA or TXA+RXB */
142 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf550);
143 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf550);
144 }
145
146 } else if (channel > 35) {
147 /* signal source */
148 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547);
149 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547);
150 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75);
151 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75);
152
153 /* inverse or not */
154 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);
155 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0);
156 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);
157 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0);
158
159 /* antenna switch table */
160 if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) {
161 /* 2TX or 2RX */
162 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501);
163 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501);
164 } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) {
165 /* TXA+RXA or TXB+RXB */
166 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500);
167 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500);
168 } else {
169 /* TXB+RXA or TXA+RXB */
170 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005);
171 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005);
172 }
173 } else
174 return FALSE;
175
176
177 } else {
178 if (((pDM_Odm->CutVersion == ODM_CUT_A) || (pDM_Odm->CutVersion == ODM_CUT_B)) && (pDM_Odm->RFEType < 2)) {
179 if (channel <= 14) {
180 /* signal source */
181 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570);
182 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570);
183 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45);
184 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45);
185 } else if (channel > 35) {
186 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517);
187 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517);
188 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45);
189 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45);
190 } else
191 return FALSE;
192
193 /* delay 400ns for PAPE */
194 ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211);
195
196 /* antenna switch table */
197 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555);
198 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555);
199
200 /* inverse or not */
201 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);
202 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0);
203 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);
204 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0);
205
206 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__));
207 } else {
208 if (channel <= 14) {
209 /* signal source */
210 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774);
211 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774);
212 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57);
213 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57);
214 } else if (channel > 35) {
215 /* signal source */
216 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547);
217 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547);
218 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75);
219 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75);
220 } else
221 return FALSE;
222
223 /* inverse or not */
224 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);
225 ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0);
226 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);
227 ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0);
228
229 /* delay 400ns for PAPE */
230 /* ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); */
231
232 /* antenna switch table */
233 if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) {
234 /* 2TX or 2RX */
235 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501);
236 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501);
237 } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) {
238 /* TXA+RXA or TXB+RXB */
239 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500);
240 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500);
241 } else {
242 /* TXB+RXA or TXA+RXB */
243 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005);
244 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005);
245 }
246 }
247 }
248
249 /* chip top mux */
250 ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3);
251 ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0);
252 ODM_SetBBReg(pDM_Odm, 0x40, BIT2, 0x1);
253
254 /* from s0 or s1 */
255 ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30);
256 ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3);
257
258 /* input or output */
259 ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f);
260 ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3);
261
262 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, TxPath 0x%x, RxPath 0x%x)\n", __func__, channel, pDM_Odm->TXAntStatus, pDM_Odm->RXAntStatus));
263
264 return TRUE;
265 }
266
267 VOID
phydm_ccapar_by_rfe_8822b(IN PDM_ODM_T pDM_Odm)268 phydm_ccapar_by_rfe_8822b(
269 IN PDM_ODM_T pDM_Odm
270 )
271 {
272 #if !(DM_ODM_SUPPORT_TYPE == ODM_CE)
273 u4Byte cca_ifem_bcut[12][4] = {
274 /*20M*/
275 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
276 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
277 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
278 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
279 /*40M*/
280 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
281 {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/
282 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
283 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
284 /*80M*/
285 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
286 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
287 {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/
288 {0x00000000, 0x00000000, 0x00000000, 0x00000000} }; /*Reg83C*/
289 u4Byte cca_efem_bcut[12][4] = {
290 /*20M*/
291 {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
292 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
293 {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
294 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
295 /*40M*/
296 {0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/
297 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
298 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
299 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
300 /*80M*/
301 {0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/
302 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
303 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
304 {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/
305 #endif
306
307 u4Byte cca_ifem[12][4], cca_efem[12][4];
308 u1Byte row, col;
309 u4Byte reg82c, reg830, reg838, reg83c;
310
311 if (pDM_Odm->CutVersion == ODM_CUT_A)
312 return;
313 #if !(DM_ODM_SUPPORT_TYPE == ODM_CE)
314 if (pDM_Odm->CutVersion == ODM_CUT_B) {
315 ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_bcut, 48*4);
316 ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_bcut, 48*4);
317 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__));
318 } else
319 #endif
320 {
321 ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_ccut, 48*4);
322 if (pDM_Odm->RFEType == 5) {
323 ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut_RFTType5, 48*4);
324 } else if (pDM_Odm->RFEType == 3) {
325 ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut_RFTType3, 48*4);
326 } else {
327 ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut, 48*4);
328 } ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__));
329 }
330
331 if (bw_8822b == ODM_BW20M)
332 row = 0;
333 else if (bw_8822b == ODM_BW40M)
334 row = 4;
335 else
336 row = 8;
337
338 if (central_ch_8822b <= 14) {
339 if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B))
340 col = 0;
341 else
342 col = 1;
343 } else {
344 if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B))
345 col = 2;
346 else
347 col = 3;
348 }
349
350 if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 4) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) {
351 /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/
352 reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8822b;
353 reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8822b;
354 reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8822b;
355 reg83c = (cca_efem[row + 3][col] != 0)?cca_efem[row + 3][col]:reg83c_8822b;
356 } else if ((pDM_Odm->RFEType == 2)||(pDM_Odm->RFEType == 9)) {
357 /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */
358 if (central_ch_8822b <= 14) {
359 reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8822b;
360 reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8822b;
361 reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8822b;
362 reg83c = (cca_ifem[row + 3][col] != 0)?cca_ifem[row + 3][col]:reg83c_8822b;
363 } else {
364 reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8822b;
365 reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8822b;
366 reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8822b;
367 reg83c = (cca_efem[row + 3][col] != 0)?cca_efem[row + 3][col]:reg83c_8822b;
368 }
369 } else {
370 /*iFEM =>RFE type 0 & RFE type 8*/
371 reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8822b;
372 reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8822b;
373 reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8822b;
374 reg83c = (cca_ifem[row + 3][col] != 0)?cca_ifem[row + 3][col]:reg83c_8822b;
375 }
376
377 ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c);
378 ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830);
379 ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838);
380 ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, reg83c);
381 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n",
382 __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, row, col));
383 }
384
385 VOID
phydm_ccapar_by_bw_8822b(IN PDM_ODM_T pDM_Odm,IN ODM_BW_E bandwidth)386 phydm_ccapar_by_bw_8822b(
387 IN PDM_ODM_T pDM_Odm,
388 IN ODM_BW_E bandwidth
389 )
390 {
391 u4Byte reg82c;
392
393
394 if (pDM_Odm->CutVersion != ODM_CUT_A)
395 return;
396
397 /* A-cut */
398 reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord);
399
400 if (bandwidth == ODM_BW20M) {
401 /* 82c[15:12] = 4 */
402 /* 82c[27:24] = 6 */
403
404 reg82c &= (~(0x0f00f000));
405 reg82c |= ((0x4) << 12);
406 reg82c |= ((0x6) << 24);
407 } else if (bandwidth == ODM_BW40M) {
408 /* 82c[19:16] = 9 */
409 /* 82c[27:24] = 6 */
410
411 reg82c &= (~(0x0f0f0000));
412 reg82c |= ((0x9) << 16);
413 reg82c |= ((0x6) << 24);
414 } else if (bandwidth == ODM_BW80M) {
415 /* 82c[15:12] 7 */
416 /* 82c[19:16] b */
417 /* 82c[23:20] d */
418 /* 82c[27:24] 3 */
419
420 reg82c &= (~(0x0ffff000));
421 reg82c |= ((0xdb7) << 12);
422 reg82c |= ((0x3) << 24);
423 }
424
425 ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c);
426 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByBw_8822b(): Update CCA parameters for Acut\n"));
427
428 }
429
430 VOID
phydm_ccapar_by_rxpath_8822b(IN PDM_ODM_T pDM_Odm)431 phydm_ccapar_by_rxpath_8822b(
432 IN PDM_ODM_T pDM_Odm
433 )
434 {
435
436 if (pDM_Odm->CutVersion != ODM_CUT_A)
437 return;
438
439 if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) {
440 /* 838[7:4] = 8 */
441 /* 838[11:8] = 7 */
442 /* 838[15:12] = 6 */
443 /* 838[19:16] = 7 */
444 /* 838[23:20] = 7 */
445 /* 838[27:24] = 7 */
446 ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678);
447 } else {
448 /* 838[7:4] = 3 */
449 /* 838[11:8] = 3 */
450 /* 838[15:12] = 6 */
451 /* 838[19:16] = 6 */
452 /* 838[23:20] = 7 */
453 /* 838[27:24] = 7 */
454 ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633);
455 }
456 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByRxPath_8822b(): Update CCA parameters for Acut\n"));
457
458 }
459
460 VOID
phydm_rxdfirpar_by_bw_8822b(IN PDM_ODM_T pDM_Odm,IN ODM_BW_E bandwidth)461 phydm_rxdfirpar_by_bw_8822b(
462 IN PDM_ODM_T pDM_Odm,
463 IN ODM_BW_E bandwidth
464 )
465 {
466 if (bandwidth == ODM_BW40M) {
467 /* RX DFIR for BW40 */
468 ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x1);
469 ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x0);
470 ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0);
471 ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0);
472 } else if (bandwidth == ODM_BW80M) {
473 /* RX DFIR for BW80 */
474 ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2);
475 ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1);
476 ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0);
477 ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0);
478 } else {
479 /* RX DFIR for BW20, BW10 and BW5*/
480 ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2);
481 ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2);
482 ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1);
483 ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x1);
484 }
485 }
486
487 BOOLEAN
phydm_write_txagc_1byte_8822b(IN PDM_ODM_T pDM_Odm,IN u4Byte PowerIndex,IN ODM_RF_RADIO_PATH_E Path,IN u1Byte HwRate)488 phydm_write_txagc_1byte_8822b(
489 IN PDM_ODM_T pDM_Odm,
490 IN u4Byte PowerIndex,
491 IN ODM_RF_RADIO_PATH_E Path,
492 IN u1Byte HwRate
493 )
494 {
495 u4Byte offset_txagc[2] = {0x1d00, 0x1d80};
496 u1Byte rate_idx = (HwRate & 0xfc), i;
497 u1Byte rate_offset = (HwRate & 0x3);
498 u4Byte txagc_content = 0x0;
499
500 /* For debug command only!!!! */
501
502 /* Error handling */
503 if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) {
504 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", Path));
505 return FALSE;
506 }
507
508 /* For HW limitation, We can't write TXAGC once a byte. */
509 for (i = 0; i < 4; i++) {
510 if (i != rate_offset)
511 txagc_content = txagc_content|(config_phydm_read_txagc_8822b(pDM_Odm, Path, rate_idx + i) << (i << 3));
512 else
513 txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3));
514 }
515 ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content);
516
517 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n",
518 Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex));
519 return TRUE;
520 }
521
522 VOID
phydm_init_hw_info_by_rfe_type_8822b(IN PDM_ODM_T pDM_Odm)523 phydm_init_hw_info_by_rfe_type_8822b(
524 IN PDM_ODM_T pDM_Odm
525 )
526 {
527 u2Byte mask_path_a = 0x0303;
528 u2Byte mask_path_b = 0x0c0c;
529 /*u2Byte mask_path_c = 0x3030;*/
530 /*u2Byte mask_path_d = 0xc0c0;*/
531
532 pDM_Odm->bInitHwInfoByRfe = FALSE;
533
534 if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) {
535 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G));
536
537 if (pDM_Odm->RFEType == 6) {
538 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b)));
539 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b)));
540 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b)));
541 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b)));
542 } else if (pDM_Odm->RFEType == 7) {
543 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a|mask_path_b)));
544 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a|mask_path_b)));
545 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a|mask_path_b)));
546 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a|mask_path_b)));
547 } else {
548 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b)));
549 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b)));
550 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b)));
551 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));
552 }
553
554 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1);
555
556 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE);
557 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);
558 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE);
559 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE);
560 } else if (pDM_Odm->RFEType == 2) {
561 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA_5G));
562 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b)));
563 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));
564
565 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);
566
567 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);
568 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);
569 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);
570 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE);
571 } else if (pDM_Odm->RFEType == 9) {
572 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G));
573 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));
574
575 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1);
576
577 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);
578 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);
579 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);
580 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);
581 } else if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) {
582 /* RFE type 3: 8822BS\8822BU TFBGA iFEM */
583 /* RFE type 5: 8822BE TFBGA iFEM */
584 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0);
585
586 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);
587
588 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);
589 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE);
590 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);
591 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);
592 } else if (pDM_Odm->RFEType == 4) {
593 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G));
594 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b)));
595 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b)));
596 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b)));
597 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));
598
599 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);
600
601 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE);
602 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);
603 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE);
604 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE);
605 } else if (pDM_Odm->RFEType == 8) {
606 /* RFE Type 8: TFBGA iFEM AP */
607 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0);
608
609 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);
610
611 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);
612 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE);
613 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);
614 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);
615 } else {
616 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0);
617
618 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1);
619
620 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);
621 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE);
622 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);
623 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);
624 }
625
626 pDM_Odm->bInitHwInfoByRfe = TRUE;
627
628 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): RFE type (%d), Board type (0x%x), Package type (%d)\n", pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType));
629 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA));
630 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA));
631 }
632
633 s4Byte
phydm_get_condition_number_8822B(IN PDM_ODM_T pDM_Odm)634 phydm_get_condition_number_8822B(
635 IN PDM_ODM_T pDM_Odm
636 )
637 {
638 s4Byte ret_val;
639
640 ODM_SetBBReg( pDM_Odm, 0x1988, BIT22, 0x1);
641 ret_val = (s4Byte)ODM_GetBBReg(pDM_Odm, 0xf84, (BIT17|BIT16|bMaskLWord));
642
643 if (bw_8822b == 0) {
644 ret_val = ret_val << (8 - 4);
645 ret_val = ret_val / 234;
646 } else if (bw_8822b == 1) {
647 ret_val = ret_val << (7 - 4);
648 ret_val = ret_val / 108;
649 } else if (bw_8822b == 2) {
650 ret_val = ret_val << (6 - 4);
651 ret_val = ret_val / 52;
652 }
653
654 return ret_val;
655 }
656
657
658 /* ======================================================================== */
659
660 /* ======================================================================== */
661 /* These following functions can be used by driver*/
662
663 u4Byte
config_phydm_read_rf_reg_8822b(IN PDM_ODM_T pDM_Odm,IN ODM_RF_RADIO_PATH_E RFPath,IN u4Byte RegAddr,IN u4Byte BitMask)664 config_phydm_read_rf_reg_8822b(
665 IN PDM_ODM_T pDM_Odm,
666 IN ODM_RF_RADIO_PATH_E RFPath,
667 IN u4Byte RegAddr,
668 IN u4Byte BitMask
669 )
670 {
671 u4Byte Readback_Value, Direct_Addr;
672 u4Byte offset_readRF[2] = {0x2800, 0x2c00};
673 u4Byte power_RF[2] = {0x1c, 0xec};
674
675 /* Error handling.*/
676 if (RFPath > ODM_RF_PATH_B) {
677 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", RFPath));
678 return INVALID_RF_DATA;
679 }
680
681 /* Error handling. Check if RF power is enable or not */
682 /* 0xffffffff means RF power is disable */
683 if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) {
684 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): Read fail, RF is disabled\n"));
685 return INVALID_RF_DATA;
686 }
687
688 /* Calculate offset */
689 RegAddr &= 0xff;
690 Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2);
691
692 /* RF register only has 20bits */
693 BitMask &= bRFRegOffsetMask;
694
695 /* Read RF register directly */
696 Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask);
697 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n",
698 RFPath, RegAddr, Readback_Value, BitMask));
699 return Readback_Value;
700 }
701
702 BOOLEAN
config_phydm_write_rf_reg_8822b(IN PDM_ODM_T pDM_Odm,IN ODM_RF_RADIO_PATH_E RFPath,IN u4Byte RegAddr,IN u4Byte BitMask,IN u4Byte Data)703 config_phydm_write_rf_reg_8822b(
704 IN PDM_ODM_T pDM_Odm,
705 IN ODM_RF_RADIO_PATH_E RFPath,
706 IN u4Byte RegAddr,
707 IN u4Byte BitMask,
708 IN u4Byte Data
709 )
710 {
711 u4Byte DataAndAddr = 0, Data_original = 0;
712 u4Byte offset_writeRF[2] = {0xc90, 0xe90};
713 u4Byte power_RF[2] = {0x1c, 0xec};
714 u1Byte BitShift;
715
716 /* Error handling.*/
717 if (RFPath > ODM_RF_PATH_B) {
718 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", RFPath));
719 return FALSE;
720 }
721
722 /* Read RF register content first */
723 RegAddr &= 0xff;
724 BitMask = BitMask & bRFRegOffsetMask;
725
726 if (BitMask != bRFRegOffsetMask) {
727 Data_original = config_phydm_read_rf_reg_8822b(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask);
728
729 /* Error handling. RF is disabled */
730 if (config_phydm_read_rf_check_8822b(Data_original) == FALSE) {
731 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n"));
732 return FALSE;
733 }
734
735 /* check bit mask */
736 if (BitMask != 0xfffff) {
737 for (BitShift = 0; BitShift <= 19; BitShift++) {
738 if (((BitMask >> BitShift) & 0x1) == 1)
739 break;
740 }
741 Data = ((Data_original) & (~BitMask)) | (Data << BitShift);
742 }
743 } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) {
744 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disabled\n"));
745 return FALSE;
746 }
747
748 /* Put write addr in [27:20] and write data in [19:00] */
749 DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff;
750
751 /* Write Operation */
752 ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr);
753 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
754 RFPath, RegAddr, Data, Data_original, BitMask));
755 return TRUE;
756 }
757
758 BOOLEAN
config_phydm_write_txagc_8822b(IN PDM_ODM_T pDM_Odm,IN u4Byte PowerIndex,IN ODM_RF_RADIO_PATH_E Path,IN u1Byte HwRate)759 config_phydm_write_txagc_8822b(
760 IN PDM_ODM_T pDM_Odm,
761 IN u4Byte PowerIndex,
762 IN ODM_RF_RADIO_PATH_E Path,
763 IN u1Byte HwRate
764 )
765 {
766 u4Byte offset_txagc[2] = {0x1d00, 0x1d80};
767 u1Byte rate_idx = (HwRate & 0xfc);
768
769 /* Input need to be HW rate index, not driver rate index!!!! */
770
771 if (pDM_Odm->bDisablePhyApi) {
772 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n"));
773 return TRUE;
774 }
775
776 /* Error handling */
777 if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) {
778 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", Path));
779 return FALSE;
780 }
781
782 /* driver need to construct a 4-byte power index */
783 ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex);
784
785 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n",
786 Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex));
787 return TRUE;
788 }
789
790 u1Byte
config_phydm_read_txagc_8822b(IN PDM_ODM_T pDM_Odm,IN ODM_RF_RADIO_PATH_E Path,IN u1Byte HwRate)791 config_phydm_read_txagc_8822b(
792 IN PDM_ODM_T pDM_Odm,
793 IN ODM_RF_RADIO_PATH_E Path,
794 IN u1Byte HwRate
795 )
796 {
797 u1Byte readBack_data;
798
799 /* Input need to be HW rate index, not driver rate index!!!! */
800
801 /* Error handling */
802 if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) {
803 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", Path));
804 return INVALID_TXAGC_DATA;
805 }
806
807 /* Disable TX AGC report */
808 ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); /* need to check */
809
810 /* Set data rate index (bit0~6) and path index (bit7) */
811 ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7)));
812
813 /* Enable TXAGC report */
814 ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1);
815
816 /* Read TX AGC report */
817 readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000);
818
819 /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */
820 ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0);
821
822 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data));
823 return readBack_data;
824 }
825
826 BOOLEAN
config_phydm_switch_band_8822b(IN PDM_ODM_T pDM_Odm,IN u1Byte central_ch)827 config_phydm_switch_band_8822b(
828 IN PDM_ODM_T pDM_Odm,
829 IN u1Byte central_ch
830 )
831 {
832 u4Byte rf_reg18;
833 BOOLEAN rf_reg_status = TRUE;
834
835 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n"));
836
837 if (pDM_Odm->bDisablePhyApi) {
838 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n"));
839 return TRUE;
840 }
841
842 rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask);
843 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
844
845 if (central_ch <= 14) {
846 /* 2.4G */
847
848 /* Enable CCK block */
849 ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1);
850
851 /* Disable MAC CCK check */
852 ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0);
853
854 /* Disable BB CCK check */
855 ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0);
856
857 /*CCA Mask*/
858 ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/
859
860 /* RF band */
861 rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8)));
862 } else if (central_ch > 35) {
863 /* 5G */
864
865 /* Enable BB CCK check */
866 ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1);
867
868 /* Enable CCK check */
869 ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1);
870
871 /* Disable CCK block */
872 ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0);
873
874 /*CCA Mask*/
875 ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/
876 //ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/
877
878 /* RF band */
879 rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8)));
880 rf_reg18 = (rf_reg18|BIT8|BIT16);
881 } else {
882 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch));
883 return FALSE;
884 }
885
886 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18);
887
888 if (pDM_Odm->RFType > ODM_1T1R)
889 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18);
890
891 if (phydm_rfe_8822b(pDM_Odm, central_ch) == FALSE)
892 return FALSE;
893
894 if (rf_reg_status == FALSE) {
895 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch));
896 return FALSE;
897 }
898
899 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch));
900 return TRUE;
901 }
902
903 BOOLEAN
config_phydm_switch_channel_8822b(IN PDM_ODM_T pDM_Odm,IN u1Byte central_ch)904 config_phydm_switch_channel_8822b(
905 IN PDM_ODM_T pDM_Odm,
906 IN u1Byte central_ch
907 )
908 {
909 pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
910 u4Byte rf_reg18 = 0, rf_regB8 = 0, rf_regBE = 0xff;
911 BOOLEAN rf_reg_status = TRUE;
912 u1Byte low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
913 u1Byte middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7};
914 u1Byte high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
915
916 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n"));
917
918 if (pDM_Odm->bDisablePhyApi) {
919 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n"));
920 return TRUE;
921 }
922
923 central_ch_8822b = central_ch;
924 rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask);
925 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
926 rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0)));
927
928 if (pDM_Odm->CutVersion == ODM_CUT_A) {
929 rf_regB8 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask);
930 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_regB8);
931 }
932
933 /* Switch band and channel */
934 if (central_ch <= 14) {
935 /* 2.4G */
936
937 /* 1. RF band and channel*/
938 rf_reg18 = (rf_reg18|central_ch);
939
940 /* 2. AGC table selection */
941 ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x0);
942 pDM_DigTable->agcTableIdx = 0x0;
943
944 /* 3. Set central frequency for clock offset tracking */
945 ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a);
946
947 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
948 if (pDM_Odm->CutVersion == ODM_CUT_A)
949 rf_regB8 = rf_regB8 | BIT19;
950
951 /* CCK TX filter parameters */
952 if (central_ch == 14) {
953 ODM_SetBBReg(pDM_Odm, 0xa20, bMaskHWord, 0x8488);
954 ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x00006577);
955 ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x0000);
956 } else {
957 ODM_SetBBReg(pDM_Odm, 0xa20, bMaskHWord, (rega20_8822b>>16));
958 ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, rega24_8822b);
959 ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, (rega28_8822b & bMaskLWord));
960 }
961
962 } else if (central_ch > 35) {
963 /* 5G */
964
965 /* 1. RF band and channel*/
966 rf_reg18 = (rf_reg18 | central_ch);
967
968 /* 2. AGC table selection */
969 if ((central_ch >= 36) && (central_ch <= 64)) {
970 ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x1);
971 pDM_DigTable->agcTableIdx = 0x1;
972 } else if ((central_ch >= 100) && (central_ch <= 144)) {
973 ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x2);
974 pDM_DigTable->agcTableIdx = 0x2;
975 } else if (central_ch >= 149) {
976 ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x3);
977 pDM_DigTable->agcTableIdx = 0x3;
978 } else {
979 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch));
980 return FALSE;
981 }
982
983 /* 3. Set central frequency for clock offset tracking */
984 if ((central_ch >= 36) && (central_ch <= 48))
985 ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494);
986 else if ((central_ch >= 52) && (central_ch <= 64))
987 ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453);
988 else if ((central_ch >= 100) && (central_ch <= 116))
989 ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452);
990 else if ((central_ch >= 118) && (central_ch <= 177))
991 ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412);
992 else {
993 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch));
994 return FALSE;
995 }
996
997 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
998 if (pDM_Odm->CutVersion == ODM_CUT_A) {
999 if ((central_ch >= 57) && (central_ch <= 75))
1000 rf_regB8 = rf_regB8 & (~BIT19);
1001 else
1002 rf_regB8 = rf_regB8 | BIT19;
1003 }
1004 } else {
1005 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch));
1006 return FALSE;
1007 }
1008
1009 /* Modify IGI for MP driver to aviod PCIE interference */
1010 if ((pDM_Odm->mp_mode == TRUE) && ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5))) {
1011 if (central_ch == 14)
1012 ODM_Write_DIG(pDM_Odm, 0x26);
1013 else
1014 ODM_Write_DIG(pDM_Odm, 0x20);
1015 }
1016
1017 /* Modify the setting of register 0xBE to reduce phase noise */
1018 if (central_ch <= 14)
1019 rf_regBE = 0x0;
1020 else if ((central_ch >= 36) && (central_ch <= 64))
1021 rf_regBE = low_band[(central_ch - 36)>>1];
1022 else if ((central_ch >= 100) && (central_ch <= 144))
1023 rf_regBE = middle_band[(central_ch - 100)>>1];
1024 else if ((central_ch >= 149) && (central_ch <= 177))
1025 rf_regBE = high_band[(central_ch - 149)>>1];
1026 else
1027 rf_regBE = 0xff;
1028
1029 if (rf_regBE != 0xff)
1030 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xbe, (BIT17|BIT16|BIT15), rf_regBE);
1031 else {
1032 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch));
1033 return FALSE;
1034 }
1035
1036 /* Fix channel 144 issue, ask by RFSI Alvin*/
1037 /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720; 2G don't care*/
1038 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
1039 if (central_ch == 144) {
1040 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x1);
1041 rf_reg18 = (rf_reg18 | BIT17);
1042 } else {
1043 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x0);
1044
1045 if (central_ch > 144)
1046 rf_reg18 = (rf_reg18 | BIT18);
1047 else if (central_ch >= 80)
1048 rf_reg18 = (rf_reg18 | BIT17);
1049 }
1050
1051 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18);
1052
1053 if (pDM_Odm->CutVersion == ODM_CUT_A)
1054 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8);
1055
1056 if (pDM_Odm->RFType > ODM_1T1R) {
1057 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18);
1058
1059 if (pDM_Odm->CutVersion == ODM_CUT_A)
1060 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0xb8, bRFRegOffsetMask, rf_regB8);
1061 }
1062
1063 if (rf_reg_status == FALSE) {
1064 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch));
1065 return FALSE;
1066 }
1067
1068 phydm_ccapar_by_rfe_8822b(pDM_Odm);
1069 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch));
1070 return TRUE;
1071 }
1072
1073 BOOLEAN
config_phydm_switch_bandwidth_8822b(IN PDM_ODM_T pDM_Odm,IN u1Byte primary_ch_idx,IN ODM_BW_E bandwidth)1074 config_phydm_switch_bandwidth_8822b(
1075 IN PDM_ODM_T pDM_Odm,
1076 IN u1Byte primary_ch_idx,
1077 IN ODM_BW_E bandwidth
1078 )
1079 {
1080 u4Byte rf_reg18;
1081 u1Byte IGI;
1082 BOOLEAN rf_reg_status = TRUE;
1083
1084 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n"));
1085
1086 if (pDM_Odm->bDisablePhyApi) {
1087 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n"));
1088 return TRUE;
1089 }
1090
1091 /* Error handling */
1092 if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) {
1093 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx));
1094 return FALSE;
1095 }
1096
1097 bw_8822b = bandwidth;
1098 rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask);
1099 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1100
1101 /* Switch bandwidth */
1102 switch (bandwidth) {
1103 case ODM_BW20M:
1104 {
1105 /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
1106 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M);
1107
1108 /* ADC clock = 160M clock for BW20 */
1109 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0);
1110 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1);
1111
1112 /* DAC clock = 160M clock for BW20 */
1113 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0);
1114 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1);
1115
1116 /* ADC buffer clock */
1117 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1);
1118
1119 /* RF bandwidth */
1120 rf_reg18 = (rf_reg18 | BIT11 | BIT10);
1121
1122 break;
1123 }
1124 case ODM_BW40M:
1125 {
1126 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */
1127 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M));
1128
1129 /* CCK primary channel */
1130 if (primary_ch_idx == 1)
1131 ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx);
1132 else
1133 ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0);
1134
1135 /* ADC clock = 160M clock for BW40 */
1136 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0);
1137 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1);
1138
1139 /* DAC clock = 160M clock for BW20 */
1140 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0);
1141 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1);
1142
1143 /* ADC buffer clock */
1144 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1);
1145
1146 /* RF bandwidth */
1147 rf_reg18 = (rf_reg18 & (~(BIT11|BIT10)));
1148 rf_reg18 = (rf_reg18|BIT11);
1149
1150 break;
1151 }
1152 case ODM_BW80M:
1153 {
1154 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */
1155 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M));
1156
1157 /* ADC clock = 160M clock for BW80 */
1158 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0);
1159 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1);
1160
1161 /* DAC clock = 160M clock for BW20 */
1162 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0);
1163 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1);
1164
1165 /* ADC buffer clock */
1166 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1);
1167
1168 /* RF bandwidth */
1169 rf_reg18 = (rf_reg18 & (~(BIT11|BIT10)));
1170 rf_reg18 = (rf_reg18|BIT10);
1171
1172 break;
1173 }
1174 case ODM_BW5M:
1175 {
1176 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
1177 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M));
1178
1179 /* ADC clock = 40M clock */
1180 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2);
1181 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0);
1182
1183 /* DAC clock = 160M clock for BW20 */
1184 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2);
1185 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0);
1186
1187 /* ADC buffer clock */
1188 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0);
1189 ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1);
1190
1191 /* RF bandwidth */
1192 rf_reg18 = (rf_reg18|BIT11|BIT10);
1193
1194 break;
1195 }
1196 case ODM_BW10M:
1197 {
1198 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
1199 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M));
1200
1201 /* ADC clock = 80M clock */
1202 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3);
1203 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0);
1204
1205 /* DAC clock = 160M clock for BW20 */
1206 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3);
1207 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0);
1208
1209 /* ADC buffer clock */
1210 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0);
1211 ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1);
1212
1213 /* RF bandwidth */
1214 rf_reg18 = (rf_reg18|BIT11|BIT10);
1215
1216 break;
1217 }
1218 default:
1219 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx));
1220 }
1221
1222 /* Write RF register */
1223 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18);
1224
1225 if (pDM_Odm->RFType > ODM_1T1R)
1226 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18);
1227
1228 if (rf_reg_status == FALSE) {
1229 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx));
1230 return FALSE;
1231 }
1232
1233 /* Modify RX DFIR parameters */
1234 phydm_rxdfirpar_by_bw_8822b(pDM_Odm, bandwidth);
1235
1236 /* Modify CCA parameters */
1237 phydm_ccapar_by_bw_8822b(pDM_Odm, bandwidth);
1238 phydm_ccapar_by_rfe_8822b(pDM_Odm);
1239
1240 /* Toggle RX path to avoid RX dead zone issue */
1241 ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0);
1242 ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (pDM_Odm->RXAntStatus|(pDM_Odm->RXAntStatus<<4)));
1243
1244 /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */
1245 IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
1246 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2);
1247 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2);
1248 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI);
1249 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI);
1250
1251 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx));
1252 return TRUE;
1253 }
1254
1255 BOOLEAN
config_phydm_switch_channel_bw_8822b(IN PDM_ODM_T pDM_Odm,IN u1Byte central_ch,IN u1Byte primary_ch_idx,IN ODM_BW_E bandwidth)1256 config_phydm_switch_channel_bw_8822b(
1257 IN PDM_ODM_T pDM_Odm,
1258 IN u1Byte central_ch,
1259 IN u1Byte primary_ch_idx,
1260 IN ODM_BW_E bandwidth
1261 )
1262 {
1263
1264 /* Switch band */
1265 if (config_phydm_switch_band_8822b(pDM_Odm, central_ch) == FALSE)
1266 return FALSE;
1267
1268 /* Switch channel */
1269 if (config_phydm_switch_channel_8822b(pDM_Odm, central_ch) == FALSE)
1270 return FALSE;
1271
1272 /* Switch bandwidth */
1273 if (config_phydm_switch_bandwidth_8822b(pDM_Odm, primary_ch_idx, bandwidth) == FALSE)
1274 return FALSE;
1275
1276 return TRUE;
1277 }
1278
1279 BOOLEAN
config_phydm_trx_mode_8822b(IN PDM_ODM_T pDM_Odm,IN ODM_RF_PATH_E TxPath,IN ODM_RF_PATH_E RxPath,IN BOOLEAN bTx2Path)1280 config_phydm_trx_mode_8822b(
1281 IN PDM_ODM_T pDM_Odm,
1282 IN ODM_RF_PATH_E TxPath,
1283 IN ODM_RF_PATH_E RxPath,
1284 IN BOOLEAN bTx2Path
1285 )
1286 {
1287 BOOLEAN rf_reg_status = TRUE;
1288 u1Byte IGI;
1289 u4Byte rf_reg33 = 0;
1290 u2Byte counter = 0;
1291 //PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1292 //PADAPTER pAdapter = pDM_Odm->Adapter;
1293 //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
1294
1295 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n"));
1296
1297 if (pDM_Odm->bDisablePhyApi) {
1298 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n"));
1299 return TRUE;
1300 }
1301
1302 if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) {
1303 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", TxPath));
1304 return FALSE;
1305 }
1306
1307 if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) {
1308 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", RxPath));
1309 return FALSE;
1310 }
1311
1312 /* RF mode of path-A and path-B */
1313 /* Cannot shut down path-A, beacause synthesizer will be shut down when path-A is in shut down mode */
1314 if ((TxPath|RxPath) & ODM_RF_A)
1315 ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x3231);
1316 else
1317 ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x1111);
1318
1319 if ((TxPath|RxPath) & ODM_RF_B)
1320 ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x3231);
1321 else
1322 ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x1111);
1323
1324 /* Set TX antenna by Nsts */
1325 ODM_SetBBReg(pDM_Odm, 0x93c, (BIT19|BIT18), 0x3);
1326 ODM_SetBBReg(pDM_Odm, 0x80c, (BIT29|BIT28), 0x1);
1327
1328 /* Control CCK TX path by 0xa07[7] */
1329 ODM_SetBBReg(pDM_Odm, 0x80c, BIT30, 0x1);
1330
1331 /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
1332 if (TxPath & ODM_RF_A) {
1333 ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x001);
1334 ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8);
1335 } else if (TxPath & ODM_RF_B) {
1336 ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x002);
1337 ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4);
1338 }
1339
1340 /* TX logic map and TX path en for Nsts = 2*/
1341 if ((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))
1342 ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x01);
1343 else
1344 ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x43);
1345
1346 /* TX path enable */
1347 ODM_SetBBReg(pDM_Odm, 0x80c, bMaskByte0, ((TxPath << 4)|TxPath));
1348
1349 /* Tx2path for 1ss */
1350 if (!((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))) {
1351 if (bTx2Path || pDM_Odm->mp_mode) {
1352 /* 2Tx for OFDM */
1353 ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x043);
1354
1355 /* 2Tx for CCK */
1356 ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc);
1357 }
1358 }
1359
1360 /* Always disable MRC for CCK CCA */
1361 ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0);
1362
1363 /* Always disable MRC for CCK barker */
1364 ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0);
1365
1366 /* CCK RX 1st and 2nd path setting*/
1367 if (RxPath & ODM_RF_A)
1368 ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x0);
1369 else if (RxPath & ODM_RF_B)
1370 ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x5);
1371
1372 /* RX path enable */
1373 ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, ((RxPath << 4)|RxPath));
1374
1375 if ((RxPath == ODM_RF_A) || (RxPath == ODM_RF_B)) {
1376 /* 1R */
1377
1378 /* Disable MRC for CCA */
1379 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); */
1380
1381 /* Disable MRC for barker */
1382 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); */
1383
1384 /* Disable CCK antenna diversity */
1385 /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */
1386
1387 /* Disable Antenna weighting */
1388 ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x0);
1389 ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x0);
1390 ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x0);
1391 } else {
1392 /* 2R */
1393
1394 /* Enable MRC for CCA */
1395 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x1); */
1396
1397 /* Enable MRC for barker */
1398 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x1); */
1399
1400 /* Disable CCK antenna diversity */
1401 /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */
1402
1403 /* Enable Antenna weighting */
1404 ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x1);
1405 ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x1);
1406 ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x1);
1407 }
1408
1409 /* Update TXRX antenna status for PHYDM */
1410 pDM_Odm->TXAntStatus = (TxPath & 0x3);
1411 pDM_Odm->RXAntStatus = (RxPath & 0x3);
1412
1413 /* MP driver need to support path-B TX\RX */
1414
1415 while(1){
1416 counter++;
1417 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000);
1418 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001);
1419
1420 ODM_delay_us(2);
1421 rf_reg33 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask);
1422
1423 if ((rf_reg33 == 0x00001) && (config_phydm_read_rf_check_8822b(rf_reg33)))
1424 break;
1425 else if (counter == 100) {
1426 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting, because writing RF mode table is fail\n"));
1427 return FALSE;
1428 }
1429 }
1430
1431 if ((pDM_Odm->mp_mode) || (*pDM_Odm->pAntennaTest) || (pDM_Odm->Normalrxpath)) {
1432 /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e 0xef 0x00000 suggested by Lucas*/
1433 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000);
1434 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001);
1435 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034);
1436 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080e);
1437 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000);
1438 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode or Antenna test mode!! support path-B TX and RX\n"));
1439 } else {
1440 /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c 0xef 0x00000 */
1441 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000);
1442 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001);
1443 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034);
1444 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080c);
1445 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000);
1446 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n"));
1447 }
1448
1449 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000);
1450
1451 if (rf_reg_status == FALSE) {
1452 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", TxPath, RxPath));
1453 return FALSE;
1454 }
1455
1456 /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */
1457 IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
1458 ODM_Write_DIG(pDM_Odm, IGI - 2);
1459 ODM_Write_DIG(pDM_Odm, IGI);
1460
1461 /* Modify CCA parameters */
1462 phydm_ccapar_by_rxpath_8822b(pDM_Odm);
1463 phydm_ccapar_by_rfe_8822b(pDM_Odm);
1464 phydm_rfe_8822b(pDM_Odm, central_ch_8822b);
1465
1466 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath));
1467 return TRUE;
1468 }
1469
1470 BOOLEAN
config_phydm_parameter_init(IN PDM_ODM_T pDM_Odm,IN ODM_PARAMETER_INIT_E type)1471 config_phydm_parameter_init(
1472 IN PDM_ODM_T pDM_Odm,
1473 IN ODM_PARAMETER_INIT_E type
1474 )
1475 {
1476 if (type == ODM_PRE_SETTING) {
1477 ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0);
1478 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Pre setting: disable OFDM and CCK block\n"));
1479 } else if (type == ODM_POST_SETTING) {
1480 ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3);
1481 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Post setting: enable OFDM and CCK block\n"));
1482 reg82c_8822b = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord);
1483 reg838_8822b = ODM_GetBBReg(pDM_Odm, 0x838, bMaskDWord);
1484 reg830_8822b = ODM_GetBBReg(pDM_Odm, 0x830, bMaskDWord);
1485 reg83c_8822b = ODM_GetBBReg(pDM_Odm, 0x83c, bMaskDWord);
1486 rega20_8822b = ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord);
1487 rega24_8822b = ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord);
1488 rega28_8822b = ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord);
1489 } else {
1490 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Wrong type!!\n"));
1491 return FALSE;
1492 }
1493
1494 return TRUE;
1495 }
1496
1497 /* ======================================================================== */
1498 #endif /* RTL8822B_SUPPORT == 1 */
1499
1500