1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25 #include "mp_precomp.h"
26 #include "../phydm_precomp.h"
27
28 #if (RTL8822B_SUPPORT == 1)
29 #if (PHYDM_FW_API_ENABLE_8822B == 1)
30 /* @======================================================================== */
31 /* @These following functions can be used for PHY DM only*/
32
33 enum channel_width bw_8822b;
34 u8 central_ch_8822b;
35 u8 central_ch_8822b_drp;
36
37 u32 cca_ifem_ccut[3][4] = {
38 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
39 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
40 {0x87765541, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/
41 };
42
43 u32 cca_efem_ccut[3][4] = {
44 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
45 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
46 {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/
47 };
48
49 u32 cca_ifem_ccut_rfe[3][4] = {
50 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
51 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
52 {0x87765541, 0x86666341, 0x87765561, 0x86666361} /*Reg838*/
53 };
54
55 __iram_odm_func__
phydm_igi_toggle_8822b(struct dm_struct * dm)56 void phydm_igi_toggle_8822b(struct dm_struct *dm)
57 {
58 u32 igi = 0x20;
59
60 igi = odm_get_bb_reg(dm, R_0xc50, 0x7f);
61 odm_set_bb_reg(dm, R_0xc50, 0x7f, (igi - 2));
62 odm_set_bb_reg(dm, R_0xc50, 0x7f, igi);
63 odm_set_bb_reg(dm, R_0xe50, 0x7f, (igi - 2));
64 odm_set_bb_reg(dm, R_0xe50, 0x7f, igi);
65 }
66
67 __iram_odm_func__
phydm_8822b_type18_rfe(struct dm_struct * dm,u8 channel)68 void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
69 {
70 if (channel <= 14) {
71 /* signal source */
72 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x745774);
73 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x745774);
74 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
75 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
76 } else if ((channel > 35) && (channel <= 64)) {
77 /* signal source */
78 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
79 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
80 odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7577);
81 odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7577);
82 odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
83 odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
84 } else if (channel > 64) {
85 /* signal source */
86 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
87 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
88 odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7577);
89 odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7577);
90 odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
91 odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
92 }
93
94 /* invertor and antenna switch */
95 if (channel <= 14) {
96 /* inverse or not */
97 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x8);
98 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x2);
99 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x8);
100 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x2);
101
102 /* antenna switch table */
103 if (dm->rx_ant_status == BB_PATH_AB ||
104 dm->tx_ant_status == BB_PATH_AB) {
105 /* 2TX or 2RX */
106 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xf050);
107 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xf050);
108 } else if (dm->rx_ant_status == dm->tx_ant_status) {
109 /* TXA+RXA or TXB+RXB */
110 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xf055);
111 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xf055);
112 } else {
113 /* TXB+RXA or TXA+RXB */
114 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xf550);
115 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xf550);
116 }
117
118 } else if (channel > 35) {
119 /* inverse or not */
120 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
121 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10) | BIT(9)
122 | BIT(8)), 0x0);
123 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
124 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10) | BIT(9)
125 | BIT(8)), 0x0);
126
127 if (channel <= 64)
128 odm_set_bb_reg(dm, 0xcbc, BIT(9), 0x1);
129 else
130 odm_set_bb_reg(dm, 0xcbc, BIT(8), 0x1);
131
132 /* delay 400ns for PAPE */
133 /* odm_set_bb_reg(p_dm, 0x810, MASKBYTE3|BIT20|BIT21*/
134 /* |BIT22|BIT23, 0x211); */
135
136 /* antenna switch table */
137 if (dm->rx_ant_status == BB_PATH_AB ||
138 dm->tx_ant_status == BB_PATH_AB) {
139 /* 2TX or 2RX */
140 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
141 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
142 } else if (dm->rx_ant_status == dm->tx_ant_status) {
143 /* TXA+RXA or TXB+RXB */
144 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
145 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
146 } else {
147 /* TXB+RXA or TXA+RXB */
148 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
149 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
150 }
151 }
152 }
153
154 __iram_odm_func__
phydm_8822b_type15_rfe(struct dm_struct * dm,u8 channel)155 void phydm_8822b_type15_rfe(struct dm_struct *dm, u8 channel)
156 {
157 if (channel <= 14) {
158 /* signal source */
159 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777777);
160 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777777);
161 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x77);
162 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x77);
163
164 } else if ((channel > 35) && (channel <= 64)) {
165 /* signal source */
166 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777747);
167 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777747);
168 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE0, 0x57);
169 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE0, 0x57);
170
171 } else if (channel > 64) {
172 /* signal source */
173 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777747);
174 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777747);
175 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE0, 0x75);
176 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE0, 0x75);
177
178 } else {
179 return;
180 }
181
182 /* @inverse or not */
183 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
184 odm_set_bb_reg(dm, R_0xcbc, BIT(11) | BIT(10) | BIT(9) | BIT(8), 0x0);
185 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
186 odm_set_bb_reg(dm, R_0xebc, BIT(11) | BIT(10) | BIT(9) | BIT(8), 0x0);
187
188 /* @antenna switch table */
189 if (channel <= 14) {
190 if (dm->rx_ant_status == BB_PATH_AB ||
191 dm->tx_ant_status == BB_PATH_AB) {
192 /* @2TX or 2RX */
193 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
194 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
195 } else if (dm->rx_ant_status == dm->tx_ant_status) {
196 /* TXA+RXA or TXB+RXB */
197 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
198 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
199 } else {
200 /* TXB+RXA or TXA+RXB */
201 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
202 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
203 }
204 } else if (channel > 35) {
205 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa5a5);
206 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa5a5);
207 }
208 }
209
210 __iram_odm_func__
phydm_check_bit_mask(u32 bit_mask,u32 data_original,u32 data)211 u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original, u32 data)
212 {
213 u8 bit_shift;
214
215 if (bit_mask != 0xfffff) {
216 for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
217 if (((bit_mask >> bit_shift) & 0x1) == 1)
218 break;
219 }
220 return ((data_original) & (~bit_mask)) | (data << bit_shift);
221 }
222
223 return data;
224 }
225
226 __iram_odm_func__
phydm_rfe_8822b_setting(struct dm_struct * dm,u8 rfe_n,u8 mux_sel,u8 inv_en,u8 source_sel)227 void phydm_rfe_8822b_setting(struct dm_struct *dm, u8 rfe_n, u8 mux_sel,
228 u8 inv_en, u8 source_sel)
229 {
230 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======>\n", __func__);
231 PHYDM_DBG(dm, ODM_PHY_CONFIG,
232 "RFE[%d]:{Path=0x%x}{inv_en=%d}{source=0x%x}\n", rfe_n,
233 mux_sel, inv_en, source_sel);
234
235 if (rfe_n > 11) {
236 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong RFE=%d}\n", rfe_n);
237 return;
238 }
239
240 /*@[Path_mux_sel]*/
241 odm_set_bb_reg(dm, R_0x1990, BIT(rfe_n),
242 ((mux_sel == BB_PATH_A) ? 0 : 1));
243
244 /*@[Inv_en]*/
245 odm_set_bb_reg(dm, R_0xcbc, BIT(rfe_n), (u32)inv_en);
246 odm_set_bb_reg(dm, R_0xebc, BIT(rfe_n), (u32)inv_en);
247
248 /*@[Output Source Signal Selection]*/
249 if (rfe_n <= 7) {
250 odm_set_bb_reg(dm, R_0xcb0, ((0xf) << (rfe_n * 4)),
251 (u32)source_sel);
252 odm_set_bb_reg(dm, R_0xeb0, ((0xf) << (rfe_n * 4)),
253 (u32)source_sel);
254 } else {
255 odm_set_bb_reg(dm, R_0xcb4, ((0xf) << ((rfe_n - 8) * 4)),
256 (u32)source_sel);
257 odm_set_bb_reg(dm, R_0xeb4, ((0xf) << ((rfe_n - 8) * 4)),
258 (u32)source_sel);
259 }
260 }
261
262 __iram_odm_func__
phydm_rfe_8822b_init(struct dm_struct * dm)263 void phydm_rfe_8822b_init(struct dm_struct *dm)
264 {
265 PHYDM_DBG(dm, ODM_PHY_CONFIG, "8822B RFE_Init, RFE_type=((%d))\n",
266 dm->rfe_type);
267
268 /* @chip top mux */
269 odm_set_bb_reg(dm, R_0x64, BIT(29) | BIT(28), 0x3);
270 odm_set_bb_reg(dm, R_0x4c, BIT(26) | BIT(25), 0x0);
271 odm_set_bb_reg(dm, R_0x40, BIT(2), 0x1);
272
273 /* @from s0 or s1 */
274 odm_set_bb_reg(dm, R_0x1990, 0x3f, 0x30);
275 odm_set_bb_reg(dm, R_0x1990, (BIT(11) | BIT(10)), 0x3);
276
277 /* @input or output */
278 odm_set_bb_reg(dm, R_0x974, 0x3f, 0x3f);
279 odm_set_bb_reg(dm, R_0x974, (BIT(11) | BIT(10)), 0x3);
280 }
281
282 __iram_odm_func__
phydm_rfe_4_11(struct dm_struct * dm,u8 channel)283 void phydm_rfe_4_11(struct dm_struct *dm, u8 channel)
284 {
285 boolean is_channel_2g = (channel <= 14) ? true : false;
286
287 /*TRSW=trsw_forced_BT ? 0x804[0]:(0xCB8[2]?0xCB8[0]:trsw_lut);*/
288 /*trsw_lut = TXON*/
289 /*TRSWB = trsw_forced_BT ? (~0x804[0]) :*/
290 /*@(0xCB8[2] ? 0xCB8[1] : trswb_lut); trswb_lut = TXON*/
291 /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */
292 #if 0
293 /*odm_set_bb_reg(dm, R_0x804, (BIT(1)|BIT(0)), 0x0);*/
294 #endif
295 /* @Default setting is in PHY parameters */
296
297 if (is_channel_2g) {
298 /* signal source */
299 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x745774);
300 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x745774);
301 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
302 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
303
304 /* @inverse or not */
305 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x8);
306 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x2);
307 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x8);
308 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x2);
309
310 /* @antenna switch table */
311 if (dm->rx_ant_status == BB_PATH_AB ||
312 dm->tx_ant_status == BB_PATH_AB) {
313 /* @2TX or 2RX */
314 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xf050);
315 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xf050);
316 } else if (dm->rx_ant_status == dm->tx_ant_status) {
317 /* TXA+RXA or TXB+RXB */
318 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xf055);
319 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xf055);
320 } else {
321 /* TXB+RXA or TXA+RXB */
322 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xf550);
323 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xf550);
324 }
325
326 } else {
327 /* signal source */
328 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x477547);
329 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x477547);
330 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x75);
331 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x75);
332
333 /* @inverse or not */
334 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
335 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
336 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
337 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
338
339 /* @antenna switch table */
340 if (dm->rx_ant_status == BB_PATH_AB ||
341 dm->tx_ant_status == BB_PATH_AB) {
342 /* @2TX or 2RX */
343 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
344 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
345 } else if (dm->rx_ant_status == dm->tx_ant_status) {
346 /* TXA+RXA or TXB+RXB */
347 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
348 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
349 } else {
350 /* TXB+RXA or TXA+RXB */
351 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
352 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
353 }
354 }
355 }
356
357 __iram_odm_func__
phydm_rfe_efem(struct dm_struct * dm,u8 channel)358 void phydm_rfe_efem(struct dm_struct *dm, u8 channel)
359 {
360 boolean is_channel_2g = (channel <= 14) ? true : false;
361 u8 rfe_type = dm->rfe_type;
362
363 if (dm->cut_version == ODM_CUT_B && rfe_type < 2) {
364 if (is_channel_2g) {
365 /* signal source */
366 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x704570);
367 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x704570);
368 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45);
369 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45);
370 } else {
371 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x174517);
372 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x174517);
373 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45);
374 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45);
375 }
376
377 /* @delay 400ns for PAPE */
378 odm_set_bb_reg(dm, R_0x810, 0xfff00000, 0x211);
379
380 /* @antenna switch table */
381 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa555);
382 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa555);
383
384 /* @inverse or not */
385 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
386 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
387 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
388 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
389 } else {
390 if (is_channel_2g) {
391 /* signal source */
392 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x705770);
393 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x705770);
394 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
395 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
396 odm_set_bb_reg(dm, R_0xcb8, BIT(4), 0);
397 odm_set_bb_reg(dm, R_0xeb8, BIT(4), 0);
398 } else {
399 /* signal source */
400 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
401 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
402 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x75);
403 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x75);
404 odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
405 odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
406 }
407
408 /* @inverse or not */
409 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
410 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
411 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
412 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
413
414 /* @delay 400ns for PAPE */
415 /* odm_set_bb_reg(dm, R_0x810, MASKBYTE3|BIT20|BIT21|BIT22|*/
416 /*@BIT23, 0x211); */
417
418 /* @antenna switch table */
419 if (dm->rx_ant_status == BB_PATH_AB ||
420 dm->tx_ant_status == BB_PATH_AB) {
421 /* @2TX or 2RX */
422 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
423 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
424 } else if (dm->rx_ant_status == dm->tx_ant_status) {
425 /* TXA+RXA or TXB+RXB */
426 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
427 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
428 } else {
429 /* TXB+RXA or TXA+RXB */
430 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
431 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
432 }
433 }
434 }
435
436 __iram_odm_func__
phydm_rfe_ifem(struct dm_struct * dm,u8 channel)437 void phydm_rfe_ifem(struct dm_struct *dm, u8 channel)
438 {
439 boolean is_channel_2g = (channel <= 14) ? true : false;
440
441 if (is_channel_2g) {
442 /* signal source */
443 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x745774);
444 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x745774);
445 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
446 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
447 } else {
448 /* signal source */
449 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x477547);
450 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x477547);
451 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x75);
452 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x75);
453 }
454
455 /* @inverse or not */
456 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
457 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
458 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
459 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
460
461 /* @antenna switch table */
462 if (is_channel_2g) {
463 if (dm->rx_ant_status == BB_PATH_AB ||
464 dm->tx_ant_status == BB_PATH_AB) {
465 /* @2TX or 2RX */
466 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
467 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
468 } else if (dm->rx_ant_status == dm->tx_ant_status) {
469 /* TXA+RXA or TXB+RXB */
470 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
471 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
472 } else {
473 /* TXB+RXA or TXA+RXB */
474 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
475 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
476 }
477 } else {
478 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa5a5);
479 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa5a5);
480 }
481 }
482
483 __iram_odm_func__
phydm_rfe_2t3r(struct dm_struct * dm,u8 channel)484 void phydm_rfe_2t3r(struct dm_struct *dm, u8 channel)
485 {
486 #if 0
487 /* @[MAC] */
488 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);/* path-A, RFE_CTRL_8 */
489 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);/* path-A, RFE_CTRL_9 */
490 /* @[BB] */
491 odm_set_bb_reg(dm, R_0x970, BIT(9) | BIT(8), 0x3);/* RFE_buffer */
492 odm_set_bb_reg(dm, R_0x1990, BIT(8), 0x0);
493 /* r_rfe_path_sel_ (RFE_CTRL_8) */
494 odm_set_bb_reg(dm, R_0x1990, BIT(9), 0x0);
495 /* r_rfe_path_sel_ (RFE_CTRL_9) */
496 odm_set_bb_reg(dm, R_0xcbc, BIT(19), 0x0);/* RFE_buffer */
497 odm_set_bb_reg(dm, R_0xcbc, BIT(8), 0x0);/* rfe_inv (RFE_CTRL_8) */
498 odm_set_bb_reg(dm, R_0xcbc, BIT(9), 0x1);/* rfe_inv (RFE_CTRL_9) */
499 odm_set_bb_reg(dm, R_0xcb4, 0xF, 0x8);/* path-A, RFE_CTRL_8 */
500 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 0x8);/* path-A, RFE_CTRL_9 */
501 #endif
502 odm_set_mac_reg(dm, R_0x40, BIT(2), 1);
503 odm_set_bb_reg(dm, R_0x970, BIT(5), 1); /* RFE_buffer */
504 odm_set_bb_reg(dm, R_0x970, BIT(10), 1); /* RFE_buffer */
505 odm_set_bb_reg(dm, R_0x1990, BIT(5), 0x0);
506 /*@r_rfe_path_sel_ (RFE_CTRL_5) */
507 odm_set_bb_reg(dm, R_0x1990, BIT(10), 0x0);
508 /*@r_rfe_path_sel_ (RFE_CTRL_10) */
509 odm_set_bb_reg(dm, R_0xcbc, BIT(19), 0x0); /* RFE_buffer */
510 odm_set_bb_reg(dm, R_0xcbc, BIT(5), 0x0); /* rfe_inv (RFE_CTRL_5) */
511 odm_set_bb_reg(dm, R_0xcbc, BIT(10), 0x1); /* rfe_inv (RFE_CTRL_10) */
512 odm_set_bb_reg(dm, R_0xcb0, 0xF00000, 0x8); /* path-A, RFE_CTRL_5 */
513 odm_set_bb_reg(dm, R_0xcb4, 0xF00, 0x8); /* path-A, RFE_CTRL_10 */
514 }
515
516 __iram_odm_func__
phydm_rfe_2t4r(struct dm_struct * dm,u8 channel)517 void phydm_rfe_2t4r(struct dm_struct *dm, u8 channel)
518 {
519 odm_set_mac_reg(dm, R_0x40, BIT(2), 1);
520 odm_set_bb_reg(dm, R_0x970, BIT(5), 1); /* RFE_buffer */
521 odm_set_bb_reg(dm, R_0x970, BIT(10), 1); /* RFE_buffer */
522 odm_set_bb_reg(dm, R_0x1990, BIT(5), 0x0);
523 /*@r_rfe_path_sel_ (RFE_CTRL_5) */
524 odm_set_bb_reg(dm, R_0x1990, BIT(10), 0x1);
525 /*@r_rfe_path_sel_ Path B (RFE_CTRL_10) */
526 odm_set_bb_reg(dm, R_0xcbc, BIT(19), 0x0); /* RFE_buffer */
527 odm_set_bb_reg(dm, R_0xebc, BIT(19), 0x0); /* RFE_buffer */
528 odm_set_bb_reg(dm, R_0xcbc, BIT(5), 0x0); /* rfe_inv (RFE_CTRL_5) */
529 odm_set_bb_reg(dm, R_0xebc, BIT(10), 0x0); /* rfe_inv (RFE_CTRL_10) */
530 odm_set_bb_reg(dm, R_0xcb0, 0xF00000, 0x8); /* path-A, RFE_CTRL_5 */
531 odm_set_bb_reg(dm, R_0xeb4, 0xF00, 0x8); /* path-B, RFE_CTRL_10 */
532 }
533
534 __iram_odm_func__
phydm_rfe_smtant(struct dm_struct * dm,u8 channel)535 void phydm_rfe_smtant(struct dm_struct *dm, u8 channel)
536 {
537 boolean is_channel_2g = (channel <= 14) ? true : false;
538
539 if (is_channel_2g) {
540 #if 0
541 /* signal source */
542 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x705770);
543 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x705770);
544 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
545 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
546 odm_set_bb_reg(dm, R_0xcb8, BIT(4), 0);
547 odm_set_bb_reg(dm, R_0xeb8, BIT(4), 0);
548
549 /* @inverse or not */
550 odm_set_bb_reg(dm, R_0xcbc, 0x3f, 0x0);
551 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
552 odm_set_bb_reg(dm, R_0xebc, 0x3f, 0x0);
553 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
554 #endif
555 } else {
556 /* signal source */
557 #if 1
558 /*path A*/
559 odm_set_bb_reg(dm, R_0x1990, BIT(3), 0); /*RFE_CTRL_3*/ /*A_0*/
560 odm_set_bb_reg(dm, R_0x1990, BIT(0), 0); /*RFE_CTRL_0*/ /*A_1*/
561 odm_set_bb_reg(dm, R_0x1990, BIT(8), 0); /*RFE_CTRL_8*/ /*A_2*/
562
563 /*path B*/
564 odm_set_bb_reg(dm, R_0x1990, BIT(4), 1); /*RFE_CTRL_4*/ /*B_0*/
565 odm_set_bb_reg(dm, R_0x1990, BIT(11), 1); /*RFE_CTRL_11*//*B_1*/
566 odm_set_bb_reg(dm, R_0x1990, BIT(9), 1); /*RFE_CTRL_9*/ /*B_2*/
567
568 odm_set_bb_reg(dm, R_0xcb0, MASKDWORD, 0x77178519);
569 #if 0
570 /* odm_set_bb_reg(dm, R_0xeb0, MASKDWORD, 0x77177517); */
571 #endif
572 odm_set_bb_reg(dm, R_0xeb0, MASKDWORD, 0x771c7517);
573 odm_set_bb_reg(dm, R_0xcb4, MASKDWORD, 0x757a);
574 #if 0
575 /* odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x7577); */
576 #endif
577 odm_set_bb_reg(dm, R_0xeb4, MASKDWORD, 0xd5e7);
578
579 /* @inverse or not */
580 odm_set_bb_reg(dm, R_0xcbc, 0xfff, 0x0);
581 odm_set_bb_reg(dm, R_0xebc, 0xfff, 0x0);
582 #else
583 phydm_rfe_8822b_setting(dm, 1, BB_PATH_A, 0, PAPE_5G);
584 phydm_rfe_8822b_setting(dm, 2, BB_PATH_A, 0, TRSW_B);
585 phydm_rfe_8822b_setting(dm, 5, BB_PATH_B, 0, PAPE_5G);
586 phydm_rfe_8822b_setting(dm, 10, BB_PATH_B, 0, TRSW_B);
587 #endif
588
589 odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
590 odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
591 }
592
593 /* @delay 400ns for PAPE */
594 /* @odm_set_bb_reg(dm, R_0x810, MASKBYTE3|BIT20|BIT21|BIT22|*/
595 /* @BIT23, 0x211); */
596
597 /* @antenna switch table */
598 if (dm->rx_ant_status == BB_PATH_AB ||
599 dm->tx_ant_status == BB_PATH_AB) {
600 /* @2TX or 2RX */
601 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
602 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
603 } else if (dm->rx_ant_status == dm->tx_ant_status) {
604 /* TXA+RXA or TXB+RXB */
605 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
606 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
607 } else {
608 /* TXB+RXA or TXA+RXB */
609 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
610 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
611 }
612 }
613
614 __iram_odm_func__
615 boolean
phydm_rfe_8822b(struct dm_struct * dm,u8 channel)616 phydm_rfe_8822b(struct dm_struct *dm, u8 channel)
617 {
618 boolean is_channel_2g = (channel <= 14) ? true : false;
619 u8 rfe_type = dm->rfe_type;
620
621 PHYDM_DBG(dm, ODM_PHY_CONFIG,
622 "[8822B] Update RFE PINs: CH:%d, T/RX_path:{ 0x%x, 0x%x}, cut_ver:%d, rfe_type:%d\n",
623 channel, dm->tx_ant_status, dm->rx_ant_status,
624 dm->cut_version, rfe_type);
625
626 if ((channel > 14 && channel < 36) || channel == 0)
627 return false;
628
629 /* @Distinguish the setting band */
630 dm->rfe_hwsetting_band = (is_channel_2g) ? 1 : 2;
631
632 /* @HW Setting for each RFE type */
633 if (rfe_type == 4 || rfe_type == 11)
634 phydm_rfe_4_11(dm, channel);
635 else if ((rfe_type == 1) || (rfe_type == 2) || (rfe_type == 6) ||
636 (rfe_type == 7) || (rfe_type == 9))
637 /* @eFem */
638 phydm_rfe_efem(dm, channel);
639 else if ((rfe_type == 0) || (rfe_type == 3) || (rfe_type == 5) ||
640 (rfe_type == 8) || (rfe_type == 10) || (rfe_type == 12) ||
641 (rfe_type == 13) || (rfe_type == 14) || (rfe_type == 16) ||
642 (rfe_type == 17) || (rfe_type == 19))
643 /* @iFEM */
644 phydm_rfe_ifem(dm, channel);
645 else if (rfe_type == 15)
646 /* @iFEM for Microsoft, 5G low/high band at S0 */
647 phydm_8822b_type15_rfe(dm, channel);
648 else if (rfe_type == 18)
649 /* @eFEM for Roku, 5G low/high band at S0/S1 */
650 phydm_8822b_type18_rfe(dm, channel);
651
652 #if (defined(CONFIG_2T3R_ANTENNA))
653 else if (rfe_type == ANT_2T3R_RFE_TYPE)
654 phydm_rfe_2t3r(dm, channel);
655
656 #endif
657 #if (defined(CONFIG_2T4R_ANTENNA))
658 else if (rfe_type == ANT_2T4R_RFE_TYPE)
659 phydm_rfe_2t4r(dm, channel);
660
661 #endif
662 #if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
663 else if (rfe_type == SMTANT_TMP_RFE_TYPE) {
664 /*@modify from RFE_TYPE = 1*/
665 phydm_rfe_smtant(dm, channel);
666 }
667 #endif
668 return true;
669 }
670
671 __iram_odm_func__
672 boolean
phydm_rfe_8822b_lps(struct dm_struct * dm,boolean enable_sw_rfe)673 phydm_rfe_8822b_lps(struct dm_struct *dm, boolean enable_sw_rfe)
674 {
675 u8 rfe_type = dm->rfe_type;
676 u32 rf_reg18_ch = 0;
677
678 rf_reg18_ch = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18, 0xff);
679
680 /* @HW Setting for each RFE type */
681 if (rfe_type == 4) {
682 if (rf_reg18_ch <= 14) {
683 /* signal source */
684 if (!enable_sw_rfe) {
685 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x745774);
686 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x745774);
687 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
688 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
689 } else {
690 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777777);
691 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777777);
692 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x77);
693 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x77);
694 }
695 } else if (rf_reg18_ch > 35) {
696 /* signal source */
697 if (!enable_sw_rfe) {
698 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x477547);
699 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x477547);
700 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x75);
701 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x75);
702 } else {
703 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777777);
704 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777777);
705 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x77);
706 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x77);
707 }
708 } else {
709 return false;
710 }
711 } else if ((rfe_type == 1) || (rfe_type == 2) ||
712 (rfe_type == 6) || (rfe_type == 7) ||
713 (rfe_type == 9) || (rfe_type == 11)) {
714 /* @eFem */
715 if (rf_reg18_ch <= 14) {
716 /* signal source */
717 if (!enable_sw_rfe) {
718 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x705770);
719 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x705770);
720 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x57);
721 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x57);
722 } else {
723 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777777);
724 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777777);
725 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x77);
726 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x77);
727 }
728 } else if (rf_reg18_ch > 35) {
729 /* signal source */
730 if (!enable_sw_rfe) {
731 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
732 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
733 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x75);
734 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x75);
735 } else {
736 odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x777777);
737 odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x777777);
738 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x77);
739 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x77);
740 }
741 } else {
742 return false;
743 }
744 } else {
745 return true;
746 }
747 return true;
748 }
749
750 __iram_odm_func__
phydm_is_dfs_channel(u8 channel_num)751 u8 phydm_is_dfs_channel(u8 channel_num)
752 {
753 if (channel_num >= 52 && channel_num <= 140)
754 return 1;
755 else
756 return 0;
757 }
758
759 __iram_odm_func__
phydm_ccapar_by_rfe_8822b(struct dm_struct * dm)760 void phydm_ccapar_by_rfe_8822b(struct dm_struct *dm)
761 {
762 u32 cca_ifem[3][4], cca_efem[3][4];
763 u8 col;
764 u32 reg82c, reg830, reg838;
765 boolean is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false;
766 u8 bw_40 = CHANNEL_WIDTH_40;
767
768 odm_move_memory(dm, cca_efem, cca_efem_ccut, 12 * 4);
769 if (dm->rfe_type == 3 || dm->rfe_type == 5 ||
770 dm->rfe_type == 12 || dm->rfe_type == 15 ||
771 dm->rfe_type == 16 || dm->rfe_type == 17 ||
772 dm->rfe_type == 19) {
773 odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfe, 12 * 4);
774 is_rfe_type = true;
775 } else {
776 odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 12 * 4);
777 }
778 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Update CCA para for Ccut\n");
779
780 if (central_ch_8822b <= 14) {
781 if (dm->rx_ant_status == BB_PATH_A ||
782 dm->rx_ant_status == BB_PATH_B)
783 col = 0; /*@1R 2G*/
784 else
785 col = 1; /*@2R 2G*/
786 } else {
787 if (dm->rx_ant_status == BB_PATH_A ||
788 dm->rx_ant_status == BB_PATH_B)
789 col = 2; /*@1R 5G*/
790 else
791 col = 3; /*@2R 5G*/
792 }
793
794 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 6 ||
795 dm->rfe_type == 7 || dm->rfe_type == 11) {
796 /* @eFEM */
797 reg82c = cca_efem[0][col]; reg830 = cca_efem[1][col];
798 reg838 = cca_efem[2][col]; is_efem_cca = true;
799 } else if ((dm->rfe_type == 2) || (dm->rfe_type == 9)) {
800 /*@5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */
801 if (central_ch_8822b <= 14) {
802 reg82c = cca_ifem[0][col]; reg830 = cca_ifem[1][col];
803 reg838 = cca_ifem[2][col];
804 is_ifem_cca = true;
805 } else {
806 reg82c = cca_efem[0][col]; reg830 = cca_efem[1][col];
807 reg838 = cca_efem[2][col]; is_efem_cca = true;
808 }
809 } else {
810 /* @iFEM */
811 reg82c = cca_ifem[0][col]; reg830 = cca_ifem[1][col];
812 reg838 = cca_ifem[2][col]; is_ifem_cca = true;
813 }
814 odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c);
815
816 if (is_ifem_cca) {
817 if ((dm->cut_version == ODM_CUT_B && (col == 1 || col == 3) &&
818 bw_8822b == bw_40) ||
819 (!is_rfe_type && col == 3 && bw_8822b == bw_40) ||
820 (dm->rfe_type == 5 && col == 3))
821 odm_set_bb_reg(dm, R_0x830, MASKDWORD, 0x79a0ea28);
822 else
823 odm_set_bb_reg(dm, R_0x830, MASKDWORD, reg830);
824 } else {
825 odm_set_bb_reg(dm, R_0x830, MASKDWORD, reg830);
826 }
827 odm_set_bb_reg(dm, R_0x838, MASKDWORD, reg838);
828
829 if (is_efem_cca && !(dm->cut_version == ODM_CUT_B))
830 odm_set_bb_reg(dm, R_0x83c, MASKDWORD, 0x9194b2b9);
831 /* @enlarge big jump size in type 16 for MS case */
832 if (dm->rfe_type == 16 && central_ch_8822b <= 14)
833 odm_set_bb_reg(dm, R_0x8c8, BIT(3) | BIT(2) | BIT(1), 0x3);
834 /* @CCA parameters adjust for 20MHz on DFS channel */
835 if ((*dm->band_width == CHANNEL_WIDTH_20) &&
836 (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
837 ((*dm->channel >= 100) && (*dm->channel <= 144))))
838 odm_set_bb_reg(dm, 0x838, 0xf0, 0x4);
839 PHYDM_DBG(dm, ODM_PHY_CONFIG, "(Pkt%d, Intf%d, RFE%d), col=%d\n",
840 dm->package_type, dm->support_interface, dm->rfe_type, col);
841 }
842
843 __iram_odm_func__
phydm_rxdfirpar_by_bw_8822b(struct dm_struct * dm,enum channel_width bandwidth)844 void phydm_rxdfirpar_by_bw_8822b(struct dm_struct *dm,
845 enum channel_width bandwidth)
846 {
847 if (bandwidth == CHANNEL_WIDTH_40) {
848 /* RX DFIR for BW40 */
849 odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x1);
850 odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x0);
851 odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0);
852 odm_set_bb_reg(dm, R_0xe20, BIT(31), 0x0);
853 } else if (bandwidth == CHANNEL_WIDTH_80) {
854 /* RX DFIR for BW80 */
855 odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
856 odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x1);
857 odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0);
858 odm_set_bb_reg(dm, R_0xe20, BIT(31), 0x0);
859 } else {
860 /* RX DFIR for BW20, BW10 and BW5*/
861 odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
862 odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2);
863 odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x1);
864 odm_set_bb_reg(dm, R_0xe20, BIT(31), 0x1);
865 }
866 #if 0
867 /* PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_rxdfirpar_by_bw_8822b\n");*/
868 #endif
869 }
870
871 __iram_odm_func__
872 boolean
phydm_write_txagc_1byte_8822b(struct dm_struct * dm,u32 pw_idx,enum rf_path path,u8 hw_rate)873 phydm_write_txagc_1byte_8822b(struct dm_struct *dm,
874 u32 pw_idx, enum rf_path path, u8 hw_rate)
875 {
876 #if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1)
877 u32 offset_txagc[2] = {0x1d00, 0x1d80};
878 u8 rate_idx = (hw_rate & 0xfc), i;
879 u8 rate_offset = (hw_rate & 0x3);
880 u8 ret = 0;
881 u32 txagc_idx = 0x0;
882
883 /* @For debug command only!!!! */
884
885 /* @Error handling */
886 if (path > RF_PATH_B || hw_rate > 0x53) {
887 PHYDM_DBG(dm, ODM_PHY_CONFIG, "unsupported path (%d)\n", path);
888 return false;
889 }
890
891 /* @For HW limitation, We can't write TXAGC once a byte. */
892 for (i = 0; i < 4; i++) {
893 if (i != rate_offset) {
894 ret = config_phydm_read_txagc_8822b(dm, path,
895 rate_idx + i);
896 txagc_idx = txagc_idx | (ret << (i << 3));
897 } else {
898 txagc_idx = txagc_idx | ((pw_idx & 0x3f) << (i << 3));
899 }
900 }
901 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
902 txagc_idx);
903
904 PHYDM_DBG(dm, ODM_PHY_CONFIG, "path-%d rate_idx 0x%x (0x%x) = 0x%x\n",
905 path, hw_rate, (offset_txagc[path] + hw_rate), pw_idx);
906 return true;
907 #else
908 return false;
909 #endif
910 }
911
912 __iram_odm_func__
phydm_get_condi_num_acc_8822b(void * dm_void)913 void phydm_get_condi_num_acc_8822b(void *dm_void)
914 {
915 #if (PHYDM_FW_API_FUNC_ENABLE_8822B)
916 struct dm_struct *dm = (struct dm_struct *)dm_void;
917 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
918 u8 i = 0;
919
920 for (i = 0; i < CN_CNT_MAX; i++) {
921 odm_set_bb_reg(dm, R_0x1988, 0x3fff00, (i << 4));
922 dbg->condi_num_cdf[i] = odm_read_1byte(dm, R_0xf87);
923 }
924
925 #if 0
926 /*@disable report condition number*/
927 /*odm_set_bb_reg(dm, R_0x1988, BIT(22), 0x0);*/
928 #endif
929 #endif
930 }
931
932 __iram_odm_func__
phydm_get_condi_num_8822b(struct dm_struct * dm)933 u32 phydm_get_condi_num_8822b(struct dm_struct *dm)
934 {
935 u32 val = 0;
936 u32 condi_num_avg_fine = 0;
937
938 odm_set_bb_reg(dm, R_0x1988, BIT(22), 0x1);
939
940 /*@get condi_num_avg U(18,4)*/
941 val = odm_get_bb_reg(dm, R_0xf84, (BIT(17) | BIT(16) | MASKLWORD));
942
943 if (bw_8822b == CHANNEL_WIDTH_80) {
944 /*@CN_avg_fine = val*(256/234) ~= val*1.0941 ~= val*(1+2^-4+2^-5)*/
945 condi_num_avg_fine = val + (val >> 4) + (val >> 5);
946
947 } else if (bw_8822b == CHANNEL_WIDTH_40) {
948 /*@CN_avg_fine = val*(128/108) ~= val*1.185 ~= val*(1+2^-3)*/
949 condi_num_avg_fine = val + (val >> 3);
950 } else if (bw_8822b == CHANNEL_WIDTH_20) {
951 /*@CN_avg_fine = val*(64/52) ~= val*1.23 ~= val*(1+2^-3)*/
952 condi_num_avg_fine = val + (val >> 3);
953 }
954
955 return condi_num_avg_fine;/*U(18,4)*/
956 }
957
958 /* @======================================================================== */
959
960 /* @======================================================================== */
961 /* @These following functions can be used by driver*/
962
963 __iram_odm_func__
config_phydm_read_rf_reg_8822b(struct dm_struct * dm,enum rf_path path,u32 reg_addr,u32 bit_mask)964 u32 config_phydm_read_rf_reg_8822b(struct dm_struct *dm,
965 enum rf_path path, u32 reg_addr,
966 u32 bit_mask)
967 {
968 u32 readback_value, direct_addr;
969 u32 offset_read_rf[2] = {0x2800, 0x2c00};
970
971 /* @Error handling.*/
972 if (path > RF_PATH_B) {
973 PHYDM_DBG(dm, ODM_PHY_CONFIG, "unsupported path (%d)\n", path);
974 return INVALID_RF_DATA;
975 }
976
977 /* @Calculate offset */
978 reg_addr &= 0xff;
979 direct_addr = offset_read_rf[path] + (reg_addr << 2);
980
981 /* RF register only has 20bits */
982 bit_mask &= RFREGOFFSETMASK;
983
984 /* Read RF register directly */
985 readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
986 PHYDM_DBG(dm, ODM_PHY_CONFIG, "RF-%d 0x%x = 0x%x, bit mask = 0x%x\n",
987 path, reg_addr, readback_value, bit_mask);
988 return readback_value;
989 }
990
991 __iram_odm_func__
992 boolean
config_phydm_write_rf_reg_8822b(struct dm_struct * dm,enum rf_path path,u32 reg_addr,u32 bit_mask,u32 data)993 config_phydm_write_rf_reg_8822b(struct dm_struct *dm,
994 enum rf_path path, u32 reg_addr, u32 bit_mask,
995 u32 data)
996 {
997 u32 data_and_addr = 0, data_original = 0, ret = 0;
998 u32 offset_write_rf[2] = {0xc90, 0xe90};
999
1000 /* @Error handling.*/
1001 if (path > RF_PATH_B) {
1002 PHYDM_DBG(dm, ODM_PHY_CONFIG, "unsupported path (%d)\n", path);
1003 return false;
1004 }
1005
1006 /* Read RF register content first */
1007 reg_addr &= 0xff;
1008 bit_mask = bit_mask & RFREGOFFSETMASK;
1009
1010 if (bit_mask != RFREGOFFSETMASK) {
1011 ret = config_phydm_read_rf_reg_8822b(dm, path, reg_addr,
1012 RFREGOFFSETMASK);
1013 data_original = ret;
1014
1015 /* @Error handling. RF is disabled */
1016 if (config_phydm_read_rf_check_8822b(data_original) == false) {
1017 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1018 "Write fail, RF is disable\n");
1019 return false;
1020 }
1021
1022 /* @check bit mask */
1023 data = phydm_check_bit_mask(bit_mask, data_original, data);
1024 }
1025
1026 /* Put write addr in [27:20] and write data in [19:00] */
1027 data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
1028
1029 /* Write operation */
1030 odm_set_bb_reg(dm, offset_write_rf[path], MASKDWORD, data_and_addr);
1031 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1032 "RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", path,
1033 reg_addr, data, data_original, bit_mask);
1034
1035 #if (defined(CONFIG_RUN_IN_DRV))
1036 if (dm->support_interface == ODM_ITRF_PCIE)
1037 ODM_delay_us(13);
1038 #elif (defined(CONFIG_RUN_IN_FW))
1039 ODM_delay_us(13);
1040 #endif
1041
1042 return true;
1043 }
1044
1045 __iram_odm_func__
1046 boolean
config_phydm_write_txagc_8822b(struct dm_struct * dm,u32 pw_idx,enum rf_path path,u8 hw_rate)1047 config_phydm_write_txagc_8822b(struct dm_struct *dm,
1048 u32 pw_idx, enum rf_path path, u8 hw_rate)
1049 {
1050 u32 offset_txagc[2] = {0x1d00, 0x1d80};
1051 u8 rate_idx = (hw_rate & 0xfc);
1052
1053 /* @Input need to be HW rate index, not driver rate index!!!! */
1054
1055 if (dm->is_disable_phy_api) {
1056 PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API for dbg\n");
1057 return true;
1058 }
1059
1060 /* @Error handling */
1061 if (path > RF_PATH_B || hw_rate > 0x53) {
1062 PHYDM_DBG(dm, ODM_PHY_CONFIG, "unsupported path (%d)\n", path);
1063 return false;
1064 }
1065
1066 /* @driver need to construct a 4-byte power index */
1067 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, pw_idx);
1068
1069 PHYDM_DBG(dm, ODM_PHY_CONFIG, "path-%d rate_idx 0x%x (0x%x) = 0x%x\n",
1070 path, hw_rate, (offset_txagc[path] + hw_rate), pw_idx);
1071 return true;
1072 }
1073
1074 __iram_odm_func__
config_phydm_read_txagc_8822b(struct dm_struct * dm,enum rf_path path,u8 hw_rate)1075 u8 config_phydm_read_txagc_8822b(struct dm_struct *dm,
1076 enum rf_path path, u8 hw_rate)
1077 {
1078 #if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1)
1079 u8 read_back_data;
1080
1081 /* @Input need to be HW rate index, not driver rate index!!!! */
1082
1083 /* @Error handling */
1084 if (path > RF_PATH_B || hw_rate > 0x53) {
1085 PHYDM_DBG(dm, ODM_PHY_CONFIG, "unsupported path (%d)\n", path);
1086 return INVALID_TXAGC_DATA;
1087 }
1088
1089 /* @Disable TX AGC report */
1090 odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0); /* need to check */
1091
1092 /* Set data rate index (bit0~6) and path index (bit7) */
1093 odm_set_bb_reg(dm, R_0x1998, MASKBYTE0, (hw_rate | (path << 7)));
1094
1095 /* @Enable TXAGC report */
1096 odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x1);
1097
1098 /* Read TX AGC report */
1099 read_back_data = (u8)odm_get_bb_reg(dm, R_0xd30, 0x7f0000);
1100
1101 /* @Driver have to disable TXAGC report after reading TXAGC */
1102 /* @(ref. user guide v11) */
1103 odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0);
1104
1105 PHYDM_DBG(dm, ODM_PHY_CONFIG, "path-%d rate index 0x%x = 0x%x\n", path,
1106 hw_rate, read_back_data);
1107 return read_back_data;
1108 #else
1109 return 0;
1110 #endif
1111 }
1112
1113 __iram_odm_func__
phydm_dsde_init(struct dm_struct * dm)1114 void phydm_dsde_init(struct dm_struct *dm)
1115 {
1116 /* Reset NBI/CSI everytime after changing channel/BW/band */
1117 odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
1118 odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
1119 odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
1120 odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
1121 odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
1122 odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
1123 odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
1124 odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
1125 odm_set_bb_reg(dm, R_0x874, BIT(0), 0x0);
1126 }
1127
1128 __iram_odm_func__
phydm_dsde_ch_idx(struct dm_struct * dm)1129 u8 phydm_dsde_ch_idx(struct dm_struct *dm)
1130 {
1131 u8 idx = 0;
1132
1133 /* @2G Channel Setting > 20M: 5, 6, 7, 8, 13; 40M: 3~11 */
1134 if ((*dm->channel >= 1) && (*dm->channel <= 14)) {
1135 if (*dm->band_width == CHANNEL_WIDTH_20) {
1136 if (*dm->channel >= 5 && *dm->channel <= 8)
1137 idx = *dm->channel - 5;
1138 else if (*dm->channel == 13)
1139 idx = 4;
1140 else
1141 idx = 16;
1142 } else {
1143 if (*dm->channel >= 3 && *dm->channel <= 11)
1144 idx = *dm->channel + 2;
1145 else
1146 idx = 16;
1147 }
1148 } else {
1149 /* @5G Channel Setting > 20M: 153, 161; */
1150 /* @40M: 54, 118, 151, 159 */
1151 /* @80M: 58, 122, 155, 155 */
1152 switch (*dm->channel) {
1153 case 153:
1154 idx = 0;
1155 break;
1156 case 161:
1157 idx = 1;
1158 break;
1159 case 54:
1160 idx = 2;
1161 break;
1162 case 118:
1163 idx = 3;
1164 break;
1165 case 151:
1166 idx = 4;
1167 break;
1168 case 159:
1169 idx = 5;
1170 break;
1171 case 58:
1172 idx = 6;
1173 break;
1174 case 122:
1175 idx = 7;
1176 break;
1177 case 155:
1178 idx = 8;
1179 break;
1180 default:
1181 idx = 16;
1182 break;
1183 }
1184 }
1185 return idx;
1186 }
1187
1188 __iram_odm_func__
phydm_dsde_nbi(struct dm_struct * dm)1189 void phydm_dsde_nbi(struct dm_struct *dm)
1190 {
1191 #if (PHYDM_FW_API_FUNC_ENABLE_8822B)
1192 u8 set_nbi = PHYDM_SET_NO_NEED;
1193
1194 /* Modify CCA parameters due to NBI */
1195 if (dm->rfe_type == 15 || dm->rfe_type == 16)
1196 odm_set_bb_reg(dm, 0x82c, 0xff000, 0x86);
1197 else
1198 odm_set_bb_reg(dm, 0x82c, 0xff000, 0x97);
1199 if (dm->rfe_type == 12 || dm->rfe_type == 19) {
1200 if (*dm->band_width == CHANNEL_WIDTH_20) {
1201 if (*dm->channel >= 5 && *dm->channel <= 7)
1202 odm_set_bb_reg(dm, 0x82c, 0xf000, 0x3);
1203 }
1204 } else {
1205 odm_set_bb_reg(dm, 0x82c, 0xf000, 0x7);
1206 }
1207 if (*dm->band_width == CHANNEL_WIDTH_20) {
1208 if (*dm->channel == 153)
1209 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1210 *dm->channel, 20, 5760,
1211 PHYDM_DONT_CARE);
1212 else if (*dm->channel == 161)
1213 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1214 *dm->channel, 20, 5800,
1215 PHYDM_DONT_CARE);
1216 else if (*dm->channel >= 5 && *dm->channel <= 8)
1217 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1218 *dm->channel, 20, 2440,
1219 PHYDM_DONT_CARE);
1220 else if (*dm->channel == 13)
1221 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1222 *dm->channel, 20, 2480,
1223 PHYDM_DONT_CARE);
1224 else
1225 set_nbi = PHYDM_SET_NO_NEED;
1226 } else if (*dm->band_width == CHANNEL_WIDTH_40) {
1227 if (*dm->channel == 54) {
1228 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1229 *dm->channel, 40, 5280,
1230 PHYDM_DONT_CARE);
1231 } else if (*dm->channel == 118) {
1232 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1233 *dm->channel, 40, 5600,
1234 PHYDM_DONT_CARE);
1235 } else if (*dm->channel == 151) {
1236 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1237 *dm->channel, 40, 5760,
1238 PHYDM_DONT_CARE);
1239 } else if (*dm->channel == 159) {
1240 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1241 *dm->channel, 40, 5800,
1242 PHYDM_DONT_CARE);
1243 /* @2.4G */
1244 } else if ((*dm->channel >= 4) && (*dm->channel <= 6)) {
1245 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1246 *dm->channel, 40, 2440,
1247 PHYDM_DONT_CARE);
1248 } else if (*dm->channel == 11) {
1249 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1250 *dm->channel, 40, 2480,
1251 PHYDM_DONT_CARE);
1252 } else {
1253 set_nbi = PHYDM_SET_NO_NEED;
1254 }
1255 } else if (*dm->band_width == CHANNEL_WIDTH_80) {
1256 if (*dm->channel == 58)
1257 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1258 *dm->channel, 80, 5280,
1259 PHYDM_DONT_CARE);
1260 else if (*dm->channel == 122)
1261 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1262 *dm->channel, 80, 5600,
1263 PHYDM_DONT_CARE);
1264 else if (*dm->channel == 155)
1265 set_nbi = phydm_nbi_setting(dm, FUNC_ENABLE,
1266 *dm->channel, 80, 5760,
1267 PHYDM_DONT_CARE);
1268 else
1269 set_nbi = PHYDM_SET_NO_NEED;
1270 } else {
1271 set_nbi = PHYDM_SET_NO_NEED;
1272 }
1273 #endif
1274 }
1275
1276 __iram_odm_func__
phydm_dsde_csi(struct dm_struct * dm)1277 void phydm_dsde_csi(struct dm_struct *dm)
1278 {
1279 #if (PHYDM_FW_API_FUNC_ENABLE_8822B)
1280 u8 set_result_csi = PHYDM_SET_NO_NEED;
1281
1282 if (*dm->band_width == CHANNEL_WIDTH_20) {
1283 if (*dm->channel == 153)
1284 set_result_csi =
1285 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1286 20, 5760, PHYDM_DONT_CARE);
1287 else if (*dm->channel == 161)
1288 set_result_csi =
1289 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1290 20, 5800, PHYDM_DONT_CARE);
1291 else if (*dm->channel >= 5 && *dm->channel <= 8)
1292 set_result_csi =
1293 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1294 20, 2440, PHYDM_DONT_CARE);
1295 else if (*dm->channel == 13)
1296 set_result_csi =
1297 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1298 20, 2480, PHYDM_DONT_CARE);
1299 else
1300 set_result_csi = PHYDM_SET_NO_NEED;
1301 } else if (*dm->band_width == CHANNEL_WIDTH_40) {
1302 if (*dm->channel == 151)
1303 set_result_csi =
1304 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1305 40, 5760, PHYDM_DONT_CARE);
1306 else if (*dm->channel == 159)
1307 set_result_csi =
1308 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1309 40, 5800, PHYDM_DONT_CARE);
1310 else if ((*dm->channel >= 3) && (*dm->channel <= 10))
1311 set_result_csi =
1312 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1313 40, 2440, PHYDM_DONT_CARE);
1314 else if (*dm->channel == 11)
1315 set_result_csi =
1316 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1317 40, 2480, PHYDM_DONT_CARE);
1318 else
1319 set_result_csi = PHYDM_SET_NO_NEED;
1320 } else if (*dm->band_width == CHANNEL_WIDTH_80) {
1321 if (*dm->channel == 58)
1322 set_result_csi =
1323 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1324 80, 5280, PHYDM_DONT_CARE);
1325 else if (*dm->channel == 122)
1326 set_result_csi =
1327 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1328 80, 5600, PHYDM_DONT_CARE);
1329 else if (*dm->channel == 155)
1330 set_result_csi =
1331 phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel,
1332 80, 5760, PHYDM_DONT_CARE);
1333 else
1334 set_result_csi = PHYDM_SET_NO_NEED;
1335 } else {
1336 set_result_csi = PHYDM_SET_NO_NEED;
1337 }
1338 #endif
1339 }
1340
1341 __iram_odm_func__
phydm_dynamic_spur_det_eliminate(struct dm_struct * dm)1342 void phydm_dynamic_spur_det_eliminate(struct dm_struct *dm)
1343 {
1344 #if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1)
1345 u32 freq_2g[FREQ_PT_2G_NUM] = {0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFC67,
1346 0xFCE7, 0xFCA7, 0xFC67, 0xFC27, 0xFFE6,
1347 0xFFA6, 0xFF66, 0xFF26, 0xFCE7};
1348 u32 freq_5g[FREQ_PT_5G_NUM] = {0xFFC0, 0xFFC0, 0xFC81, 0xFC81, 0xFC41,
1349 0xFC40, 0xFF80, 0xFF80, 0xFF40, 0xFD42};
1350 u32 freq_2g_n1[FREQ_PT_2G_NUM] = {0}, freq_2g_p1[FREQ_PT_2G_NUM] = {0};
1351 u32 freq_5g_n1[FREQ_PT_5G_NUM] = {0}, freq_5g_p1[FREQ_PT_5G_NUM] = {0};
1352 u32 f_pt_2g = 0, f_pt_5g = 0, f_pt_2g_b = 0, f_pt_5g_b = 0;
1353 u32 max_ret_psd_final = 0, max_ret_psd_b_final = 0;
1354 u32 max_ret_psd_2nd[PSD_SMP_NUM] = {0};
1355 u32 max_ret_psd_b_2nd[PSD_SMP_NUM] = {0};
1356 u32 psd_set[PSD_VAL_NUM] = {0}, psd_set_B[PSD_VAL_NUM] = {0};
1357 u32 rank_psd_index_in[PSD_VAL_NUM] = {0};
1358 u32 rank_sample_index_in[PSD_SMP_NUM] = {0};
1359 u32 rank_psd_index_out[PSD_VAL_NUM] = {0};
1360 u32 rank_sample_index_out[PSD_SMP_NUM] = {0};
1361 u32 reg_910_15_12 = 0;
1362 u8 j = 0, k = 0, threshold_nbi = 0x8D, threshold_csi = 0x8D, idx = 0;
1363 boolean s_dopsd = false, s_donbi_a = false;
1364 boolean s_docsi = false, s_donbi_b = false;
1365
1366 phydm_dsde_init(dm);
1367 idx = phydm_dsde_ch_idx(dm);
1368
1369 if (idx <= 16) {
1370 s_dopsd = true;
1371 } else {
1372 PHYDM_DBG(dm, ODM_COMP_API,
1373 "Idx Exceed, Not Support Dyn_Elmntr\n");
1374 return;
1375 }
1376
1377 PHYDM_DBG(dm, ODM_COMP_API, "idx=%d, BW=%d, ch=%d\n", idx,
1378 *dm->band_width, *dm->channel);
1379
1380 for (k = 0; k < FREQ_PT_2G_NUM; k++) {
1381 freq_2g_n1[k] = freq_2g[k] - 1; freq_2g_p1[k] = freq_2g[k] + 1;
1382 }
1383
1384 for (k = 0; k < FREQ_PT_5G_NUM; k++) {
1385 freq_5g_n1[k] = freq_5g[k] - 1; freq_5g_p1[k] = freq_5g[k] + 1;
1386 }
1387
1388 if (!s_dopsd || idx > 13) {
1389 PHYDM_DBG(dm, ODM_COMP_API,
1390 "s_dopsd=flase, Not Support Dyn_Elmntr\n");
1391 return;
1392 }
1393
1394 for (k = 0; k < PSD_SMP_NUM; k++) {
1395 if (k == 0) {
1396 f_pt_2g = freq_2g_n1[idx];
1397 f_pt_2g_b = freq_2g_n1[idx] | BIT(16);
1398 if (idx < 10) {
1399 f_pt_5g = freq_5g_n1[idx];
1400 f_pt_5g_b = freq_5g_n1[idx] | BIT(16);
1401 }
1402 } else if (k == 1) {
1403 f_pt_2g = freq_2g[idx];
1404 f_pt_2g_b = freq_2g[idx] | BIT(16);
1405 if (idx < 10) {
1406 f_pt_5g = freq_5g[idx];
1407 f_pt_5g_b = freq_5g[idx] | BIT(16);
1408 }
1409 } else if (k == 2) {
1410 f_pt_2g = freq_2g_p1[idx];
1411 f_pt_2g_b = freq_2g_p1[idx] | BIT(16);
1412 if (idx < 10) {
1413 f_pt_5g = freq_5g_p1[idx];
1414 f_pt_5g_b = freq_5g_p1[idx] | BIT(16);
1415 }
1416 }
1417
1418 for (j = 0; j < PSD_VAL_NUM; j++) {
1419 /* @disable 3-wire, path-A & apth-B */
1420 odm_set_bb_reg(dm, R_0xc00, MASKBYTE0, 0x4);
1421 odm_set_bb_reg(dm, R_0xe00, MASKBYTE0, 0x4);
1422 reg_910_15_12 = odm_get_bb_reg(dm, R_0x910, (BIT(15) |
1423 BIT(14) | BIT(13) |
1424 BIT(12)));
1425
1426 if (dm->rx_ant_status & BB_PATH_A) {
1427 odm_set_bb_reg(dm, R_0x808, MASKBYTE0,
1428 (((BB_PATH_A) << 4) |
1429 BB_PATH_A)); /*path-A*/
1430
1431 if ((*dm->channel >= 1) && (*dm->channel <= 14))
1432 /* Start PSD at 2G */
1433 odm_set_bb_reg(dm, R_0x910, MASKDWORD,
1434 BIT(22) | f_pt_2g);
1435 else
1436 /* Start PSD at 5G */
1437 odm_set_bb_reg(dm, R_0x910, MASKDWORD,
1438 BIT(22) | f_pt_5g);
1439
1440 ODM_delay_us(500);
1441
1442 psd_set[j] = odm_get_bb_reg(dm, R_0xf44,
1443 MASKLWORD);
1444 /* turn off PSD */
1445 odm_set_bb_reg(dm, R_0x910, BIT(22), 0x0);
1446 }
1447
1448 if (dm->rx_ant_status & BB_PATH_B) {
1449 odm_set_bb_reg(dm, R_0x808, MASKBYTE0,
1450 (((BB_PATH_B) << 4) |
1451 BB_PATH_B)); /*path-B*/
1452
1453 if ((*dm->channel > 0) && (*dm->channel <= 14))
1454 /* Start PSD at 2G */
1455 odm_set_bb_reg(dm, R_0x910, MASKDWORD,
1456 BIT(22) | f_pt_2g_b);
1457 else
1458 /* Start PSD at 5G */
1459 odm_set_bb_reg(dm, R_0x910, MASKDWORD,
1460 BIT(22) | f_pt_5g_b);
1461
1462 ODM_delay_us(500);
1463
1464 psd_set_B[j] = odm_get_bb_reg(dm, R_0xf44,
1465 MASKLWORD);
1466
1467 /* turn off PSD */
1468 odm_set_bb_reg(dm, R_0x910, BIT(22), 0x0);
1469 }
1470
1471 /*@eanble 3-wire*/
1472 odm_set_bb_reg(dm, R_0xc00, MASKBYTE0, 0x7);
1473 odm_set_bb_reg(dm, R_0xe00, MASKBYTE0, 0x7);
1474 odm_set_bb_reg(dm, R_0x910, (BIT(15) | BIT(14) |
1475 BIT(13) | BIT(12)), reg_910_15_12);
1476
1477 odm_set_bb_reg(dm, R_0x808, MASKBYTE0,
1478 (((dm->rx_ant_status) << 4) |
1479 dm->rx_ant_status));
1480
1481 /* Toggle IGI to let RF enter RX mode */
1482 /* @because BB doesn't send 3-wire command */
1483 /* when RX path is enable */
1484 phydm_igi_toggle_8822b(dm);
1485 }
1486 if (dm->rx_ant_status & BB_PATH_A) {
1487 phydm_seq_sorting(dm, psd_set, rank_psd_index_in,
1488 rank_psd_index_out, PSD_VAL_NUM);
1489 max_ret_psd_2nd[k] = psd_set[0];
1490 }
1491 if (dm->rx_ant_status & BB_PATH_B) {
1492 phydm_seq_sorting(dm, psd_set_B, rank_psd_index_in,
1493 rank_psd_index_out, PSD_VAL_NUM);
1494 max_ret_psd_b_2nd[k] = psd_set_B[0];
1495 }
1496 }
1497
1498 if (dm->rx_ant_status & BB_PATH_A) {
1499 phydm_seq_sorting(dm, max_ret_psd_2nd, rank_sample_index_in,
1500 rank_sample_index_out, PSD_SMP_NUM);
1501 max_ret_psd_final = max_ret_psd_2nd[0];
1502
1503 if (max_ret_psd_final >= threshold_nbi)
1504 s_donbi_a = true;
1505 else
1506 s_donbi_a = false;
1507 }
1508 if (dm->rx_ant_status & BB_PATH_B) {
1509 phydm_seq_sorting(dm, max_ret_psd_b_2nd, rank_sample_index_in,
1510 rank_sample_index_out, PSD_SMP_NUM);
1511 max_ret_psd_b_final = max_ret_psd_b_2nd[0];
1512
1513 if (max_ret_psd_b_final >= threshold_nbi)
1514 s_donbi_b = true;
1515 else
1516 s_donbi_b = false;
1517 }
1518
1519 PHYDM_DBG(dm, ODM_COMP_API,
1520 "max_ret_psd_final = %d, max_ret_psd_b_final = %d\n",
1521 max_ret_psd_final, max_ret_psd_b_final);
1522
1523 if (max_ret_psd_final >= threshold_csi ||
1524 max_ret_psd_b_final >= threshold_csi)
1525 s_docsi = true;
1526 else
1527 s_docsi = false;
1528
1529 if (s_donbi_a || s_donbi_b)
1530 phydm_dsde_nbi(dm);
1531
1532 if (s_docsi)
1533 phydm_dsde_csi(dm);
1534
1535 #endif /*PHYDM_SPUR_CANCELL_ENABLE_8822B == 1*/
1536 }
1537
1538 __iram_odm_func__
phydm_spur_calibration_8822b(struct dm_struct * dm)1539 void phydm_spur_calibration_8822b(struct dm_struct *dm)
1540 {
1541 #ifdef CONFIG_8822B_SPUR_CALIBRATION
1542 if (*dm->is_scan_in_process)
1543 return;
1544
1545 odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
1546 odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
1547 odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
1548 phydm_dynamic_spur_det_eliminate(dm);
1549 PHYDM_DBG(dm, ODM_COMP_API, "Enable spur eliminator at normal\n");
1550 #else
1551 PHYDM_DBG(dm, ODM_COMP_API, "NBI and CSI notch at normal\n");
1552 #endif
1553 }
1554
1555 __iram_odm_func__
1556 boolean
config_phydm_switch_band_8822b(struct dm_struct * dm,u8 central_ch)1557 config_phydm_switch_band_8822b(struct dm_struct *dm,
1558 u8 central_ch)
1559 {
1560 u32 rf_reg18;
1561 boolean rf_reg_status = true;
1562 u32 reg_8;
1563
1564 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======>\n", __func__);
1565
1566 if (dm->is_disable_phy_api) {
1567 PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API for dbg\n");
1568 return true;
1569 }
1570
1571 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18,
1572 RFREGOFFSETMASK);
1573 rf_reg_status = rf_reg_status &
1574 config_phydm_read_rf_check_8822b(rf_reg18);
1575
1576 if (central_ch <= 14) {
1577 /* @2.4G */
1578
1579 /* @Enable CCK block */
1580 odm_set_bb_reg(dm, R_0x808, BIT(28), 0x1);
1581
1582 /* @Disable MAC CCK check */
1583 odm_set_bb_reg(dm, R_0x454, BIT(7), 0x0);
1584
1585 /* @Disable BB CCK check */
1586 odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x0);
1587
1588 /*@CCA Mask*/
1589 odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*@default value*/
1590
1591 /* RF band */
1592 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1593
1594 /* RxHP dynamic control */
1595 /* QFN eFEM RxHP are always low at 2G */
1596 reg_8 = odm_get_bb_reg(dm, R_0x19a8, BIT(31));
1597
1598 /* SoML on */
1599 if (reg_8 == 0x1) {
1600 odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
1601 odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
1602 if (dm->rfe_type == 3 || dm->rfe_type == 5 ||
1603 dm->rfe_type == 8 || dm->rfe_type == 17) {
1604 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD,
1605 0x08108492);
1606 odm_set_bb_reg(dm, R_0x8d8, BIT(19), 0x0);
1607 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
1608 } else {
1609 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD,
1610 0x08108000);
1611 odm_set_bb_reg(dm, R_0x8d8, BIT(19), 0x0);
1612 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
1613 }
1614 }
1615
1616 /* SoML off */
1617 if (reg_8 == 0x0) {
1618 odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
1619 odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
1620 if (dm->rfe_type == 1 || dm->rfe_type == 6 ||
1621 dm->rfe_type == 7 || dm->rfe_type == 9) {
1622 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD,
1623 0x08108000);
1624 odm_set_bb_reg(dm, R_0x8d8, BIT(19), 0x0);
1625 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
1626 } else {
1627 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD,
1628 0x08108492);
1629 odm_set_bb_reg(dm, R_0x8d8, BIT(19), 0x0);
1630 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
1631 }
1632 }
1633
1634 if (dm->rfe_type == 12 || dm->rfe_type == 19) {
1635 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb3, RFREGOFFSETMASK,
1636 0x3C360);
1637 odm_set_rf_reg(dm, RF_PATH_B, RF_0xb3, RFREGOFFSETMASK,
1638 0x3C360);
1639 }
1640
1641 } else if (central_ch > 35) {
1642 /* @5G */
1643
1644 /* @Enable BB CCK check */
1645 odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x1);
1646
1647 /* @Enable CCK check */
1648 odm_set_bb_reg(dm, R_0x454, BIT(7), 0x1);
1649
1650 /* @Disable CCK block */
1651 odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0);
1652
1653 /*@CCA Mask*/
1654 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1655 /*@CCA mask = 13.6us*/
1656 odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 34);
1657 #else
1658 if (!dm->wifi_test)
1659 /*@CCA mask = 13.6us*/
1660 odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 34);
1661 else
1662 /*@default value*/
1663 odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15);
1664 #endif
1665
1666 /* RF band */
1667 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1668 rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
1669
1670 /* RxHP dynamic control */
1671 reg_8 = odm_get_bb_reg(dm, R_0x19a8, BIT(31));
1672
1673 /* SoML on */
1674 if (reg_8 == 0x1) {
1675 odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
1676 odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
1677 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
1678 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
1679 }
1680
1681 /* SoML off */
1682 if (reg_8 == 0x0) {
1683 odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
1684 odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
1685 if (dm->rfe_type == 1 || dm->rfe_type == 6 ||
1686 dm->rfe_type == 7 || dm->rfe_type == 9) {
1687 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD,
1688 0x08108000);
1689 odm_set_bb_reg(dm, R_0x8d8, BIT(19), 0x0);
1690 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
1691 } else {
1692 odm_set_bb_reg(dm, R_0x8cc, MASKDWORD,
1693 0x08108492);
1694 odm_set_bb_reg(dm, R_0x8d8, BIT(19), 0x0);
1695 odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
1696 }
1697 }
1698
1699 if (dm->rfe_type == 12 || dm->rfe_type == 19) {
1700 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb3, RFREGOFFSETMASK,
1701 0xFC760);
1702 odm_set_rf_reg(dm, RF_PATH_B, RF_0xb3, RFREGOFFSETMASK,
1703 0xFC760);
1704 }
1705 } else {
1706 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail to switch band (ch: %d)\n",
1707 central_ch);
1708 return false;
1709 }
1710
1711 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
1712
1713 if (dm->rf_type > RF_1T1R)
1714 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREGOFFSETMASK,
1715 rf_reg18);
1716
1717 if (phydm_rfe_8822b(dm, central_ch) == false)
1718 return false;
1719
1720 if (!rf_reg_status) {
1721 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1722 "Fail to switch band (ch: %d), write RF_reg fail\n",
1723 central_ch);
1724 return false;
1725 }
1726
1727 /* @Dynamic spur detection by PSD and NBI/CSI mask */
1728 if (*dm->mp_mode) {
1729 odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
1730 odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
1731 odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
1732
1733 phydm_dynamic_spur_det_eliminate(dm);
1734 } else {
1735 /* Normal mode */
1736 phydm_spur_calibration_8822b(dm);
1737 }
1738
1739 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Success to switch band (ch: %d)\n",
1740 central_ch);
1741 return true;
1742 }
1743
1744 __iram_odm_func__
phydm_rxagc_switch_8822b(struct dm_struct * dm,boolean enable_rxagc_switch)1745 void phydm_rxagc_switch_8822b(struct dm_struct *dm,
1746 boolean enable_rxagc_switch)
1747 {
1748 if (dm->rfe_type == 15 || dm->rfe_type == 16) {
1749 PHYDM_DBG(dm, ODM_COMP_API, "Microsoft case!\n");
1750
1751 } else {
1752 PHYDM_DBG(dm, ODM_COMP_API, "Not Microsoft case\n");
1753 return;
1754 }
1755
1756 if (enable_rxagc_switch) {
1757 if ((*dm->channel >= 36) && (*dm->channel <= 64)) {
1758 odm_set_bb_reg(dm, R_0x958, BIT(4), 0x1);
1759 odm_set_bb_reg(dm, R_0xc1c, (BIT(11) | BIT(10) |
1760 BIT(9) | BIT(8)), 0x1);
1761 odm_set_bb_reg(dm, R_0xe1c, (BIT(11) | BIT(10) |
1762 BIT(9) | BIT(8)), 0x5);
1763 } else if ((*dm->channel >= 100) && (*dm->channel <= 144)) {
1764 odm_set_bb_reg(dm, R_0x958, BIT(4), 0x1);
1765 odm_set_bb_reg(dm, R_0xc1c, (BIT(11) | BIT(10) |
1766 BIT(9) | BIT(8)), 0x2);
1767 odm_set_bb_reg(dm, R_0xe1c, (BIT(11) | BIT(10) |
1768 BIT(9) | BIT(8)), 0x6);
1769 } else if (*dm->channel >= 149) {
1770 odm_set_bb_reg(dm, R_0x958, BIT(4), 0x1);
1771 odm_set_bb_reg(dm, R_0xc1c, (BIT(11) | BIT(10) |
1772 BIT(9) | BIT(8)), 0x3);
1773 odm_set_bb_reg(dm, R_0xe1c, (BIT(11) | BIT(10) |
1774 BIT(9) | BIT(8)), 0x7);
1775 }
1776 dm->brxagcswitch = true;
1777 PHYDM_DBG(dm, ODM_COMP_API,
1778 "Microsoft case! AGC table (path-b) is switched!\n");
1779
1780 } else {
1781 if ((*dm->channel >= 36) && (*dm->channel <= 64)) {
1782 odm_set_bb_reg(dm, R_0x958, BIT(4), 0x1);
1783 odm_set_bb_reg(dm, R_0xc1c, (BIT(11) | BIT(10) |
1784 BIT(9) | BIT(8)), 0x1);
1785 odm_set_bb_reg(dm, R_0xe1c, (BIT(11) | BIT(10) |
1786 BIT(9) | BIT(8)), 0x1);
1787 } else if ((*dm->channel >= 100) && (*dm->channel <= 144)) {
1788 odm_set_bb_reg(dm, R_0x958, BIT(4), 0x1);
1789 odm_set_bb_reg(dm, R_0xc1c, (BIT(11) | BIT(10) |
1790 BIT(9) | BIT(8)), 0x2);
1791 odm_set_bb_reg(dm, R_0xe1c, (BIT(11) | BIT(10) |
1792 BIT(9) | BIT(8)), 0x2);
1793 } else if (*dm->channel >= 149) {
1794 odm_set_bb_reg(dm, R_0x958, BIT(4), 0x1);
1795 odm_set_bb_reg(dm, R_0xc1c, (BIT(11) | BIT(10) |
1796 BIT(9) | BIT(8)), 0x3);
1797 odm_set_bb_reg(dm, R_0xe1c, (BIT(11) | BIT(10) |
1798 BIT(9) | BIT(8)), 0x3);
1799 }
1800 dm->brxagcswitch = false;
1801 PHYDM_DBG(dm, ODM_COMP_API,
1802 "AGC table are the same on path-a and b\n");
1803 }
1804 }
1805
1806 __iram_odm_func__
1807 boolean
config_phydm_switch_channel_8822b(struct dm_struct * dm,u8 central_ch)1808 config_phydm_switch_channel_8822b(struct dm_struct *dm,
1809 u8 central_ch)
1810 {
1811 struct phydm_dig_struct *dig_tab = &dm->dm_dig_table;
1812 u32 rf_reg18 = 0, rf_reg_be = 0xff;
1813 boolean rf_reg_status = true;
1814 u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5,
1815 0x0, 0x0, 0x7, 0x6, 0x6};
1816 u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0,
1817 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6,
1818 0x5, 0x0, 0x0, 0x7};
1819 u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7,
1820 0x7, 0x6, 0x5, 0x5, 0x0};
1821 u8 band_index = 0;
1822
1823 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> ch=%d\n", __func__,
1824 central_ch);
1825
1826 if (dm->is_disable_phy_api) {
1827 PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API for dbg\n");
1828 return true;
1829 }
1830 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1831 /*@Make protection*/
1832 if (central_ch == 165 && bw_8822b != CHANNEL_WIDTH_20)
1833 config_phydm_switch_bandwidth_8822b(dm, 0, CHANNEL_WIDTH_20);
1834 #endif
1835 central_ch_8822b = central_ch;
1836
1837 /* @Errir handling for wrong HW setting due to wrong channel setting */
1838 if (central_ch_8822b <= 14)
1839 band_index = 1;
1840 else
1841 band_index = 2;
1842
1843 if (dm->rfe_hwsetting_band != band_index)
1844 phydm_rfe_8822b(dm, central_ch_8822b);
1845
1846 if (dm->rfe_type == 15 || dm->rfe_type == 18)
1847 phydm_rfe_8822b(dm, central_ch_8822b);
1848
1849 /* RF register setting */
1850 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18,
1851 RFREGOFFSETMASK);
1852 rf_reg_status = rf_reg_status &
1853 config_phydm_read_rf_check_8822b(rf_reg18);
1854 rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
1855
1856 /* Switch band and channel */
1857 if (central_ch <= 14) {
1858 /* @2.4G */
1859
1860 /* @1. RF band and channel*/
1861 rf_reg18 = (rf_reg18 | central_ch);
1862
1863 /* @2. AGC table selection */
1864 odm_set_bb_reg(dm, R_0x958, 0x1f, 0x0);
1865 dig_tab->agc_table_idx = 0x0;
1866
1867 /* @3. Set central frequency for clock offset tracking */
1868 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x96a);
1869
1870 /* @CCK TX filter parameters */
1871
1872 if (central_ch == 14) {
1873 odm_set_bb_reg(dm, R_0xa24, MASKDWORD, 0x00006577);
1874 odm_set_bb_reg(dm, R_0xa28, MASKLWORD, 0x0000);
1875 } else {
1876 odm_set_bb_reg(dm, R_0xa24, MASKDWORD, 0x384f6577);
1877 odm_set_bb_reg(dm, R_0xa28, MASKLWORD, 0x1525);
1878 }
1879
1880 } else if (central_ch > 35) {
1881 /* @5G */
1882
1883 /* @1. RF band and channel*/
1884 rf_reg18 = (rf_reg18 | central_ch);
1885
1886 /* @2. AGC table selection */
1887 if (!(dm->rfe_type == 15 || dm->rfe_type == 16)) {
1888 if (central_ch >= 36 && central_ch <= 64) {
1889 odm_set_bb_reg(dm, R_0x958, 0x1f, 0x1);
1890 dig_tab->agc_table_idx = 0x1;
1891 } else if ((central_ch >= 100) && (central_ch <= 144)) {
1892 odm_set_bb_reg(dm, R_0x958, 0x1f, 0x2);
1893 dig_tab->agc_table_idx = 0x2;
1894 } else if (central_ch >= 149) {
1895 odm_set_bb_reg(dm, R_0x958, 0x1f, 0x3);
1896 dig_tab->agc_table_idx = 0x3;
1897 } else {
1898 PHYDM_DBG(dm, ODM_PHY_CONFIG, "(AGC) Fail\n");
1899 return false;
1900 }
1901 } else if ((dm->rfe_type == 15) || (dm->rfe_type == 16)) {
1902 if (dm->brxagcswitch)
1903 phydm_rxagc_switch_8822b(dm, true);
1904 else
1905 phydm_rxagc_switch_8822b(dm, false);
1906 }
1907
1908 /* @3. Set central frequency for clock offset tracking */
1909 if (central_ch >= 36 && central_ch <= 48) {
1910 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x494);
1911 } else if ((central_ch >= 52) && (central_ch <= 64)) {
1912 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x453);
1913 } else if ((central_ch >= 100) && (central_ch <= 116)) {
1914 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x452);
1915 } else if ((central_ch >= 118) && (central_ch <= 177)) {
1916 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x412);
1917 } else {
1918 PHYDM_DBG(dm, ODM_PHY_CONFIG, "(fc_area)Fail\n");
1919 return false;
1920 }
1921
1922 } else {
1923 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail\n");
1924 return false;
1925 }
1926
1927 /* @Modify IGI for MP driver to aviod PCIE interference */
1928 if (*dm->mp_mode && (dm->rfe_type == 3 || dm->rfe_type == 5)) {
1929 if (central_ch == 14)
1930 odm_write_dig(dm, 0x26);
1931 else
1932 odm_write_dig(dm, 0x20);
1933 }
1934
1935 /* @Modify the setting of register 0xBE to reduce phase noise */
1936 if (central_ch <= 14)
1937 rf_reg_be = 0x0;
1938 else if ((central_ch >= 36) && (central_ch <= 64))
1939 rf_reg_be = low_band[(central_ch - 36) >> 1];
1940 else if ((central_ch >= 100) && (central_ch <= 144))
1941 rf_reg_be = middle_band[(central_ch - 100) >> 1];
1942 else if ((central_ch >= 149) && (central_ch <= 177))
1943 rf_reg_be = high_band[(central_ch - 149) >> 1];
1944
1945 if (rf_reg_be != 0xff) {
1946 odm_set_rf_reg(dm, RF_PATH_A, RF_0xbe, (BIT(17) | BIT(16) |
1947 BIT(15)), rf_reg_be);
1948 } else {
1949 PHYDM_DBG(dm, ODM_PHY_CONFIG, "(phase noise)Fail\n");
1950 return false;
1951 }
1952
1953 /* @Fix channel 144 issue, ask by RFSI Alvin*/
1954 /* @00 when freq < 5400; 01 when 5400<=freq<=5720; */
1955 /* @10 when freq > 5720; 2G don't care*/
1956 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
1957 if (central_ch == 144) {
1958 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(18), 0x1);
1959 rf_reg18 = (rf_reg18 | BIT(17));
1960 } else {
1961 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(18), 0x0);
1962
1963 if (central_ch > 144)
1964 rf_reg18 = (rf_reg18 | BIT(18));
1965 else if (central_ch >= 80)
1966 rf_reg18 = (rf_reg18 | BIT(17));
1967 }
1968
1969 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
1970
1971 if (dm->rf_type > RF_1T1R)
1972 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREGOFFSETMASK,
1973 rf_reg18);
1974
1975 if (!rf_reg_status) {
1976 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail, write RF_reg fail\n");
1977 return false;
1978 }
1979
1980 /* @Debug for RF resister reading error */
1981 /* @during synthesizer parameters parsing */
1982 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, BIT(19), 0);
1983 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, BIT(19), 1);
1984
1985 phydm_igi_toggle_8822b(dm);
1986 phydm_ccapar_by_rfe_8822b(dm);
1987
1988 /* @Dynamic spur detection by PSD and NBI/CSI mask */
1989 if (*dm->mp_mode) {
1990 odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
1991 odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
1992 odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
1993
1994 phydm_dynamic_spur_det_eliminate(dm);
1995 } else {
1996 /* Normal mode */
1997 phydm_spur_calibration_8822b(dm);
1998 }
1999 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Success\n");
2000 return true;
2001 }
2002
2003 __iram_odm_func__
2004 boolean
config_phydm_switch_agc_tab_8822b(struct dm_struct * dm,u8 channel,enum agc_tab_sel tab_sel)2005 config_phydm_switch_agc_tab_8822b(struct dm_struct *dm,
2006 u8 channel, enum agc_tab_sel tab_sel)
2007 {
2008 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> channel=%d, table_sel=%d\n",
2009 __func__, channel, tab_sel);
2010
2011 return true;
2012 }
2013
2014 __iram_odm_func__
2015 boolean
config_phydm_switch_bandwidth_8822b(struct dm_struct * dm,u8 primary_ch_idx,enum channel_width bw)2016 config_phydm_switch_bandwidth_8822b(struct dm_struct *dm,
2017 u8 primary_ch_idx,
2018 enum channel_width bw)
2019 {
2020 u32 rf_reg18, val32;
2021 boolean rf_reg_status = true;
2022 u8 rfe_type = dm->rfe_type;
2023 u8 bandwidth = bw;
2024
2025 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> primary_ch=%d, bw=%d\n",
2026 __func__, primary_ch_idx, bandwidth);
2027
2028 if (dm->is_disable_phy_api) {
2029 PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API for dbg\n");
2030 return true;
2031 }
2032
2033 /* @Error handling */
2034 if (bandwidth >= CHANNEL_WIDTH_MAX ||
2035 (bandwidth == CHANNEL_WIDTH_40 && primary_ch_idx > 2) ||
2036 (bandwidth == CHANNEL_WIDTH_80 && primary_ch_idx > 4)) {
2037 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail 1\n");
2038 return false;
2039 }
2040 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
2041 /*@Make protection*/
2042 if (central_ch_8822b == 165 && !(*dm->mp_mode))
2043 bandwidth = CHANNEL_WIDTH_20;
2044 #endif
2045 bw_8822b = bandwidth;
2046 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18,
2047 RFREG_MASK);
2048 rf_reg_status = rf_reg_status &
2049 config_phydm_read_rf_check_8822b(rf_reg18);
2050
2051 /* Switch bandwidth */
2052 switch (bandwidth) {
2053 case CHANNEL_WIDTH_20: {
2054 #if 0
2055 /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, */
2056 /* rf mode([1:0]) = 20M */
2057 /* odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, CHANNEL_WIDTH_20);*/
2058 #endif
2059
2060 #if 0
2061 /* @ADC clock = 160M clock for BW20 */
2062 /* odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x0);*/
2063 /* odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x1);*/
2064 #endif
2065
2066 #if 0
2067 /* @DAC clock = 160M clock for BW20 */
2068 /* odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x0);*/
2069 /* odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x1);*/
2070 #endif
2071
2072 val32 = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
2073 val32 &= 0xFFCFFC00;
2074 val32 |= (CHANNEL_WIDTH_20);
2075 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, val32);
2076
2077 /* @ADC buffer clock */
2078 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
2079
2080 /* RF bandwidth */
2081 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
2082
2083 break;
2084 }
2085 case CHANNEL_WIDTH_40: {
2086 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel */
2087 /* rf mode([1:0]) = 40M */
2088 /* odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, */
2089 /* @(((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40));*/
2090
2091 /* @CCK primary channel */
2092 if (primary_ch_idx == 1)
2093 odm_set_bb_reg(dm, R_0xa00, BIT(4), primary_ch_idx);
2094 else
2095 odm_set_bb_reg(dm, R_0xa00, BIT(4), 0);
2096
2097 #if 0
2098 /* @ADC clock = 160M clock for BW40 */
2099 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(11) | BIT(10)), 0x0);*/
2100 /*odm_set_bb_reg(dm, R_0x8ac, BIT(17), 0x1);*/
2101 #endif
2102
2103 #if 0
2104 /* @DAC clock = 160M clock for BW20 */
2105 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(23) | BIT(22)), 0x0);*/
2106 /*odm_set_bb_reg(dm, R_0x8ac, BIT(29), 0x1);*/
2107 #endif
2108
2109 val32 = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
2110 val32 &= 0xFF3FF300;
2111 val32 |= (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40);
2112 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, val32);
2113
2114 /* @ADC buffer clock */
2115 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
2116
2117 /* RF bandwidth */
2118 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
2119 rf_reg18 = (rf_reg18 | BIT(11));
2120
2121 break;
2122 }
2123 case CHANNEL_WIDTH_80: {
2124 #if 0
2125 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel */
2126 /* rf mode([1:0]) = 80M */
2127 /*odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, */
2128 /* @(((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80));*/
2129 #endif
2130
2131 #if 0
2132 /* @ADC clock = 160M clock for BW80 */
2133 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(13) | BIT(12)), 0x0);*/
2134 /*odm_set_bb_reg(dm, R_0x8ac, BIT(18), 0x1);*/
2135 #endif
2136
2137 #if 0
2138 /* @DAC clock = 160M clock for BW20 */
2139 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(25) | BIT(24)), 0x0);*/
2140 /*odm_set_bb_reg(dm, R_0x8ac, BIT(30), 0x1);*/
2141 #endif
2142
2143 val32 = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
2144 val32 &= 0xFCEFCF00;
2145 val32 |= (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80);
2146 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, val32);
2147
2148 /* @ADC buffer clock */
2149 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
2150
2151 /* RF bandwidth */
2152 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
2153 rf_reg18 = (rf_reg18 | BIT(10));
2154
2155 /* Parameters for SD4 TP requirement */
2156 if (rfe_type == 2 || rfe_type == 3 || rfe_type == 17) {
2157 odm_set_bb_reg(dm, R_0x840, 0x0000f000, 0x6);
2158 odm_set_bb_reg(dm, R_0x8c8, BIT(10), 0x1);
2159 }
2160
2161 break;
2162 }
2163 case CHANNEL_WIDTH_5: {
2164 #if 0
2165 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, */
2166 /* rf mode([1:0]) = 20M */
2167 /*@dm_set_bb_reg(dm, 0x8ac, MASKBYTE0, */
2168 /* @(BIT(6) | CHANNEL_WIDTH_20));*/
2169 #endif
2170
2171 #if 0
2172 /* @ADC clock = 40M clock */
2173 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x2);*/
2174 /*odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0);*/
2175 #endif
2176
2177 #if 0
2178 /* @DAC clock = 160M clock for BW20 */
2179 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x2);*/
2180 /*odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0);*/
2181 #endif
2182
2183 val32 = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
2184 val32 &= 0xEFEEFE00;
2185 val32 |= ((BIT(6) | CHANNEL_WIDTH_20));
2186 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, val32);
2187
2188 /* @ADC buffer clock */
2189 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0);
2190 odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1);
2191
2192 /* RF bandwidth */
2193 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
2194
2195 break;
2196 }
2197 case CHANNEL_WIDTH_10: {
2198 #if 0
2199 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, */
2200 /* rf mode([1:0]) = 20M */
2201 /* odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, */
2202 /* @(BIT(7) | CHANNEL_WIDTH_20));*/
2203 #endif
2204
2205 #if 0
2206 /* @ADC clock = 80M clock */
2207 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x3);*/
2208 /*odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0);*/
2209 #endif
2210
2211 #if 0
2212 /* @DAC clock = 160M clock for BW20 */
2213 /*odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x3);*/
2214 /*odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0);*/
2215 #endif
2216
2217 val32 = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
2218 val32 &= 0xEFFEFF00;
2219 val32 |= ((BIT(7) | CHANNEL_WIDTH_20));
2220 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, val32);
2221
2222 /* @ADC buffer clock */
2223 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0);
2224 odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1);
2225
2226 /* RF bandwidth */
2227 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
2228
2229 break;
2230 }
2231 default:
2232 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail 2\n");
2233 }
2234
2235 /* Write RF register */
2236 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
2237
2238 if (dm->rf_type > RF_1T1R)
2239 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREGOFFSETMASK,
2240 rf_reg18);
2241
2242 if (!rf_reg_status) {
2243 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail, write RF_reg fail\n");
2244 return false;
2245 }
2246
2247 /* @Modify RX DFIR parameters */
2248 phydm_rxdfirpar_by_bw_8822b(dm, bandwidth);
2249
2250 /* @Modify CCA parameters */
2251 phydm_ccapar_by_rfe_8822b(dm);
2252
2253 /* @Dynamic spur detection by PSD and NBI/CSI mask */
2254 if (*dm->mp_mode) {
2255 odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
2256 odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
2257 odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
2258
2259 phydm_dynamic_spur_det_eliminate(dm);
2260 } else {
2261 /* Normal mode */
2262 phydm_spur_calibration_8822b(dm);
2263 }
2264
2265 /* Toggle RX path to avoid RX dead zone issue */
2266 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x0);
2267 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, (dm->rx_ant_status |
2268 (dm->rx_ant_status << 4)));
2269
2270 /* Toggle IGI to let RF enter RX mode */
2271 phydm_igi_toggle_8822b(dm);
2272
2273 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Success\n");
2274 return true;
2275 }
2276
2277 __iram_odm_func__
2278 boolean
config_phydm_switch_channel_bw_8822b(struct dm_struct * dm,u8 central_ch,u8 primary_ch_idx,enum channel_width bw)2279 config_phydm_switch_channel_bw_8822b(struct dm_struct *dm,
2280 u8 central_ch,
2281 u8 primary_ch_idx,
2282 enum channel_width bw)
2283 {
2284 u8 bandwidth = bw;
2285 /* Switch band */
2286 if (!config_phydm_switch_band_8822b(dm, central_ch))
2287 return false;
2288
2289 /* Switch channel */
2290 if (!config_phydm_switch_channel_8822b(dm, central_ch))
2291 return false;
2292
2293 /* Switch bandwidth */
2294 if (!config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx, bandwidth))
2295 return false;
2296
2297 return true;
2298 }
2299
2300 __odm_func__
2301 void
phydm_config_cck_tx_path_8822b(struct dm_struct * dm,enum bb_path tx_path)2302 phydm_config_cck_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path)
2303 {
2304 if (tx_path == BB_PATH_A)
2305 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
2306 else if (tx_path == BB_PATH_B)
2307 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
2308 else
2309 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
2310 }
2311
2312 __odm_func__
2313 void
phydm_config_ofdm_tx_path_8822b(struct dm_struct * dm,enum bb_path tx_path_en,enum bb_path tx_path_sel_1ss)2314 phydm_config_ofdm_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path_en,
2315 enum bb_path tx_path_sel_1ss)
2316 {
2317 /* @Set TX logic map and TX path_en*/
2318 if (tx_path_en == BB_PATH_A) { /* @1T, 1ss */
2319 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
2320 } else if (tx_path_en == BB_PATH_B) {
2321 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
2322 } else { /*BB_PATH_AB*/
2323 if (tx_path_sel_1ss == BB_PATH_A) {
2324 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
2325 odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
2326 } else if (tx_path_sel_1ss == BB_PATH_B) {
2327 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
2328 odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
2329 } else { /*BB_PATH_AB*/
2330 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x043);
2331 odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
2332 }
2333 }
2334 #if 1
2335 /* @TX logic map and TX path en for Nsts = 2*/
2336 /*
2337 * @Due to LO is stand-by while 1T at path-b in normal driver,
2338 * @so 0x940 is the same setting btw path-A/B
2339 */
2340 if (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {
2341 odm_set_bb_reg(dm, R_0x940, 0xf0, 0x1);
2342 odm_set_bb_reg(dm, R_0x940, 0xff00, 0x0);
2343 }
2344 #endif
2345 }
2346
2347 __iram_odm_func__
phydm_config_tx_path_8822b(struct dm_struct * dm,enum bb_path tx_path,enum bb_path tx_path_sel_1ss,enum bb_path tx_path_sel_cck)2348 void phydm_config_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path,
2349 enum bb_path tx_path_sel_1ss,
2350 enum bb_path tx_path_sel_cck)
2351 {
2352 dm->tx_ant_status = (u8)tx_path;
2353 dm->tx_1ss_status = tx_path_sel_1ss;
2354
2355 /* Set TX antenna by Nsts */
2356 odm_set_bb_reg(dm, R_0x93c, (BIT(19) | BIT(18)), 0x3);
2357 odm_set_bb_reg(dm, R_0x80c, (BIT(29) | BIT(28)), 0x1);
2358
2359 /* @Control CCK TX path by 0xa07[7] */
2360 odm_set_bb_reg(dm, R_0x80c, BIT(30), 0x1);
2361 /* TX path HW block enable */
2362 odm_set_bb_reg(dm, R_0x80c, MASKBYTE0, (tx_path << 4) | tx_path);
2363
2364 /*---- [CCK] ----*/
2365 phydm_config_cck_tx_path_8822b(dm, tx_path_sel_cck);
2366
2367 /*---- [OFDM] ----*/
2368 #if 1
2369 phydm_config_ofdm_tx_path_8822b(dm, tx_path, tx_path_sel_1ss);
2370 #else
2371 /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
2372 if (tx_path & BB_PATH_A) {
2373 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
2374 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
2375 } else if (tx_path & BB_PATH_B) {
2376 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
2377 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
2378 }
2379
2380 /* TX logic map and TX path en for Nsts = 2*/
2381 /* @Due to LO is stand-by while 1T at path-b in normal driver, */
2382 /* so 0x940 is the same setting btw path-A/B*/
2383 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B)
2384 odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x01);
2385 else
2386 odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x43);
2387
2388
2389 /* Tx2path for 1ss */
2390 if (!(tx_path == BB_PATH_A || tx_path == BB_PATH_B)) {
2391 if (is_tx2_path || *dm->mp_mode) {
2392 /* @2Tx for OFDM */
2393 odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x043);
2394 /* @2Tx for CCK */
2395 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
2396 }
2397 }
2398 #endif
2399 }
2400
2401 __iram_odm_func__
phydm_config_rx_path_8822b(struct dm_struct * dm,enum bb_path rx_path)2402 void phydm_config_rx_path_8822b(struct dm_struct *dm, enum bb_path rx_path)
2403 {
2404 dm->rx_ant_status = (u8)rx_path;
2405
2406 /*@Disable MRC for CCK CCA */
2407 odm_set_bb_reg(dm, R_0xa2c, BIT(22), 0x0);
2408 /*@Disable MRC for CCK barker */
2409 odm_set_bb_reg(dm, R_0xa2c, BIT(18), 0x0);
2410
2411 /* @CCK RX 1st and 2nd path setting*/
2412 if (rx_path & BB_PATH_A)
2413 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0); /*@00,00*/
2414 else if (rx_path & BB_PATH_B)
2415 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@01,01*/
2416
2417 /* RX path enable */
2418 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, (rx_path << 4) | rx_path);
2419
2420 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
2421 /* @Disable Antenna weighting */
2422 odm_set_bb_reg(dm, R_0x1904, BIT(16), 0x0);
2423 /* @htstf ant-wgt enable = 0*/
2424 odm_set_bb_reg(dm, R_0x800, BIT(28), 0x0);
2425 /* @MRC_mode = 'original ZF eqz'*/
2426 odm_set_bb_reg(dm, R_0x850, BIT(23), 0x0);
2427 } else {
2428 /* @Enable Antenna weighting */
2429 odm_set_bb_reg(dm, R_0x1904, BIT(16), 0x1);
2430 /* @htstf ant-wgt enable = 1*/
2431 odm_set_bb_reg(dm, R_0x800, BIT(28), 0x1);
2432 /* @MRC_mode = 'modified ZF eqz'*/
2433 odm_set_bb_reg(dm, R_0x850, BIT(23), 0x1);
2434 }
2435 }
2436
2437 __iram_odm_func__
2438 boolean
config_phydm_trx_mode_8822b(struct dm_struct * dm,enum bb_path tx_path_en,enum bb_path rx_path,enum bb_path tx_path_sel_1ss)2439 config_phydm_trx_mode_8822b(struct dm_struct *dm,
2440 enum bb_path tx_path_en,
2441 enum bb_path rx_path,
2442 enum bb_path tx_path_sel_1ss)
2443 {
2444 #ifdef CONFIG_PATH_DIVERSITY
2445 struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
2446 #endif
2447 u32 rf_reg33 = 0;
2448 u16 counter = 0;
2449
2450 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> TX:0x%x, RX:0x%x\n", __func__,
2451 tx_path_en, rx_path);
2452
2453 if (dm->is_disable_phy_api) {
2454 PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API\n");
2455 return true;
2456 }
2457
2458 if ((tx_path_en & ~BB_PATH_AB) || (rx_path & ~BB_PATH_AB)) {
2459 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong set\n");
2460 return false;
2461 }
2462
2463 /* @[mode table] RF mode of path-A and path-B
2464 * Cannot shut down path-A, beacause synthesizer will be shut down
2465 * when path-A is in shut down mode
2466 */
2467
2468 /* @[3-wire setting]
2469 * 0:shutdown, 1:standby, 2:TX, 3:RX
2470 */
2471 if ((tx_path_en | rx_path) & BB_PATH_A)
2472 odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x3231);
2473 else
2474 odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x1111);
2475
2476 if ((tx_path_en | rx_path) & BB_PATH_B)
2477 odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x3231);
2478 else
2479 odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x1111);
2480
2481 #ifdef CONFIG_PATH_DIVERSITY
2482 if (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {
2483 p_div->stop_path_div = true;
2484 tx_path_sel_1ss = tx_path_en;
2485 } else if (tx_path_en == BB_PATH_AB) {
2486 if (tx_path_sel_1ss == BB_PATH_AUTO) {
2487 p_div->stop_path_div = false;
2488 tx_path_sel_1ss = p_div->default_tx_path;
2489 } else { /* @BB_PATH_AB, BB_PATH_A, BB_PATH_B*/
2490 p_div->stop_path_div = true;
2491 }
2492 }
2493 #else
2494 tx_path_sel_1ss = tx_path_en;
2495 #endif
2496
2497 /*@[TX Antenna Setting] ==========================================*/
2498 phydm_config_tx_path_8822b(dm, tx_path_en,
2499 tx_path_sel_1ss, tx_path_sel_1ss);
2500
2501 /*@[RX Antenna Setting] ==========================================*/
2502 phydm_config_rx_path_8822b(dm, rx_path);
2503
2504 /* @MP driver need to support path-B TX\RX */
2505 while (1) {
2506 counter++;
2507 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
2508 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREG_MASK, 0x00001);
2509
2510 ODM_delay_us(2);
2511 rf_reg33 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x33,
2512 RFREG_MASK);
2513
2514 if (rf_reg33 == 0x00001 &&
2515 (config_phydm_read_rf_check_8822b(rf_reg33))) {
2516 break;
2517 } else if (counter == 100) {
2518 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2519 "Fail, write RF mode table fail\n");
2520 return false;
2521 }
2522 }
2523
2524 if (*dm->mp_mode || *dm->antenna_test || dm->normal_rx_path ||
2525 tx_path_sel_1ss == BB_PATH_B || tx_path_sel_1ss == BB_PATH_AUTO) {
2526 /* @0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e */
2527 /* @0xef 0x00000 suggested by Lucas*/
2528 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
2529 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREG_MASK, 0x00001);
2530 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREG_MASK, 0x00034);
2531 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREG_MASK, 0x4080e);
2532 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x00000);
2533 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2534 "MP/Ant test mode, support path-B TRX\n");
2535 } else {
2536 /* @0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c */
2537 /* @0xef 0x00000 */
2538 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
2539 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREG_MASK, 0x00001);
2540 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREG_MASK, 0x00034);
2541 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREG_MASK, 0x4080c);
2542 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x00000);
2543 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2544 "Normal mode, not support path-B TRX\n");
2545 }
2546
2547 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x00000);
2548
2549 /* Toggle igi to let RF enter RX mode, */
2550 /* @because BB doesn't send 3-wire command when RX path is enable */
2551 phydm_igi_toggle_8822b(dm);
2552
2553 /* @Modify CCA parameters */
2554 phydm_ccapar_by_rfe_8822b(dm);
2555
2556 /* @HW Setting depending on RFE type & band */
2557 phydm_rfe_8822b(dm, central_ch_8822b);
2558
2559 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Set Success\n");
2560 return true;
2561 }
2562
2563 __iram_odm_func__
2564 boolean
config_phydm_parameter_init_8822b(struct dm_struct * dm,enum odm_parameter_init type)2565 config_phydm_parameter_init_8822b(struct dm_struct *dm,
2566 enum odm_parameter_init type)
2567 {
2568 if (type == ODM_PRE_SETTING) {
2569 odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x0);
2570 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2571 "Pre set: disable OFDM/CCK block\n");
2572 } else if (type == ODM_POST_SETTING) {
2573 odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x3);
2574 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2575 "Post set: enable OFDM/CCK block\n");
2576 } else {
2577 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Wrong type!!\n", __func__);
2578 return false;
2579 }
2580
2581 return true;
2582 }
2583
2584 /* @======================================================================== */
2585 #endif /*PHYDM_FW_API_ENABLE_8822B == 1*/
2586 #endif /* RTL8822B_SUPPORT == 1 */
2587