1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
18 #if RT_PLATFORM == PLATFORM_MACOSX
19 #include "phydm_precomp.h"
20 #else
21 #include "../phydm_precomp.h"
22 #endif
23 #else
24 #include "../../phydm_precomp.h"
25 #endif
26
27 #if (RTL8703B_SUPPORT == 1)
28
29 /*---------------------------Define Local Constant---------------------------*/
30 /* IQK */
31 #define IQK_DELAY_TIME_8703B 10
32 #define LCK_DELAY_TIME_8703B 100
33
34 /* LTE_COEX */
35 #define REG_LTECOEX_CTRL 0x07C0
36 #define REG_LTECOEX_WRITE_DATA 0x07C4
37 #define REG_LTECOEX_READ_DATA 0x07C8
38 #define REG_LTECOEX_PATH_CONTROL 0x70
39
40 /* 2010/04/25 MH Define the max tx power tracking tx agc power. */
41 #define ODM_TXPWRTRACK_MAX_IDX8703B 6
42
43 #define idx_0xc94 0
44 #define idx_0xc80 1
45 #define idx_0xc4c 2
46
47 #define idx_0xc14 0
48 #define idx_0xca0 1
49
50 #define KEY 0
51 #define VAL 1
52
53 /*---------------------------Define Local Constant---------------------------*/
54
55 /* 3============================================================
56 * 3 Tx Power Tracking
57 * 3============================================================ */
58
set_iqk_matrix_8703b(struct dm_struct * dm,u8 OFDM_index,u8 rf_path,s32 iqk_result_x,s32 iqk_result_y)59 void set_iqk_matrix_8703b(struct dm_struct *dm, u8 OFDM_index, u8 rf_path,
60 s32 iqk_result_x, s32 iqk_result_y)
61 {
62 s32 ele_A = 0, ele_D = 0, ele_C = 0, value32;
63 s32 ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0;
64
65 rf_path = RF_PATH_A;
66
67 if (OFDM_index >= OFDM_TABLE_SIZE)
68 OFDM_index = OFDM_TABLE_SIZE - 1;
69 else if (OFDM_index < 0)
70 OFDM_index = 0;
71
72 if (iqk_result_x != 0 && (*dm->band_type == ODM_BAND_2_4G)) {
73 /* new element D */
74 ele_D = (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22;
75 ele_D_ext = (((iqk_result_x * ele_D) >> 7) & 0x01);
76
77 /* new element A */
78 if ((iqk_result_x & 0x00000200) != 0) /* consider minus */
79 iqk_result_x = iqk_result_x | 0xFFFFFC00;
80 ele_A = ((iqk_result_x * ele_D) >> 8) & 0x000003FF;
81 ele_A_ext = ((iqk_result_x * ele_D) >> 7) & 0x1;
82 /* new element C */
83 if ((iqk_result_y & 0x00000200) != 0)
84 iqk_result_y = iqk_result_y | 0xFFFFFC00;
85 ele_C = ((iqk_result_y * ele_D) >> 8) & 0x000003FF;
86 ele_C_ext = ((iqk_result_y * ele_D) >> 7) & 0x1;
87
88 switch (rf_path) {
89 case RF_PATH_A:
90 /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */
91 /* write 0xc80 */
92 value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
93 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
94 /* write 0xc94 */
95 value32 = (ele_C & 0x000003C0) >> 6;
96 odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
97 /* write 0xc4c */
98 value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29);
99 value32 = (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)))) | value32;
100 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
101 break;
102 case RF_PATH_B:
103 /* write new elements A, C, D to regC88, regC9C, regC4C, and element B is always 0 */
104 /* write 0xc88 */
105 value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
106 odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
107 /* write 0xc9c */
108 value32 = (ele_C & 0x000003C0) >> 6;
109 odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
110 /* write 0xc4c */
111 value32 = (ele_D_ext << 24) | (ele_A_ext << 27) | (ele_C_ext << 25);
112 value32 = (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(24) | BIT(27) | BIT(25)))) | value32;
113 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
114 break;
115 default:
116 break;
117 }
118 } else {
119 switch (rf_path) {
120 case RF_PATH_A:
121 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
122 odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
123 value32 = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)));
124 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
125 break;
126
127 case RF_PATH_B:
128 odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
129 odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
130 value32 = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(24) | BIT(27) | BIT(25)));
131 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
132 break;
133
134 default:
135 break;
136 }
137 }
138
139 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
140 "TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n",
141 (rf_path == RF_PATH_A ? 'A' : 'B'), (u32)iqk_result_x,
142 (u32)iqk_result_y, (u32)ele_A, (u32)ele_C, (u32)ele_D,
143 (u32)ele_A_ext, (u32)ele_C_ext, (u32)ele_D_ext);
144 }
145
set_cck_filter_coefficient_8703b(struct dm_struct * dm,u8 cck_swing_index)146 void set_cck_filter_coefficient_8703b(struct dm_struct *dm, u8 cck_swing_index)
147 {
148 odm_write_1byte(dm, 0xa22, cck_swing_table_ch1_ch14_88f[cck_swing_index][0]);
149 odm_write_1byte(dm, 0xa23, cck_swing_table_ch1_ch14_88f[cck_swing_index][1]);
150 odm_write_1byte(dm, 0xa24, cck_swing_table_ch1_ch14_88f[cck_swing_index][2]);
151 odm_write_1byte(dm, 0xa25, cck_swing_table_ch1_ch14_88f[cck_swing_index][3]);
152 odm_write_1byte(dm, 0xa26, cck_swing_table_ch1_ch14_88f[cck_swing_index][4]);
153 odm_write_1byte(dm, 0xa27, cck_swing_table_ch1_ch14_88f[cck_swing_index][5]);
154 odm_write_1byte(dm, 0xa28, cck_swing_table_ch1_ch14_88f[cck_swing_index][6]);
155 odm_write_1byte(dm, 0xa29, cck_swing_table_ch1_ch14_88f[cck_swing_index][7]);
156 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch1_ch14_88f[cck_swing_index][8]);
157 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch1_ch14_88f[cck_swing_index][9]);
158 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch1_ch14_88f[cck_swing_index][10]);
159 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch1_ch14_88f[cck_swing_index][11]);
160 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch1_ch14_88f[cck_swing_index][12]);
161 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch1_ch14_88f[cck_swing_index][13]);
162 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch1_ch14_88f[cck_swing_index][14]);
163 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch1_ch14_88f[cck_swing_index][15]);
164 }
165
do_iqk_8703b(void * dm_void,u8 delta_thermal_index,u8 thermal_value,u8 threshold)166 void do_iqk_8703b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
167 u8 threshold)
168 {
169 struct dm_struct *dm = (struct dm_struct *)dm_void;
170 odm_reset_iqk_result(dm);
171 dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
172 halrf_iqk_trigger(dm, false);
173 }
174
175 /*-----------------------------------------------------------------------------
176 * Function: odm_TxPwrTrackSetPwr88E()
177 *
178 * Overview: 88E change all channel tx power accordign to flag.
179 * OFDM & CCK are all different.
180 *
181 * Input: NONE
182 *
183 * Output: NONE
184 *
185 * Return: NONE
186 *
187 * Revised History:
188 * When Who Remark
189 * 04/23/2012 MHC Create version 0.
190 *
191 *---------------------------------------------------------------------------*/
odm_tx_pwr_track_set_pwr_8703b(void * dm_void,enum pwrtrack_method method,u8 rf_path,u8 channel_mapped_index)192 void odm_tx_pwr_track_set_pwr_8703b(void *dm_void, enum pwrtrack_method method,
193 u8 rf_path, u8 channel_mapped_index)
194 {
195 struct dm_struct *dm = (struct dm_struct *)dm_void;
196 struct _ADAPTER *adapter = dm->adapter;
197 u8 pwr_tracking_limit_ofdm = 34; /* +0dB */
198 u8 pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1; /* -2dB */
199 u8 tx_rate = 0xFF;
200 u8 final_ofdm_swing_index = 0;
201 u8 final_cck_swing_index = 0;
202 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
203 struct _hal_rf_ *rf = &(dm->rf_table);
204
205 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
206 #if (MP_DRIVER == 1) /*win MP */
207 PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
208
209 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
210 #else /*win normal*/
211 PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo);
212 if (!mgnt_info->ForcedDataRate) { /*auto rate*/
213 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
214 } else
215 tx_rate = (u8)mgnt_info->ForcedDataRate;
216 #endif
217 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
218 if (*dm->mp_mode == true) { /*CE MP*/
219 #ifdef CONFIG_MP_INCLUDED
220 PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
221
222 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
223 #endif
224 } else { /*CE normal*/
225 u16 rate = *(dm->forced_data_rate);
226
227 if (!rate) { /*auto rate*/
228 if (dm->number_linked_client != 0)
229 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
230 else
231 tx_rate = rf->p_rate_index;
232 } else /*force rate*/
233 tx_rate = (u8)rate;
234 }
235 #endif
236
237 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>ODM_TxPwrTrackSetPwr8703B\n");
238
239 if (tx_rate != 0xFF) {
240 /*2 CCK*/
241 if ((tx_rate >= MGN_1M && tx_rate <= MGN_5_5M) || tx_rate == MGN_11M)
242 pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1;
243 /*2 OFDM*/
244 else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
245 pwr_tracking_limit_ofdm = 36; /*+3dB*/
246 else if (tx_rate == MGN_54M)
247 pwr_tracking_limit_ofdm = 34; /*+2dB*/
248 /*2 HT*/
249 else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2)) /*QPSK/BPSK*/
250 pwr_tracking_limit_ofdm = 38; /*+4dB*/
251 else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4)) /*16QAM*/
252 pwr_tracking_limit_ofdm = 36; /*+3dB*/
253 else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7)) /*64QAM*/
254 pwr_tracking_limit_ofdm = 34; /*+2dB*/
255 else
256 pwr_tracking_limit_ofdm = cali_info->default_ofdm_index; /*Default OFDM index = 30*/
257 }
258 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "tx_rate=0x%x, pwr_tracking_limit=%d\n",
259 tx_rate, pwr_tracking_limit_ofdm);
260
261 if (method == TXAGC) {
262 u32 pwr = 0, tx_agc = 0;
263
264 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
265 "odm_TxPwrTrackSetPwr8703B CH=%d\n", *(dm->channel));
266
267 cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path];
268
269 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
270 #if (MP_DRIVER != 1)
271 cali_info->modify_tx_agc_flag_path_a = true;
272 cali_info->modify_tx_agc_flag_path_a_cck = true;
273
274 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, CCK);
275 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
276 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
277 #else
278 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
279 pwr += cali_info->power_index_offset[rf_path];
280 odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
281 tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
282 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc);
283 RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: CCK Tx-rf(A) Power = 0x%x\n", tx_agc));
284
285 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
286 pwr += (cali_info->bb_swing_idx_ofdm[rf_path] - cali_info->bb_swing_idx_ofdm_base[rf_path]);
287 tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
288 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
289 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
290 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
291 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
292 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc);
293 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc);
294 RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: OFDM Tx-rf(A) Power = 0x%x\n", tx_agc));
295 #endif
296 #endif
297 } else if (method == BBSWING) {
298 final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
299 final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
300
301 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
302 " cali_info->default_ofdm_index=%d, cali_info->DefaultCCKIndex=%d, cali_info->absolute_ofdm_swing_idx[rf_path]=%d, cali_info->remnant_cck_swing_idx=%d rf_path = %d\n",
303 cali_info->default_ofdm_index,
304 cali_info->default_cck_index,
305 cali_info->absolute_ofdm_swing_idx[rf_path],
306 cali_info->remnant_cck_swing_idx, rf_path);
307
308 /* Adjust BB swing by OFDM IQ matrix */
309 if (final_ofdm_swing_index >= pwr_tracking_limit_ofdm)
310 final_ofdm_swing_index = pwr_tracking_limit_ofdm;
311 else if (final_ofdm_swing_index < 0)
312 final_ofdm_swing_index = 0;
313
314 if (final_cck_swing_index >= CCK_TABLE_SIZE_88F)
315 final_cck_swing_index = CCK_TABLE_SIZE_88F - 1;
316 else if (cali_info->bb_swing_idx_cck < 0)
317 final_cck_swing_index = 0;
318
319 set_iqk_matrix_8703b(dm, final_ofdm_swing_index, RF_PATH_A,
320 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
321 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
322
323 set_cck_filter_coefficient_8703b(dm, final_cck_swing_index);
324
325 } else if (method == MIX_MODE) {
326 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
327 " dm->default_ofdm_index=%d, dm->DefaultCCKIndex=%d, dm->absolute_ofdm_swing_idx[rf_path]=%d, dm->remnant_cck_swing_idx=%d rf_path = %d\n",
328 cali_info->default_ofdm_index,
329 cali_info->default_cck_index,
330 cali_info->absolute_ofdm_swing_idx[rf_path],
331 cali_info->remnant_cck_swing_idx, rf_path);
332
333 final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
334 final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
335
336 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
337 " dm->default_ofdm_index=%d, dm->DefaultCCKIndex=%d, dm->absolute_ofdm_swing_idx[rf_path]=%d rf_path = %d\n",
338 cali_info->default_ofdm_index,
339 cali_info->default_cck_index,
340 cali_info->absolute_ofdm_swing_idx[rf_path], rf_path);
341
342 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
343 " final_ofdm_swing_index=%d, final_cck_swing_index=%d rf_path=%d\n",
344 final_ofdm_swing_index, final_cck_swing_index, rf_path);
345
346 if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) { /*BBSwing higher then Limit*/
347 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
348
349 set_iqk_matrix_8703b(dm, pwr_tracking_limit_ofdm, RF_PATH_A,
350 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
351 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
352
353 cali_info->modify_tx_agc_flag_path_a = true;
354 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
355 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
356
357 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
358 " ******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
359 pwr_tracking_limit_ofdm,
360 cali_info->remnant_ofdm_swing_idx[rf_path]);
361 } else if (final_ofdm_swing_index < 0) {
362 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
363
364 set_iqk_matrix_8703b(dm, 0, RF_PATH_A,
365 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
366 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
367
368 cali_info->modify_tx_agc_flag_path_a = true;
369 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
370 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
371
372 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
373 " ******Path_A Lower then BBSwing lower bound 0, Remnant tx_agc value = %d\n",
374 cali_info->remnant_ofdm_swing_idx[rf_path]);
375 } else {
376 set_iqk_matrix_8703b(dm, final_ofdm_swing_index, RF_PATH_A,
377 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
378 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
379
380 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
381 " ******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n",
382 final_ofdm_swing_index);
383
384 if (cali_info->modify_tx_agc_flag_path_a) { /*If tx_agc has changed, reset tx_agc again*/
385 cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
386 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
387 odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
388 cali_info->modify_tx_agc_flag_path_a = false;
389
390 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
391 " ******Path_A dm->Modify_TxAGC_Flag = false\n");
392 }
393 }
394 if (final_cck_swing_index > pwr_tracking_limit_cck) {
395 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
396 " final_cck_swing_index(%d) > pwr_tracking_limit_cck(%d)\n",
397 final_cck_swing_index, pwr_tracking_limit_cck);
398
399 cali_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit_cck;
400
401 set_cck_filter_coefficient_8703b(dm, pwr_tracking_limit_cck);
402
403 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
404 "******Path_A CCK Over Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx = %d\n",
405 pwr_tracking_limit_cck,
406 cali_info->remnant_cck_swing_idx);
407
408 cali_info->modify_tx_agc_flag_path_a_cck = true;
409
410 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
411
412 } else if (final_cck_swing_index < 0) { /* Lowest CCK index = 0 */
413
414 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
415 " final_cck_swing_index(%d) < 0 pwr_tracking_limit_cck(%d)\n",
416 final_cck_swing_index, pwr_tracking_limit_cck);
417
418 cali_info->remnant_cck_swing_idx = final_cck_swing_index;
419
420 set_cck_filter_coefficient_8703b(dm, 0);
421
422 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
423 "******Path_A CCK Under Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx = %d\n",
424 0, cali_info->remnant_cck_swing_idx);
425
426 cali_info->modify_tx_agc_flag_path_a_cck = true;
427
428 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
429
430 } else {
431 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
432 " else final_cck_swing_index=%d pwr_tracking_limit_cck(%d)\n",
433 final_cck_swing_index, pwr_tracking_limit_cck);
434
435 set_cck_filter_coefficient_8703b(dm, final_cck_swing_index);
436
437 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
438 "******Path_A CCK Compensate with BBSwing, final_cck_swing_index = %d\n",
439 final_cck_swing_index);
440
441 cali_info->modify_tx_agc_flag_path_a_cck = false;
442
443 cali_info->remnant_cck_swing_idx = 0;
444
445 if (cali_info->modify_tx_agc_flag_path_a_cck) { /*If tx_agc has changed, reset tx_agc again*/
446 cali_info->remnant_cck_swing_idx = 0;
447 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
448 cali_info->modify_tx_agc_flag_path_a_cck = false;
449 }
450 }
451
452 } else {
453 return; /* This method is not supported. */
454 }
455 }
456
get_delta_swing_table_8703b(void * dm_void,u8 ** temperature_up_a,u8 ** temperature_down_a,u8 ** temperature_up_b,u8 ** temperature_down_b)457 void get_delta_swing_table_8703b(void *dm_void, u8 **temperature_up_a,
458 u8 **temperature_down_a, u8 **temperature_up_b,
459 u8 **temperature_down_b)
460 {
461 struct dm_struct *dm = (struct dm_struct *)dm_void;
462 struct _ADAPTER *adapter = dm->adapter;
463 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
464 struct _hal_rf_ *rf = &(dm->rf_table);
465 u8 tx_rate = 0xFF;
466 u8 channel = *dm->channel;
467
468 if (*dm->mp_mode == true) {
469 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
470 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
471 #if (MP_DRIVER == 1)
472 PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
473
474 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
475 #endif
476 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
477 #ifdef CONFIG_MP_INCLUDED
478 PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
479
480 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
481 #endif
482 #endif
483 #endif
484 } else {
485 u16 rate = *(dm->forced_data_rate);
486
487 if (!rate) { /*auto rate*/
488 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
489 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
490 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
491 if (dm->number_linked_client != 0)
492 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
493 else
494 tx_rate = rf->p_rate_index;
495 #endif
496 } else /*force rate*/
497 tx_rate = (u8)rate;
498 }
499
500 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Power Tracking tx_rate=0x%X\n",
501 tx_rate);
502
503 if (1 <= channel && channel <= 14) {
504 if (IS_CCK_RATE(tx_rate)) {
505 *temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
506 *temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
507 *temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
508 *temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
509 } else {
510 *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
511 *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
512 *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
513 *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
514 }
515 } else {
516 *temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
517 *temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
518 *temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
519 *temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
520 }
521
522 return;
523 }
524
get_delta_swing_xtal_table_8703b(void * dm_void,s8 ** temperature_up_xtal,s8 ** temperature_down_xtal)525 void get_delta_swing_xtal_table_8703b(void *dm_void, s8 **temperature_up_xtal,
526 s8 **temperature_down_xtal)
527 {
528 struct dm_struct *dm = (struct dm_struct *)dm_void;
529 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
530
531 *temperature_up_xtal = cali_info->delta_swing_table_xtal_p;
532 *temperature_down_xtal = cali_info->delta_swing_table_xtal_n;
533 }
534
odm_txxtaltrack_set_xtal_8703b(void * dm_void)535 void odm_txxtaltrack_set_xtal_8703b(void *dm_void)
536 {
537 struct dm_struct *dm = (struct dm_struct *)dm_void;
538 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
539
540 s8 crystal_cap;
541
542 crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x3F;
543 crystal_cap = crystal_cap + cali_info->xtal_offset;
544
545 if (crystal_cap < 0)
546 crystal_cap = 0;
547 else if (crystal_cap > 63)
548 crystal_cap = 63;
549
550 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
551 "crystal_cap(%d)= dm->dm_cfo_track.crystal_cap_default(%d) + cali_info->xtal_offset(%d)\n",
552 crystal_cap, dm->dm_cfo_track.crystal_cap_default, cali_info->xtal_offset);
553
554 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
555
556 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "crystal_cap(0x2c) 0x%X\n",
557 odm_get_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000));
558 }
559
configure_txpower_track_8703b(struct txpwrtrack_cfg * config)560 void configure_txpower_track_8703b(struct txpwrtrack_cfg *config)
561 {
562 config->swing_table_size_cck = CCK_TABLE_SIZE;
563 config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
564 config->threshold_iqk = IQK_THRESHOLD;
565 config->average_thermal_num = AVG_THERMAL_NUM_8703B;
566 config->rf_path_count = MAX_PATH_NUM_8703B;
567 config->thermal_reg_addr = RF_T_METER_8703B;
568
569 config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr_8703b;
570 config->do_iqk = do_iqk_8703b;
571 config->phy_lc_calibrate = halrf_lck_trigger;
572 config->get_delta_swing_table = get_delta_swing_table_8703b;
573 config->get_delta_swing_xtal_table = get_delta_swing_xtal_table_8703b;
574 config->odm_txxtaltrack_set_xtal = odm_txxtaltrack_set_xtal_8703b;
575 }
576
577 /* 1 7. IQK */
578 #define MAX_TOLERANCE 5
579 #define IQK_DELAY_TIME 1 /* ms */
580
581 u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_path_a_iqk_8703b(struct dm_struct * dm)582 phy_path_a_iqk_8703b(
583 struct dm_struct *dm)
584 {
585 u32 reg_eac, reg_e94, reg_e9c;
586 u8 result = 0x00, ktime;
587 u32 original_path, original_gnt;
588
589 RF_DBG(dm, DBG_RF_IQK, "[IQK]TX IQK!\n");
590
591 /*8703b IQK v2.0 20150713*/
592 /*1 Tx IQK*/
593 /*IQK setting*/
594 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
595 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
596 /*path-A IQK setting*/
597 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
598 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
599 odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
600 odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
601 /* odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x8214010a);*/
602 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x8214030f);
603 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28110000);
604 odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
605 odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
606
607 /*LO calibration setting*/
608 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x00462911);
609
610 /*leave IQK mode*/
611 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
612
613 /*PA, PAD setting*/
614 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
615 odm_set_rf_reg(dm, RF_PATH_A, RF_0x55, 0x0007f, 0x7);
616 odm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, RFREGOFFSETMASK, 0x0d400);
617
618 /*enter IQK mode*/
619 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
620
621 #if 1
622 /*path setting*/
623 /*Save Original path Owner, Original GNT*/
624 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
625 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
626 ODM_delay_ms(1);
627 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
628
629 /*set GNT_WL=1/GNT_BT=0 and path owner to WiFi for pause BT traffic*/
630 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
631 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
632 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1); /*0x70[26] =1 --> path Owner to WiFi*/
633 #endif
634
635 /*One shot, path A LOK & IQK*/
636 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
637 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
638
639 /* delay x ms */
640 ODM_delay_ms(IQK_DELAY_TIME_8703B);
641 ktime = 0;
642 while ((odm_get_bb_reg(dm, R_0xe90, MASKDWORD) == 0) && ktime < 10) {
643 ODM_delay_ms(5);
644 ktime++;
645 }
646
647 #if 1
648 /*path setting*/
649 /*Restore GNT_WL/GNT_BT and path owner*/
650 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
651 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
652 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
653
654 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
655 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
656 ODM_delay_ms(1);
657 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
658
659 #endif
660
661 /*leave IQK mode*/
662 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
663 /* PA/PAD controlled by 0x0*/
664 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
665
666 /* Check failed*/
667 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
668 reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
669 reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
670 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
671 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
672 reg_e9c);
673 /*monitor image power before & after IQK*/
674 RF_DBG(dm, DBG_RF_IQK,
675 "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
676 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
677 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
678
679 if (!(reg_eac & BIT(28)) &&
680 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
681 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
682
683 result |= 0x01;
684
685 return result;
686 }
687
688 u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_path_a_rx_iqk_8703b(struct dm_struct * dm)689 phy_path_a_rx_iqk_8703b(
690 struct dm_struct *dm)
691 {
692 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp, tmp;
693 u8 result = 0x00, ktime;
694 u32 original_path, original_gnt;
695
696 RF_DBG(dm, DBG_RF_IQK, "[IQK]RX IQK:Get TXIMR setting\n");
697 /* 1 Get TX_XY */
698
699 /* IQK setting */
700 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
701 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
702
703 /* path-A IQK setting */
704 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
705 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
706 odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
707 odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
708
709 /* odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82160c1f); */
710 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x8216000f);
711 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28110000);
712 odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
713 odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
714
715 /* LO calibration setting */
716 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a911);
717
718 /* leave IQK mode */
719 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
720
721 /* modify RXIQK mode table */
722 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
723 odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
724 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x00007);
725 /*IQK PA off*/
726 /* odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7fb7); */
727 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0x57db7);
728
729 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
730
731 #if 1
732 /*path setting*/
733 /*Save Original path Owner, Original GNT*/
734 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
735 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
736 ODM_delay_ms(1);
737 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
738
739 /*set GNT_WL=1/GNT_BT=0 and path owner to WiFi for pause BT traffic*/
740 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
741 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
742 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1); /*0x70[26] =1 --> path Owner to WiFi*/
743 #endif
744
745 /* One shot, path A LOK & IQK */
746 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
747 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
748
749 /* delay x ms */
750 ODM_delay_ms(IQK_DELAY_TIME_8703B);
751 ktime = 0;
752 while ((odm_get_bb_reg(dm, R_0xe90, MASKDWORD) == 0) && ktime < 10) {
753 ODM_delay_ms(5);
754 ktime++;
755 }
756
757 #if 1
758 /*path setting*/
759 /*Restore GNT_WL/GNT_BT and path owner*/
760 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
761 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
762 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
763
764 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
765 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
766 ODM_delay_ms(1);
767 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
768
769 #endif
770
771 /* leave IQK mode */
772 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
773
774 /* Check failed */
775 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
776 reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
777 reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
778 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
779 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
780 reg_e9c);
781 /*monitor image power before & after IQK*/
782 RF_DBG(dm, DBG_RF_IQK,
783 "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
784 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
785 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
786
787 /* Allen 20131125 */
788 tmp = (reg_e9c & 0x03FF0000) >> 16;
789 if ((tmp & 0x200) > 0)
790 tmp = 0x400 - tmp;
791
792 if (!(reg_eac & BIT(28)) &&
793 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
794 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
795
796 result |= 0x01;
797 else /* if Tx not OK, ignore Rx */
798 return result;
799
800 u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
801 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, u4tmp);
802 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe40 = 0x%x u4tmp = 0x%x\n",
803 odm_get_bb_reg(dm, REG_TX_IQK, MASKDWORD), u4tmp);
804
805 /* 1 RX IQK */
806 RF_DBG(dm, DBG_RF_IQK, "[IQK]RX IQK\n");
807
808 /* IQK setting */
809 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
810
811 /* path-A IQK setting */
812 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
813 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
814 odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
815 odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
816
817 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82110000);
818 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28160c1f);
819 /* odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x2816001f);*/
820 odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
821 odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
822
823 /* LO calibration setting */
824 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
825
826 /* modify RXIQK mode table */
827 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
828 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
829 odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
830 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x00007);
831 /*PA off*/
832 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7d77);
833
834 /*PA, PAD setting*/
835 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
836 odm_set_rf_reg(dm, RF_PATH_A, RF_0x55, 0x0007f, 0x5);
837
838 /*enter IQK mode*/
839 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
840
841 #if 1
842 /*path setting*/
843 /*Save Original path Owner, Original GNT*/
844 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
845 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
846 ODM_delay_ms(1);
847 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
848
849 /*set GNT_WL=1/GNT_BT=0 and path owner to WiFi for pause BT traffic*/
850 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
851 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
852 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1); /*0x70[26] =1 --> path Owner to WiFi*/
853 #endif
854
855 /* One shot, path A LOK & IQK */
856 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
857 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
858
859 /* delay x ms */
860 ODM_delay_ms(IQK_DELAY_TIME_8703B);
861 ktime = 0;
862 while ((odm_get_bb_reg(dm, R_0xe90, MASKDWORD) == 0) && ktime < 10) {
863 ODM_delay_ms(5);
864 ktime++;
865 }
866
867 #if 1
868 /*path setting*/
869 /*Restore GNT_WL/GNT_BT and path owner*/
870 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
871 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
872 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
873
874 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
875 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
876 ODM_delay_ms(1);
877 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
878
879 #endif
880
881 /*leave IQK mode*/
882 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
883 /* PA/PAD controlled by 0x0 */
884 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
885
886 /* Check failed */
887 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
888 reg_ea4 = odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
889 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
890 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", reg_ea4,
891 reg_eac);
892 /* monitor image power before & after IQK */
893 RF_DBG(dm, DBG_RF_IQK,
894 "[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
895 odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
896 odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
897
898 /* Allen 20131125 */
899 tmp = (reg_eac & 0x03FF0000) >> 16;
900 if ((tmp & 0x200) > 0)
901 tmp = 0x400 - tmp;
902
903 if (!(reg_eac & BIT(27)) && /*if Tx is OK, check whether Rx is OK*/
904 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
905 (((reg_eac & 0x03FF0000) >> 16) != 0x36) &&
906 (((reg_ea4 & 0x03FF0000) >> 16) < 0x11a) &&
907 (((reg_ea4 & 0x03FF0000) >> 16) > 0xe6) &&
908 tmp < 0x1a)
909 result |= 0x02;
910 else /* if Tx not OK, ignore Rx */
911 RF_DBG(dm, DBG_RF_IQK, "path A Rx IQK fail!!\n");
912
913 return result;
914 }
915
_phy_path_a_fill_iqk_matrix8703b(struct dm_struct * dm,boolean is_iqk_ok,s32 result[][8],u8 final_candidate,boolean is_tx_only)916 void _phy_path_a_fill_iqk_matrix8703b(struct dm_struct *dm, boolean is_iqk_ok,
917 s32 result[][8], u8 final_candidate,
918 boolean is_tx_only)
919 {
920 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
921 u32 oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0;
922 s32 Y, TX0_C;
923
924 RF_DBG(dm, DBG_RF_IQK, "[IQK]path A IQ Calibration %s !\n",
925 (is_iqk_ok) ? "Success" : "Failed");
926
927 if (final_candidate == 0xFF)
928 return;
929
930 else if (is_iqk_ok) {
931 oldval_0 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
932
933 X = result[final_candidate][0];
934 if ((X & 0x00000200) != 0)
935 X = X | 0xFFFFFC00;
936 TX0_A = (X * oldval_0) >> 8;
937 RF_DBG(dm, DBG_RF_IQK,
938 "[IQK]X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A,
939 oldval_0);
940 tmp0xc80 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) & 0xfffffc00) | (TX0_A & 0x3ff);
941 tmp0xc4c = (((X * oldval_0 >> 7) & 0x1) << 31) | (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & 0x7fffffff);
942
943 Y = result[final_candidate][1];
944 if ((Y & 0x00000200) != 0)
945 Y = Y | 0xFFFFFC00;
946
947 /* 2 Tx IQC */
948 TX0_C = (Y * oldval_0) >> 8;
949 RF_DBG(dm, DBG_RF_IQK, "[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C);
950
951 tmp0xc94 = (((TX0_C & 0x3C0) >> 6) << 28) | (odm_get_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKDWORD) & 0x0fffffff);
952
953 cali_info->tx_iqc_8703b[idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
954 cali_info->tx_iqc_8703b[idx_0xc94][VAL] = tmp0xc94;
955
956 tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F) << 16;
957
958 cali_info->tx_iqc_8703b[idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
959 cali_info->tx_iqc_8703b[idx_0xc80][VAL] = tmp0xc80;
960
961 tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y * oldval_0 >> 7) & 0x1) << 29);
962
963 cali_info->tx_iqc_8703b[idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
964 cali_info->tx_iqc_8703b[idx_0xc4c][VAL] = tmp0xc4c;
965
966 if (is_tx_only) {
967 RF_DBG(dm, DBG_RF_IQK, "[IQK]%s only Tx OK\n",
968 __func__);
969
970 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
971 cali_info->rx_iqc_8703b[idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
972 cali_info->rx_iqc_8703b[idx_0xca0][VAL] = 0xfffffff & odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
973 cali_info->rx_iqc_8703b[idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
974 cali_info->rx_iqc_8703b[idx_0xc14][VAL] = 0x40000100;
975 return;
976 }
977
978 reg = result[final_candidate][2];
979 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
980 if (RTL_ABS(reg, 0x100) >= 16)
981 reg = 0x100;
982 #endif
983
984 /* 2 Rx IQC */
985 tmp0xc14 = (0x40000100 & 0xfffffc00) | reg;
986
987 reg = result[final_candidate][3] & 0x3F;
988 tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10);
989
990 cali_info->rx_iqc_8703b[idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
991 cali_info->rx_iqc_8703b[idx_0xc14][VAL] = tmp0xc14;
992
993 reg = (result[final_candidate][3] >> 6) & 0xF;
994 tmp0xca0 = odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0x0fffffff) | (reg << 28);
995
996 cali_info->rx_iqc_8703b[idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
997 cali_info->rx_iqc_8703b[idx_0xca0][VAL] = tmp0xca0;
998 }
999 }
1000
1001 #if 0
1002 void
1003 _phy_path_b_fill_iqk_matrix8703b(
1004 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1005 struct dm_struct *dm,
1006 #else
1007 void *adapter,
1008 #endif
1009 boolean is_iqk_ok,
1010 s32 result[][8],
1011 u8 final_candidate,
1012 boolean is_tx_only /* do Tx only */
1013 )
1014 {
1015 u32 oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0;
1016 s32 Y, TX1_C;
1017 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1018 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1019 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1020 struct dm_struct *dm = &hal_data->odmpriv;
1021 #endif
1022 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1023 struct dm_struct *dm = &hal_data->DM_OutSrc;
1024 #endif
1025 #endif
1026 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1027
1028 RF_DBG(dm, DBG_RF_IQK, "[IQK]path B IQ Calibration %s !\n",
1029 (is_iqk_ok) ? "Success" : "Failed");
1030
1031 if (final_candidate == 0xFF)
1032 return;
1033
1034 else if (is_iqk_ok) {
1035 oldval_1 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
1036
1037
1038 X = result[final_candidate][4];
1039 if ((X & 0x00000200) != 0)
1040 X = X | 0xFFFFFC00;
1041 TX1_A = (X * oldval_1) >> 8;
1042 RF_DBG(dm, DBG_RF_IQK, "[IQK]X = 0x%x, TX1_A = 0x%x\n", X,
1043 TX1_A);
1044
1045 tmp0xc80 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) & 0xfffffc00) | (TX1_A & 0x3ff);
1046 tmp0xc4c = (((X * oldval_1 >> 7) & 0x1) << 31) | (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & 0x7fffffff);
1047
1048 Y = result[final_candidate][5];
1049 if ((Y & 0x00000200) != 0)
1050 Y = Y | 0xFFFFFC00;
1051
1052 TX1_C = (Y * oldval_1) >> 8;
1053 RF_DBG(dm, DBG_RF_IQK, "[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y,
1054 TX1_C);
1055
1056 /*2 Tx IQC*/
1057
1058 tmp0xc94 = (((TX1_C & 0x3C0) >> 6) << 28) | (odm_get_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKDWORD) & 0x0fffffff);
1059
1060 cali_info->tx_iqc_8703b[PATH_S0][idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
1061 cali_info->tx_iqc_8703b[PATH_S0][idx_0xc94][VAL] = tmp0xc94;
1062
1063 tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C & 0x3F) << 16;
1064 cali_info->tx_iqc_8703b[PATH_S0][idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
1065 cali_info->tx_iqc_8703b[PATH_S0][idx_0xc80][VAL] = tmp0xc80;
1066
1067 tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y * oldval_1 >> 7) & 0x1) << 29);
1068 cali_info->tx_iqc_8703b[PATH_S0][idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
1069 cali_info->tx_iqc_8703b[PATH_S0][idx_0xc4c][VAL] = tmp0xc4c;
1070
1071 if (is_tx_only) {
1072 RF_DBG(dm, DBG_RF_IQK, "[IQK]%s only Tx OK\n",
1073 __func__);
1074
1075 cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1076 cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][VAL] = 0x40000100;
1077 cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1078 cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][VAL] = 0x0fffffff & odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
1079 return;
1080 }
1081
1082 /* 2 Rx IQC */
1083 reg = result[final_candidate][6];
1084 tmp0xc14 = (0x40000100 & 0xfffffc00) | reg;
1085
1086 reg = result[final_candidate][7] & 0x3F;
1087 tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10);
1088
1089 cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1090 cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][VAL] = tmp0xc14;
1091
1092 reg = (result[final_candidate][7] >> 6) & 0xF;
1093 tmp0xca0 = odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0x0fffffff) | (reg << 28);
1094
1095 cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1096 cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][VAL] = tmp0xca0;
1097 }
1098 }
1099 #endif
1100
1101 boolean
odm_set_iqc_by_rfpath_8703b(struct dm_struct * dm)1102 odm_set_iqc_by_rfpath_8703b(struct dm_struct *dm)
1103 {
1104 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1105
1106 if (cali_info->tx_iqc_8703b[idx_0xc80][VAL] != 0x0 && cali_info->rx_iqc_8703b[idx_0xc14][VAL] != 0x0) {
1107 RF_DBG(dm, DBG_RF_IQK, "[IQK]reload RF IQC!!!\n");
1108 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xc80 = 0x%x!!!\n",
1109 cali_info->tx_iqc_8703b[idx_0xc80][VAL]);
1110 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xc14 = 0x%x!!!\n",
1111 cali_info->tx_iqc_8703b[idx_0xc14][VAL]);
1112
1113 /* TX IQC */
1114 odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc94][KEY], MASKH4BITS, (cali_info->tx_iqc_8703b[idx_0xc94][VAL] >> 28));
1115 odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc80][KEY], MASKDWORD, cali_info->tx_iqc_8703b[idx_0xc80][VAL]);
1116 odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc4c][KEY], BIT(31), (cali_info->tx_iqc_8703b[idx_0xc4c][VAL] >> 31));
1117 odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc4c][KEY], BIT(29), ((cali_info->tx_iqc_8703b[idx_0xc4c][VAL] & BIT(29)) >> 29));
1118
1119 /* RX IQC */
1120 odm_set_bb_reg(dm, cali_info->rx_iqc_8703b[idx_0xc14][KEY], MASKDWORD, cali_info->rx_iqc_8703b[idx_0xc14][VAL]);
1121 odm_set_bb_reg(dm, cali_info->rx_iqc_8703b[idx_0xca0][KEY], MASKDWORD, cali_info->rx_iqc_8703b[idx_0xca0][VAL]);
1122 return true;
1123
1124 } else {
1125 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQC value invalid!!!\n");
1126 return false;
1127 }
1128 }
1129
_phy_save_adda_registers8703b(struct dm_struct * dm,u32 * adda_reg,u32 * adda_backup,u32 register_num)1130 void _phy_save_adda_registers8703b(struct dm_struct *dm, u32 *adda_reg,
1131 u32 *adda_backup, u32 register_num)
1132 {
1133 u32 i;
1134
1135 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1136 if (odm_check_power_status(dm) == false)
1137 return;
1138 #endif
1139
1140 /* RF_DBG(dm,DBG_RF_IQK, "Save ADDA parameters.\n"); */
1141 for (i = 0; i < register_num; i++)
1142 adda_backup[i] = odm_get_bb_reg(dm, adda_reg[i], MASKDWORD);
1143 }
1144
_phy_save_mac_registers8703b(struct dm_struct * dm,u32 * mac_reg,u32 * mac_backup)1145 void _phy_save_mac_registers8703b(struct dm_struct *dm, u32 *mac_reg,
1146 u32 *mac_backup)
1147 {
1148 u32 i;
1149
1150 /* RF_DBG(dm,DBG_RF_IQK, "Save MAC parameters.\n"); */
1151 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1152 mac_backup[i] = odm_read_1byte(dm, mac_reg[i]);
1153
1154 mac_backup[i] = odm_read_4byte(dm, mac_reg[i]);
1155 }
1156
_phy_reload_adda_registers8703b(struct dm_struct * dm,u32 * adda_reg,u32 * adda_backup,u32 regiester_num)1157 void _phy_reload_adda_registers8703b(struct dm_struct *dm, u32 *adda_reg,
1158 u32 *adda_backup, u32 regiester_num)
1159 {
1160 u32 i;
1161
1162 /* RF_DBG(dm,DBG_RF_IQK, "Reload ADDA power saving parameters !\n"); */
1163 for (i = 0; i < regiester_num; i++)
1164 odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, adda_backup[i]);
1165 }
1166
_phy_reload_mac_registers8703b(struct dm_struct * dm,u32 * mac_reg,u32 * mac_backup)1167 void _phy_reload_mac_registers8703b(struct dm_struct *dm, u32 *mac_reg,
1168 u32 *mac_backup)
1169 {
1170 u32 i;
1171
1172 /* RF_DBG(dm,DBG_RF_IQK, "Reload MAC parameters !\n"); */
1173 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1174 odm_write_1byte(dm, mac_reg[i], (u8)mac_backup[i]);
1175
1176 odm_write_4byte(dm, mac_reg[i], mac_backup[i]);
1177 }
1178
_phy_path_adda_on8703b(struct dm_struct * dm,u32 * adda_reg,boolean is_path_a_on)1179 void _phy_path_adda_on8703b(struct dm_struct *dm, u32 *adda_reg,
1180 boolean is_path_a_on)
1181 {
1182 u32 path_on;
1183 u32 i;
1184
1185 /* RF_DBG(dm,DBG_RF_IQK, "ADDA ON.\n"); */
1186 path_on = 0x03c00014;
1187 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1188 odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, path_on);
1189 }
1190
_phy_mac_setting_calibration8703b(struct dm_struct * dm,u32 * mac_reg,u32 * mac_backup)1191 void _phy_mac_setting_calibration8703b(struct dm_struct *dm, u32 *mac_reg,
1192 u32 *mac_backup)
1193 {
1194 u32 i = 0;
1195
1196 /* RF_DBG(dm,DBG_RF_IQK, "MAC settings for Calibration.\n"); */
1197 odm_write_1byte(dm, mac_reg[i], 0x3F);
1198 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1199 odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(3))));
1200 /*remove 0x40[5]setting for coex reason */
1201 /*odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(5))));*/
1202 }
1203
1204 boolean
phy_simularity_compare_8703b(struct dm_struct * dm,s32 result[][8],u8 c1,u8 c2,boolean is2t)1205 phy_simularity_compare_8703b(struct dm_struct *dm, s32 result[][8], u8 c1,
1206 u8 c2, boolean is2t)
1207 {
1208 u32 i, j, diff, simularity_bit_map, bound = 0;
1209 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1210 boolean is_result = true;
1211
1212 /* #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
1213 /* bool is2T = IS_92C_SERIAL( hal_data->version_id);
1214 * #else */
1215 /* #endif */
1216
1217 s32 tmp1 = 0, tmp2 = 0;
1218
1219 if (is2t)
1220 bound = 8;
1221 else
1222 bound = 4;
1223
1224 /* RF_DBG(dm,DBG_RF_IQK, "===> IQK:phy_simularity_compare_8192e c1 %d c2 %d!!!\n", c1, c2); */
1225
1226 simularity_bit_map = 0;
1227
1228 for (i = 0; i < bound; i++) {
1229 if (i == 1 || i == 3 || i == 5 || i == 7) {
1230 if ((result[c1][i] & 0x00000200) != 0)
1231 tmp1 = result[c1][i] | 0xFFFFFC00;
1232 else
1233 tmp1 = result[c1][i];
1234
1235 if ((result[c2][i] & 0x00000200) != 0)
1236 tmp2 = result[c2][i] | 0xFFFFFC00;
1237 else
1238 tmp2 = result[c2][i];
1239 } else {
1240 tmp1 = result[c1][i];
1241 tmp2 = result[c2][i];
1242 }
1243
1244 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1245
1246 if (diff > MAX_TOLERANCE) {
1247 /* RF_DBG(dm,DBG_RF_IQK, "IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i]); */
1248
1249 if ((i == 2 || i == 6) && !simularity_bit_map) {
1250 if (result[c1][i] + result[c1][i + 1] == 0)
1251 final_candidate[(i / 4)] = c2;
1252 else if (result[c2][i] + result[c2][i + 1] == 0)
1253 final_candidate[(i / 4)] = c1;
1254 else
1255 simularity_bit_map = simularity_bit_map | (1 << i);
1256 } else
1257 simularity_bit_map = simularity_bit_map | (1 << i);
1258 }
1259 }
1260
1261 /* RF_DBG(dm,DBG_RF_IQK, "IQK:phy_simularity_compare_8192e simularity_bit_map %x !!!\n", simularity_bit_map); */
1262
1263 if (simularity_bit_map == 0) {
1264 for (i = 0; i < (bound / 4); i++) {
1265 if (final_candidate[i] != 0xFF) {
1266 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1267 result[3][j] = result[final_candidate[i]][j];
1268 is_result = false;
1269 }
1270 }
1271 return is_result;
1272 }
1273
1274 if (!(simularity_bit_map & 0x03)) { /*path A TX OK*/
1275 for (i = 0; i < 2; i++)
1276 result[3][i] = result[c1][i];
1277 }
1278
1279 if (!(simularity_bit_map & 0x0c)) { /*path A RX OK*/
1280 for (i = 2; i < 4; i++)
1281 result[3][i] = result[c1][i];
1282 }
1283
1284 if (!(simularity_bit_map & 0x30)) { /*path B TX OK*/
1285 for (i = 4; i < 6; i++)
1286 result[3][i] = result[c1][i];
1287 }
1288
1289 if (!(simularity_bit_map & 0xc0)) { /*path B RX OK*/
1290 for (i = 6; i < 8; i++)
1291 result[3][i] = result[c1][i];
1292 }
1293
1294 return false;
1295 }
1296
_phy_check_coex_status_8703b(struct dm_struct * dm,boolean beforek)1297 void _phy_check_coex_status_8703b(struct dm_struct *dm, boolean beforek)
1298 {
1299 u8 u1b_tmp;
1300 u16 count = 0;
1301 u8 h2c_parameter;
1302
1303 #if MP_DRIVER != 1
1304 if (beforek) {
1305 /* Set H2C cmd to inform FW (enable). */
1306 h2c_parameter = 1;
1307 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1308 /* Check 0x1e6 or 100ms timeout*/
1309 count = 0;
1310 u1b_tmp = odm_read_1byte(dm, 0x1e6);
1311 while (u1b_tmp != 0x1 && count < 5000) {
1312 ODM_delay_us(20);
1313 u1b_tmp = odm_read_1byte(dm, 0x1e6);
1314 count++;
1315 }
1316
1317 if (count >= 5000)
1318 RF_DBG(dm, DBG_RF_INIT,
1319 "[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)",
1320 count);
1321
1322 /* Wait BT IQK finished. */
1323 /* polling 0x1e7[0]=1 or 600ms timeout */
1324 count = 0;
1325 u1b_tmp = odm_read_1byte(dm, 0x1e7);
1326 while ((!(u1b_tmp & BIT(0))) && count < 30000) {
1327 ODM_delay_us(20);
1328 u1b_tmp = odm_read_1byte(dm, 0x1e7);
1329 count++;
1330 }
1331
1332 if (count >= 30000)
1333 RF_DBG(dm, DBG_RF_INIT,
1334 "[IQK]Waiting BT IQK finish time out! count(%d)",
1335 count);
1336 } else {
1337 /* Set H2C cmd to inform FW (disable). */
1338 h2c_parameter = 0;
1339 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1340 /* Check 0x1e6 or 100ms timeout */
1341 count = 0;
1342 u1b_tmp = odm_read_1byte(dm, 0x1e6);
1343 while (u1b_tmp != 0 && count < 5000) {
1344 ODM_delay_us(20);
1345 u1b_tmp = odm_read_1byte(dm, 0x1e6);
1346 count++;
1347 }
1348
1349 if (count >= 5000)
1350 RF_DBG(dm, DBG_RF_INIT,
1351 "[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)",
1352 count);
1353 }
1354 #endif
1355 }
1356
_phy_iq_calibrate_8703b(struct dm_struct * dm,s32 result[][8],u8 t)1357 void _phy_iq_calibrate_8703b(struct dm_struct *dm, s32 result[][8], u8 t)
1358 {
1359 u32 i;
1360 u8 path_aok = 0x0, path_bok = 0x0;
1361 u8 tmp0xc50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
1362 //u8 tmp0xc58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
1363 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
1364 REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
1365 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1366 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1367 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1368 REG_TX_TO_TX, REG_RX_CCK,
1369 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1370 REG_RX_TO_RX, REG_STANDBY,
1371 REG_SLEEP, REG_PMPD_ANAEN};
1372 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1373 REG_TXPAUSE, REG_BCN_CTRL,
1374 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1375
1376 /*since 92C & 92D have the different define in IQK_BB_REG*/
1377 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1378 REG_OFDM_0_TRX_PATH_ENABLE, REG_OFDM_0_TR_MUX_PAR,
1379 REG_FPGA0_XCD_RF_INTERFACE_SW, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1380 REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
1381 REG_FPGA0_XB_RF_INTERFACE_OE, REG_CCK_0_AFE_SETTING};
1382 u32 retry_count;
1383 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1384 retry_count = 2;
1385 #ifdef MP_TEST
1386 if (*(dm->mp_mode))
1387 retry_count = 9;
1388 #endif
1389 #endif
1390
1391 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1392 #if MP_DRIVER
1393 retry_count = 1;
1394 #else
1395 retry_count = 2;
1396 #endif
1397 #endif
1398
1399 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1400 if (*(dm->mp_mode))
1401 retry_count = 1;
1402 else
1403 retry_count = 2;
1404 #endif
1405
1406 /* Note: IQ calibration must be performed after loading*/
1407 /*PHY_REG.txt , and radio_a, radio_b.txt*/
1408
1409 /* u32 bbvalue; */
1410
1411 if (t == 0) {
1412 /* bbvalue = odm_get_bb_reg(dm, REG_FPGA0_RFMOD, MASKDWORD);
1413 * RT_DISP(FINIT, INIT_IQK, ("_phy_iq_calibrate_8188e()==>0x%08x\n",bbvalue)); */
1414
1415 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQ Calibration for %d times\n", t);
1416
1417 /* Save ADDA parameters, turn path A ADDA on*/
1418 _phy_save_adda_registers8703b(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1419 _phy_save_mac_registers8703b(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
1420 _phy_save_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1421 }
1422 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQ Calibration for %d times\n", t);
1423
1424 _phy_path_adda_on8703b(dm, ADDA_REG, true);
1425 /* MAC settings */
1426 _phy_mac_setting_calibration8703b(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
1427 /* BB setting */
1428 /*odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT24, 0x00);*/
1429 odm_set_bb_reg(dm, REG_CCK_0_AFE_SETTING, 0x0f000000, 0xf);
1430 odm_set_bb_reg(dm, REG_OFDM_0_TRX_PATH_ENABLE, MASKDWORD, 0x03a05600);
1431 odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800e4);
1432 odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x25204000);
1433
1434 /* path A TX IQK */
1435 #if 1
1436
1437 for (i = 0; i < retry_count; i++) {
1438 path_aok = phy_path_a_iqk_8703b(dm);
1439 if (path_aok == 0x01) {
1440 RF_DBG(dm, DBG_RF_IQK, "[IQK]Tx IQK Success!!\n");
1441 result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1442 result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1443 break;
1444 }
1445 }
1446 #endif
1447
1448 /* path A RXIQK */
1449 #if 1
1450
1451 for (i = 0; i < retry_count; i++) {
1452 path_aok = phy_path_a_rx_iqk_8703b(dm);
1453 if (path_aok == 0x03) {
1454 RF_DBG(dm, DBG_RF_IQK, "[IQK]Rx IQK Success!!\n");
1455 /* result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
1456 * result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
1457 result[t][2] = (odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1458 result[t][3] = (odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1459 break;
1460 }
1461
1462 RF_DBG(dm, DBG_RF_IQK, "[IQK]Rx IQK Fail!!\n");
1463 }
1464
1465 if (0x00 == path_aok)
1466 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK failed!!\n");
1467
1468 #endif
1469
1470 /* path B TX IQK */
1471 #if 0
1472
1473 #if MP_DRIVER != 1
1474 if ((*dm->is_1_antenna == false) || ((*dm->is_1_antenna == true) && (*dm->rf_default_path == 1))
1475 || dm->support_interface == ODM_ITRF_USB)
1476 #endif
1477 {
1478 for (i = 0 ; i < retry_count ; i++) {
1479 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1480 path_bok = phy_path_b_iqk_8703b(adapter);
1481 #else
1482 path_bok = phy_path_b_iqk_8703b(dm);
1483 #endif
1484 /* if(path_bok == 0x03){ */
1485 if (path_bok == 0x01) {
1486 RF_DBG(dm, DBG_RF_IQK,
1487 "[IQK]S0 Tx IQK Success!!\n");
1488 result[t][4] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1489 result[t][5] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1490 break;
1491 }
1492 }
1493 #endif
1494
1495 /* path B RX IQK */
1496 #if 0
1497
1498 for (i = 0 ; i < retry_count ; i++) {
1499 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1500 path_bok = phy_path_b_rx_iqk_8703b(adapter);
1501 #else
1502 path_bok = phy_path_b_rx_iqk_8703b(dm);
1503 #endif
1504 if (path_bok == 0x03) {
1505 RF_DBG(dm, DBG_RF_IQK,
1506 "[IQK]S0 Rx IQK Success!!\n");
1507 /* result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
1508 * result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
1509 result[t][6] = (odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1510 result[t][7] = (odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1511 break;
1512
1513 } else
1514 RF_DBG(dm, DBG_RF_IQK,
1515 "[IQK]S0 Rx IQK Fail!!\n");
1516 }
1517
1518
1519
1520 if (0x00 == path_bok)
1521 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0 IQK failed!!\n");
1522 }
1523 #endif
1524
1525 /* Back to BB mode, load original value */
1526 RF_DBG(dm, DBG_RF_IQK,
1527 "[IQK]IQK:Back to BB mode, load original value!\n");
1528 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
1529
1530 if (t != 0) {
1531 /* Reload ADDA power saving parameters*/
1532 _phy_reload_adda_registers8703b(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1533 /* Reload MAC parameters*/
1534 _phy_reload_mac_registers8703b(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
1535 _phy_reload_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1536 /* Allen initial gain 0xc50 */
1537 /* Restore RX initial gain */
1538 odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, 0x50);
1539 odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, tmp0xc50);
1540 /* load 0xe30 IQC default value */
1541 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1542 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1543 }
1544 RF_DBG(dm, DBG_RF_IQK, "[IQK]%s <==\n", __func__);
1545 }
1546
_phy_lc_calibrate_8703b(struct dm_struct * dm,boolean is2T)1547 void _phy_lc_calibrate_8703b(struct dm_struct *dm, boolean is2T)
1548 {
1549 u8 tmp_reg;
1550 u32 rf_bmode = 0, lc_cal, cnt;
1551
1552 /*Check continuous TX and Packet TX*/
1553 tmp_reg = odm_read_1byte(dm, 0xd03);
1554
1555 if ((tmp_reg & 0x70) != 0) /*Deal with contisuous TX case*/
1556 odm_write_1byte(dm, 0xd03, tmp_reg & 0x8F); /*disable all continuous TX*/
1557 else /* Deal with Packet TX case*/
1558 odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* block all queues*/
1559
1560 /*backup RF0x18*/
1561 lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
1562
1563 /*Start LCK*/
1564 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
1565
1566 for (cnt = 0; cnt < 100; cnt++) {
1567 if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
1568 break;
1569
1570 ODM_delay_ms(10);
1571 }
1572 if (cnt == 100)
1573 RF_DBG(dm, DBG_RF_LCK, "LCK time out\n");
1574
1575 /*Recover channel number*/
1576 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
1577
1578 /*Restore original situation*/
1579 if ((tmp_reg & 0x70) != 0) {
1580 /*Deal with contisuous TX case*/
1581 odm_write_1byte(dm, 0xd03, tmp_reg);
1582 } else {
1583 /* Deal with Packet TX case*/
1584 odm_write_1byte(dm, REG_TXPAUSE, 0x00);
1585 }
1586 }
1587
1588 /* IQK version: 0x5 20171109 */
1589 /* 1. add coex. related setting*/
1590
phy_iq_calibrate_8703b(void * dm_void,boolean is_recovery)1591 void phy_iq_calibrate_8703b(void *dm_void, boolean is_recovery)
1592 {
1593 struct dm_struct *dm = (struct dm_struct *)dm_void;
1594 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1595 s32 result[4][8]; /* last is final result */
1596 u8 i, final_candidate, indexforchannel;
1597 boolean is_patha_ok, is_pathb_ok;
1598 s32 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc, reg_tmp = 0;
1599 boolean is12simular, is13simular, is23simular;
1600 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1601 REG_OFDM_0_XA_RX_IQ_IMBALANCE, REG_OFDM_0_XB_RX_IQ_IMBALANCE,
1602 REG_OFDM_0_ECCA_THRESHOLD, REG_OFDM_0_AGC_RSSI_TABLE,
1603 REG_OFDM_0_XA_TX_IQ_IMBALANCE, REG_OFDM_0_XB_TX_IQ_IMBALANCE,
1604 REG_OFDM_0_XC_TX_AFE, REG_OFDM_0_XD_TX_AFE,
1605 REG_OFDM_0_RX_IQ_EXT_ANTA};
1606 boolean is_reload_iqk = false;
1607
1608 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
1609 if (is_recovery)
1610 #else /* for ODM_WIN */
1611 if (is_recovery && !dm->is_in_hct_test) /* YJ,add for PowerTest,120405 */
1612 #endif
1613 {
1614 RF_DBG(dm, DBG_RF_INIT, "[IQK]%s: Return due to is_recovery!\n",
1615 __func__);
1616 _phy_reload_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, 9);
1617 return;
1618 }
1619
1620 if (*dm->mp_mode == false) {
1621 #if MP_DRIVER != 1
1622 /* check if IQK had been done before!! */
1623 RF_DBG(dm, DBG_RF_IQK, "[IQK] 0xc80 = 0x%x\n",
1624 cali_info->tx_iqc_8703b[idx_0xc80][VAL]);
1625 if (odm_set_iqc_by_rfpath_8703b(dm)) {
1626 RF_DBG(dm, DBG_RF_IQK,
1627 "[IQK]IQK value is reloaded!!!\n");
1628 is_reload_iqk = true;
1629 }
1630 if (is_reload_iqk)
1631 return;
1632 #endif
1633 }
1634 /*Check & wait if BT is doing IQK*/
1635 if (*(dm->mp_mode) == false)
1636 _phy_check_coex_status_8703b(dm, true);
1637
1638 /* IQK start!!!!!!!!!! */
1639 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK:Start!!!\n");
1640 for (i = 0; i < 8; i++) {
1641 result[0][i] = 0;
1642 result[1][i] = 0;
1643 result[2][i] = 0;
1644 result[3][i] = 0;
1645 }
1646 final_candidate = 0xff;
1647 is_patha_ok = false;
1648 is_pathb_ok = false;
1649 is12simular = false;
1650 is23simular = false;
1651 is13simular = false;
1652
1653 for (i = 0; i < 3; i++) {
1654 _phy_iq_calibrate_8703b(dm, result, i);
1655 if (i == 1) {
1656 is12simular = phy_simularity_compare_8703b(dm, result, 0, 1, true);
1657 if (is12simular) {
1658 final_candidate = 0;
1659 RF_DBG(dm, DBG_RF_IQK,
1660 "[IQK]IQK: is12simular final_candidate is %x\n",
1661 final_candidate);
1662 break;
1663 }
1664 }
1665
1666 if (i == 2) {
1667 is13simular = phy_simularity_compare_8703b(dm, result, 0, 2, true);
1668 if (is13simular) {
1669 final_candidate = 0;
1670 RF_DBG(dm, DBG_RF_IQK,
1671 "[IQK]IQK: is13simular final_candidate is %x\n",
1672 final_candidate);
1673
1674 break;
1675 }
1676 is23simular = phy_simularity_compare_8703b(dm, result, 1, 2, true);
1677 if (is23simular) {
1678 final_candidate = 1;
1679 RF_DBG(dm, DBG_RF_IQK,
1680 "[IQK]IQK: is23simular final_candidate is %x\n",
1681 final_candidate);
1682 } else {
1683 for (i = 0; i < 8; i++)
1684 reg_tmp += result[3][i];
1685
1686 if (reg_tmp != 0)
1687 final_candidate = 3;
1688 else
1689 final_candidate = 0xFF;
1690 }
1691 }
1692 }
1693 /* RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n"));*/
1694
1695 for (i = 0; i < 4; i++) {
1696 rege94 = result[i][0];
1697 rege9c = result[i][1];
1698 regea4 = result[i][2];
1699 regeac = result[i][3];
1700 regeb4 = result[i][4];
1701 regebc = result[i][5];
1702 regec4 = result[i][6];
1703 regecc = result[i][7];
1704 RF_DBG(dm, DBG_RF_IQK,
1705 "[IQK]IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ",
1706 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
1707 regecc);
1708 }
1709
1710 if (final_candidate != 0xff) {
1711 dm->rf_calibrate_info.rege94 = rege94 = result[final_candidate][0];
1712 dm->rf_calibrate_info.rege9c = rege9c = result[final_candidate][1];
1713 regea4 = result[final_candidate][2];
1714 regeac = result[final_candidate][3];
1715 dm->rf_calibrate_info.regeb4 = regeb4 = result[final_candidate][4];
1716 dm->rf_calibrate_info.regebc = regebc = result[final_candidate][5];
1717 regec4 = result[final_candidate][6];
1718 regecc = result[final_candidate][7];
1719 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK: final_candidate is %x\n",
1720 final_candidate);
1721 RF_DBG(dm, DBG_RF_IQK,
1722 "[IQK]IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ",
1723 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
1724 regecc);
1725 is_patha_ok = is_pathb_ok = true;
1726 } else {
1727 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK: FAIL use default value\n");
1728 dm->rf_calibrate_info.rege94 = dm->rf_calibrate_info.regeb4 = 0x100; /* X default value */
1729 dm->rf_calibrate_info.rege9c = dm->rf_calibrate_info.regebc = 0x0; /* Y default value */
1730 }
1731
1732 /* fill IQK matrix */
1733 if (rege94 != 0)
1734 _phy_path_a_fill_iqk_matrix8703b(dm, is_patha_ok, result, final_candidate, (regea4 == 0));
1735 /* if (regeb4 != 0)
1736 * _phy_path_b_fill_iqk_matrix8703b(adapter, is_pathb_ok, result, final_candidate, (regec4 == 0)); */
1737
1738 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1739 indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
1740 #else
1741 indexforchannel = 0;
1742 #endif
1743
1744 /* To Fix BSOD when final_candidate is 0xff
1745 * by sherry 20120321 */
1746 if (final_candidate < 4) {
1747 for (i = 0; i < iqk_matrix_reg_num; i++)
1748 dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].value[0][i] = result[final_candidate][i];
1749 dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].is_iqk_done = true;
1750 }
1751 /* RT_DISP(FINIT, INIT_IQK, ("\nIQK OK indexforchannel %d.\n", indexforchannel)); */
1752 RF_DBG(dm, DBG_RF_IQK, "[IQK]\nIQK OK indexforchannel %d.\n",
1753 indexforchannel);
1754 _phy_save_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
1755 /* fill IQK register */
1756 odm_set_iqc_by_rfpath_8703b(dm);
1757 if (*dm->mp_mode == false) {
1758 _phy_check_coex_status_8703b(dm, false);
1759 }
1760 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK finished\n");
1761 }
1762
phy_lc_calibrate_8703b(void * dm_void)1763 void phy_lc_calibrate_8703b(void *dm_void)
1764 {
1765 struct dm_struct *dm = (struct dm_struct *)dm_void;
1766
1767 _phy_lc_calibrate_8703b(dm, false);
1768 }
1769
_phy_set_rf_path_switch_8703b(struct dm_struct * dm,boolean is_main,boolean is2T)1770 void _phy_set_rf_path_switch_8703b(
1771 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
1772 struct dm_struct *dm,
1773 #else
1774 void *adapter,
1775 #endif
1776 boolean is_main, boolean is2T)
1777 {
1778 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1779 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1780 struct dm_struct *dm = &hal_data->DM_OutSrc;
1781 #endif
1782
1783 if (is_main) { /*Set WIFI S1*/
1784 odm_set_bb_reg(dm, R_0x7c4, MASKLWORD, 0x7703);
1785 odm_set_bb_reg(dm, R_0x7c0, MASKDWORD, 0xC00F0038);
1786 } else { /*Set BT S0*/
1787 odm_set_bb_reg(dm, R_0x7c4, MASKLWORD, 0xCC03);
1788 odm_set_bb_reg(dm, R_0x7c0, MASKDWORD, 0xC00F0038);
1789 }
1790 }
1791
phy_set_rf_path_switch_8703b(struct dm_struct * dm,boolean is_main)1792 void phy_set_rf_path_switch_8703b(
1793 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
1794 struct dm_struct *dm,
1795 #else
1796 void *adapter,
1797 #endif
1798 boolean is_main)
1799 {
1800 #if DISABLE_BB_RF
1801 return;
1802 #endif
1803
1804 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1805 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1806 _phy_set_rf_path_switch_8703b(dm, is_main, true);
1807 #else
1808 _phy_set_rf_path_switch_8703b(adapter, is_main, true);
1809 #endif
1810 #endif
1811 }
1812
1813 /*return value true => WIFI(S1); false => BT(S0)*/
_phy_query_rf_path_switch_8703b(struct dm_struct * dm,boolean is2T)1814 boolean _phy_query_rf_path_switch_8703b(
1815 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1816 struct dm_struct *dm,
1817 #else
1818 void *adapter,
1819 #endif
1820 boolean is2T)
1821 {
1822 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1823 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1824 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1825 struct dm_struct *dm = &hal_data->odmpriv;
1826 #endif
1827 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1828 struct dm_struct *dm = &hal_data->DM_OutSrc;
1829 #endif
1830 #endif
1831
1832 if (odm_get_bb_reg(dm, R_0x7c4, MASKLWORD) == 0x7703)
1833 return true;
1834 else
1835 return false;
1836 }
1837
1838 /*return value true => WIFI(S1); false => BT(S0)*/
phy_query_rf_path_switch_8703b(struct dm_struct * dm)1839 boolean phy_query_rf_path_switch_8703b(
1840 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1841 struct dm_struct *dm
1842 #else
1843 void *adapter
1844 #endif
1845 )
1846 {
1847 #if DISABLE_BB_RF
1848 return true;
1849 #endif
1850
1851 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1852 return _phy_query_rf_path_switch_8703b(adapter, false);
1853 #else
1854 return _phy_query_rf_path_switch_8703b(dm, false);
1855 #endif
1856 }
1857 #endif
1858