1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
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41 // consequential damages, including without limitation, lost of profit or
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43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
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61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 //-------------------------------------------------------------------------------------------------
80 // Include Files
81 //-------------------------------------------------------------------------------------------------
82 #include "MsCommon.h"
83 #include "MsTypes.h"
84 #include "drvMIU.h"
85 #include "regMIU.h"
86 #include "halMIU.h"
87 #include "halCHIP.h"
88
89 //-------------------------------------------------------------------------------------------------
90 // Driver Compiler Options
91 //-------------------------------------------------------------------------------------------------
92
93
94 //-------------------------------------------------------------------------------------------------
95 // Local Defines
96 //-------------------------------------------------------------------------------------------------
97 #define MIU_HAL_ERR(x, args...) {printf(x, ##args);}
98 #define HAL_MIU_SSC_DBG(x) //x
99
100 #define MIU_CLIENT_GP0 \
101 MIU_CLIENT_NONE, \
102 MIU_CLIENT_VD_TTX_RW, \
103 MIU_CLIENT_VD_TTXSL_W, \
104 MIU_CLIENT_USB3_RW, \
105 MIU_CLIENT_DUMMY, \
106 MIU_CLIENT_SECURE_R2_RW, \
107 MIU_CLIENT_TSP_ORZ_RW, \
108 MIU_CLIENT_PM51_RW, \
109 MIU_CLIENT_TSP_ORZ2_RW, \
110 MIU_CLIENT_USB_UHC0_RW, \
111 MIU_CLIENT_USB_UHC1_RW, \
112 MIU_CLIENT_USB_UHC2_RW, \
113 MIU_CLIENT_MVD_BBU_RW, \
114 MIU_CLIENT_EMAC_RW, \
115 MIU_CLIENT_BDMA_RW, \
116 MIU_CLIENT_DUMMY
117
118 #define MIU_CLIENT_GP1 \
119 MIU_CLIENT_GE_RW, \
120 MIU_CLIENT_DEMOD_RW, \
121 MIU_CLIENT_MVD_RW, \
122 MIU_CLIENT_MIIC0_RW, \
123 MIU_CLIENT_NAND_RW, \
124 MIU_CLIENT_GPD_RW, \
125 MIU_CLIENT_DSCRMB_RW, \
126 MIU_CLIENT_JPD_RW, \
127 MIU_CLIENT_TSO_RW, \
128 MIU_CLIENT_HISPEED_UART_RW, \
129 MIU_CLIENT_TSP_RW, \
130 MIU_CLIENT_TSP_PVR0_W, \
131 MIU_CLIENT_VD_COMB_W, \
132 MIU_CLIENT_VD_COMB_R, \
133 MIU_CLIENT_MFE0_W, \
134 MIU_CLIENT_MFEH_R
135
136 #define MIU_CLIENT_GP2 \
137 MIU_CLIENT_DUMMY, \
138 MIU_CLIENT_DUMMY, \
139 MIU_CLIENT_DUMMY, \
140 MIU_CLIENT_DUMMY, \
141 MIU_CLIENT_DUMMY, \
142 MIU_CLIENT_DUMMY, \
143 MIU_CLIENT_DUMMY, \
144 MIU_CLIENT_DUMMY, \
145 MIU_CLIENT_DUMMY, \
146 MIU_CLIENT_DUMMY, \
147 MIU_CLIENT_DUMMY, \
148 MIU_CLIENT_DUMMY, \
149 MIU_CLIENT_DUMMY, \
150 MIU_CLIENT_DUMMY, \
151 MIU_CLIENT_DUMMY, \
152 MIU_CLIENT_DUMMY
153
154 #define MIU_CLIENT_GP3 \
155 MIU_CLIENT_AUDIO_RW, \
156 MIU_CLIENT_MAU1_RW, \
157 MIU_CLIENT_VD_R2I_R, \
158 MIU_CLIENT_DUMMY, \
159 MIU_CLIENT_DUMMY, \
160 MIU_CLIENT_DUMMY, \
161 MIU_CLIENT_DUMMY, \
162 MIU_CLIENT_DUMMY, \
163 MIU_CLIENT_DUMMY, \
164 MIU_CLIENT_DUMMY, \
165 MIU_CLIENT_DUMMY, \
166 MIU_CLIENT_DUMMY, \
167 MIU_CLIENT_DUMMY, \
168 MIU_CLIENT_DUMMY, \
169 MIU_CLIENT_DUMMY, \
170 MIU_CLIENT_DUMMY
171
172 #define MIU_CLIENT_GP4 \
173 MIU_CLIENT_HVD_BBU_R, \
174 MIU_CLIENT_HVD_RW, \
175 MIU_CLIENT_EVD_RW, \
176 MIU_CLIENT_EVD_BBU_R, \
177 MIU_CLIENT_EVD_ENGINE1_RW, \
178 MIU_CLIENT_DUMMY, \
179 MIU_CLIENT_MVD_256BIT_RW, \
180 MIU_CLIENT_DUMMY, \
181 MIU_CLIENT_DUMMY, \
182 MIU_CLIENT_DUMMY, \
183 MIU_CLIENT_DUMMY, \
184 MIU_CLIENT_DUMMY, \
185 MIU_CLIENT_DUMMY, \
186 MIU_CLIENT_DUMMY, \
187 MIU_CLIENT_DUMMY, \
188 MIU_CLIENT_DUMMY
189
190 #define MIU_CLIENT_GP5 \
191 MIU_CLIENT_DS_R, \
192 MIU_CLIENT_OD_RW, \
193 MIU_CLIENT_MVOP_256BIT_R, \
194 MIU_CLIENT_MVOP1_256BIT_R, \
195 MIU_CLIENT_DUMMY, \
196 MIU_CLIENT_GOP0_R, \
197 MIU_CLIENT_GOP1_R, \
198 MIU_CLIENT_GOP2_R, \
199 MIU_CLIENT_DUMMY, \
200 MIU_CLIENT_SC_PDW_W, \
201 MIU_CLIENT_SC_OP_R, \
202 MIU_CLIENT_SC_IPMAIN_RW, \
203 MIU_CLIENT_SC_IPSUB_RW, \
204 MIU_CLIENT_SC_LD_RW, \
205 MIU_CLIENT_VE_RW, \
206 MIU_CLIENT_SC_DIPW_RW
207
208 #define MIU_CLIENT_GP6 \
209 MIU_CLIENT_DUMMY, \
210 MIU_CLIENT_DUMMY, \
211 MIU_CLIENT_DUMMY, \
212 MIU_CLIENT_DUMMY, \
213 MIU_CLIENT_DUMMY, \
214 MIU_CLIENT_DUMMY, \
215 MIU_CLIENT_DUMMY, \
216 MIU_CLIENT_DUMMY, \
217 MIU_CLIENT_DUMMY, \
218 MIU_CLIENT_DUMMY, \
219 MIU_CLIENT_DUMMY, \
220 MIU_CLIENT_DUMMY, \
221 MIU_CLIENT_DUMMY, \
222 MIU_CLIENT_DUMMY, \
223 MIU_CLIENT_DUMMY, \
224 MIU_CLIENT_DUMMY
225
226 #define MIU_CLIENT_GP7 \
227 MIU_CLIENT_MIPS_RW, \
228 MIU_CLIENT_G3D_RW, \
229 MIU_CLIENT_DUMMY, \
230 MIU_CLIENT_DUMMY, \
231 MIU_CLIENT_DUMMY, \
232 MIU_CLIENT_DUMMY, \
233 MIU_CLIENT_DUMMY, \
234 MIU_CLIENT_DUMMY, \
235 MIU_CLIENT_DUMMY, \
236 MIU_CLIENT_DUMMY, \
237 MIU_CLIENT_DUMMY, \
238 MIU_CLIENT_DUMMY, \
239 MIU_CLIENT_DUMMY, \
240 MIU_CLIENT_DUMMY, \
241 MIU_CLIENT_DUMMY, \
242 MIU_CLIENT_DUMMY
243
244 #define MIU1_CLIENT_GP0 \
245 MIU_CLIENT_NONE, \
246 MIU_CLIENT_VD_TTX_RW, \
247 MIU_CLIENT_VD_TTXSL_W, \
248 MIU_CLIENT_USB3_RW, \
249 MIU_CLIENT_DUMMY, \
250 MIU_CLIENT_SECURE_R2_RW, \
251 MIU_CLIENT_TSP_ORZ_RW, \
252 MIU_CLIENT_PM51_RW, \
253 MIU_CLIENT_TSP_ORZ2_RW, \
254 MIU_CLIENT_USB_UHC0_RW, \
255 MIU_CLIENT_USB_UHC1_RW, \
256 MIU_CLIENT_USB_UHC2_RW, \
257 MIU_CLIENT_MVD_BBU_RW, \
258 MIU_CLIENT_EMAC_RW, \
259 MIU_CLIENT_BDMA_RW, \
260 MIU_CLIENT_DUMMY
261
262 #define MIU1_CLIENT_GP1 \
263 MIU_CLIENT_GE_RW, \
264 MIU_CLIENT_DEMOD_RW, \
265 MIU_CLIENT_MVD_RW, \
266 MIU_CLIENT_MIIC0_RW, \
267 MIU_CLIENT_NAND_RW, \
268 MIU_CLIENT_GPD_RW, \
269 MIU_CLIENT_DSCRMB_RW, \
270 MIU_CLIENT_JPD_RW, \
271 MIU_CLIENT_TSO_RW, \
272 MIU_CLIENT_HISPEED_UART_RW, \
273 MIU_CLIENT_TSP_RW, \
274 MIU_CLIENT_TSP_PVR0_W, \
275 MIU_CLIENT_VD_COMB_W, \
276 MIU_CLIENT_VD_COMB_R, \
277 MIU_CLIENT_MFE0_W, \
278 MIU_CLIENT_MFEH_R
279
280 #define MIU1_CLIENT_GP2 \
281 MIU_CLIENT_DUMMY, \
282 MIU_CLIENT_DUMMY, \
283 MIU_CLIENT_DUMMY, \
284 MIU_CLIENT_DUMMY, \
285 MIU_CLIENT_DUMMY, \
286 MIU_CLIENT_DUMMY, \
287 MIU_CLIENT_DUMMY, \
288 MIU_CLIENT_DUMMY, \
289 MIU_CLIENT_DUMMY, \
290 MIU_CLIENT_DUMMY, \
291 MIU_CLIENT_DUMMY, \
292 MIU_CLIENT_DUMMY, \
293 MIU_CLIENT_DUMMY, \
294 MIU_CLIENT_DUMMY, \
295 MIU_CLIENT_DUMMY, \
296 MIU_CLIENT_DUMMY
297
298 #define MIU1_CLIENT_GP3 \
299 MIU_CLIENT_AUDIO_RW, \
300 MIU_CLIENT_MAU1_RW, \
301 MIU_CLIENT_VD_R2I_R, \
302 MIU_CLIENT_DUMMY, \
303 MIU_CLIENT_DUMMY, \
304 MIU_CLIENT_DUMMY, \
305 MIU_CLIENT_DUMMY, \
306 MIU_CLIENT_DUMMY, \
307 MIU_CLIENT_DUMMY, \
308 MIU_CLIENT_DUMMY, \
309 MIU_CLIENT_DUMMY, \
310 MIU_CLIENT_DUMMY, \
311 MIU_CLIENT_DUMMY, \
312 MIU_CLIENT_DUMMY, \
313 MIU_CLIENT_DUMMY, \
314 MIU_CLIENT_DUMMY
315
316 #define MIU1_CLIENT_GP4 \
317 MIU_CLIENT_HVD_BBU_R, \
318 MIU_CLIENT_HVD_RW, \
319 MIU_CLIENT_EVD_RW, \
320 MIU_CLIENT_EVD_BBU_R, \
321 MIU_CLIENT_EVD_ENGINE1_RW, \
322 MIU_CLIENT_DUMMY, \
323 MIU_CLIENT_MVD_256BIT_RW, \
324 MIU_CLIENT_DUMMY, \
325 MIU_CLIENT_DUMMY, \
326 MIU_CLIENT_DUMMY, \
327 MIU_CLIENT_DUMMY, \
328 MIU_CLIENT_DUMMY, \
329 MIU_CLIENT_DUMMY, \
330 MIU_CLIENT_DUMMY, \
331 MIU_CLIENT_DUMMY, \
332 MIU_CLIENT_DUMMY
333
334 #define MIU1_CLIENT_GP5 \
335 MIU_CLIENT_DS_R, \
336 MIU_CLIENT_OD_RW, \
337 MIU_CLIENT_MVOP_256BIT_R, \
338 MIU_CLIENT_MVOP1_256BIT_R, \
339 MIU_CLIENT_DUMMY, \
340 MIU_CLIENT_GOP0_R, \
341 MIU_CLIENT_GOP1_R, \
342 MIU_CLIENT_GOP2_R, \
343 MIU_CLIENT_DUMMY, \
344 MIU_CLIENT_SC_PDW_W, \
345 MIU_CLIENT_SC_OP_R, \
346 MIU_CLIENT_SC_IPMAIN_RW, \
347 MIU_CLIENT_SC_IPSUB_RW, \
348 MIU_CLIENT_SC_LD_RW, \
349 MIU_CLIENT_VE_RW, \
350 MIU_CLIENT_SC_DIPW_RW
351
352 #define MIU1_CLIENT_GP6 \
353 MIU_CLIENT_DUMMY, \
354 MIU_CLIENT_DUMMY, \
355 MIU_CLIENT_DUMMY, \
356 MIU_CLIENT_DUMMY, \
357 MIU_CLIENT_DUMMY, \
358 MIU_CLIENT_DUMMY, \
359 MIU_CLIENT_DUMMY, \
360 MIU_CLIENT_DUMMY, \
361 MIU_CLIENT_DUMMY, \
362 MIU_CLIENT_DUMMY, \
363 MIU_CLIENT_DUMMY, \
364 MIU_CLIENT_DUMMY, \
365 MIU_CLIENT_DUMMY, \
366 MIU_CLIENT_DUMMY, \
367 MIU_CLIENT_DUMMY, \
368 MIU_CLIENT_DUMMY
369
370 #define MIU1_CLIENT_GP7 \
371 MIU_CLIENT_MIPS_RW, \
372 MIU_CLIENT_G3D_RW, \
373 MIU_CLIENT_DUMMY, \
374 MIU_CLIENT_DUMMY, \
375 MIU_CLIENT_DUMMY, \
376 MIU_CLIENT_DUMMY, \
377 MIU_CLIENT_DUMMY, \
378 MIU_CLIENT_DUMMY, \
379 MIU_CLIENT_DUMMY, \
380 MIU_CLIENT_DUMMY, \
381 MIU_CLIENT_DUMMY, \
382 MIU_CLIENT_DUMMY, \
383 MIU_CLIENT_DUMMY, \
384 MIU_CLIENT_DUMMY, \
385 MIU_CLIENT_DUMMY, \
386 MIU_CLIENT_DUMMY
387
388 #define KHz (1000UL)
389 #define MHz (1000000UL)
390 #define MPPL (432)
391 #define DDR_FACTOR (524288)
392 #define DDFSPAN_FACTOR (131072)
393 #define IDNUM_KERNELPROTECT (8)
394
395 //-------------------------------------------------------------------------------------------------
396 // Local Structures
397 //-------------------------------------------------------------------------------------------------
398 const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] =
399 {
400 {
401 MIU_CLIENT_GP0,
402 MIU_CLIENT_GP1,
403 MIU_CLIENT_GP2,
404 MIU_CLIENT_GP3,
405 MIU_CLIENT_GP4,
406 MIU_CLIENT_GP5,
407 MIU_CLIENT_GP6,
408 MIU_CLIENT_GP7
409 },
410 {
411 MIU1_CLIENT_GP0,
412 MIU1_CLIENT_GP1,
413 MIU1_CLIENT_GP2,
414 MIU1_CLIENT_GP3,
415 MIU1_CLIENT_GP4,
416 MIU1_CLIENT_GP5,
417 MIU1_CLIENT_GP6,
418 MIU1_CLIENT_GP7
419 }
420 };
421
422 MS_U8 clientId_KernelProtect[IDNUM_KERNELPROTECT] =
423 {
424 MIU_CLIENT_MIPS_RW,
425 MIU_CLIENT_NAND_RW,
426 MIU_CLIENT_USB_UHC0_RW,
427 MIU_CLIENT_USB_UHC1_RW,
428 MIU_CLIENT_USB_UHC2_RW,
429 MIU_CLIENT_USB3_RW,
430 MIU_CLIENT_NONE,
431 MIU_CLIENT_NONE
432 };
433 //-------------------------------------------------------------------------------------------------
434 // Global Variables
435 //-------------------------------------------------------------------------------------------------
436
437 //-------------------------------------------------------------------------------------------------
438 // Local Variables
439 //-------------------------------------------------------------------------------------------------
440 static MS_U32 _gMIU_MapBase = 0x1f200000;
441 static MS_U32 _gPM_MapBase = 0x1f000000;
442
443 MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] =
444 {
445 {{0}, {0}, {0}, {0}},
446 {{0}, {0}, {0}, {0}}
447 }; //ID enable for protect block 0~3
448
449 MS_U32 IDs[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] =
450 {
451 {0}, {0}
452 }; //IDs for protection
453
454 //-------------------------------------------------------------------------------------------------
455 // Debug Functions
456 //-------------------------------------------------------------------------------------------------
457
458 //-------------------------------------------------------------------------------------------------
459 // Local Functions
460 //-------------------------------------------------------------------------------------------------
461
462 //-------------------------------------------------------------------------------------------------
463 // Type and Structure Declaration
464 //-------------------------------------------------------------------------------------------------
465
466 //-------------------------------------------------------------------------------------------------
467 // Global Functions
468 //-------------------------------------------------------------------------------------------------
HAL_MIU_SetIOMapBase(MS_U32 u32Base)469 void HAL_MIU_SetIOMapBase(MS_U32 u32Base)
470 {
471 _gMIU_MapBase = u32Base;
472 HAL_MIU_SSC_DBG(printf("MIU _gMIU_MapBase= %lx\n", _gMIU_MapBase));
473 }
474
HAL_MIU_SetPMIOMapBase(MS_U32 u32Base)475 void HAL_MIU_SetPMIOMapBase(MS_U32 u32Base)
476 {
477 _gPM_MapBase = u32Base;
478 HAL_MIU_SSC_DBG(printf("MIU _gPM_MapBase= %lx\n", _gPM_MapBase));
479 }
480
HAL_MIU_GetClientInfo(MS_U8 u8MiuDev,eMIUClientID eClientID)481 MS_S16 HAL_MIU_GetClientInfo(MS_U8 u8MiuDev, eMIUClientID eClientID)
482 {
483 MS_U8 idx;
484
485 if (MIU_MAX_DEVICE <= u8MiuDev)
486 {
487 printf("Wrong MIU device:%u\n", u8MiuDev);
488 return (-1);
489 }
490
491 for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++)
492 if (eClientID == clientTbl[u8MiuDev][idx])
493 return idx;
494 return (-1);
495 }
496
497 ////////////////////////////////////////////////////////////////////////////////
498 /// @brief \b Function \b Name: HAL_MIU_ReadByte
499 /// @brief \b Function \b Description: read 1 Byte data
500 /// @param <IN> \b u32RegAddr: register address
501 /// @param <OUT> \b None :
502 /// @param <RET> \b MS_U8
503 /// @param <GLOBAL> \b None :
504 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ReadByte(MS_U32 u32RegAddr)505 MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegAddr)
506 {
507 return ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
508 }
509
510
511 ////////////////////////////////////////////////////////////////////////////////
512 /// @brief \b Function \b Name: HAL_MIU_PM_ReadByte
513 /// @brief \b Function \b Description: read 1 Byte data
514 /// @param <IN> \b u32RegAddr: register address
515 /// @param <OUT> \b None :
516 /// @param <RET> \b MS_U8
517 /// @param <GLOBAL> \b None :
518 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_PM_ReadByte(MS_U32 u32RegAddr)519 MS_U8 HAL_MIU_PM_ReadByte(MS_U32 u32RegAddr)
520 {
521 return ((volatile MS_U8*)(_gPM_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
522 }
523
524 ////////////////////////////////////////////////////////////////////////////////
525 /// @brief \b Function \b Name: HAL_MIU_Read4Byte
526 /// @brief \b Function \b Description: read 2 Byte data
527 /// @param <IN> \b u32RegAddr: register address
528 /// @param <OUT> \b None :
529 /// @param <RET> \b MS_U16
530 /// @param <GLOBAL> \b None :
531 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Read2Byte(MS_U32 u32RegAddr)532 MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegAddr)
533 {
534 return ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr];
535 }
536
537
538 ////////////////////////////////////////////////////////////////////////////////
539 /// @brief \b Function \b Name: HAL_MIU_Read4Byte
540 /// @brief \b Function \b Description: read 4 Byte data
541 /// @param <IN> \b u32RegAddr: register address
542 /// @param <OUT> \b None :
543 /// @param <RET> \b MS_U32
544 /// @param <GLOBAL> \b None :
545 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Read4Byte(MS_U32 u32RegAddr)546 MS_U32 HAL_MIU_Read4Byte(MS_U32 u32RegAddr)
547 {
548 return (HAL_MIU_Read2Byte(u32RegAddr) | HAL_MIU_Read2Byte(u32RegAddr+2) << 16);
549 }
550
551
552 ////////////////////////////////////////////////////////////////////////////////
553 /// @brief \b Function \b Name: HAL_MIU_WriteByte
554 /// @brief \b Function \b Description: write 1 Byte data
555 /// @param <IN> \b u32RegAddr: register address
556 /// @param <IN> \b u8Val : 1 byte data
557 /// @param <OUT> \b None :
558 /// @param <RET> \b TRUE: Ok FALSE: Fail
559 /// @param <GLOBAL> \b None :
560 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_WriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)561 MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
562 {
563 if (!u32RegAddr)
564 {
565 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
566 return FALSE;
567 }
568
569 ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
570 return TRUE;
571 }
572
573
574 ////////////////////////////////////////////////////////////////////////////////
575 /// @brief \b Function \b Name: HAL_MIU_Write2Byte
576 /// @brief \b Function \b Description: write 2 Byte data
577 /// @param <IN> \b u32RegAddr: register address
578 /// @param <IN> \b u16Val : 2 byte data
579 /// @param <OUT> \b None :
580 /// @param <RET> \b TRUE: Ok FALSE: Fail
581 /// @param <GLOBAL> \b None :
582 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Write2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)583 MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
584 {
585 if (!u32RegAddr)
586 {
587 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
588 return FALSE;
589 }
590
591 ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr] = u16Val;
592 return TRUE;
593 }
594
595
596 ////////////////////////////////////////////////////////////////////////////////
597 /// @brief \b Function \b Name: HAL_BDMA_Write4Byte
598 /// @brief \b Function \b Description: write 4 Byte data
599 /// @param <IN> \b u32RegAddr: register address
600 /// @param <IN> \b u32Val : 4 byte data
601 /// @param <OUT> \b None :
602 /// @param <RET> \b TRUE: Ok FALSE: Fail
603 /// @param <GLOBAL> \b None :
604 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)605 MS_BOOL HAL_MIU_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
606 {
607 if (!u32RegAddr)
608 {
609 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
610 return FALSE;
611 }
612
613 HAL_MIU_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
614 HAL_MIU_Write2Byte(u32RegAddr+2, u32Val >> 16);
615 return TRUE;
616 }
617
618
619 ////////////////////////////////////////////////////////////////////////////////
620 /// @brief \b Function \b Name: HAL_BDMA_WriteByte
621 /// @brief \b Function \b Description: write 1 Byte data
622 /// @param <IN> \b u32RegAddr: register address
623 /// @param <IN> \b u8Val : 1 byte data
624 /// @param <OUT> \b None :
625 /// @param <RET> \b TRUE: Ok FALSE: Fail
626 /// @param <GLOBAL> \b None :
627 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_WriteRegBit(MS_U32 u32RegAddr,MS_U8 u8Mask,MS_BOOL bEnable)628 MS_BOOL HAL_MIU_WriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable)
629 {
630 MS_U8 u8Val = HAL_MIU_ReadByte(u32RegAddr);
631 if (!u32RegAddr)
632 {
633 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
634 return FALSE;
635 }
636
637 u8Val = HAL_MIU_ReadByte(u32RegAddr);
638 u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask);
639 HAL_MIU_WriteByte(u32RegAddr, u8Val);
640 return TRUE;
641 }
642
HAL_MIU_Write2BytesBit(MS_U32 u32RegOffset,MS_BOOL bEnable,MS_U16 u16Mask)643 void HAL_MIU_Write2BytesBit(MS_U32 u32RegOffset, MS_BOOL bEnable, MS_U16 u16Mask)
644 {
645 MS_U16 val = HAL_MIU_Read2Byte(u32RegOffset);
646 val = (bEnable) ? (val | u16Mask) : (val & ~u16Mask);
647 HAL_MIU_Write2Byte(u32RegOffset, val);
648 }
649
HAL_MIU_SetProtectID(MS_U32 u32Reg,MS_U8 u8MiuDev,MS_U32 u32ClientID)650 void HAL_MIU_SetProtectID(MS_U32 u32Reg, MS_U8 u8MiuDev, MS_U32 u32ClientID)
651 {
652 MS_S16 sVal = HAL_MIU_GetClientInfo(u8MiuDev, (eMIUClientID)u32ClientID);
653 MS_S16 sIDVal;
654
655 if (0 > sVal)
656 sVal = 0;
657
658 sIDVal = HAL_MIU_ReadByte(u32Reg);
659 sIDVal &= 0x80;
660 sIDVal |= sVal;
661 HAL_MIU_WriteByte(u32Reg, sIDVal);
662 }
663
HAL_MIU_SetGroupID(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)664 MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
665 {
666 MS_U32 u32index0, u32index1;
667 MS_U8 u8ID;
668 MS_U8 u8isfound0, u8isfound1;
669 MS_U16 u16idenable;
670
671 if ( u8MiuSel >= MIU_MAX_DEVICE )
672 return FALSE;
673
674 //reset IDenables for protect u8Blockx
675 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
676 {
677 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
678 }
679
680 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
681 {
682 u8ID = pu8ProtectId[u32index0];
683
684 //Unused ID
685 if(u8ID == 0)
686 continue;
687
688 u8isfound0 = FALSE;
689
690 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
691 {
692 if(IDs[u8MiuSel][u32index1] == (MS_U32) u8ID)
693 {
694 //ID reused former setting
695 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
696 u8isfound0 = TRUE;
697 break;
698 }
699 }
700
701
702 //Need to create new ID in IDs
703 if(u8isfound0 != TRUE)
704 {
705 u8isfound1 = FALSE;
706
707 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
708 {
709 if(IDs[u8MiuSel][u32index1] == 0)
710 {
711 IDs[u8MiuSel][u32index1] = (MS_U32) u8ID;
712 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
713 u8isfound1 = TRUE;
714 break;
715 }
716 }
717
718 //ID overflow
719 if(u8isfound1 == FALSE)
720 return FALSE;
721 }
722 }
723
724 u16idenable = 0;
725
726 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
727 {
728 if(IDEnables[u8MiuSel][u8Blockx][u32index0] == 1)
729 u16idenable |= (1<<u32index0);
730 }
731
732 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
733
734 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
735 {
736 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, (u8MiuSel== E_MIU_1), IDs[u8MiuSel][u32index0]);
737 }
738
739 return TRUE;
740 }
741
HAL_MIU_SetGroupID2(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U32 * pu32ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)742 MS_BOOL HAL_MIU_SetGroupID2(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U32 *pu32ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
743 {
744 MS_U32 u32index0, u32index1;
745 MS_U32 u32ID;
746 MS_U8 u8isfound0, u8isfound1;
747 MS_U16 u16idenable;
748
749 if ( u8MiuSel >= MIU_MAX_DEVICE )
750 return FALSE;
751
752 //reset IDenables for protect u8Blockx
753 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
754 {
755 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
756 }
757
758 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
759 {
760 u32ID = pu32ProtectId[u32index0];
761
762 //Unused ID
763 if(u32ID == 0)
764 continue;
765
766 u8isfound0 = FALSE;
767
768 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
769 {
770 if(IDs[u8MiuSel][u32index1] == u32ID)
771 {
772 //ID reused former setting
773 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
774 u8isfound0 = TRUE;
775 break;
776 }
777 }
778
779
780 //Need to create new ID in IDs
781 if(u8isfound0 != TRUE)
782 {
783 u8isfound1 = FALSE;
784
785 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
786 {
787 if(IDs[u8MiuSel][u32index1] == 0)
788 {
789 IDs[u8MiuSel][u32index1] = u32ID;
790 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
791 u8isfound1 = TRUE;
792 break;
793 }
794 }
795
796 //ID overflow
797 if(u8isfound1 == FALSE)
798 return FALSE;
799 }
800 }
801
802 u16idenable = 0;
803
804 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
805 {
806 if(IDEnables[u8MiuSel][u8Blockx][u32index0] == 1)
807 u16idenable |= (1<<u32index0);
808 }
809
810 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
811
812 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
813 {
814 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, (u8MiuSel== E_MIU_1), IDs[u8MiuSel][u32index0]);
815 }
816
817 return TRUE;
818 }
819
HAL_MIU_ResetGroupID(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)820 MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
821 {
822 MS_U32 u32index0, u32index1;
823 MS_U8 u8isIDNoUse;
824 MS_U16 u16idenable;
825
826 if ( u8MiuSel >= MIU_MAX_DEVICE )
827 return FALSE;
828
829 //reset IDenables for protect u8Blockx
830 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
831 {
832 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
833 }
834
835 u16idenable = 0x0;
836
837 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
838
839 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
840 {
841 u8isIDNoUse = FALSE;
842
843 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++)
844 {
845 if(IDEnables[u8MiuSel][u32index1][u32index0] == 1)
846 {
847 //protect ID is still be used
848 u8isIDNoUse = FALSE;
849 break;
850 }
851 u8isIDNoUse = TRUE;
852 }
853
854 if(u8isIDNoUse == TRUE)
855 IDs[u8MiuSel][u32index0] = 0;
856 }
857
858 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
859 {
860 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, (u8MiuSel== E_MIU_1), IDs[u8MiuSel][u32index0]);
861 }
862
863 return TRUE;
864 }
865
866 ////////////////////////////////////////////////////////////////////////////////
867 /// @brief \b Function \b Name: HAL_MIU_GetDefaultClientID_KernelProtect()
868 /// @brief \b Function \b Description: Get default client id array pointer for protect kernel
869 /// @param <RET> \b : The pointer of Array of client IDs
870 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetDefaultClientID_KernelProtect()871 MS_U8* HAL_MIU_GetDefaultClientID_KernelProtect()
872 {
873 if(IDNUM_KERNELPROTECT > 0)
874 return (MS_U8 *)&clientId_KernelProtect[0];
875
876 return NULL;
877 }
878
879 ////////////////////////////////////////////////////////////////////////////////
880 /// @brief \b Function \b Name: HAL_MIU_ProtectAlign()
881 /// @brief \b Function \b Description: Get the page shift for MIU protect
882 /// @param <*u32PageShift>\b IN: Page shift
883 /// @param <RET> \b OUT: None
884 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ProtectAlign(void)885 MS_U32 HAL_MIU_ProtectAlign(void)
886 {
887 MS_U32 u32PageShift;
888
889 u32PageShift = MIU_PAGE_SHIFT;
890 return u32PageShift;
891 }
892
893 ////////////////////////////////////////////////////////////////////////////////
894 /// @brief \b Function \b Name: HAL_MIU_Dram_Size()
895 /// @brief \b Function \b Description: Set up Dram size for MIU protect
896 /// @param MiuID \b IN : MIU ID
897 /// @param DramSize \b IN : Specified Dram size for MIU protect
898 /// @param <OUT> \b None :
899 /// @param <RET> \b None :
900 /// @param <GLOBAL> \b None :
901 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Dram_Size(MS_U8 MiuID,MS_U8 DramSize)902 MS_BOOL HAL_MIU_Dram_Size(MS_U8 MiuID, MS_U8 DramSize)
903 {
904 MS_U32 u32RegAddr;
905
906 if(E_MIU_0 == (MIU_ID)MiuID)
907 {
908 u32RegAddr = MIU_PROTECT_DDR_SIZE;
909 switch (DramSize)
910 {
911 case E_MIU_DDR_32MB:
912 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_32MB);
913 break;
914 case E_MIU_DDR_64MB:
915 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_64MB);
916 break;
917 case E_MIU_DDR_128MB:
918 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_128MB);
919 break;
920 case E_MIU_DDR_256MB:
921 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_256MB);
922 break;
923 case E_MIU_DDR_512MB:
924 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_512MB);
925 break;
926 case E_MIU_DDR_1024MB:
927 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_1024MB);
928 break;
929 case E_MIU_DDR_2048MB:
930 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_2048MB);
931 break;
932 default:
933 return false;
934 }
935 }
936 else
937 {
938 u32RegAddr = MIU1_PROTECT_DDR_SIZE;
939 switch (DramSize)
940 {
941 case E_MIU_DDR_32MB:
942 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_32MB);
943 break;
944 case E_MIU_DDR_64MB:
945 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_64MB);
946 break;
947 case E_MIU_DDR_128MB:
948 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_128MB);
949 break;
950 case E_MIU_DDR_256MB:
951 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_256MB);
952 break;
953 case E_MIU_DDR_512MB:
954 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_512MB);
955 break;
956 case E_MIU_DDR_1024MB:
957 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_1024MB);
958 break;
959 case E_MIU_DDR_2048MB:
960 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_2048MB);
961 break;
962 default:
963 return false;
964 }
965 }
966 return true;
967 }
968
969 ////////////////////////////////////////////////////////////////////////////////
970 /// @brief \b Function \b Name: HAL_MIU_Dram_ReadSize()
971 /// @brief \b Function \b Description: Set up Dram size for MIU protect
972 /// @param MiuID \b IN : MIU ID
973 /// @param DramSize \b IN : Specified Dram size for MIU protect
974 /// @param <OUT> \b None :
975 /// @param <RET> \b None :
976 /// @param <GLOBAL> \b None :
977 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Dram_ReadSize(MS_U8 MiuID,MIU_DDR_SIZE * pDramSize)978 MS_BOOL HAL_MIU_Dram_ReadSize(MS_U8 MiuID, MIU_DDR_SIZE *pDramSize)
979 {
980 return FALSE;
981 }
982
983 ////////////////////////////////////////////////////////////////////////////////
984 /// @brief \b Function \b Name: MDrv_MIU_GetClinetNumber()
985 /// @brief \b Function \b Description: Get the number of clients for specific MIU block
986 /// @param DramSize \b IN : MIU Block to protect (0 ~ 3)
987 /// @param <OUT> \b None :
988 /// @param <RET> \b None :
989 /// @param <GLOBAL> \b None :
990 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ClinetNumber(MS_U8 u8Blockx)991 MS_U8 HAL_MIU_ClinetNumber(MS_U8 u8Blockx)
992 {
993 MS_U8 u8ClientNumber;
994
995 switch (u8Blockx)
996 {
997 case E_MIU_BLOCK_0:
998 u8ClientNumber = MIU_BLOCK0_CLIENT_NUMBER;
999 break;
1000 case E_MIU_BLOCK_1:
1001 u8ClientNumber = MIU_BLOCK1_CLIENT_NUMBER;
1002 break;
1003 case E_MIU_BLOCK_2:
1004 u8ClientNumber = MIU_BLOCK2_CLIENT_NUMBER;
1005 break;
1006 case E_MIU_BLOCK_3:
1007 u8ClientNumber = MIU_BLOCK3_CLIENT_NUMBER;
1008 break;
1009 default:
1010 u8ClientNumber = 0;
1011 }
1012
1013 return u8ClientNumber;
1014 }
1015
1016 ////////////////////////////////////////////////////////////////////////////////
1017 /// @brief \b Function \b Name: HAL_MIU_Protect()
1018 /// @brief \b Function \b Description: Enable/Disable MIU Protection mode
1019 /// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4)
1020 /// @param *pu8ProtectId \b IN : Allow specified client IDs to write
1021 /// @param u32Start \b IN : Starting address
1022 /// @param u32End \b IN : End address
1023 /// @param bSetFlag \b IN : Disable or Enable MIU protection
1024 /// - -Disable(0)
1025 /// - -Enable(1)
1026 /// @param <OUT> \b None :
1027 /// @param <RET> \b None :
1028 /// @param <GLOBAL> \b None :
1029 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Protect(MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32Start,MS_U32 u32End,MS_BOOL bSetFlag)1030 MS_BOOL HAL_MIU_Protect(
1031 MS_U8 u8Blockx,
1032 MS_U8 *pu8ProtectId,
1033 MS_U32 u32Start,
1034 MS_U32 u32End,
1035 MS_BOOL bSetFlag
1036 )
1037 {
1038 MS_U32 u32RegAddr;
1039 MS_U32 u32RegAddrStar;
1040 MS_U32 u32RegAddrMSB;
1041 MS_U32 u32RegAddrIDenable;
1042 MS_U32 u32MiuProtectEn;
1043 MS_U32 u32Reg;
1044 MS_U16 u16Data;
1045 MS_U16 u16Data1;
1046 MS_U8 u8Data;
1047 MS_U8 u8MiuSel;
1048
1049 u8MiuSel = E_MIU_0;
1050 // Incorrect Block ID
1051 if(u8Blockx > 3)
1052 {
1053 MIU_HAL_ERR("Err: Out of the number of protect device\n")
1054 return false;
1055 }
1056 else if(((u32Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ((u32End & ((1 << MIU_PAGE_SHIFT) -1)) != 0))
1057 {
1058 MIU_HAL_ERR("Err: Protected address should be aligned to 8KB\n")
1059 return false;
1060 }
1061 else if(u32Start >= u32End)
1062 {
1063 MIU_HAL_ERR("Err: Start address is equal to or more than end address\n")
1064 return false;
1065 }
1066
1067 //write_enable
1068 u8Data = 1 << u8Blockx;
1069
1070 if( u32Start < HAL_MIU1_BASE)
1071 {
1072 u32MiuProtectEn = MIU_PROTECT_EN;
1073 u32Reg = MIU_REG_BASE;
1074
1075 switch (u8Blockx)
1076 {
1077 case E_MIU_BLOCK_0:
1078 u32RegAddr = MIU_PROTECT0_ID0;
1079 u32RegAddrMSB = MIU_PROTECT0_MSB;
1080 u32RegAddrStar = MIU_PROTECT0_START;
1081 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
1082 break;
1083 case E_MIU_BLOCK_1:
1084 u32RegAddr = MIU_PROTECT0_ID0;
1085 u32RegAddrMSB = MIU_PROTECT1_MSB;
1086 u32RegAddrStar = MIU_PROTECT1_START;
1087 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
1088 break;
1089 case E_MIU_BLOCK_2:
1090 u32RegAddr = MIU_PROTECT0_ID0;
1091 u32RegAddrMSB = MIU_PROTECT2_MSB;
1092 u32RegAddrStar = MIU_PROTECT2_START;
1093 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
1094 break;
1095 case E_MIU_BLOCK_3:
1096 u32RegAddr = MIU_PROTECT0_ID0;
1097 u32RegAddrMSB = MIU_PROTECT3_MSB;
1098 u32RegAddrStar = MIU_PROTECT3_START;
1099 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
1100 break;
1101 default:
1102 return false;
1103 }
1104 }
1105 else
1106 {
1107 u32MiuProtectEn = MIU1_PROTECT_EN;
1108 u32Reg = MIU1_REG_BASE;
1109
1110 switch (u8Blockx)
1111 {
1112 case E_MIU_BLOCK_0:
1113 u32RegAddr = MIU1_PROTECT0_ID0;
1114 u32RegAddrMSB = MIU1_PROTECT0_MSB;
1115 u32RegAddrStar = MIU1_PROTECT0_START;
1116 u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE;
1117 break;
1118 break;
1119 case E_MIU_BLOCK_1:
1120 u32RegAddr = MIU1_PROTECT0_ID0;
1121 u32RegAddrMSB = MIU1_PROTECT1_MSB;
1122 u32RegAddrStar = MIU1_PROTECT1_START;
1123 u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE;
1124 break;
1125 case E_MIU_BLOCK_2:
1126 u32RegAddr = MIU1_PROTECT0_ID0;
1127 u32RegAddrMSB = MIU1_PROTECT2_MSB;
1128 u32RegAddrStar = MIU1_PROTECT2_START;
1129 u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE;
1130 break;
1131 case E_MIU_BLOCK_3:
1132 u32RegAddr = MIU1_PROTECT0_ID0;
1133 u32RegAddrMSB = MIU1_PROTECT3_MSB;
1134 u32RegAddrStar = MIU1_PROTECT3_START;
1135 u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE;
1136 break;
1137 default:
1138 return false;
1139 }
1140 u32Start-=HAL_MIU1_BASE;
1141 u32End-=HAL_MIU1_BASE;;
1142 u8MiuSel = E_MIU_1;
1143 }
1144
1145 // Disable MIU protect
1146 HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data,DISABLE);
1147
1148 if ( bSetFlag )
1149 {
1150 // Set Protect IDs
1151 if(HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable) == FALSE)
1152 {
1153 return FALSE;
1154 }
1155
1156 // Set BIT29,30 of start/end address
1157 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1158 u16Data1 &= ~(0x0003 << (u8Blockx * 4));
1159 u16Data1 |= (MS_U16)((u32Start >> 29) << (u8Blockx * 4));
1160 u16Data1 &= ~(0x0003 << (u8Blockx * 4 + 2));
1161 u16Data1 |= (MS_U16)(((u32End -1) >> 29) << (u8Blockx * 4 + 2));
1162 HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1);
1163
1164 // Start Address
1165 u16Data = (MS_U16)(u32Start >> MIU_PAGE_SHIFT); //8k/unit
1166 HAL_MIU_Write2Byte(u32RegAddrStar , u16Data);
1167
1168 // End Address
1169 u16Data = (MS_U16)((u32End >> MIU_PAGE_SHIFT)-1); //8k/unit;
1170 HAL_MIU_Write2Byte(u32RegAddrStar + 2, u16Data);
1171
1172 // Enable MIU protect
1173 HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE);
1174 }
1175 else
1176 {
1177 // Reset Protect IDs
1178 HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable);
1179 }
1180
1181 // clear log
1182 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
1183 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
1184
1185 return TRUE;
1186 }
1187
1188 ////////////////////////////////////////////////////////////////////////////////
1189 /// @brief \b Function \b Name: HAL_MIU_ProtectEx()
1190 /// @brief \b Function \b Description: Enable/Disable MIU Protection mode
1191 /// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4)
1192 /// @param *pu32ProtectId \b IN : Allow specified client IDs to write
1193 /// @param u32Start \b IN : Starting address
1194 /// @param u32End \b IN : End address
1195 /// @param bSetFlag \b IN : Disable or Enable MIU protection
1196 /// - -Disable(0)
1197 /// - -Enable(1)
1198 /// @param <OUT> \b None :
1199 /// @param <RET> \b None :
1200 /// @param <GLOBAL> \b None :
1201 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ProtectEx(MS_U8 u8Blockx,MS_U32 * pu32ProtectId,MS_PHY phyStart,MS_PHY phyEnd,MS_BOOL bSetFlag)1202 MS_BOOL HAL_MIU_ProtectEx(
1203 MS_U8 u8Blockx,
1204 MS_U32 *pu32ProtectId,
1205 MS_PHY phyStart,
1206 MS_PHY phyEnd,
1207 MS_BOOL bSetFlag
1208 )
1209 {
1210 MS_U32 u32RegAddr;
1211 MS_U32 u32RegAddrStar;
1212 MS_U32 u32RegAddrMSB;
1213 MS_U32 u32RegAddrIDenable;
1214 MS_U32 u32MiuProtectEn;
1215 MS_U32 u32Reg;
1216 MS_U16 u16Data;
1217 MS_U16 u16Data1;
1218 MS_U8 u8Data;
1219 MS_U8 u8MiuSel;
1220
1221 u8MiuSel = E_MIU_0;
1222 // Incorrect Block ID
1223 if(u8Blockx > 3)
1224 {
1225 MIU_HAL_ERR("Err: Out of the number of protect device\n")
1226 return false;
1227 }
1228 else if(((phyStart & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ((phyEnd & ((1 << MIU_PAGE_SHIFT) -1)) != 0))
1229 {
1230 MIU_HAL_ERR("Err: Protected address should be aligned to 8KB\n")
1231 return false;
1232 }
1233 else if(phyStart >= phyEnd)
1234 {
1235 MIU_HAL_ERR("Err: Start address is equal to or more than end address\n")
1236 return false;
1237 }
1238
1239 //write_enable
1240 u8Data = 1 << u8Blockx;
1241
1242 if( phyStart < HAL_MIU1_BASE)
1243 {
1244 u32MiuProtectEn = MIU_PROTECT_EN;
1245 u32Reg = MIU_REG_BASE;
1246
1247 switch (u8Blockx)
1248 {
1249 case E_MIU_BLOCK_0:
1250 u32RegAddr = MIU_PROTECT0_ID0;
1251 u32RegAddrMSB = MIU_PROTECT0_MSB;
1252 u32RegAddrStar = MIU_PROTECT0_START;
1253 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
1254 break;
1255 case E_MIU_BLOCK_1:
1256 u32RegAddr = MIU_PROTECT0_ID0;
1257 u32RegAddrMSB = MIU_PROTECT1_MSB;
1258 u32RegAddrStar = MIU_PROTECT1_START;
1259 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
1260 break;
1261 case E_MIU_BLOCK_2:
1262 u32RegAddr = MIU_PROTECT0_ID0;
1263 u32RegAddrMSB = MIU_PROTECT2_MSB;
1264 u32RegAddrStar = MIU_PROTECT2_START;
1265 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
1266 break;
1267 case E_MIU_BLOCK_3:
1268 u32RegAddr = MIU_PROTECT0_ID0;
1269 u32RegAddrMSB = MIU_PROTECT3_MSB;
1270 u32RegAddrStar = MIU_PROTECT3_START;
1271 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
1272 break;
1273 default:
1274 return false;
1275 }
1276 }
1277 else
1278 {
1279 u32MiuProtectEn = MIU1_PROTECT_EN;
1280 u32Reg = MIU1_REG_BASE;
1281
1282 switch (u8Blockx)
1283 {
1284 case E_MIU_BLOCK_0:
1285 u32RegAddr = MIU1_PROTECT0_ID0;
1286 u32RegAddrMSB = MIU1_PROTECT0_MSB;
1287 u32RegAddrStar = MIU1_PROTECT0_START;
1288 u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE;
1289 break;
1290 break;
1291 case E_MIU_BLOCK_1:
1292 u32RegAddr = MIU1_PROTECT0_ID0;
1293 u32RegAddrMSB = MIU1_PROTECT1_MSB;
1294 u32RegAddrStar = MIU1_PROTECT1_START;
1295 u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE;
1296 break;
1297 case E_MIU_BLOCK_2:
1298 u32RegAddr = MIU1_PROTECT0_ID0;
1299 u32RegAddrMSB = MIU1_PROTECT2_MSB;
1300 u32RegAddrStar = MIU1_PROTECT2_START;
1301 u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE;
1302 break;
1303 case E_MIU_BLOCK_3:
1304 u32RegAddr = MIU1_PROTECT0_ID0;
1305 u32RegAddrMSB = MIU1_PROTECT3_MSB;
1306 u32RegAddrStar = MIU1_PROTECT3_START;
1307 u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE;
1308 break;
1309 default:
1310 return false;
1311 }
1312 phyStart-=HAL_MIU1_BASE;
1313 phyEnd-=HAL_MIU1_BASE;;
1314 u8MiuSel = E_MIU_1;
1315 }
1316
1317 // Disable MIU protect
1318 HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data,DISABLE);
1319
1320 if ( bSetFlag )
1321 {
1322 // Set Protect IDs
1323 if(HAL_MIU_SetGroupID2(u8MiuSel, u8Blockx, pu32ProtectId, u32RegAddr, u32RegAddrIDenable) == FALSE)
1324 {
1325 return FALSE;
1326 }
1327
1328 // Set BIT29,30 of start/end address
1329 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1330 u16Data1 &= ~(0x0003 << (u8Blockx * 4));
1331 u16Data1 |= (MS_U16)((phyStart >> 29) << (u8Blockx * 4));
1332 u16Data1 &= ~(0x0003 << (u8Blockx * 4 + 2));
1333 u16Data1 |= (MS_U16)(((phyEnd -1) >> 29) << (u8Blockx * 4 + 2));
1334 HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1);
1335
1336 // Start Address
1337 u16Data = (MS_U16)(phyStart >> MIU_PAGE_SHIFT); //8k/unit
1338 HAL_MIU_Write2Byte(u32RegAddrStar , u16Data);
1339
1340 // End Address
1341 u16Data = (MS_U16)((phyEnd >> MIU_PAGE_SHIFT)-1); //8k/unit;
1342 HAL_MIU_Write2Byte(u32RegAddrStar + 2, u16Data);
1343
1344 // Enable MIU protect
1345 HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE);
1346 }
1347 else
1348 {
1349 // Reset Protect IDs
1350 HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, NULL, u32RegAddr, u32RegAddrIDenable);
1351 }
1352
1353 // clear log
1354 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
1355 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
1356
1357 return TRUE;
1358 }
1359
1360 #define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO)
1361 #define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID)
1362
HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev,MIU_PortectInfo * pInfo)1363 MS_BOOL HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev, MIU_PortectInfo *pInfo)
1364 {
1365 MS_U16 ret = 0;
1366 MS_U16 loaddr = 0;
1367 MS_U16 hiaddr = 0;
1368 MS_U32 u32Address = 0;
1369 MS_U32 u32Reg = (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE;
1370
1371 if (!pInfo)
1372 return FALSE;
1373
1374 ret = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_STATUS);
1375 loaddr = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_LOADDR);
1376 hiaddr = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_HIADDR);
1377
1378 pInfo->bHit = false;
1379
1380 if (REG_MIU_PROTECT_HIT_FALG & ret)
1381 {
1382 pInfo->bHit = TRUE;
1383
1384 pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(ret);
1385 pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(ret) >> 4);
1386 pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(ret) & 0x0F);
1387 u32Address = (MS_U32)((hiaddr << 16) | loaddr) ;
1388 u32Address = u32Address * MIU_PROTECT_ADDRESS_UNIT;
1389
1390 printf("MIU%u Block:%u Group:%u ClientID:%u Hitted_Address:0x%lx<->0x%lx\n", u8MiuDev,
1391 pInfo->u8Block, pInfo->u8Group, pInfo->u8ClientID, (long unsigned int)u32Address, (long unsigned int)(u32Address + MIU_PROTECT_ADDRESS_UNIT - 1));
1392
1393 //clear log
1394 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
1395 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
1396 }
1397
1398 return TRUE;
1399 }
1400
1401 ////////////////////////////////////////////////////////////////////////////////
1402 /// @brief \b Function \b Name: HAL_MIU_SetSsc()
1403 /// @brief \b Function \b Description: MDrv_MIU_SetSsc, @Step & Span
1404 /// @param u16Fmodulation \b IN : 20KHz ~ 40KHz (Input Value = 20 ~ 40)
1405 /// @param u16FDeviation \b IN : under 0.1% ~ 2% (Input Value = 1 ~ 20)
1406 /// @param bEnable \b IN :
1407 /// @param None \b OUT :
1408 /// @param None \b RET :
1409 /// @param None \b GLOBAL :
1410 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetSsc(MS_U8 u8MiuDev,MS_U16 u16Fmodulation,MS_U16 u16FDeviation,MS_BOOL bEnable)1411 MS_BOOL HAL_MIU_SetSsc(MS_U8 u8MiuDev, MS_U16 u16Fmodulation, MS_U16 u16FDeviation, MS_BOOL bEnable)
1412 {
1413 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE;
1414 MS_U16 u16DDFSpan;
1415 MS_U16 u16Input_DIV_First,u16Input_DIV_Second,u16Loop_DIV_First,u16Loop_DIV_Second;
1416 MS_U8 u8Temp,i;
1417
1418 //Pre check the input
1419 if(u8MiuDev == E_MIU_0)
1420 {
1421 uRegBase = MIU_ATOP_BASE;
1422 }
1423 else if(u8MiuDev == E_MIU_1)
1424 {
1425 uRegBase = MIU1_ATOP_BASE;
1426 }
1427 else
1428 {
1429 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuDev );
1430 return FALSE;
1431 }
1432
1433 HAL_MIU_SSC_DBG(printf("MMIO base:%lx uRegBase:%lx\n", _gMIU_MapBase, uRegBase));
1434
1435 if ((u16Fmodulation<20)||(u16Fmodulation>40))
1436 {
1437 MIU_HAL_ERR("SSC u16Fmodulation Error...(20KHz - 40KHz)\n");
1438 return 0;
1439 }
1440
1441 if ((u16FDeviation<1)||(u16FDeviation>20))
1442 {
1443 MIU_HAL_ERR("SSC u16FDeviation Error...(0.1%% - 2%% ==> 1 ~20)\n");
1444 return 0;
1445 }
1446
1447 HAL_MIU_SSC_DBG(printf("---> u16Fmodulation = %d u16FDeviation = %d \n",(int)u16Fmodulation,(int)u16FDeviation));
1448 //<1>.Caculate DDFM = (Loop_DIV_First * Loop_DIV_Second)/(Input_DIV_First * Input_DIV_Second);
1449 //Prepare Input_DIV_First
1450 u8Temp = ((MS_U16)(HAL_MIU_Read2Byte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0x3)); //Bit 9,8 (0x110D36)
1451 u16Input_DIV_First = 0x01;
1452 for (i=0;i<u8Temp;i++)
1453 u16Input_DIV_First = u16Input_DIV_First << 1;
1454 //Prepare Input_DIV_Second
1455 u16Input_DIV_Second = 0;// no mapping in Einstein(HAL_MIU_ReadByte(uRegBase+MIU_PLL_INPUT_DIV_2ND)); //Bit 0~7 (0x101222)
1456 if (u16Input_DIV_Second == 0)
1457 u16Input_DIV_Second = 1;
1458 //Prepare Loop_DIV_First
1459 u8Temp = ((HAL_MIU_ReadByte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0xC)>>2); //Bit 11,10 (0x110D36)
1460 u16Loop_DIV_First = 0x01;
1461 for (i=0;i<u8Temp;i++)
1462 u16Loop_DIV_First = u16Loop_DIV_First << 1;
1463
1464 //Prepare Loop_DIV_Second
1465 u16Loop_DIV_Second = (HAL_MIU_ReadByte(uRegBase+MIU_PLL_LOOP_DIV_2ND))&0x1F; //Bit 0~4 (0x101223)
1466 if (u16Loop_DIV_Second == 0)
1467 u16Loop_DIV_Second = 1;
1468
1469 //<2>.From DDFSET register to get DDRPLL
1470 uDDFSET = HAL_MIU_Read4Byte(uRegBase+MIU_DDFSET) & 0x00ffffff;
1471 //DDRPLL = MPPL * DDR_FACTOR * Loop_First * Loop_Second / DDFSET * Input_First * Input_Second
1472 HAL_MIU_SSC_DBG(printf("---> Loop_First:%u Loop_Second:%u\n", u16Loop_DIV_First, u16Loop_DIV_Second));
1473 HAL_MIU_SSC_DBG(printf("---> Input_first:%u Input_second:%u\n", u16Input_DIV_First, u16Input_DIV_Second));
1474 uDDR_MHz = (MPPL * DDR_FACTOR * u16Loop_DIV_First * u16Loop_DIV_Second)/ (uDDFSET*u16Input_DIV_First*u16Input_DIV_Second);
1475 HAL_MIU_SSC_DBG(printf("---> uDDFSET = 0x%lx\n",uDDFSET));
1476 HAL_MIU_SSC_DBG(printf("---> DDR_MHZ = 0x%lx (%d MHz)\n",uDDR_MHz,(int)uDDR_MHz));
1477
1478 //<3>.Caculate DDFSPAN = (MPLL * DDFSPAN_FACTOR * MHz) / (DDFSET * Fmodulation * KHz)
1479 u16DDFSpan = (MS_U32)((DDFSPAN_FACTOR * MPPL/u16Fmodulation)* 1000/uDDFSET);
1480 HAL_MIU_SSC_DBG(printf("---> DDFSPAN = 0x%x (%d)\n",u16DDFSpan,(int)u16DDFSpan));
1481 if (u16DDFSpan > 0x3FFF)
1482 {
1483 u16DDFSpan = 0x3FFF;
1484 HAL_MIU_SSC_DBG(printf("??? DDFSPAN overflow > 0x3FFF, Fource set to 0x03FF\n"));
1485 }
1486
1487 //Write to Register
1488 HAL_MIU_Write2Byte(uRegBase+MIU_DDFSPAN,u16DDFSpan);
1489 //<4>.Caculate DDFSTEP = (FDeviation*DDFSET/10)/(DDFSPAN*100)
1490 uDDFStep = (MS_U32)((u16FDeviation * (uDDFSET/10))/(u16DDFSpan*100));
1491 HAL_MIU_SSC_DBG(printf("---> DDFSTEP = 0x%lx (%lu)\n",uDDFStep,uDDFStep));
1492 //Write to Register
1493 uDDFStep &= (0x03FF);
1494 HAL_MIU_Write2Byte(uRegBase+MIU_DDFSTEP,(HAL_MIU_Read2Byte(uRegBase+MIU_DDFSTEP) & (~0x03FF))|uDDFStep);
1495
1496 //<5>.Set ENABLE
1497 if(bEnable == ENABLE)
1498 HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)|0xC0));
1499 else
1500 HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)&(~0xC0))|0x80);
1501
1502 return 1;
1503 }
1504
1505 ////////////////////////////////////////////////////////////////////////////////
1506 /// @brief \b Function \b Name: HAL_MIU_MaskReq()
1507 /// @brief \b Function \b Description: Mask MIU request
1508 /// @param u8Miu IN \b : miu0 or miu1
1509 /// @param eClientID IN \b : client ID
1510 /// @param None OUT \b :
1511 /// @param None RET \b :
1512 /// @param None GLOBAL \b :
1513 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_MaskReq(MS_U8 u8Miu,eMIUClientID eClientID)1514 void HAL_MIU_MaskReq(MS_U8 u8Miu, eMIUClientID eClientID)
1515 {
1516 MS_S16 sVal;
1517
1518 sVal = HAL_MIU_GetClientInfo(u8Miu, eClientID);
1519 if (sVal < 0)
1520 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1521 else
1522 {
1523 MS_U32 u32Reg = REG_MIU_RQX_MASK(MIU_GET_CLIENT_GROUP(sVal));
1524
1525 u32Reg += (u8Miu == 0) ? MIU_REG_BASE : MIU1_REG_BASE;
1526 HAL_MIU_Write2BytesBit(u32Reg, TRUE, BIT(MIU_GET_CLIENT_POS(sVal)));
1527 }
1528 }
1529
1530 ////////////////////////////////////////////////////////////////////////////////
1531 /// @brief \b Function \b Name: HAL_MIU_UnMaskReq()
1532 /// @brief \b Function \b Description: Mask MIU request
1533 /// @param u8Miu IN \b : miu0 or miu1
1534 /// @param eClientID IN \b : client ID
1535 /// @param None OUT \b :
1536 /// @param None RET \b :
1537 /// @param None GLOBAL \b :
1538 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_UnMaskReq(MS_U8 u8Miu,eMIUClientID eClientID)1539 void HAL_MIU_UnMaskReq(MS_U8 u8Miu, eMIUClientID eClientID)
1540 {
1541 MS_S16 sVal;
1542
1543 sVal = HAL_MIU_GetClientInfo(u8Miu, eClientID);
1544 if (sVal < 0)
1545 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1546 else
1547 {
1548 MS_U32 u32Reg = REG_MIU_RQX_MASK(MIU_GET_CLIENT_GROUP(sVal));
1549
1550 u32Reg += (u8Miu == 0) ? MIU_REG_BASE : MIU1_REG_BASE;
1551 HAL_MIU_Write2BytesBit(u32Reg, FALSE, BIT(MIU_GET_CLIENT_POS(sVal)));
1552 }
1553 }
1554
1555 ////////////////////////////////////////////////////////////////////////////////
1556 /// @brief \b Function \b Name: HAL_MIU_SelMIU()
1557 /// @brief \b Function \b Description: MIU selection
1558 /// @param u8MiuDev IN \b : miu device
1559 /// @param u16ClientID IN \b : client ID
1560 /// @param None OUT \b :
1561 /// @param None RET \b :
1562 /// @param None GLOBAL \b :
1563 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SelMIU(eMIU_SelType eType,eMIUClientID eClientID)1564 MS_BOOL HAL_MIU_SelMIU(eMIU_SelType eType, eMIUClientID eClientID)
1565 {
1566 MS_S16 sVal;
1567 MS_U32 u32Reg = 0;
1568
1569 //MIU 0
1570 sVal = HAL_MIU_GetClientInfo(0, eClientID);
1571 if (sVal < 0)
1572 goto fail;
1573
1574 u32Reg = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal));
1575 HAL_MIU_Write2BytesBit(u32Reg, (MIU_SELTYPE_MIU1 == eType), BIT(MIU_GET_CLIENT_POS(sVal)));
1576
1577 //MIU 1
1578 sVal = HAL_MIU_GetClientInfo(1, eClientID);
1579 if (sVal < 0)
1580 goto fail;
1581 u32Reg = MIU1_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal));
1582 HAL_MIU_Write2BytesBit(u32Reg, (MIU_SELTYPE_MIU_ALL == eType), BIT(MIU_GET_CLIENT_POS(sVal)));
1583
1584 return TRUE;
1585
1586 fail:
1587 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1588 return FALSE;
1589 }
1590
1591 ////////////////////////////////////////////////////////////////////////////////
1592 /// @brief \b Function \b Name: MDrv_MIU_Mask_Req_OPM_R()
1593 /// @brief \b Function \b Description: Set OPM MIU mask
1594 /// @param u8Mask IN \b : miu mask
1595 /// @param u8Miu IN \b : miu0 or miu1
1596 /// @param None OUT \b :
1597 /// @param None RET \b :
1598 /// @param None GLOBAL \b :
1599 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_OPM_R(MS_U8 u8Mask,MS_U8 u8Miu)1600 void HAL_MIU_Mask_Req_OPM_R(MS_U8 u8Mask, MS_U8 u8Miu)
1601 {
1602
1603 if(u8Miu == 0)
1604 _MaskMiuReq_OPM_R(u8Mask);
1605 else
1606 _MaskMiu1Req_OPM_R(u8Mask);
1607
1608 }
1609
1610
1611 ////////////////////////////////////////////////////////////////////////////////
1612 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_R()
1613 /// @brief \b Function \b Description: Set OPM MIU mask
1614 /// @param u8Mask IN \b : miu mask
1615 /// @param u8Miu IN \b : miu0 or miu1
1616 /// @param None OUT \b :
1617 /// @param None RET \b :
1618 /// @param None GLOBAL \b :
1619 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_R(MS_U8 u8Mask,MS_U8 u8Miu)1620 void HAL_MIU_Mask_Req_DNRB_R(MS_U8 u8Mask, MS_U8 u8Miu)
1621 {
1622
1623 if (u8Miu == 0)
1624 _MaskMiuReq_DNRB_R(u8Mask);
1625 else
1626 _MaskMiu1Req_DNRB_R(u8Mask);
1627 }
1628
1629
1630 ////////////////////////////////////////////////////////////////////////////////
1631 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_W()
1632 /// @brief \b Function \b Description: Set OPM MIU mask
1633 /// @param u8Mask IN \b : miu mask
1634 /// @param u8Miu IN \b : miu0 or miu1
1635 /// @param None OUT \b :
1636 /// @param None RET \b :
1637 /// @param None GLOBAL \b :
1638 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_W(MS_U8 u8Mask,MS_U8 u8Miu)1639 void HAL_MIU_Mask_Req_DNRB_W(MS_U8 u8Mask, MS_U8 u8Miu)
1640 {
1641
1642 if (u8Miu == 0)
1643 _MaskMiuReq_DNRB_W(u8Mask);
1644 else
1645 _MaskMiu1Req_DNRB_W(u8Mask);
1646 }
1647
1648
1649 ////////////////////////////////////////////////////////////////////////////////
1650 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_RW()
1651 /// @brief \b Function \b Description: Set OPM MIU mask
1652 /// @param u8Mask IN \b : miu mask
1653 /// @param u8Miu IN \b : miu0 or miu1
1654 /// @param None OUT \b :
1655 /// @param None RET \b :
1656 /// @param None GLOBAL \b :
1657 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_RW(MS_U8 u8Mask,MS_U8 u8Miu)1658 void HAL_MIU_Mask_Req_DNRB_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1659 {
1660 if (u8Miu == 0)
1661 _MaskMiuReq_DNRB_RW(u8Mask);
1662 else
1663 _MaskMiu1Req_DNRB_RW(u8Mask);
1664
1665 }
1666
1667
1668 ////////////////////////////////////////////////////////////////////////////////
1669 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_SC_RW()
1670 /// @brief \b Function \b Description: Set OPM MIU mask
1671 /// @param u8Mask IN \b : miu mask
1672 /// @param u8Miu IN \b : miu0 or miu1
1673 /// @param None OUT \b :
1674 /// @param None RET \b :
1675 /// @param None GLOBAL \b :
1676 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_SC_RW(MS_U8 u8Mask,MS_U8 u8Miu)1677 void HAL_MIU_Mask_Req_SC_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1678 {
1679
1680 if (u8Miu == 0)
1681 _MaskMiuReq_SC_RW(u8Mask);
1682 else
1683 _MaskMiu1Req_SC_RW(u8Mask);
1684
1685 }
1686
1687
1688 ////////////////////////////////////////////////////////////////////////////////
1689 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVOP_R()
1690 /// @brief \b Function \b Description: Set OPM MIU mask
1691 /// @param u8Mask IN \b : miu mask
1692 /// @param u8Miu IN \b : miu0 or miu1
1693 /// @param None OUT \b :
1694 /// @param None RET \b :
1695 /// @param None GLOBAL \b :
1696 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVOP_R(MS_U8 u8Mask,MS_U8 u8Miu)1697 void HAL_MIU_Mask_Req_MVOP_R(MS_U8 u8Mask, MS_U8 u8Miu)
1698 {
1699 HAL_MIU_MaskReq(u8Miu, MIU_CLIENT_MVOP_64BIT_R);
1700 }
1701
1702 ////////////////////////////////////////////////////////////////////////////////
1703 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_R()
1704 /// @brief \b Function \b Description: Set OPM MIU mask
1705 /// @param u8Mask IN \b : miu mask
1706 /// @param u8Miu IN \b : miu0 or miu1
1707 /// @param None OUT \b :
1708 /// @param None RET \b :
1709 /// @param None GLOBAL \b :
1710 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_R(MS_U8 u8Mask,MS_U8 u8Miu)1711 void HAL_MIU_Mask_Req_MVD_R(MS_U8 u8Mask, MS_U8 u8Miu)
1712 {
1713 _FUNC_NOT_USED();
1714 }
1715
1716 ////////////////////////////////////////////////////////////////////////////////
1717 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_W()
1718 /// @brief \b Function \b Description: Set OPM MIU mask
1719 /// @param u8Mask IN \b : miu mask
1720 /// @param u8Miu IN \b : miu0 or miu1
1721 /// @param None OUT \b :
1722 /// @param None RET \b :
1723 /// @param None GLOBAL \b :
1724 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_W(MS_U8 u8Mask,MS_U8 u8Miu)1725 void HAL_MIU_Mask_Req_MVD_W(MS_U8 u8Mask, MS_U8 u8Miu)
1726 {
1727 _FUNC_NOT_USED();
1728 }
1729
1730
1731 ////////////////////////////////////////////////////////////////////////////////
1732 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_RW()
1733 /// @brief \b Function \b Description: Set OPM MIU mask
1734 /// @param u8Mask IN \b : miu mask
1735 /// @param u8Miu IN \b : miu0 or miu1
1736 /// @param None OUT \b :
1737 /// @param None RET \b :
1738 /// @param None GLOBAL \b :
1739 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_RW(MS_U8 u8Mask,MS_U8 u8Miu)1740 void HAL_MIU_Mask_Req_MVD_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1741 {
1742 HAL_MIU_MaskReq(u8Miu, MIU_CLIENT_MVD_RW);
1743 }
1744
1745
1746 ////////////////////////////////////////////////////////////////////////////////
1747 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_AUDIO_RW()
1748 /// @brief \b Function \b Description: Set OPM MIU mask
1749 /// @param u8Mask IN \b : miu mask
1750 /// @param u8Miu IN \b : miu0 or miu1
1751 /// @param None OUT \b :
1752 /// @param None RET \b :
1753 /// @param None GLOBAL \b :
1754 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_AUDIO_RW(MS_U8 u8Mask,MS_U8 u8Miu)1755 void HAL_MIU_Mask_Req_AUDIO_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1756 {
1757 if (u8Miu == 0)
1758 _MaskMiuReq_AUDIO_RW(u8Mask);
1759 else
1760 _MaskMiu1Req_AUDIO_RW(u8Mask);
1761
1762 }
1763
1764 ////////////////////////////////////////////////////////////////////////////////
1765 /// @brief \b Function \b Name: HAL_MIU_GET_MUX()
1766 /// @brief \b Function \b Description:
1767 /// @param None IN \b :
1768 /// @param None IN \b :
1769 /// @param None OUT \b :
1770 /// @param None RET \b :
1771 /// @param None GLOBAL \b :
1772 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GET_MUX(void)1773 MS_U16 HAL_MIU_GET_MUX(void)
1774 {
1775 return 0x0000;
1776 }
1777
1778 ////////////////////////////////////////////////////////////////////////////////
1779 /// @brief \b Function \b Name: HAL_MIU_SwitchMIU()
1780 /// @brief \b Function \b Description:
1781 /// @param u8MiuID \b IN : select MIU0 or MIU1
1782 /// @param None \b RET:
1783 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_VOP_SwitchMIU(MS_U8 u8MiuID)1784 void HAL_MIU_VOP_SwitchMIU(MS_U8 u8MiuID)
1785 {
1786 HAL_MIU_SelMIU((eMIU_SelType)u8MiuID, MIU_CLIENT_MVOP_64BIT_R);
1787 }
1788
1789 ////////////////////////////////////////////////////////////////////////////////
1790 /// @brief \b Function \b Name: HAL_MIU_IsI64Mode()
1791 /// @brief \b Function \b Description:
1792 /// @param None \b RET: 0: not support, 64 or 128 bits
1793 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_IsI64Mode(void)1794 MS_U16 HAL_MIU_IsI64Mode(void)
1795 {
1796 return (HAL_MIU_ReadByte(MIU_REG_BASE+0x04) & REG_MIU_I64_MODE) ? (64) : (128);
1797 }
1798
1799 ////////////////////////////////////////////////////////////////////////////////
1800 /// @brief \b Function \b Name: HAL_MIU_IsInitMiu1()
1801 /// @brief \b Function \b Description:
1802 /// @param None \b RET:
1803 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_IsInitMiu1(void)1804 MS_BOOL HAL_MIU_IsInitMiu1(void)
1805 {
1806 return (HAL_MIU_Read2Byte(MIU1_REG_BASE) & REG_MIU_INIT_DONE) ? TRUE : FALSE;
1807 }
1808
1809 ////////////////////////////////////////////////////////////////////////////////
1810 /// @brief \b Function \b Name: HAL_MIU_SetGroupPriority()
1811 /// @brief \b Function \b Description: This function for set each group priority
1812 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1813 /// @param sPriority \b IN : gropu priority
1814 /// @param None \b RET: 0: Fail 1: Ok
1815 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetGroupPriority(MS_U8 u8MiuDev,MIU_GroupPriority sPriority)1816 MS_BOOL HAL_MIU_SetGroupPriority(MS_U8 u8MiuDev, MIU_GroupPriority sPriority)
1817 {
1818 MS_U8 u8Val = 0;
1819 MS_U32 u32RegAddr = REG_MIU_GROUP_PRIORITY;
1820
1821 u8Val = (sPriority.u84th << 6 | sPriority.u83rd << 4 | sPriority.u82nd << 2 | sPriority.u81st);
1822 printf("Change miu%u group priority:%x\n", u8MiuDev, u8Val);
1823
1824 u32RegAddr += (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE;
1825 HAL_MIU_Write2BytesBit(u32RegAddr,DISABLE, BIT8);
1826 HAL_MIU_WriteByte(u32RegAddr, u8Val);
1827 HAL_MIU_Write2BytesBit(u32RegAddr,ENABLE, BIT8);
1828 return TRUE;
1829 }
1830
1831 ////////////////////////////////////////////////////////////////////////////////
1832 /// @brief \b Function \b Name: HAL_MIU_SetGroupPriority()
1833 /// @brief \b Function \b Description: This function for set each group priority
1834 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1835 /// @param eClientID \b IN : client ID
1836 /// @param bMask \b IN : TRUE: Mask high priority FALSE: Unmask hih priority
1837 /// @param None \b RET: 0: Fail 1: Ok
1838 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetHPriorityMask(MS_U8 u8MiuDev,eMIUClientID eClientID,MS_BOOL bMask)1839 MS_BOOL HAL_MIU_SetHPriorityMask(MS_U8 u8MiuDev, eMIUClientID eClientID, MS_BOOL bMask)
1840 {
1841 MS_S16 sVal;
1842
1843 sVal = HAL_MIU_GetClientInfo(u8MiuDev, eClientID);
1844 if (sVal < 0)
1845 {
1846 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1847 return FALSE;
1848 }
1849 else
1850 {
1851 MS_U32 u32Reg = REG_MIU_RQX_HPMASK(MIU_GET_CLIENT_GROUP(sVal));
1852
1853 u32Reg += (u8MiuDev == 0) ? MIU_REG_BASE : MIU1_REG_BASE;
1854 HAL_MIU_Write2BytesBit(u32Reg, bMask, BIT(MIU_GET_CLIENT_POS(sVal)));
1855 }
1856 return TRUE;
1857 }
1858
HAL_MIU_GetAutoPhaseResult(MS_U32 * miu0,MS_U32 * miu1)1859 MS_BOOL HAL_MIU_GetAutoPhaseResult(MS_U32 *miu0, MS_U32 *miu1)
1860 {
1861 static MS_U32 u32Miu0 = 0, u32Miu1 = 0;
1862
1863 if (!u32Miu0)
1864 {
1865 u32Miu0 = HAL_MIU_Read4Byte(0x3390); //miu0 result
1866 u32Miu1 = HAL_MIU_Read4Byte(0x3394); //miu1 result
1867 *miu0 = u32Miu0;
1868 *miu1 = u32Miu1;
1869 }
1870 else
1871 {
1872 *miu0 = u32Miu0;
1873 *miu1 = u32Miu1;
1874 }
1875 return TRUE;
1876 }
1877
HAL_MIU_EnableScramble(MS_BOOL bEnable)1878 MS_BOOL HAL_MIU_EnableScramble(MS_BOOL bEnable)
1879 {
1880 return FALSE; // not implemented yet
1881 }
1882
HAL_MIU_IsScrambleEnabled(void)1883 MS_BOOL HAL_MIU_IsScrambleEnabled(void)
1884 {
1885 return FALSE; // not implemented yet
1886 }
1887
1888 ////////////////////////////////////////////////////////////////////////////////
1889 /// @brief \b Function \b Name: HAL_MIU_SetLoadingRequest
1890 /// @brief \b Function \b Description: Set loading request
1891 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1892 /// @return \b 0: Fail 1: OK
1893 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetLoadingRequest(MS_U8 u8MiuDev)1894 MS_BOOL HAL_MIU_SetLoadingRequest(MS_U8 u8MiuDev)
1895 {
1896 MS_U32 u32RegAddr;
1897
1898 if (u8MiuDev == 1)
1899 {
1900 u32RegAddr = MIU1_BW_REQUEST;
1901 }
1902 else
1903 {
1904 u32RegAddr = MIU_BW_REQUEST;
1905 }
1906
1907 HAL_MIU_Write2Byte(u32RegAddr, 0x0050);
1908 HAL_MIU_Write2Byte(u32RegAddr, 0x0051);
1909
1910 return TRUE;
1911 }
1912
1913 ////////////////////////////////////////////////////////////////////////////////
1914 /// @brief \b Function \b Name: HAL_MIU_GetLoadingRequest
1915 /// @brief \b Function \b Description: Get loading request
1916 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1917 /// @param *u32Loading \b IN : percentage of MIU loading
1918 /// @return \b 0: Fail 1: OK
1919 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetLoadingRequest(MS_U8 u8MiuDev,MS_U32 * u32Loading)1920 MS_BOOL HAL_MIU_GetLoadingRequest(MS_U8 u8MiuDev, MS_U32 *u32Loading)
1921 {
1922 MS_U16 u16Reg;
1923 MS_U32 u32RegAddr;
1924
1925 if (u8MiuDev == 1)
1926 {
1927 u32RegAddr = MIU1_BW_RESULT;
1928 }
1929 else
1930 {
1931 u32RegAddr = MIU_BW_RESULT;
1932 }
1933
1934 u16Reg = HAL_MIU_Read2Byte(u32RegAddr);
1935 *u32Loading =(MS_U32)((float)u16Reg * 100 / 0x400);
1936
1937 printf("MIU%d loading: %d%%\n", u8MiuDev, (int)(*u32Loading));
1938
1939 return TRUE;
1940 }
1941
1942 ////////////////////////////////////////////////////////////////////////////////
1943 /// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource
1944 /// @brief \b Function \b Description: Parse occupied resource to software structure
1945 /// @return \b 0: Fail 1: OK
1946 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ParseOccupiedResource(void)1947 MS_BOOL HAL_MIU_ParseOccupiedResource(void)
1948 {
1949 MS_U8 u8MiuSel;
1950 MS_U8 u8Blockx;
1951 MS_U8 u8ClientID;
1952 MS_U16 u16idenable;
1953 MS_U32 u32index;
1954 MS_U32 u32RegAddr;
1955 MS_U32 u32RegAddrIDenable;
1956
1957 for(u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++)
1958 {
1959 for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++)
1960 {
1961 if(u8MiuSel == E_MIU_0)
1962 {
1963 u32RegAddr = MIU_PROTECT0_ID0;
1964
1965 switch (u8Blockx)
1966 {
1967 case E_MIU_BLOCK_0:
1968 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
1969 break;
1970 case E_MIU_BLOCK_1:
1971 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
1972 break;
1973 case E_MIU_BLOCK_2:
1974 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
1975 break;
1976 case E_MIU_BLOCK_3:
1977 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
1978 break;
1979 default:
1980 return false;
1981 }
1982 }// if(u8MiuSel == E_MIU_0)
1983 else
1984 {
1985 u32RegAddr = MIU1_PROTECT0_ID0;
1986
1987 switch (u8Blockx)
1988 {
1989 case E_MIU_BLOCK_0:
1990 u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE;
1991 break;
1992 case E_MIU_BLOCK_1:
1993 u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE;
1994 break;
1995 case E_MIU_BLOCK_2:
1996 u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE;
1997 break;
1998 case E_MIU_BLOCK_3:
1999 u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE;
2000 break;
2001 default:
2002 return false;
2003 }
2004 }// if(u8MiuSel == E_MIU_0)
2005
2006 u16idenable = HAL_MIU_Read2Byte(u32RegAddrIDenable);
2007 for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++)
2008 {
2009 IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16idenable >> u32index) & 0x1)? 1: 0;
2010 }
2011 }//for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++)
2012
2013 for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++)
2014 {
2015 u8ClientID = HAL_MIU_ReadByte(u32RegAddr + u32index);
2016 IDs[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID];
2017 }
2018 }//for(u8MiuSel = E_MIU_0; u8MiuSel < E_MIU_NUM; u8MiuSel++)
2019
2020 return TRUE;
2021 }
2022
2023
HAL_MIU_PrintMIUProtectArea(MS_U8 u8Blockx,MS_U8 miu_dev)2024 void HAL_MIU_PrintMIUProtectArea(MS_U8 u8Blockx,MS_U8 miu_dev)
2025 {
2026
2027 MS_U16 val_16,val1_16,val2_16;
2028 MS_U32 val_32;
2029 MS_U32 u32RegAddrMSB;
2030 MS_U32 u32RegAddrStar;
2031
2032
2033 if( miu_dev == 0 )
2034 {
2035 u32RegAddrMSB = MIU_PROTECT0_MSB;
2036 switch (u8Blockx)
2037 {
2038 case 0:
2039 u32RegAddrStar = MIU_PROTECT0_START;
2040 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2041 val1_16 = ( val1_16 & 0x1 );
2042 val2_16 = ( val1_16 & 0xC );
2043 break;
2044
2045 case 1:
2046 u32RegAddrStar = MIU_PROTECT1_START;
2047 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2048 val1_16 = ( val1_16 & 0x10 );
2049 val2_16 = ( val1_16 & 0xC0 );
2050 break;
2051
2052 case 2:
2053 u32RegAddrStar = MIU_PROTECT2_START;
2054 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2055 val1_16 = ( val1_16 & 0x100 );
2056 val2_16 = ( val1_16 & 0xC00 );
2057 break;
2058
2059 case 3:
2060 u32RegAddrStar = MIU_PROTECT3_START;
2061 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2062 val1_16 = ( val1_16 & 0x1000 );
2063 val2_16 = ( val1_16 & 0xC000 );
2064 break;
2065
2066 default:
2067 printf("error miu protect block number\n");
2068 return ;
2069 }
2070
2071 //protect start address
2072 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar);
2073 val_32 = ( ( val_16 ) | (( val1_16 ) << 4 )) << MIU_PAGE_SHIFT;
2074 printf("miu0 protect%d startaddr is 0x%lx\n",u8Blockx,(long unsigned int)val_32);
2075
2076 //protect end address
2077 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar+0x2);
2078
2079 val_32 = ((( val_16 + 1 ) | (( val1_16 ) << 4 ) ) << MIU_PAGE_SHIFT ) - 1;
2080 printf("miu0 protect%d endaddr is 0x%lx\n",u8Blockx,(long unsigned int)val_32);
2081
2082 }
2083
2084
2085 if( miu_dev == 1 )
2086 {
2087 u32RegAddrMSB = MIU1_PROTECT0_MSB;
2088 switch (u8Blockx)
2089 {
2090 case 0:
2091 u32RegAddrStar = MIU1_PROTECT0_START;
2092 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2093 val1_16 = ( val1_16 & 0x1 );
2094 val2_16 = ( val1_16 & 0xC );
2095 break;
2096
2097 case 1:
2098 u32RegAddrStar = MIU1_PROTECT1_START;
2099 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2100 val1_16 = ( val1_16 & 0x10 );
2101 val2_16 = ( val1_16 & 0xC0 );
2102 break;
2103
2104 case 2:
2105 u32RegAddrStar = MIU1_PROTECT2_START;
2106 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2107 val1_16 = ( val1_16 & 0x100 );
2108 val2_16 = ( val1_16 & 0xC00 );
2109 break;
2110
2111 case 3:
2112 u32RegAddrStar = MIU1_PROTECT3_START;
2113 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2114 val1_16 = ( val1_16 & 0x1000 );
2115 val2_16 = ( val1_16 & 0xC000 );
2116 break;
2117
2118 default:
2119 printf("error miu protect block number\n");
2120 return ;
2121 }
2122
2123 //protect start address
2124 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar);
2125 val_32 = ( ( val_16 ) | (( val1_16 ) << 4 )) << MIU_PAGE_SHIFT;
2126 printf("miu1 protect%d startaddr is 0x%lx\n",u8Blockx,(long unsigned int)val_32);
2127
2128 //protect end address
2129 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar+0x2);
2130
2131 val_32 = ((( val_16 + 1 ) | (( val1_16 ) << 4 ) ) << MIU_PAGE_SHIFT ) - 1;
2132 printf("miu1 protect%d endaddr is 0x%lx\n",u8Blockx,(long unsigned int)val_32);
2133
2134 }
2135
2136
2137 }
2138
HAL_MIU_PrintMIUProtectInfo(void)2139 void HAL_MIU_PrintMIUProtectInfo(void)
2140 {
2141 MS_U32 u32MiuProtectEn;
2142 MS_U32 u32MiuProtectIdEn;
2143
2144 MS_U8 val_8;
2145 MS_U16 val_16;
2146
2147 u32MiuProtectEn = MIU_PROTECT_EN;
2148
2149 u32MiuProtectIdEn= MIU_PROTECT0_ID_ENABLE;
2150
2151 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
2152
2153 //printf("val=%d\n",val);
2154
2155 if ( (val_8 & 0xf) != 0 )
2156 {
2157 printf("miu0 protect is enabled\n");
2158
2159 //protect_ID_enable information
2160 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2161 if ( val_16 != 0 )
2162 {
2163 printf("miu0 protect0_ID_enable is 0x%x\n",val_16);
2164 HAL_MIU_PrintMIUProtectArea(0,0);
2165 }
2166
2167 u32MiuProtectIdEn= MIU_PROTECT1_ID_ENABLE;
2168 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2169 if ( val_16 != 0 )
2170 {
2171 printf("miu0 protect1_ID_enable is 0x%x\n",val_16);
2172 HAL_MIU_PrintMIUProtectArea(1,0);
2173 }
2174
2175 u32MiuProtectIdEn= MIU_PROTECT2_ID_ENABLE;
2176 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2177 if ( val_16 != 0 )
2178 {
2179 printf("miu0 protect2_ID_enable is 0x%x\n",val_16);
2180 HAL_MIU_PrintMIUProtectArea(2,0);
2181 }
2182
2183 u32MiuProtectIdEn= MIU_PROTECT3_ID_ENABLE;
2184 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2185 if ( val_16 != 0 )
2186 {
2187 printf("miu0 protect3_ID_enable is 0x%x\n",val_16);
2188 HAL_MIU_PrintMIUProtectArea(3,0);
2189 }
2190
2191 }
2192 else
2193 {
2194 printf("miu0 protect is not enabled\n");
2195 }
2196
2197 u32MiuProtectEn=MIU1_PROTECT_EN;
2198
2199 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
2200
2201 //printf("val=%d\n",val);
2202
2203 if ( (val_8 & 0xf) != 0x0 )
2204 {
2205 printf("miu1 protect is enabled\n");
2206
2207 //protect_ID_enable information
2208 u32MiuProtectIdEn= MIU1_PROTECT0_ID_ENABLE;
2209 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2210 if ( val_16 != 0 )
2211 {
2212 printf("miu1 protect0_ID_enable is 0x%x\n",val_16);
2213 HAL_MIU_PrintMIUProtectArea(0,1);
2214 }
2215
2216 u32MiuProtectIdEn= MIU1_PROTECT1_ID_ENABLE;
2217 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2218 if ( val_16 != 0 )
2219 {
2220 printf("miu1 protect1_ID_enable is 0x%x\n",val_16);
2221 HAL_MIU_PrintMIUProtectArea(1,1);
2222 }
2223
2224 u32MiuProtectIdEn= MIU1_PROTECT2_ID_ENABLE;
2225 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2226 if ( val_16 != 0 )
2227 {
2228 printf("miu1 protect2_ID_enable is 0x%x\n",val_16);
2229 HAL_MIU_PrintMIUProtectArea(2,1);
2230 }
2231
2232 u32MiuProtectIdEn= MIU1_PROTECT3_ID_ENABLE;
2233 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2234 if ( val_16 != 0 )
2235 {
2236 printf("miu1 protect3_ID_enable is 0x%x\n",val_16);
2237 HAL_MIU_PrintMIUProtectArea(3,1);
2238 }
2239
2240
2241 }
2242 else
2243 {
2244 printf("miu1 protect is not enabled\n");
2245
2246 }
2247 }
2248
2249 ////////////////////////////////////////////////////////////////////////////////
2250 /// @brief \b Function \b Name: HAL_MIU_GetClientWidth
2251 /// @brief \b Function \b Description: Get MIU client bus width
2252 /// @param u8MiuDev \b IN : select MIU0 or MIU1
2253 /// @param eClientID \b IN : client ID
2254 /// @param pClientWidth \b IN : client bus width
2255 /// @return \b 0 : Fail 1: OK
2256 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetClientWidth(MS_U8 u8MiuDevi,eMIUClientID eClientID,eMIU_ClientWidth * pClientWidth)2257 MS_BOOL HAL_MIU_GetClientWidth(MS_U8 u8MiuDevi, eMIUClientID eClientID, eMIU_ClientWidth *pClientWidth)
2258 {
2259 MS_U32 u32Reg;
2260 MS_S16 sVal;
2261 MS_U16 u16Group;
2262 MS_U16 u16Client;
2263 MS_U16 u16RegVal;
2264
2265 sVal = HAL_MIU_GetClientInfo(u8MiuDevi, eClientID);
2266
2267 if (sVal < 0)
2268 {
2269 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
2270 return FALSE;
2271 }
2272 else
2273 {
2274 u16Group = MIU_GET_CLIENT_GROUP(sVal);
2275 u16Client = MIU_GET_CLIENT_POS(sVal);
2276
2277 if(u16Group >= 3)
2278 {
2279 *pClientWidth = E_MIU_CLIENT_256BIT;
2280 return TRUE;
2281 }
2282
2283 u32Reg = REG_MI64_FORCE + (MIU_GET_CLIENT_GROUP(sVal) << 1);
2284 u16RegVal = HAL_MIU_Read2Byte(u32Reg);
2285
2286 if(u16RegVal & (1 << u16Client))
2287 *pClientWidth = E_MIU_CLIENT_64BIT;
2288 else
2289 *pClientWidth = E_MIU_CLIENT_128BIT;
2290
2291 return TRUE;
2292 }
2293 }
2294
HAL_MIU_GetDramType(MS_U32 eMiu,MIU_DDR_TYPE * pType)2295 MS_BOOL HAL_MIU_GetDramType(MS_U32 eMiu, MIU_DDR_TYPE* pType)
2296 {
2297 MS_U32 u32Reg;
2298
2299 if (eMiu >= MIU_MAX_DEVICE)
2300 return FALSE;
2301
2302 switch (eMiu)
2303 {
2304 case 0:
2305 u32Reg = REG_MIU_DDR_STATUS;
2306 break;
2307 case 1:
2308 u32Reg = REG_MIU1_DDR_STATUS;
2309 break;
2310 default:
2311 return FALSE;
2312 }
2313
2314 if (HAL_MIU_Read2Byte(u32Reg)& REG_MIU_DDR4)
2315 {
2316 *pType = E_MIU_DDR4;
2317 }
2318 else
2319 {
2320 *pType = E_MIU_DDR3;
2321 }
2322
2323 return TRUE;
2324 }
2325