1 /*
2 * Copyright (c) 2020-2026, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stddef.h>
8 #include <stdint.h>
9
10 #include <common/debug.h>
11 #include <lib/mmio.h>
12
13 #include "pfc_regs.h"
14
15 static const PFC_REGS pfc_mux_reg_tbl[] = {
16 #if RZA3M
17 /* P22(sd0) */
18 {
19 { PFC_ON, (uintptr_t)PFC_PMC04, 0x3e }, /* PMC */
20 { PFC_ON, (uintptr_t)PFC_PFC04, 0 }, /* PFC */
21 { PFC_OFF, (uintptr_t)PFC_IOLH04,
22 0x0000010101010101 }, /* IOLH */
23 { PFC_OFF, (uintptr_t)PFC_PUPD04,
24 0x0000000000000000 }, /* PUPD */
25 { PFC_OFF, (uintptr_t)PFC_SR04, 0x0000010101010101 }, /* SR */
26 { PFC_ON, (uintptr_t)NULL, 0 } /* IEN */
27 },
28 /* P6(scif0) */
29 {
30 { PFC_ON, (uintptr_t)PFC_PMC16, 0x3 }, /* PMC */
31 { PFC_ON, (uintptr_t)PFC_PFC16, 0x11 }, /* PFC */
32 { PFC_OFF, (uintptr_t)PFC_IOLH16,
33 0x0000000000000101 }, /* IOLH */
34 { PFC_OFF, (uintptr_t)PFC_PUPD16,
35 0x0000000000000000 }, /* PUPD */
36 { PFC_OFF, (uintptr_t)PFC_SR16, 0x0000000000000101 }, /* SR */
37 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
38 },
39 #else /* RZA3M */
40 /* P0(sd0) & P0(sd1) */
41 {
42 { PFC_ON, (uintptr_t)PFC_PMC10, 0x0F }, /* PMC */
43 { PFC_ON, (uintptr_t)PFC_PFC10, 0x00001111 }, /* PFC */
44 { PFC_OFF, (uintptr_t)PFC_IOLH10,
45 0x0000000001010101 }, /* IOLH */
46 { PFC_OFF, (uintptr_t)PFC_PUPD10,
47 0x0000000000000000 }, /* PUPD */
48 { PFC_OFF, (uintptr_t)PFC_SR10, 0x0000000001010101 }, /* SR */
49 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
50 },
51 #if (DEVICE_TYPE == 1)
52 /* P6(scif0) */
53 {
54 { PFC_ON, (uintptr_t)PFC_PMC16, 0x18 }, /* PMC */
55 { PFC_ON, (uintptr_t)PFC_PFC16, 0x00066000 }, /* PFC */
56 { PFC_OFF, (uintptr_t)PFC_IOLH16,
57 0x0000000101000000 }, /* IOLH */
58 { PFC_OFF, (uintptr_t)PFC_PUPD16,
59 0x0000000000000000 }, /* PUPD */
60 { PFC_OFF, (uintptr_t)PFC_SR16, 0x0000000101000000 }, /* SR */
61 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
62 },
63 #else
64 /* P13(scif0) */
65 {
66 { PFC_ON, (uintptr_t)PFC_PMC1D, 0x03 }, /* PMC */
67 { PFC_ON, (uintptr_t)PFC_PFC1D, 0x00000011 }, /* PFC */
68 { PFC_OFF, (uintptr_t)PFC_IOLH1D,
69 0x0000000000000101 }, /* IOLH */
70 { PFC_OFF, (uintptr_t)PFC_PUPD1D,
71 0x0000000000000000 }, /* PUPD */
72 { PFC_OFF, (uintptr_t)PFC_SR1D, 0x0000000000000101 }, /* SR */
73 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
74 },
75 #endif
76 #endif /* RZA3M */
77 };
78
79 static const PFC_REGS pfc_qspi_reg_tbl[] = {
80 #if RZA3M
81 /* QSPI0 */
82 {
83 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */
84 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */
85 { PFC_ON, (uintptr_t)PFC_IOLH05,
86 0x0000010101010101 }, /* IOLH */
87 { PFC_ON, (uintptr_t)PFC_PUPD05,
88 0x0000000000000000 }, /* PUPD */
89 { PFC_ON, (uintptr_t)PFC_SR05, 0x0000010101010101 }, /* SR */
90 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
91 },
92 #else /* RZA3M */
93 /* QSPI0 */
94 {
95 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */
96 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */
97 { PFC_ON, (uintptr_t)PFC_IOLH0A,
98 0x0000010101010101 }, /* IOLH */
99 { PFC_ON, (uintptr_t)PFC_PUPD0A,
100 0x0000000000000000 }, /* PUPD */
101 { PFC_ON, (uintptr_t)PFC_SR0A, 0x0000010101010101 }, /* SR */
102 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
103 },
104 /* QSPI1 */
105 {
106 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */
107 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */
108 { PFC_ON, (uintptr_t)PFC_IOLH0B,
109 0x0000010101010101 }, /* IOLH */
110 { PFC_ON, (uintptr_t)PFC_PUPD0B,
111 0x0000000000000000 }, /* PUPD */
112 { PFC_ON, (uintptr_t)PFC_SR0B, 0x0000010101010101 }, /* SR */
113 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
114 },
115 /* QSPIn */
116 {
117 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */
118 { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */
119 { PFC_ON, (uintptr_t)PFC_IOLH0C,
120 0x0000000000000101 }, /* IOLH */
121 { PFC_ON, (uintptr_t)PFC_PUPD0C,
122 0x0000000000000000 }, /* PUPD */
123 { PFC_ON, (uintptr_t)PFC_SR0C, 0x0000000000000000 }, /* SR */
124 { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
125 }
126 #endif /* RZA3M */
127 };
128
pfc_mux_setup(void)129 static void pfc_mux_setup(void)
130 {
131 int cnt;
132 int size = ARRAY_SIZE(pfc_mux_reg_tbl);
133
134 for (cnt = 0; cnt < size; cnt++) {
135 /* PMC */
136 if (pfc_mux_reg_tbl[cnt].pmc.flg == PFC_ON) {
137 mmio_write_8(pfc_mux_reg_tbl[cnt].pmc.reg,
138 pfc_mux_reg_tbl[cnt].pmc.val);
139 }
140 /* IOLH */
141 if (pfc_mux_reg_tbl[cnt].iolh.flg == PFC_ON) {
142 mmio_write_64(pfc_mux_reg_tbl[cnt].iolh.reg,
143 pfc_mux_reg_tbl[cnt].iolh.val);
144 }
145 /* PUPD */
146 if (pfc_mux_reg_tbl[cnt].pupd.flg == PFC_ON) {
147 mmio_write_64(pfc_mux_reg_tbl[cnt].pupd.reg,
148 pfc_mux_reg_tbl[cnt].pupd.val);
149 }
150 /* SR */
151 if (pfc_mux_reg_tbl[cnt].sr.flg == PFC_ON) {
152 mmio_write_64(pfc_mux_reg_tbl[cnt].sr.reg,
153 pfc_mux_reg_tbl[cnt].sr.val);
154 }
155 }
156 /* multiplexer terminal switching */
157 mmio_write_32(PFC_PWPR, 0x0);
158 mmio_write_32(PFC_PWPR, PWPR_PFCWE);
159
160 for (cnt = 0; cnt < size; cnt++) {
161 /* PFC */
162 if (pfc_mux_reg_tbl[cnt].pfc.flg == PFC_ON) {
163 mmio_write_32(pfc_mux_reg_tbl[cnt].pfc.reg,
164 pfc_mux_reg_tbl[cnt].pfc.val);
165 }
166 }
167
168 mmio_write_32(PFC_PWPR, 0x0);
169 mmio_write_32(PFC_PWPR, PWPR_B0Wl);
170 }
171
pfc_qspi_setup(void)172 static void pfc_qspi_setup(void)
173 {
174 int cnt;
175 int size = ARRAY_SIZE(pfc_qspi_reg_tbl);
176
177 for (cnt = 0; cnt < size; cnt++) {
178 /* PMC */
179 if (pfc_qspi_reg_tbl[cnt].pmc.flg == PFC_ON) {
180 mmio_write_64(pfc_qspi_reg_tbl[cnt].pmc.reg,
181 pfc_qspi_reg_tbl[cnt].pmc.val);
182 }
183 /* IOLH */
184 if (pfc_qspi_reg_tbl[cnt].iolh.flg == PFC_ON) {
185 mmio_write_64(pfc_qspi_reg_tbl[cnt].iolh.reg,
186 pfc_qspi_reg_tbl[cnt].iolh.val);
187 }
188 /* PUPD */
189 if (pfc_qspi_reg_tbl[cnt].pupd.flg == PFC_ON) {
190 mmio_write_64(pfc_qspi_reg_tbl[cnt].pupd.reg,
191 pfc_qspi_reg_tbl[cnt].pupd.val);
192 }
193 /* SR */
194 if (pfc_qspi_reg_tbl[cnt].sr.flg == PFC_ON) {
195 mmio_write_64(pfc_qspi_reg_tbl[cnt].sr.reg,
196 pfc_qspi_reg_tbl[cnt].sr.val);
197 }
198 }
199 /* multiplexer terminal switching */
200 mmio_write_32(PFC_PWPR, 0x0);
201 mmio_write_32(PFC_PWPR, PWPR_PFCWE);
202 for (cnt = 0; cnt < size; cnt++) {
203 /* SR */
204 if (pfc_qspi_reg_tbl[cnt].pfc.flg == PFC_ON) {
205 mmio_write_64(pfc_qspi_reg_tbl[cnt].pfc.reg,
206 pfc_qspi_reg_tbl[cnt].pfc.val);
207 }
208 }
209
210 mmio_write_32(PFC_PWPR, 0x0);
211 mmio_write_32(PFC_PWPR, PWPR_B0Wl);
212 }
213
pfc_setup(void)214 void pfc_setup(void)
215 {
216 pfc_mux_setup();
217 pfc_qspi_setup();
218 }
219