1 /******************************************************************************
2 *
3 * Copyright(c) 2019 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15 #include "_pcie.h"
16 #include "pwr.h"
17 #if MAC_AX_PCIE_SUPPORT
18
19 static u32 init_cfg_reg[MAC_AX_CHIP_ID_MAX] = {
20 R_AX_PCIE_INIT_CFG1, R_AX_PCIE_INIT_CFG1,
21 R_AX_HAXI_INIT_CFG1, R_AX_HAXI_INIT_CFG1
22 };
23
24 static u32 rxbd_mode_bit[MAC_AX_CHIP_ID_MAX] = {
25 B_AX_RXBD_MODE, B_AX_RXBD_MODE,
26 B_AX_RXBD_MODE_V1, B_AX_RXBD_MODE_V1
27 };
28
29 static u32 txhci_en_bit[MAC_AX_CHIP_ID_MAX] = {
30 B_AX_TXHCI_EN, B_AX_TXHCI_EN,
31 B_AX_TXHCI_EN_V1, B_AX_TXHCI_EN_V1
32 };
33
34 static u32 rxhci_en_bit[MAC_AX_CHIP_ID_MAX] = {
35 B_AX_RXHCI_EN, B_AX_RXHCI_EN,
36 B_AX_RXHCI_EN_V1, B_AX_RXHCI_EN_V1
37 };
38
39 static u32 dma_stop1_reg[MAC_AX_CHIP_ID_MAX] = {
40 R_AX_PCIE_DMA_STOP1, R_AX_PCIE_DMA_STOP1,
41 R_AX_HAXI_DMA_STOP1, R_AX_HAXI_DMA_STOP1
42 };
43
44 static u32 dma_stop2_reg[MAC_AX_CHIP_ID_MAX] = {
45 R_AX_PCIE_DMA_STOP2, R_AX_PCIE_DMA_STOP2,
46 R_AX_HAXI_DMA_STOP2, R_AX_HAXI_DMA_STOP2
47 };
48
49 static u32 dma_busy1_reg[MAC_AX_CHIP_ID_MAX] = {
50 R_AX_PCIE_DMA_BUSY1, R_AX_PCIE_DMA_BUSY1,
51 R_AX_HAXI_DMA_BUSY1, R_AX_HAXI_DMA_BUSY1
52 };
53
54 static u32 txbd_rwptr_clr2_reg[MAC_AX_CHIP_ID_MAX] = {
55 R_AX_TXBD_RWPTR_CLR2, R_AX_TXBD_RWPTR_CLR2,
56 R_AX_TXBD_RWPTR_CLR2_V1, R_AX_TXBD_RWPTR_CLR2_V1
57 };
58
59 static u32 dma_busy2_reg[MAC_AX_CHIP_ID_MAX] = {
60 R_AX_PCIE_DMA_BUSY2, R_AX_PCIE_DMA_BUSY2,
61 R_AX_HAXI_DMA_BUSY2, R_AX_HAXI_DMA_BUSY2
62 };
63
64 static u32 rxbd_rwptr_clr_reg[MAC_AX_CHIP_ID_MAX] = {
65 R_AX_RXBD_RWPTR_CLR, R_AX_RXBD_RWPTR_CLR,
66 R_AX_RXBD_RWPTR_CLR_V1, R_AX_RXBD_RWPTR_CLR_V1
67 };
68
69 static u32 exp_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
70 R_AX_PCIE_EXP_CTRL, R_AX_PCIE_EXP_CTRL,
71 R_AX_HAXI_EXP_CTRL, R_AX_HAXI_EXP_CTRL
72 };
73
74 static u32 max_tag_num_sh[MAC_AX_CHIP_ID_MAX] = {
75 B_AX_MAX_TAG_NUM_SH, B_AX_MAX_TAG_NUM_SH,
76 B_AX_MAX_TAG_NUM_V1_SH, B_AX_MAX_TAG_NUM_V1_SH
77 };
78
79 static u32 max_tag_num_msk[MAC_AX_CHIP_ID_MAX] = {
80 B_AX_MAX_TAG_NUM_MSK, B_AX_MAX_TAG_NUM_MSK,
81 B_AX_MAX_TAG_NUM_V1_MSK, B_AX_MAX_TAG_NUM_V1_MSK
82 };
83
84 static u32 dma_busy3_reg[MAC_AX_CHIP_ID_MAX] = {
85 R_AX_PCIE_DMA_BUSY1, R_AX_PCIE_DMA_BUSY1,
86 R_AX_HAXI_DMA_BUSY3, R_AX_HAXI_DMA_BUSY3
87 };
88
89 static u32 ch10_txbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
90 R_AX_CH10_TXBD_NUM, R_AX_CH10_TXBD_NUM,
91 R_AX_CH10_TXBD_NUM_V1, R_AX_CH10_TXBD_NUM_V1
92 };
93
94 static u32 ch11_txbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
95 R_AX_CH11_TXBD_NUM, R_AX_CH11_TXBD_NUM,
96 R_AX_CH11_TXBD_NUM_V1, R_AX_CH11_TXBD_NUM_V1
97 };
98
99 static u32 ach0_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
100 R_AX_ACH0_TXBD_DESA_L, R_AX_ACH0_TXBD_DESA_L,
101 R_AX_ACH0_TXBD_DESA_L_V1, R_AX_ACH0_TXBD_DESA_L_V1
102 };
103
104 static u32 ach0_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
105 R_AX_ACH0_TXBD_DESA_H, R_AX_ACH0_TXBD_DESA_H,
106 R_AX_ACH0_TXBD_DESA_H_V1, R_AX_ACH0_TXBD_DESA_H_V1
107 };
108
109 static u32 ach1_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
110 R_AX_ACH1_TXBD_DESA_L, R_AX_ACH1_TXBD_DESA_L,
111 R_AX_ACH1_TXBD_DESA_L_V1, R_AX_ACH1_TXBD_DESA_L_V1
112 };
113
114 static u32 ach1_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
115 R_AX_ACH1_TXBD_DESA_H, R_AX_ACH1_TXBD_DESA_H,
116 R_AX_ACH1_TXBD_DESA_H_V1, R_AX_ACH1_TXBD_DESA_H_V1
117 };
118
119 static u32 ach2_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
120 R_AX_ACH2_TXBD_DESA_L, R_AX_ACH2_TXBD_DESA_L,
121 R_AX_ACH2_TXBD_DESA_L_V1, R_AX_ACH2_TXBD_DESA_L_V1
122 };
123
124 static u32 ach2_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
125 R_AX_ACH2_TXBD_DESA_H, R_AX_ACH2_TXBD_DESA_H,
126 R_AX_ACH2_TXBD_DESA_H_V1, R_AX_ACH2_TXBD_DESA_H_V1
127 };
128
129 static u32 ach3_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
130 R_AX_ACH3_TXBD_DESA_L, R_AX_ACH3_TXBD_DESA_L,
131 R_AX_ACH3_TXBD_DESA_L_V1, R_AX_ACH3_TXBD_DESA_L_V1
132 };
133
134 static u32 ach3_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
135 R_AX_ACH3_TXBD_DESA_H, R_AX_ACH3_TXBD_DESA_H,
136 R_AX_ACH3_TXBD_DESA_H_V1, R_AX_ACH3_TXBD_DESA_H_V1
137 };
138
139 static u32 ach4_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
140 R_AX_ACH4_TXBD_DESA_L, R_AX_ACH4_TXBD_DESA_L,
141 R_AX_ACH4_TXBD_DESA_L_V1, R_AX_ACH4_TXBD_DESA_L_V1
142 };
143
144 static u32 ach4_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
145 R_AX_ACH4_TXBD_DESA_H, R_AX_ACH4_TXBD_DESA_H,
146 R_AX_ACH4_TXBD_DESA_H_V1, R_AX_ACH4_TXBD_DESA_H_V1
147 };
148
149 static u32 ach5_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
150 R_AX_ACH5_TXBD_DESA_L, R_AX_ACH5_TXBD_DESA_L,
151 R_AX_ACH5_TXBD_DESA_L_V1, R_AX_ACH5_TXBD_DESA_L_V1
152 };
153
154 static u32 ach5_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
155 R_AX_ACH5_TXBD_DESA_H, R_AX_ACH5_TXBD_DESA_H,
156 R_AX_ACH5_TXBD_DESA_H_V1, R_AX_ACH5_TXBD_DESA_H_V1
157 };
158
159 static u32 ach6_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
160 R_AX_ACH6_TXBD_DESA_L, R_AX_ACH6_TXBD_DESA_L,
161 R_AX_ACH6_TXBD_DESA_L_V1, R_AX_ACH6_TXBD_DESA_L_V1
162 };
163
164 static u32 ach6_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
165 R_AX_ACH6_TXBD_DESA_H, R_AX_ACH6_TXBD_DESA_H,
166 R_AX_ACH6_TXBD_DESA_H_V1, R_AX_ACH6_TXBD_DESA_H_V1
167 };
168
169 static u32 ach7_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
170 R_AX_ACH7_TXBD_DESA_L, R_AX_ACH7_TXBD_DESA_L,
171 R_AX_ACH7_TXBD_DESA_L_V1, R_AX_ACH7_TXBD_DESA_L_V1
172 };
173
174 static u32 ach7_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
175 R_AX_ACH7_TXBD_DESA_H, R_AX_ACH7_TXBD_DESA_H,
176 R_AX_ACH7_TXBD_DESA_H_V1, R_AX_ACH7_TXBD_DESA_H_V1
177 };
178
179 static u32 ch8_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
180 R_AX_CH8_TXBD_DESA_L, R_AX_CH8_TXBD_DESA_L,
181 R_AX_CH8_TXBD_DESA_L_V1, R_AX_CH8_TXBD_DESA_L_V1
182 };
183
184 static u32 ch8_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
185 R_AX_CH8_TXBD_DESA_H, R_AX_CH8_TXBD_DESA_H,
186 R_AX_CH8_TXBD_DESA_H_V1, R_AX_CH8_TXBD_DESA_H_V1
187 };
188
189 static u32 ch9_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
190 R_AX_CH9_TXBD_DESA_L, R_AX_CH9_TXBD_DESA_L,
191 R_AX_CH9_TXBD_DESA_L_V1, R_AX_CH9_TXBD_DESA_L_V1
192 };
193
194 static u32 ch9_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
195 R_AX_CH9_TXBD_DESA_H, R_AX_CH9_TXBD_DESA_H,
196 R_AX_CH9_TXBD_DESA_H_V1, R_AX_CH9_TXBD_DESA_H_V1
197 };
198
199 static u32 ch10_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
200 R_AX_CH10_TXBD_DESA_L, R_AX_CH10_TXBD_DESA_L,
201 R_AX_CH10_TXBD_DESA_L_V1, R_AX_CH10_TXBD_DESA_L_V1
202 };
203
204 static u32 ch10_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
205 R_AX_CH10_TXBD_DESA_H, R_AX_CH10_TXBD_DESA_H,
206 R_AX_CH10_TXBD_DESA_H_V1, R_AX_CH10_TXBD_DESA_H_V1
207 };
208
209 static u32 ch11_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
210 R_AX_CH11_TXBD_DESA_L, R_AX_CH11_TXBD_DESA_L,
211 R_AX_CH11_TXBD_DESA_L_V1, R_AX_CH11_TXBD_DESA_L_V1
212 };
213
214 static u32 ch11_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
215 R_AX_CH11_TXBD_DESA_H, R_AX_CH11_TXBD_DESA_H,
216 R_AX_CH11_TXBD_DESA_H_V1, R_AX_CH11_TXBD_DESA_H_V1
217 };
218
219 static u32 ch12_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
220 R_AX_CH12_TXBD_DESA_L, R_AX_CH12_TXBD_DESA_L,
221 R_AX_CH12_TXBD_DESA_L_V1, R_AX_CH12_TXBD_DESA_L_V1
222 };
223
224 static u32 ch12_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
225 R_AX_CH12_TXBD_DESA_H, R_AX_CH12_TXBD_DESA_H,
226 R_AX_CH12_TXBD_DESA_H_V1, R_AX_CH12_TXBD_DESA_H_V1
227 };
228
229 static u32 ach0_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
230 R_AX_ACH0_BDRAM_CTRL, R_AX_ACH0_BDRAM_CTRL,
231 R_AX_ACH0_BDRAM_CTRL_V1, R_AX_ACH0_BDRAM_CTRL_V1
232 };
233
234 static u32 ach1_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
235 R_AX_ACH1_BDRAM_CTRL, R_AX_ACH1_BDRAM_CTRL,
236 R_AX_ACH1_BDRAM_CTRL_V1, R_AX_ACH1_BDRAM_CTRL_V1
237 };
238
239 static u32 ach2_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
240 R_AX_ACH2_BDRAM_CTRL, R_AX_ACH2_BDRAM_CTRL,
241 R_AX_ACH2_BDRAM_CTRL_V1, R_AX_ACH2_BDRAM_CTRL_V1
242 };
243
244 static u32 ach3_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
245 R_AX_ACH3_BDRAM_CTRL, R_AX_ACH3_BDRAM_CTRL,
246 R_AX_ACH3_BDRAM_CTRL_V1, R_AX_ACH3_BDRAM_CTRL_V1
247 };
248
249 static u32 ach4_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
250 R_AX_ACH4_BDRAM_CTRL, R_AX_ACH4_BDRAM_CTRL,
251 R_AX_ACH4_BDRAM_CTRL_V1, R_AX_ACH4_BDRAM_CTRL_V1
252 };
253
254 static u32 ach5_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
255 R_AX_ACH5_BDRAM_CTRL, R_AX_ACH5_BDRAM_CTRL,
256 R_AX_ACH5_BDRAM_CTRL_V1, R_AX_ACH5_BDRAM_CTRL_V1
257 };
258
259 static u32 ach6_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
260 R_AX_ACH6_BDRAM_CTRL, R_AX_ACH6_BDRAM_CTRL,
261 R_AX_ACH6_BDRAM_CTRL_V1, R_AX_ACH6_BDRAM_CTRL_V1
262 };
263
264 static u32 ach7_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
265 R_AX_ACH7_BDRAM_CTRL, R_AX_ACH7_BDRAM_CTRL,
266 R_AX_ACH7_BDRAM_CTRL_V1, R_AX_ACH7_BDRAM_CTRL_V1
267 };
268
269 static u32 ch8_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
270 R_AX_CH8_BDRAM_CTRL, R_AX_CH8_BDRAM_CTRL,
271 R_AX_CH8_BDRAM_CTRL_V1, R_AX_CH8_BDRAM_CTRL_V1
272 };
273
274 static u32 ch9_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
275 R_AX_CH9_BDRAM_CTRL, R_AX_CH9_BDRAM_CTRL,
276 R_AX_CH9_BDRAM_CTRL_V1, R_AX_CH9_BDRAM_CTRL_V1
277 };
278
279 static u32 ch10_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
280 R_AX_CH10_BDRAM_CTRL, R_AX_CH10_BDRAM_CTRL,
281 R_AX_CH10_BDRAM_CTRL_V1, R_AX_CH10_BDRAM_CTRL_V1
282 };
283
284 static u32 ch11_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
285 R_AX_CH11_BDRAM_CTRL, R_AX_CH11_BDRAM_CTRL,
286 R_AX_CH11_BDRAM_CTRL_V1, R_AX_CH11_BDRAM_CTRL_V1
287 };
288
289 static u32 ch12_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
290 R_AX_CH12_BDRAM_CTRL, R_AX_CH12_BDRAM_CTRL,
291 R_AX_CH12_BDRAM_CTRL_V1, R_AX_CH12_BDRAM_CTRL_V1
292 };
293
294 static u32 rxq_rxbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
295 R_AX_RXQ_RXBD_DESA_L, R_AX_RXQ_RXBD_DESA_L,
296 R_AX_RXQ_RXBD_DESA_L_V1, R_AX_RXQ_RXBD_DESA_L_V1
297 };
298
299 static u32 rxq_rxbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
300 R_AX_RXQ_RXBD_DESA_H, R_AX_RXQ_RXBD_DESA_H,
301 R_AX_RXQ_RXBD_DESA_H_V1, R_AX_RXQ_RXBD_DESA_H_V1
302 };
303
304 static u32 rpq_rxbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
305 R_AX_RPQ_RXBD_DESA_L, R_AX_RPQ_RXBD_DESA_L,
306 R_AX_RPQ_RXBD_DESA_L_V1, R_AX_RPQ_RXBD_DESA_L_V1
307 };
308
309 static u32 rpq_rxbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
310 R_AX_RPQ_RXBD_DESA_H, R_AX_RPQ_RXBD_DESA_H,
311 R_AX_RPQ_RXBD_DESA_H_V1, R_AX_RPQ_RXBD_DESA_H_V1
312 };
313
314 static u32 rxq_rxbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
315 R_AX_RXQ_RXBD_NUM, R_AX_RXQ_RXBD_NUM,
316 R_AX_RXQ_RXBD_NUM_V1, R_AX_RXQ_RXBD_NUM_V1
317 };
318
319 static u32 rpq_rxbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
320 R_AX_RPQ_RXBD_NUM, R_AX_RPQ_RXBD_NUM,
321 R_AX_RPQ_RXBD_NUM_V1, R_AX_RPQ_RXBD_NUM_V1
322 };
323
324 struct txbd_ram mac_bdram_tbl_8852a[] = {
325 /* ACH0_QUEUE_IDX_8852AE */ {0, 5, 2},
326 /* ACH1_QUEUE_IDX_8852AE */ {5, 5, 2},
327 /* ACH2_QUEUE_IDX_8852AE */ {10, 5, 2},
328 /* ACH3_QUEUE_IDX_8852AE */ {15, 5, 2},
329 /* ACH4_QUEUE_IDX_8852AE */ {20, 5, 2},
330 /* ACH5_QUEUE_IDX_8852AE */ {25, 5, 2},
331 /* ACH6_QUEUE_IDX_8852AE */ {30, 5, 2},
332 /* ACH7_QUEUE_IDX_8852AE */ {35, 5, 2},
333 /* MGQ_B0_QUEUE_IDX_8852AE */ {40, 5, 1},
334 /* HIQ_B0_QUEUE_IDX_8852AE */ {45, 5, 1},
335 /* MGQ_B1_QUEUE_IDX_8852AE */ {50, 5, 1},
336 /* HIQ_B1_QUEUE_IDX_8852AE */ {55, 5, 1},
337 /* FWCMD_QUEUE_IDX_8852AE */ {60, 4, 1}
338 };
339
340 struct txbd_ram mac_bdram_tbl_8852b[] = {
341 /* ACH0_QUEUE_IDX_8852BE */ {0, 5, 2},
342 /* ACH1_QUEUE_IDX_8852BE */ {5, 5, 2},
343 /* ACH2_QUEUE_IDX_8852BE */ {10, 5, 2},
344 /* ACH3_QUEUE_IDX_8852BE */ {15, 5, 2},
345 /* MGQ_B0_QUEUE_IDX_8852BE */ {20, 4, 1},
346 /* HIQ_B0_QUEUE_IDX_8852BE */ {24, 4, 1},
347 /* FWCMD_QUEUE_IDX_8852BE */ {28, 4, 1}
348 };
349
350 struct txbd_ram mac_bdram_tbl_8852c[] = {
351 /* ACH0_QUEUE_IDX_8852AE */ {0, 5, 2},
352 /* ACH1_QUEUE_IDX_8852AE */ {5, 5, 2},
353 /* ACH2_QUEUE_IDX_8852AE */ {10, 5, 2},
354 /* ACH3_QUEUE_IDX_8852AE */ {15, 5, 2},
355 /* ACH4_QUEUE_IDX_8852AE */ {20, 5, 2},
356 /* ACH5_QUEUE_IDX_8852AE */ {25, 5, 2},
357 /* ACH6_QUEUE_IDX_8852AE */ {30, 5, 2},
358 /* ACH7_QUEUE_IDX_8852AE */ {35, 5, 2},
359 /* MGQ_B0_QUEUE_IDX_8852AE */ {40, 5, 1},
360 /* HIQ_B0_QUEUE_IDX_8852AE */ {45, 5, 1},
361 /* MGQ_B1_QUEUE_IDX_8852AE */ {50, 5, 1},
362 /* HIQ_B1_QUEUE_IDX_8852AE */ {55, 5, 1},
363 /* FWCMD_QUEUE_IDX_8852AE */ {60, 4, 1}
364 };
365
366 struct txbd_ram mac_bdram_tbl_8192xb[] = {
367 /* ACH0_QUEUE_IDX_8852AE */ {0, 5, 2},
368 /* ACH1_QUEUE_IDX_8852AE */ {5, 5, 2},
369 /* ACH2_QUEUE_IDX_8852AE */ {10, 5, 2},
370 /* ACH3_QUEUE_IDX_8852AE */ {15, 5, 2},
371 /* ACH4_QUEUE_IDX_8852AE */ {20, 5, 2},
372 /* ACH5_QUEUE_IDX_8852AE */ {25, 5, 2},
373 /* ACH6_QUEUE_IDX_8852AE */ {30, 5, 2},
374 /* ACH7_QUEUE_IDX_8852AE */ {35, 5, 2},
375 /* MGQ_B0_QUEUE_IDX_8852AE */ {40, 5, 1},
376 /* HIQ_B0_QUEUE_IDX_8852AE */ {45, 5, 1},
377 /* MGQ_B1_QUEUE_IDX_8852AE */ {50, 5, 1},
378 /* HIQ_B1_QUEUE_IDX_8852AE */ {55, 5, 1},
379 /* FWCMD_QUEUE_IDX_8852AE */ {60, 4, 1}
380 };
381
382 static struct mac_ax_intf_info intf_info_def_8852a = {
383 MAC_AX_BD_TRUNC,
384 MAC_AX_BD_TRUNC,
385 MAC_AX_RXBD_PKT,
386 MAC_AX_TAG_MULTI,
387 MAC_AX_TX_BURST_2048B,
388 MAC_AX_RX_BURST_128B,
389 MAC_AX_WD_DMA_INTVL_256NS,
390 MAC_AX_WD_DMA_INTVL_256NS,
391 MAC_AX_TAG_NUM_8,
392 0,
393 NULL,
394 NULL,
395 0,
396 NULL,
397 MAC_AX_PCIE_ENABLE,
398 MAC_AX_LBC_TMR_2MS,
399 MAC_AX_PCIE_DISABLE,
400 MAC_AX_PCIE_DISABLE,
401 MAC_AX_IO_RCY_ANA_TMR_60US
402 };
403
404 static struct mac_ax_intf_info intf_info_def_8852b = {
405 MAC_AX_BD_TRUNC,
406 MAC_AX_BD_TRUNC,
407 MAC_AX_RXBD_PKT,
408 MAC_AX_TAG_MULTI,
409 MAC_AX_TX_BURST_2048B,
410 MAC_AX_RX_BURST_128B,
411 MAC_AX_WD_DMA_INTVL_256NS,
412 MAC_AX_WD_DMA_INTVL_256NS,
413 MAC_AX_TAG_NUM_8,
414 0,
415 NULL,
416 NULL,
417 0,
418 NULL,
419 MAC_AX_PCIE_ENABLE,
420 MAC_AX_LBC_TMR_2MS,
421 MAC_AX_PCIE_ENABLE,
422 MAC_AX_PCIE_DISABLE,
423 MAC_AX_IO_RCY_ANA_TMR_60US
424 };
425
426 static struct mac_ax_intf_info intf_info_def_8852c = {
427 MAC_AX_BD_NORM,
428 MAC_AX_BD_NORM,
429 MAC_AX_RXBD_SEP,
430 MAC_AX_TAG_MULTI,
431 MAC_AX_TX_BURST_V1_256B,
432 MAC_AX_RX_BURST_V1_128B,
433 MAC_AX_WD_DMA_INTVL_256NS,
434 MAC_AX_WD_DMA_INTVL_256NS,
435 MAC_AX_TAG_NUM_8,
436 0,
437 NULL,
438 NULL,
439 0,
440 NULL,
441 MAC_AX_PCIE_ENABLE,
442 MAC_AX_LBC_TMR_2MS,
443 MAC_AX_PCIE_DISABLE,
444 MAC_AX_PCIE_ENABLE,
445 MAC_AX_IO_RCY_ANA_TMR_60US
446 };
447
448 static struct mac_ax_intf_info intf_info_def_8192xb = {
449 MAC_AX_BD_NORM,
450 MAC_AX_BD_NORM,
451 MAC_AX_RXBD_SEP,
452 MAC_AX_TAG_MULTI,
453 MAC_AX_TX_BURST_V1_256B,
454 MAC_AX_RX_BURST_V1_128B,
455 MAC_AX_WD_DMA_INTVL_256NS,
456 MAC_AX_WD_DMA_INTVL_256NS,
457 MAC_AX_TAG_NUM_8,
458 0,
459 NULL,
460 NULL,
461 0,
462 NULL,
463 MAC_AX_PCIE_ENABLE,
464 MAC_AX_LBC_TMR_2MS,
465 };
466
467 static struct mac_ax_pcie_cfgspc_param pcie_cfgspc_param_def = {
468 0,
469 0,
470 MAC_AX_PCIE_DISABLE,
471 MAC_AX_PCIE_ENABLE,
472 MAC_AX_PCIE_ENABLE,
473 MAC_AX_PCIE_ENABLE,
474 MAC_AX_PCIE_ENABLE,
475 MAC_AX_PCIE_CLKDLY_30US,
476 MAC_AX_PCIE_L0SDLY_4US,
477 MAC_AX_PCIE_L1DLY_16US
478 };
479
480 static struct mac_ax_pcie_cfgspc_param pcie_cfgspc_param_def_8852b = {
481 0,
482 0,
483 MAC_AX_PCIE_DISABLE,
484 MAC_AX_PCIE_ENABLE,
485 MAC_AX_PCIE_ENABLE,
486 MAC_AX_PCIE_ENABLE,
487 MAC_AX_PCIE_ENABLE,
488 MAC_AX_PCIE_CLKDLY_100US,
489 MAC_AX_PCIE_L0SDLY_4US,
490 MAC_AX_PCIE_L1DLY_16US
491 };
492
493 static struct mac_ax_pcie_ltr_param pcie_ltr_param_def = {
494 0,
495 0,
496 MAC_AX_PCIE_ENABLE,
497 MAC_AX_PCIE_ENABLE,
498 MAC_AX_PCIE_LTR_SPC_500US,
499 MAC_AX_PCIE_LTR_IDLE_TIMER_3_2MS,
500 {MAC_AX_PCIE_ENABLE, 0x28},
501 {MAC_AX_PCIE_ENABLE, 0x28},
502 {MAC_AX_PCIE_ENABLE, 0x90039003},
503 {MAC_AX_PCIE_ENABLE, 0x880b880b}
504 };
505
reg_read8_pcie(struct mac_ax_adapter * adapter,u32 addr)506 u8 reg_read8_pcie(struct mac_ax_adapter *adapter, u32 addr)
507 {
508 u8 offset, count = 0, val8;
509 u32 val, addr_shift;
510
511 if (addr >= R_AX_CMAC_FUNC_EN && addr <= R_AX_CMAC_REG_END) {
512 offset = addr & (MAC_REG_OFFSET - 1);
513 addr_shift = addr - offset;
514 val = PLTFM_REG_R32(addr_shift);
515
516 while (count < MAC_REG_POOL_COUNT) {
517 if (val != MAC_AX_R32_DEAD)
518 break;
519
520 PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
521 PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
522 val = PLTFM_REG_R32(addr_shift);
523 count++;
524 }
525
526 val8 = (u8)(val >> (offset << MAC_REG_OFFSET_SH_2));
527 } else {
528 val8 = PLTFM_REG_R8(addr);
529 }
530
531 if (count == MAC_REG_POOL_COUNT && adapter->sm.l2_st == MAC_AX_L2_EN) {
532 adapter->sm.l2_st = MAC_AX_L2_TRIG;
533 PLTFM_L2_NOTIFY(void);
534 }
535
536 return val8;
537 }
538
reg_write8_pcie(struct mac_ax_adapter * adapter,u32 addr,u8 val)539 void reg_write8_pcie(struct mac_ax_adapter *adapter, u32 addr, u8 val)
540 {
541 PLTFM_REG_W8(addr, val);
542 }
543
reg_read16_pcie(struct mac_ax_adapter * adapter,u32 addr)544 u16 reg_read16_pcie(struct mac_ax_adapter *adapter, u32 addr)
545 {
546 u8 offset, count = 0;
547 u16 val16;
548 u32 val, addr_shift;
549
550 if ((addr & (MAC_REG_OFFSET16 - 1)) != 0) {
551 PLTFM_MSG_ERR("[ERR]read16 failaddr 0x%x\n", addr);
552 return MAC_AX_R16_DEAD;
553 }
554
555 if (addr >= R_AX_CMAC_FUNC_EN && addr <= R_AX_CMAC_REG_END) {
556 offset = addr & (MAC_REG_OFFSET - 1);
557 addr_shift = addr - offset;
558 val = PLTFM_REG_R32(addr_shift);
559
560 while (count < MAC_REG_POOL_COUNT) {
561 if (val != MAC_AX_R32_DEAD)
562 break;
563
564 PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
565 PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
566 val = PLTFM_REG_R32(addr_shift);
567 count++;
568 }
569 val16 = (u16)(val >> (offset << MAC_REG_OFFSET_SH_2));
570 } else {
571 val16 = PLTFM_REG_R16(addr);
572 }
573
574 if (count == MAC_REG_POOL_COUNT && adapter->sm.l2_st == MAC_AX_L2_EN) {
575 adapter->sm.l2_st = MAC_AX_L2_TRIG;
576 PLTFM_L2_NOTIFY(void);
577 }
578
579 return val16;
580 }
581
reg_write16_pcie(struct mac_ax_adapter * adapter,u32 addr,u16 val)582 void reg_write16_pcie(struct mac_ax_adapter *adapter, u32 addr, u16 val)
583 {
584 PLTFM_REG_W16(addr, val);
585 }
586
reg_read32_pcie(struct mac_ax_adapter * adapter,u32 addr)587 u32 reg_read32_pcie(struct mac_ax_adapter *adapter, u32 addr)
588 {
589 u8 count = 0;
590 u32 val = PLTFM_REG_R32(addr);
591
592 if (addr >= R_AX_CMAC_FUNC_EN && addr <= R_AX_CMAC_REG_END) {
593 while (count < MAC_REG_POOL_COUNT) {
594 if (val != MAC_AX_R32_DEAD)
595 break;
596
597 PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
598 PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
599 val = PLTFM_REG_R32(addr);
600 count++;
601 }
602 }
603
604 if (count == MAC_REG_POOL_COUNT && adapter->sm.l2_st == MAC_AX_L2_EN) {
605 adapter->sm.l2_st = MAC_AX_L2_TRIG;
606 PLTFM_L2_NOTIFY(void);
607 }
608
609 return val;
610 }
611
reg_write32_pcie(struct mac_ax_adapter * adapter,u32 addr,u32 val)612 void reg_write32_pcie(struct mac_ax_adapter *adapter, u32 addr, u32 val)
613 {
614 PLTFM_REG_W32(addr, val);
615 }
616
dbi_r32_pcie(struct mac_ax_adapter * adapter,u16 addr,u32 * val)617 u32 dbi_r32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 *val)
618 {
619 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
620 u32 r_addr = addr & DBI_ADDR_MASK;
621 u32 val32, cnt;
622 u32 ret = MACSUCCESS;
623
624 #if MAC_AX_FEATURE_HV
625 if (adapter->env == HV_AX_FPGA)
626 return MACSUCCESS;
627 #endif
628
629 if (addr & DBI_ADDR_2LSB_MASK) {
630 PLTFM_MSG_ERR("[ERR]DBI R32 addr 0x%X not 4B align\n", addr);
631 return MACFUNCINPUT;
632 }
633
634 PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
635
636 val32 = 0;
637 val32 = SET_CLR_WORD(val32, r_addr, B_AX_DBI_ADDR);
638 MAC_REG_W32(R_AX_DBI_FLAG, val32);
639
640 val32 |= B_AX_DBI_RFLAG;
641 MAC_REG_W32(R_AX_DBI_FLAG, val32);
642
643 cnt = DBI_DLY_CNT;
644 while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_RFLAG && cnt) {
645 PLTFM_DELAY_US(DBI_DLY_US);
646 cnt--;
647 }
648
649 if (!cnt) {
650 PLTFM_MSG_ERR("[ERR]DBI R32 0x%X timeout\n", r_addr);
651 ret = MACPOLLTO;
652 goto end;
653 }
654
655 *val = MAC_REG_R32(R_AX_DBI_RDATA);
656 end:
657 PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
658 return ret;
659 }
660
dbi_w32_pcie(struct mac_ax_adapter * adapter,u16 addr,u32 data)661 u32 dbi_w32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 data)
662 {
663 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
664 u32 w_addr = addr & DBI_ADDR_MASK;
665 u32 val32, cnt;
666 u32 ret = MACSUCCESS;
667
668 #if MAC_AX_FEATURE_HV
669 if (adapter->env == HV_AX_FPGA)
670 return MACSUCCESS;
671 #endif
672
673 PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
674
675 MAC_REG_W32(R_AX_DBI_WDATA, data);
676
677 val32 = 0;
678 val32 = SET_CLR_WORD(val32, w_addr, B_AX_DBI_ADDR);
679 val32 = SET_CLR_WORD(val32, DBI_WEN_DW, B_AX_DBI_WREN);
680 MAC_REG_W32(R_AX_DBI_FLAG, val32);
681
682 val32 |= B_AX_DBI_WFLAG;
683 MAC_REG_W32(R_AX_DBI_FLAG, val32);
684
685 cnt = DBI_DLY_CNT;
686 while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_WFLAG && cnt) {
687 PLTFM_DELAY_US(DBI_DLY_US);
688 cnt--;
689 }
690
691 if (!cnt) {
692 PLTFM_MSG_ERR("[ERR]DBI W32 0x%X = 0x%x timeout\n", w_addr, data);
693 ret = MACPOLLTO;
694 goto end;
695 }
696 end:
697 PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
698 return ret;
699 }
700
dbi_r8_pcie(struct mac_ax_adapter * adapter,u16 addr,u8 * val)701 u32 dbi_r8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 *val)
702 {
703 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
704 u32 r_addr = addr & DBI_ADDR_MASK;
705 u32 addr_2lsb = addr & DBI_ADDR_2LSB_MASK;
706 u32 val32, cnt;
707 u32 ret = MACSUCCESS;
708
709 #if MAC_AX_FEATURE_HV
710 if (adapter->env == HV_AX_FPGA)
711 return MACSUCCESS;
712 #endif
713
714 PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
715
716 val32 = 0;
717 val32 = SET_CLR_WORD(val32, r_addr, B_AX_DBI_ADDR);
718 MAC_REG_W32(R_AX_DBI_FLAG, val32);
719
720 val32 |= B_AX_DBI_RFLAG;
721 MAC_REG_W32(R_AX_DBI_FLAG, val32);
722
723 cnt = DBI_DLY_CNT;
724 while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_RFLAG && cnt) {
725 PLTFM_DELAY_US(DBI_DLY_US);
726 cnt--;
727 }
728
729 if (!cnt) {
730 PLTFM_MSG_ERR("[ERR]DBI R8 0x%X timeout\n", r_addr);
731 ret = MACPOLLTO;
732 goto end;
733 }
734
735 *val = MAC_REG_R8(R_AX_DBI_RDATA + addr_2lsb);
736 end:
737 PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
738 return ret;
739 }
740
dbi_w8_pcie(struct mac_ax_adapter * adapter,u16 addr,u8 data)741 u32 dbi_w8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 data)
742 {
743 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
744 u32 w_addr = addr & DBI_ADDR_MASK;
745 u32 addr_2lsb = addr & DBI_ADDR_2LSB_MASK;
746 u32 val32, cnt;
747 u32 ret = MACSUCCESS;
748
749 #if MAC_AX_FEATURE_HV
750 if (adapter->env == HV_AX_FPGA)
751 return MACSUCCESS;
752 #endif
753
754 PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
755
756 MAC_REG_W8(R_AX_DBI_WDATA + addr_2lsb, data);
757
758 val32 = 0;
759 val32 = SET_CLR_WORD(val32, w_addr, B_AX_DBI_ADDR);
760 val32 = SET_CLR_WORD(val32, DBI_WEN_B << addr_2lsb, B_AX_DBI_WREN);
761 MAC_REG_W32(R_AX_DBI_FLAG, val32);
762
763 val32 |= B_AX_DBI_WFLAG;
764 MAC_REG_W32(R_AX_DBI_FLAG, val32);
765
766 cnt = DBI_DLY_CNT;
767 while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_WFLAG && cnt) {
768 PLTFM_DELAY_US(DBI_DLY_US);
769 cnt--;
770 }
771
772 if (!cnt) {
773 PLTFM_MSG_ERR("[ERR]DBI W8 0x%X = 0x%x timeout\n", w_addr, data);
774 ret = MACPOLLTO;
775 goto end;
776 }
777 end:
778 PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
779 return ret;
780 }
781
mdio_r16_pcie(struct mac_ax_adapter * adapter,u8 addr,u8 speed,u16 * val)782 u32 mdio_r16_pcie(struct mac_ax_adapter *adapter, u8 addr, u8 speed, u16 *val)
783 {
784 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
785 u16 val16;
786 u32 cnt;
787 u32 ret = MACSUCCESS;
788
789 #if MAC_AX_FEATURE_HV
790 if (adapter->env == HV_AX_FPGA)
791 return MACSUCCESS;
792 #endif
793
794 PLTFM_MUTEX_LOCK(&adapter->hw_info->mdio_lock);
795
796 MAC_REG_W8(R_AX_MDIO_CFG, addr & B_AX_MDIO_ADDR_MSK);
797
798 val16 = MAC_REG_R16(R_AX_MDIO_CFG);
799 if (speed == MAC_AX_PCIE_PHY_GEN1 && addr < MDIO_ADDR_PG1) {
800 val16 = SET_CLR_WORD(val16, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR);
801 } else if (speed == MAC_AX_PCIE_PHY_GEN1) {
802 val16 = SET_CLR_WORD(val16, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR);
803 } else if (speed == MAC_AX_PCIE_PHY_GEN2 && addr < MDIO_ADDR_PG1) {
804 val16 = SET_CLR_WORD(val16, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR);
805 } else if (speed == MAC_AX_PCIE_PHY_GEN2) {
806 val16 = SET_CLR_WORD(val16, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR);
807 } else {
808 PLTFM_MSG_ERR("[ERR]Error MDIO PHY Speed %d!\n", speed);
809 ret = MACFUNCINPUT;
810 goto end;
811 }
812 MAC_REG_W16(R_AX_MDIO_CFG, val16);
813
814 MAC_REG_W16(R_AX_MDIO_CFG,
815 MAC_REG_R16(R_AX_MDIO_CFG) | B_AX_MDIO_RFLAG);
816
817 cnt = MDIO_DLY_CNT;
818 while (MAC_REG_R16(R_AX_MDIO_CFG) & B_AX_MDIO_RFLAG && cnt) {
819 PLTFM_DELAY_US(MDIO_DLY_US);
820 cnt--;
821 }
822
823 if (!cnt) {
824 PLTFM_MSG_ERR("[ERR]MDIO R16 0x%X timeout\n", addr);
825 ret = MACPOLLTO;
826 goto end;
827 }
828
829 *val = MAC_REG_R16(R_AX_MDIO_RDATA);
830 end:
831 PLTFM_MUTEX_UNLOCK(&adapter->hw_info->mdio_lock);
832 return ret;
833 }
834
mdio_w16_pcie(struct mac_ax_adapter * adapter,u8 addr,u16 data,u8 speed)835 u32 mdio_w16_pcie(struct mac_ax_adapter *adapter, u8 addr, u16 data, u8 speed)
836 {
837 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
838 u16 val16;
839 u32 cnt;
840 u32 ret = MACSUCCESS;
841
842 #if MAC_AX_FEATURE_HV
843 if (adapter->env == HV_AX_FPGA)
844 return MACSUCCESS;
845 #endif
846
847 PLTFM_MUTEX_LOCK(&adapter->hw_info->mdio_lock);
848
849 MAC_REG_W16(R_AX_MDIO_WDATA, data);
850 MAC_REG_W8(R_AX_MDIO_CFG, addr & B_AX_MDIO_ADDR_MSK);
851
852 val16 = MAC_REG_R16(R_AX_MDIO_CFG);
853 if (speed == MAC_AX_PCIE_PHY_GEN1 && addr < MDIO_ADDR_PG1) {
854 val16 = SET_CLR_WORD(val16, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR);
855 } else if (speed == MAC_AX_PCIE_PHY_GEN1) {
856 val16 = SET_CLR_WORD(val16, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR);
857 } else if (speed == MAC_AX_PCIE_PHY_GEN2 && addr < MDIO_ADDR_PG1) {
858 val16 = SET_CLR_WORD(val16, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR);
859 } else if (speed == MAC_AX_PCIE_PHY_GEN2) {
860 val16 = SET_CLR_WORD(val16, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR);
861 } else {
862 PLTFM_MSG_ERR("[ERR]Error MDIO PHY Speed %d!\n", speed);
863 ret = MACFUNCINPUT;
864 goto end;
865 }
866 MAC_REG_W16(R_AX_MDIO_CFG, val16);
867
868 MAC_REG_W16(R_AX_MDIO_CFG,
869 MAC_REG_R16(R_AX_MDIO_CFG) | B_AX_MDIO_WFLAG);
870
871 cnt = MDIO_DLY_CNT;
872 while (MAC_REG_R16(R_AX_MDIO_CFG) & B_AX_MDIO_WFLAG && cnt) {
873 PLTFM_DELAY_US(MDIO_DLY_US);
874 cnt--;
875 }
876
877 if (!cnt) {
878 PLTFM_MSG_ERR("[ERR]MDIO W16 0x%X = 0x%x timeout!\n", addr, data);
879 ret = MACPOLLTO;
880 goto end;
881 }
882
883 end:
884 PLTFM_MUTEX_UNLOCK(&adapter->hw_info->mdio_lock);
885 return ret;
886 }
887
get_target(struct mac_ax_adapter * adapter,u16 * target,enum mac_ax_pcie_phy phy_rate)888 static u32 get_target(struct mac_ax_adapter *adapter, u16 *target,
889 enum mac_ax_pcie_phy phy_rate)
890 {
891 u16 tmp_u16, count;
892 u16 tar;
893 u32 ret = MACSUCCESS;
894
895 /* Enable counter */
896 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
897 if (ret != MACSUCCESS)
898 return ret;
899 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16 & ~BAC_AUTOK_ONCE_EN,
900 phy_rate);
901 if (ret != MACSUCCESS)
902 return ret;
903 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16 | BAC_AUTOK_ONCE_EN,
904 phy_rate);
905 if (ret != MACSUCCESS)
906 return ret;
907
908 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tar);
909 if (ret != MACSUCCESS)
910 return ret;
911
912 count = PCIE_POLL_AUTOK_CNT;
913 while (count && (tar & BAC_AUTOK_ONCE_EN)) {
914 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tar);
915 if (ret != MACSUCCESS)
916 return ret;
917 count--;
918 PLTFM_DELAY_US(PCIE_POLL_AUTOK_DLY_US);
919 }
920
921 if (!count) {
922 PLTFM_MSG_ERR("[ERR]AutoK get target timeout: %X\n", tar);
923 return MACPOLLTO;
924 }
925
926 tar = tar & BAC_AUTOK_HW_TAR_MSK;
927 if (tar == 0 || tar == BAC_AUTOK_HW_TAR_MSK) {
928 PLTFM_MSG_ERR("[ERR]Get target failed.\n");
929 return MACHWERR;
930 }
931
932 *target = tar;
933 return MACSUCCESS;
934 }
935
mac_auto_refclk_cal_pcie(struct mac_ax_adapter * adapter,enum mac_ax_pcie_func_ctrl en)936 static u32 mac_auto_refclk_cal_pcie(struct mac_ax_adapter *adapter,
937 enum mac_ax_pcie_func_ctrl en)
938 {
939 u8 bdr_ori, val8;
940 u16 tmp_u16;
941 u16 mgn_set;
942 u16 tar;
943 u8 l1_flag = 0;
944 u32 ret = MACSUCCESS;
945 enum mac_ax_pcie_phy phy_rate = MAC_AX_PCIE_PHY_GEN1;
946
947 #if MAC_AX_FEATURE_HV
948 if (adapter->env == HV_AX_FPGA)
949 return MACSUCCESS;
950 #endif
951
952 #if (INTF_INTGRA_HOSTREF_V1 <= INTF_INTGRA_MINREF_V1)
953 PLTFM_MSG_ERR("[ERR]INTF_INTGRA_MINREF_V1 define fail\n");
954 return MACCMP;
955 #endif
956 ret = dbi_r8_pcie(adapter, PCIE_PHY_RATE, &val8);
957 if (ret != MACSUCCESS) {
958 PLTFM_MSG_ERR("[ERR]dbi_r8_pcie 0x%x\n", PCIE_PHY_RATE);
959 return ret;
960 }
961
962 if ((val8 & (BIT1 | BIT0)) == 0x1) {
963 phy_rate = MAC_AX_PCIE_PHY_GEN1;
964 } else if ((val8 & (BIT1 | BIT0)) == 0x2) {
965 phy_rate = MAC_AX_PCIE_PHY_GEN2;
966 } else {
967 PLTFM_MSG_ERR("[ERR]PCIe PHY rate not support\n");
968 return MACHWNOSUP;
969 }
970
971 /* Disable L1BD */
972 ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &bdr_ori);
973 if (ret != MACSUCCESS) {
974 PLTFM_MSG_ERR("[ERR]dbi_r8_pcie 0x%X\n", PCIE_L1_CTRL);
975 return ret;
976 }
977
978 if (bdr_ori & PCIE_BIT_L1) {
979 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL,
980 bdr_ori & ~(PCIE_BIT_L1));
981 if (ret != MACSUCCESS) {
982 PLTFM_MSG_ERR("[ERR]dbi_w8_pcie 0x%X\n", PCIE_L1_CTRL);
983 return ret;
984 }
985 l1_flag = 1;
986 }
987
988 /* Disable function */
989 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
990 if (ret != MACSUCCESS) {
991 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
992 goto end;
993 }
994
995 if (tmp_u16 & BAC_AUTOK_EN) {
996 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1,
997 tmp_u16 & ~(BAC_AUTOK_EN), phy_rate);
998 if (ret != MACSUCCESS) {
999 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n",
1000 RAC_CTRL_PPR_V1);
1001 goto end;
1002 }
1003 }
1004
1005 if (en != MAC_AX_PCIE_ENABLE)
1006 goto end;
1007
1008 /* Set div */
1009 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
1010 if (ret != MACSUCCESS) {
1011 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
1012 goto end;
1013 }
1014
1015 tmp_u16 = SET_CLR_WOR2(tmp_u16, PCIE_AUTOK_DIV_2048, BAC_AUTOK_DIV_SH,
1016 BAC_AUTOK_DIV_MSK);
1017 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16, phy_rate);
1018 if (ret != MACSUCCESS) {
1019 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
1020 goto end;
1021 }
1022
1023 /* Obtain div and margin */
1024 ret = get_target(adapter, &tar, phy_rate);
1025 if (ret != MACSUCCESS) {
1026 PLTFM_MSG_ERR("[ERR]1st get target fail %d\n", ret);
1027 goto end;
1028 }
1029
1030 mgn_set = PCIE_AUTOK_MGN;
1031
1032 ret = mdio_w16_pcie(adapter, RAC_SET_PPR_V1, (tar & BAC_AUTOK_TAR_MSK) |
1033 (mgn_set << BAC_AUTOK_MGN_SH), phy_rate);
1034 if (ret != MACSUCCESS) {
1035 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_SET_PPR_V1);
1036 goto end;
1037 }
1038
1039 /* Enable function */
1040 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
1041 if (ret != MACSUCCESS) {
1042 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
1043 goto end;
1044 }
1045 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16 | BAC_AUTOK_EN,
1046 phy_rate);
1047 if (ret != MACSUCCESS) {
1048 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
1049 goto end;
1050 }
1051
1052 end:
1053 /* Set L1BD to ori */
1054 if (l1_flag == 1) {
1055 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, bdr_ori);
1056 if (ret != MACSUCCESS) {
1057 PLTFM_MSG_ERR("[ERR]dbi_w8_pcie 0x%X\n", PCIE_L1_CTRL);
1058 return ret;
1059 }
1060 }
1061 PLTFM_MSG_TRACE("[TRACE]%s: <==\n", __func__);
1062
1063 return ret;
1064 }
1065
update_pcie_func(u8 * val,u8 bitmask,enum mac_ax_pcie_func_ctrl ctrl,enum mac_ax_pcie_func_ctrl def_ctrl)1066 static void update_pcie_func(u8 *val, u8 bitmask,
1067 enum mac_ax_pcie_func_ctrl ctrl,
1068 enum mac_ax_pcie_func_ctrl def_ctrl)
1069 {
1070 if ((ctrl == MAC_AX_PCIE_DEFAULT &&
1071 (def_ctrl == MAC_AX_PCIE_IGNORE ||
1072 def_ctrl == MAC_AX_PCIE_DEFAULT)) || ctrl == MAC_AX_PCIE_IGNORE)
1073 return;
1074
1075 if ((ctrl == MAC_AX_PCIE_DEFAULT && def_ctrl == MAC_AX_PCIE_DISABLE) ||
1076 ctrl == MAC_AX_PCIE_DISABLE)
1077 *val &= ~(bitmask);
1078 else
1079 *val |= bitmask;
1080 }
1081
chk_stus_l1ss(struct mac_ax_adapter * adapter,u8 * val)1082 static u32 chk_stus_l1ss(struct mac_ax_adapter *adapter, u8 *val)
1083 {
1084 u16 cap_val;
1085 u8 stus_val;
1086 u8 sup_val;
1087 u32 ret;
1088 u8 val8_1, val8_2;
1089
1090 ret = dbi_r8_pcie(adapter, PCIE_L1SS_CAP + 1, &val8_1);
1091 if (ret != MACSUCCESS)
1092 return ret;
1093
1094 ret = dbi_r8_pcie(adapter, PCIE_L1SS_CAP, &val8_2);
1095 if (ret != MACSUCCESS)
1096 return ret;
1097
1098 cap_val = (u16)((val8_1 << 8) | val8_2);
1099
1100 ret = dbi_r8_pcie(adapter, PCIE_L1SS_SUP, &sup_val);
1101 if (ret != MACSUCCESS)
1102 return ret;
1103
1104 ret = dbi_r8_pcie(adapter, PCIE_L1SS_STS, &stus_val);
1105 if (ret != MACSUCCESS)
1106 return ret;
1107
1108 if (cap_val == PCIE_L1SS_ID &&
1109 (sup_val & PCIE_BIT_L1SSSUP) &&
1110 (sup_val & PCIE_L1SS_MASK) != 0 &&
1111 (stus_val & PCIE_L1SS_MASK) != 0)
1112 *val = 1;
1113 else
1114 *val = 0;
1115
1116 return ret;
1117 }
1118
update_clkdly(struct mac_ax_adapter * adapter,u8 * val,enum mac_ax_pcie_clkdly ctrl,enum mac_ax_pcie_clkdly def_ctrl)1119 u32 update_clkdly(struct mac_ax_adapter *adapter, u8 *val,
1120 enum mac_ax_pcie_clkdly ctrl,
1121 enum mac_ax_pcie_clkdly def_ctrl)
1122 {
1123 u8 tmp;
1124
1125 if (ctrl == MAC_AX_PCIE_CLKDLY_IGNORE ||
1126 def_ctrl == MAC_AX_PCIE_CLKDLY_IGNORE)
1127 return MACSUCCESS;
1128
1129 tmp = (ctrl == MAC_AX_PCIE_CLKDLY_DEF) ? def_ctrl : ctrl;
1130 switch (tmp) {
1131 case MAC_AX_PCIE_CLKDLY_0:
1132 *val = PCIE_CLKDLY_HW_0;
1133 break;
1134
1135 case MAC_AX_PCIE_CLKDLY_30US:
1136 *val = PCIE_CLKDLY_HW_30US;
1137 break;
1138
1139 case MAC_AX_PCIE_CLKDLY_50US:
1140 *val = PCIE_CLKDLY_HW_50US;
1141 break;
1142
1143 case MAC_AX_PCIE_CLKDLY_100US:
1144 *val = PCIE_CLKDLY_HW_100US;
1145 break;
1146
1147 case MAC_AX_PCIE_CLKDLY_150US:
1148 *val = PCIE_CLKDLY_HW_150US;
1149 break;
1150
1151 case MAC_AX_PCIE_CLKDLY_200US:
1152 *val = PCIE_CLKDLY_HW_200US;
1153 break;
1154 case MAC_AX_PCIE_CLKDLY_300US:
1155 *val = PCIE_CLKDLY_HW_300US;
1156 break;
1157 case MAC_AX_PCIE_CLKDLY_400US:
1158 *val = PCIE_CLKDLY_HW_400US;
1159 break;
1160 case MAC_AX_PCIE_CLKDLY_500US:
1161 *val = PCIE_CLKDLY_HW_500US;
1162 break;
1163 case MAC_AX_PCIE_CLKDLY_1MS:
1164 *val = PCIE_CLKDLY_HW_1MS;
1165 break;
1166 case MAC_AX_PCIE_CLKDLY_3MS:
1167 *val = PCIE_CLKDLY_HW_3MS;
1168 break;
1169 default:
1170 PLTFM_MSG_ERR("[ERR]CLKDLY wt val illegal!\n");
1171 return MACSTCAL;
1172 }
1173 return MACSUCCESS;
1174 }
1175
update_pcie_clk(struct mac_ax_adapter * adapter,u8 * val)1176 static u32 update_pcie_clk(struct mac_ax_adapter *adapter, u8 *val)
1177 {
1178 u32 ret = MACSUCCESS;
1179
1180 if (*val & PCIE_BIT_CLK)
1181 return MACSUCCESS;
1182
1183 if (*val & PCIE_BIT_L1) {
1184 *val &= ~(PCIE_BIT_L1);
1185 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
1186 if (ret != MACSUCCESS)
1187 return ret;
1188
1189 *val |= PCIE_BIT_CLK;
1190 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
1191 if (ret != MACSUCCESS)
1192 return ret;
1193
1194 *val |= PCIE_BIT_L1;
1195 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
1196 if (ret != MACSUCCESS)
1197 return ret;
1198
1199 PLTFM_MSG_WARN("[WARN] L1 enable & CLKREQ disable!\n");
1200 }
1201
1202 *val |= PCIE_BIT_CLK;
1203 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
1204
1205 return ret;
1206 }
1207
update_aspmdly(struct mac_ax_adapter * adapter,u8 * val,struct mac_ax_pcie_cfgspc_param * param,struct mac_ax_pcie_cfgspc_param * param_def)1208 u32 update_aspmdly(struct mac_ax_adapter *adapter, u8 *val,
1209 struct mac_ax_pcie_cfgspc_param *param,
1210 struct mac_ax_pcie_cfgspc_param *param_def)
1211 {
1212 u8 l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;
1213 u8 l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;
1214 u8 l1updval = param->l1dly_ctrl;
1215 u8 l0supdval = param->l0sdly_ctrl;
1216 u8 l1defval = param_def->l1dly_ctrl;
1217 u8 l0sdefval = param_def->l0sdly_ctrl;
1218 u8 tmp;
1219 u8 hwval;
1220
1221 if (l1updval != MAC_AX_PCIE_L1DLY_IGNORE) {
1222 tmp = (l1updval == MAC_AX_PCIE_L1DLY_DEF) ? l1defval : l1updval;
1223 switch (tmp) {
1224 case MAC_AX_PCIE_L1DLY_16US:
1225 hwval = PCIE_L1DLY_HW_16US;
1226 break;
1227
1228 case MAC_AX_PCIE_L1DLY_32US:
1229 hwval = PCIE_L1DLY_HW_32US;
1230 break;
1231
1232 case MAC_AX_PCIE_L1DLY_64US:
1233 hwval = PCIE_L1DLY_HW_64US;
1234 break;
1235
1236 case MAC_AX_PCIE_L1DLY_INFI:
1237 hwval = PCIE_L1DLY_HW_INFI;
1238 break;
1239
1240 default:
1241 PLTFM_MSG_ERR("[ERR]L1DLY wt val illegal!\n");
1242 return MACSTCAL;
1243 }
1244
1245 tmp = (hwval << SHFT_L1DLY) & l1mask;
1246 *val = (*val & ~(l1mask)) | tmp;
1247 }
1248
1249 if (l0supdval != MAC_AX_PCIE_L0SDLY_IGNORE) {
1250 tmp = (l0supdval == MAC_AX_PCIE_L0SDLY_DEF) ?
1251 l0sdefval : l0supdval;
1252 switch (tmp) {
1253 case MAC_AX_PCIE_L0SDLY_1US:
1254 hwval = PCIE_L0SDLY_HW_1US;
1255 break;
1256
1257 case MAC_AX_PCIE_L0SDLY_2US:
1258 hwval = PCIE_L0SDLY_HW_2US;
1259 break;
1260
1261 case MAC_AX_PCIE_L0SDLY_3US:
1262 hwval = PCIE_L0SDLY_HW_3US;
1263 break;
1264
1265 case MAC_AX_PCIE_L0SDLY_4US:
1266 hwval = PCIE_L0SDLY_HW_4US;
1267 break;
1268
1269 case MAC_AX_PCIE_L0SDLY_5US:
1270 hwval = PCIE_L0SDLY_HW_5US;
1271 break;
1272
1273 case MAC_AX_PCIE_L0SDLY_6US:
1274 hwval = PCIE_L0SDLY_HW_6US;
1275 break;
1276
1277 case MAC_AX_PCIE_L0SDLY_7US:
1278 hwval = PCIE_L0SDLY_HW_7US;
1279 break;
1280
1281 default:
1282 PLTFM_MSG_ERR("[ERR]L0SDLY wt val illegal!\n");
1283 return MACSTCAL;
1284 }
1285 tmp = (hwval << SHFT_L0SDLY) & l0smask;
1286 *val = (*val & ~(l0smask)) | tmp;
1287 }
1288
1289 return MACSUCCESS;
1290 }
1291
pcie_cfgspc_write(struct mac_ax_adapter * adapter,struct mac_ax_pcie_cfgspc_param * param)1292 static u32 pcie_cfgspc_write(struct mac_ax_adapter *adapter,
1293 struct mac_ax_pcie_cfgspc_param *param)
1294 {
1295 u8 l1_val;
1296 u8 aspm_val;
1297 u8 l1ss_val;
1298 u8 clk_val;
1299 u8 tmp8;
1300 struct mac_ax_pcie_cfgspc_param *param_def;
1301 u32 ret = MACSUCCESS;
1302 u8 val8;
1303
1304 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
1305 param_def = &pcie_cfgspc_param_def_8852b;
1306 else
1307 param_def = &pcie_cfgspc_param_def;
1308
1309 ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &l1_val);
1310 if (ret != MACSUCCESS)
1311 return ret;
1312 ret = dbi_r8_pcie(adapter, PCIE_ASPM_CTRL, &aspm_val);
1313 if (ret != MACSUCCESS)
1314 return ret;
1315 ret = dbi_r8_pcie(adapter, PCIE_L1SS_CTRL, &l1ss_val);
1316 if (ret != MACSUCCESS)
1317 return ret;
1318 ret = dbi_r8_pcie(adapter, PCIE_CLK_CTRL, &clk_val);
1319 if (ret != MACSUCCESS)
1320 return ret;
1321
1322 if (l1_val == 0xFF || aspm_val == 0xFF || l1ss_val == 0xFF ||
1323 clk_val == 0xFF) {
1324 PLTFM_MSG_ERR("[ERR] PCIE CFG reg read 0xFF!\n");
1325 return MACCMP;
1326 }
1327
1328 ret = dbi_r8_pcie(adapter, PCIE_L1_STS, &tmp8);
1329 if (ret != MACSUCCESS)
1330 return ret;
1331 if (((tmp8 & PCIE_BIT_STS_L0S) && param->l0s_ctrl ==
1332 MAC_AX_PCIE_DEFAULT) || (param->l0s_ctrl != MAC_AX_PCIE_DEFAULT &&
1333 param->l0s_ctrl != MAC_AX_PCIE_IGNORE))
1334 update_pcie_func(&aspm_val, PCIE_BIT_L0S,
1335 param->l0s_ctrl, param_def->l0s_ctrl);
1336
1337 if (((tmp8 & PCIE_BIT_STS_L1) && param->l1_ctrl ==
1338 MAC_AX_PCIE_DEFAULT) || (param->l1_ctrl != MAC_AX_PCIE_DEFAULT &&
1339 param->l1_ctrl != MAC_AX_PCIE_IGNORE))
1340 update_pcie_func(&l1_val, PCIE_BIT_L1,
1341 param->l1_ctrl, param_def->l1_ctrl);
1342 update_pcie_func(&l1_val, PCIE_BIT_WAKE,
1343 param->wake_ctrl, param_def->wake_ctrl);
1344 update_pcie_func(&l1_val, PCIE_BIT_CLK,
1345 param->crq_ctrl, param_def->crq_ctrl);
1346 ret = chk_stus_l1ss(adapter, &val8);
1347 if (ret != MACSUCCESS) {
1348 PLTFM_MSG_ERR("[ERR] PCIE chk_stus_l1ss\n");
1349 return ret;
1350 }
1351
1352 if ((val8 && param->l1ss_ctrl == MAC_AX_PCIE_DEFAULT) ||
1353 (param->l1ss_ctrl != MAC_AX_PCIE_DEFAULT &&
1354 param->l1ss_ctrl != MAC_AX_PCIE_IGNORE))
1355 update_pcie_func(&l1ss_val, PCIE_BIT_L1SS,
1356 param->l1ss_ctrl, param_def->l1ss_ctrl);
1357
1358 ret = update_clkdly(adapter, &clk_val, param->clkdly_ctrl,
1359 param_def->clkdly_ctrl);
1360 if (ret != MACSUCCESS)
1361 return ret;
1362
1363 ret = update_aspmdly(adapter, &aspm_val, param, param_def);
1364 if (ret != MACSUCCESS)
1365 return ret;
1366
1367 if (param->clkdly_ctrl != MAC_AX_PCIE_CLKDLY_IGNORE) {
1368 ret = dbi_w8_pcie(adapter, PCIE_CLK_CTRL, clk_val);
1369 if (ret != MACSUCCESS)
1370 return ret;
1371 }
1372
1373 if (param->l0s_ctrl != MAC_AX_PCIE_IGNORE ||
1374 param->l1dly_ctrl != MAC_AX_PCIE_L1DLY_IGNORE ||
1375 param->l0sdly_ctrl != MAC_AX_PCIE_L0SDLY_IGNORE) {
1376 ret = dbi_w8_pcie(adapter, PCIE_ASPM_CTRL, aspm_val);
1377 if (ret != MACSUCCESS)
1378 return ret;
1379 }
1380 if (param->l1_ctrl != MAC_AX_PCIE_IGNORE ||
1381 param->wake_ctrl != MAC_AX_PCIE_IGNORE ||
1382 param->crq_ctrl != MAC_AX_PCIE_IGNORE) {
1383 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, l1_val);
1384 if (ret != MACSUCCESS)
1385 return ret;
1386 }
1387 if (param->l1ss_ctrl != MAC_AX_PCIE_IGNORE) {
1388 ret = dbi_w8_pcie(adapter, PCIE_L1SS_CTRL, l1ss_val);
1389 if (ret != MACSUCCESS)
1390 return ret;
1391 }
1392
1393 return ret;
1394 }
1395
pcie_cfgspc_read(struct mac_ax_adapter * adapter,struct mac_ax_pcie_cfgspc_param * param)1396 u32 pcie_cfgspc_read(struct mac_ax_adapter *adapter,
1397 struct mac_ax_pcie_cfgspc_param *param)
1398 {
1399 u8 l1_val;
1400 u8 aspm_val;
1401 u8 l1ss_val;
1402 u8 clk_val;
1403 u8 l0smask;
1404 u8 l1mask;
1405 u32 ret;
1406
1407 ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &l1_val);
1408 if (ret != MACSUCCESS)
1409 return ret;
1410
1411 ret = dbi_r8_pcie(adapter, PCIE_ASPM_CTRL, &aspm_val);
1412 if (ret != MACSUCCESS)
1413 return ret;
1414
1415 ret = dbi_r8_pcie(adapter, PCIE_L1SS_CTRL, &l1ss_val);
1416 if (ret != MACSUCCESS)
1417 return ret;
1418
1419 ret = dbi_r8_pcie(adapter, PCIE_CLK_CTRL, &clk_val);
1420 if (ret != MACSUCCESS)
1421 return ret;
1422
1423 if (l1_val == 0xFF || aspm_val == 0xFF ||
1424 l1ss_val == 0xFF || clk_val == 0xFF) {
1425 PLTFM_MSG_ERR("[ERR] (2nd)PCIE CFG reg read 0xFF!\n");
1426 return MACCMP;
1427 }
1428
1429 param->l0s_ctrl = GET_PCIE_FUNC_STUS(aspm_val, PCIE_BIT_L0S);
1430 param->l1_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_L1);
1431 param->l1ss_ctrl = GET_PCIE_FUNC_STUS(l1ss_val, PCIE_BIT_L1SS);
1432 param->wake_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_WAKE);
1433 param->crq_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_CLK);
1434
1435 switch (clk_val) {
1436 case PCIE_CLKDLY_HW_0:
1437 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_0;
1438 break;
1439
1440 case PCIE_CLKDLY_HW_30US:
1441 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_30US;
1442 break;
1443
1444 case PCIE_CLKDLY_HW_50US:
1445 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_50US;
1446 break;
1447
1448 case PCIE_CLKDLY_HW_100US:
1449 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_100US;
1450 break;
1451
1452 case PCIE_CLKDLY_HW_150US:
1453 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_150US;
1454 break;
1455
1456 case PCIE_CLKDLY_HW_200US:
1457 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_200US;
1458 break;
1459
1460 default:
1461 param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_R_ERR;
1462 break;
1463 }
1464
1465 l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;
1466 l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;
1467
1468 switch ((aspm_val & l0smask) >> SHFT_L0SDLY) {
1469 case PCIE_L0SDLY_HW_1US:
1470 param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_1US;
1471 break;
1472
1473 case PCIE_L0SDLY_HW_3US:
1474 param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_3US;
1475 break;
1476
1477 case PCIE_L0SDLY_HW_5US:
1478 param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_5US;
1479 break;
1480
1481 case PCIE_L0SDLY_HW_7US:
1482 param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_7US;
1483 break;
1484
1485 default:
1486 param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_R_ERR;
1487 break;
1488 }
1489
1490 switch ((aspm_val & l1mask) >> SHFT_L1DLY) {
1491 case PCIE_L1DLY_HW_16US:
1492 param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_16US;
1493 break;
1494
1495 case PCIE_L1DLY_HW_32US:
1496 param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_32US;
1497 break;
1498
1499 case PCIE_L1DLY_HW_64US:
1500 param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_64US;
1501 break;
1502
1503 case PCIE_L1DLY_HW_INFI:
1504 param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_INFI;
1505 break;
1506
1507 default:
1508 param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_R_ERR;
1509 break;
1510 }
1511
1512 return ret;
1513 }
1514
cfgspc_set_pcie(struct mac_ax_adapter * adapter,struct mac_ax_pcie_cfgspc_param * param)1515 u32 cfgspc_set_pcie(struct mac_ax_adapter *adapter,
1516 struct mac_ax_pcie_cfgspc_param *param)
1517 {
1518 u32 status = MACSUCCESS;
1519
1520 if (param->write == 1)
1521 status = pcie_cfgspc_write(adapter, param);
1522
1523 if (param->read == 1)
1524 status = pcie_cfgspc_read(adapter, param);
1525
1526 return status;
1527 }
1528
pcie_ltr_write(struct mac_ax_adapter * adapter,struct mac_ax_pcie_ltr_param * param)1529 static u32 pcie_ltr_write(struct mac_ax_adapter *adapter,
1530 struct mac_ax_pcie_ltr_param *param)
1531 {
1532 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1533 u32 ltr_ctrl0, ltr_ctrl1, ltr_idle_ltcy, ltr_act_ltcy;
1534 u32 status = MACSUCCESS;
1535 struct mac_ax_pcie_ltr_param *param_def = &pcie_ltr_param_def;
1536 u32 val32;
1537 enum mac_ax_pcie_func_ctrl ctrl;
1538
1539 ltr_ctrl0 = MAC_REG_R32(R_AX_LTR_CTRL_0);
1540 ltr_ctrl1 = MAC_REG_R32(R_AX_LTR_CTRL_1);
1541 ltr_idle_ltcy = MAC_REG_R32(R_AX_LTR_IDLE_LATENCY);
1542 ltr_act_ltcy = MAC_REG_R32(R_AX_LTR_ACTIVE_LATENCY);
1543
1544 if (ltr_ctrl0 == MAC_AX_R32_FF || ltr_ctrl0 == MAC_AX_R32_EA ||
1545 ltr_ctrl1 == MAC_AX_R32_FF || ltr_ctrl1 == MAC_AX_R32_EA ||
1546 ltr_idle_ltcy == MAC_AX_R32_FF || ltr_idle_ltcy == MAC_AX_R32_EA ||
1547 ltr_act_ltcy == MAC_AX_R32_FF || ltr_act_ltcy == MAC_AX_R32_EA) {
1548 PLTFM_MSG_ERR("[ERR] LTR reg read nothing!\n");
1549 return MACCMP;
1550 }
1551
1552 if (!(param_def->ltr_ctrl == MAC_AX_PCIE_IGNORE ||
1553 param->ltr_ctrl == MAC_AX_PCIE_IGNORE ||
1554 param_def->ltr_ctrl == MAC_AX_PCIE_DEFAULT)) {
1555 ctrl = param->ltr_ctrl == MAC_AX_PCIE_DEFAULT ?
1556 param_def->ltr_ctrl : param->ltr_ctrl;
1557 ltr_ctrl0 = ctrl == MAC_AX_PCIE_ENABLE ?
1558 (ltr_ctrl0 | B_AX_LTR_EN) :
1559 (ltr_ctrl0 & ~B_AX_LTR_EN);
1560 }
1561
1562 if (!(param_def->ltr_hw_ctrl == MAC_AX_PCIE_IGNORE ||
1563 param->ltr_hw_ctrl == MAC_AX_PCIE_IGNORE ||
1564 param_def->ltr_hw_ctrl == MAC_AX_PCIE_DEFAULT)) {
1565 ctrl = param->ltr_hw_ctrl == MAC_AX_PCIE_DEFAULT ?
1566 param_def->ltr_hw_ctrl : param->ltr_hw_ctrl;
1567 ltr_ctrl0 = ctrl == MAC_AX_PCIE_ENABLE ?
1568 (ltr_ctrl0 | B_AX_LTR_HW_EN | B_AX_LTR_WD_NOEMP_CHK) :
1569 (ltr_ctrl0 & ~(B_AX_LTR_HW_EN | B_AX_LTR_WD_NOEMP_CHK));
1570 }
1571
1572 if (!(param_def->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_IGNORE ||
1573 param->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_IGNORE ||
1574 param_def->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_DEF)) {
1575 val32 = param->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_DEF ?
1576 param_def->ltr_spc_ctrl : param->ltr_spc_ctrl;
1577 ltr_ctrl0 = SET_CLR_WORD(ltr_ctrl0, val32, B_AX_LTR_SPACE_IDX);
1578 }
1579
1580 if (!(param_def->ltr_idle_timer_ctrl ==
1581 MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE ||
1582 param->ltr_idle_timer_ctrl ==
1583 MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE ||
1584 param_def->ltr_idle_timer_ctrl ==
1585 MAC_AX_PCIE_LTR_IDLE_TIMER_DEF)) {
1586 val32 = param->ltr_idle_timer_ctrl ==
1587 MAC_AX_PCIE_LTR_IDLE_TIMER_DEF ?
1588 param_def->ltr_idle_timer_ctrl :
1589 param->ltr_idle_timer_ctrl;
1590 ltr_ctrl0 = SET_CLR_WORD(ltr_ctrl0, val32,
1591 B_AX_LTR_IDLE_TIMER_IDX);
1592 }
1593
1594 if (!(param_def->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1595 param->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1596 param_def->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
1597 val32 = param->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
1598 param_def->ltr_rx0_th_ctrl.val :
1599 param->ltr_rx0_th_ctrl.val;
1600 ltr_ctrl1 = SET_CLR_WORD(ltr_ctrl1, val32, B_AX_LTR_RX0_TH);
1601 }
1602
1603 if (!(param_def->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1604 param->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1605 param_def->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
1606 val32 = param->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
1607 param_def->ltr_rx1_th_ctrl.val :
1608 param->ltr_rx1_th_ctrl.val;
1609 ltr_ctrl1 = SET_CLR_WORD(ltr_ctrl1, val32, B_AX_LTR_RX1_TH);
1610 }
1611
1612 if (!(param_def->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1613 param->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1614 param_def->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
1615 val32 = param->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
1616 param_def->ltr_idle_lat_ctrl.val :
1617 param->ltr_idle_lat_ctrl.val;
1618 ltr_idle_ltcy =
1619 SET_CLR_WORD(ltr_idle_ltcy, val32, B_AX_LTR_IDLE_LTCY);
1620 }
1621
1622 if (!(param_def->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1623 param->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
1624 param_def->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
1625 val32 = param->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
1626 param_def->ltr_act_lat_ctrl.val :
1627 param->ltr_act_lat_ctrl.val;
1628 ltr_act_ltcy =
1629 SET_CLR_WORD(ltr_act_ltcy, val32, B_AX_LTR_ACT_LTCY);
1630 }
1631
1632 MAC_REG_W32(R_AX_LTR_CTRL_0, ltr_ctrl0);
1633 MAC_REG_W32(R_AX_LTR_CTRL_1, ltr_ctrl1);
1634 MAC_REG_W32(R_AX_LTR_IDLE_LATENCY, ltr_idle_ltcy);
1635 MAC_REG_W32(R_AX_LTR_ACTIVE_LATENCY, ltr_act_ltcy);
1636
1637 return status;
1638 }
1639
pcie_ltr_read(struct mac_ax_adapter * adapter,struct mac_ax_pcie_ltr_param * param)1640 static u32 pcie_ltr_read(struct mac_ax_adapter *adapter,
1641 struct mac_ax_pcie_ltr_param *param)
1642 {
1643 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1644 u32 status = MACSUCCESS;
1645 u32 ltr_ctrl0, ltr_ctrl1, ltr_idle_ltcy, ltr_act_ltcy;
1646
1647 ltr_ctrl0 = MAC_REG_R32(R_AX_LTR_CTRL_0);
1648 ltr_ctrl1 = MAC_REG_R32(R_AX_LTR_CTRL_1);
1649 ltr_idle_ltcy = MAC_REG_R32(R_AX_LTR_IDLE_LATENCY);
1650 ltr_act_ltcy = MAC_REG_R32(R_AX_LTR_ACTIVE_LATENCY);
1651
1652 if (ltr_ctrl0 == MAC_AX_R32_FF || ltr_ctrl0 == MAC_AX_R32_EA ||
1653 ltr_ctrl1 == MAC_AX_R32_FF || ltr_ctrl1 == MAC_AX_R32_EA ||
1654 ltr_idle_ltcy == MAC_AX_R32_FF || ltr_idle_ltcy == MAC_AX_R32_EA ||
1655 ltr_act_ltcy == MAC_AX_R32_FF || ltr_act_ltcy == MAC_AX_R32_EA) {
1656 PLTFM_MSG_ERR("[ERR] LTR reg read nothing!\n");
1657 return MACCMP;
1658 }
1659
1660 param->ltr_ctrl = ltr_ctrl0 & B_AX_LTR_EN ?
1661 MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
1662
1663 param->ltr_hw_ctrl = ltr_ctrl0 & B_AX_LTR_HW_EN ?
1664 MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
1665
1666 param->ltr_spc_ctrl =
1667 (enum mac_ax_pcie_ltr_spc)
1668 GET_FIELD(ltr_ctrl0, B_AX_LTR_SPACE_IDX);
1669 param->ltr_idle_timer_ctrl =
1670 (enum mac_ax_pcie_ltr_idle_timer)
1671 GET_FIELD(ltr_ctrl0, B_AX_LTR_IDLE_TIMER_IDX);
1672
1673 param->ltr_rx0_th_ctrl.val =
1674 (u16)GET_FIELD(ltr_ctrl1, B_AX_LTR_RX0_TH);
1675 param->ltr_rx1_th_ctrl.val =
1676 (u16)GET_FIELD(ltr_ctrl1, B_AX_LTR_RX1_TH);
1677 param->ltr_idle_lat_ctrl.val =
1678 GET_FIELD(ltr_idle_ltcy, B_AX_LTR_IDLE_LTCY);
1679 param->ltr_act_lat_ctrl.val =
1680 GET_FIELD(ltr_act_ltcy, B_AX_LTR_ACT_LTCY);
1681
1682 return status;
1683 }
1684
ltr_set_pcie(struct mac_ax_adapter * adapter,struct mac_ax_pcie_ltr_param * param)1685 u32 ltr_set_pcie(struct mac_ax_adapter *adapter,
1686 struct mac_ax_pcie_ltr_param *param)
1687 {
1688 u32 ret = MACSUCCESS;
1689
1690 if (param->write) {
1691 ret = pcie_ltr_write(adapter, param);
1692 if (ret != MACSUCCESS) {
1693 PLTFM_MSG_ERR("[ERR]pcie ltr write fail %d\n", ret);
1694 return ret;
1695 }
1696 }
1697
1698 if (param->read) {
1699 ret = pcie_ltr_read(adapter, param);
1700 if (ret != MACSUCCESS) {
1701 PLTFM_MSG_ERR("[ERR]pcie ltr read fail %d\n", ret);
1702 return ret;
1703 }
1704 }
1705
1706 return ret;
1707 }
1708
ltr_sw_trigger(struct mac_ax_adapter * adapter,enum mac_ax_pcie_ltr_sw_ctrl ctrl)1709 u32 ltr_sw_trigger(struct mac_ax_adapter *adapter,
1710 enum mac_ax_pcie_ltr_sw_ctrl ctrl)
1711 {
1712 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1713 u32 val32;
1714
1715 val32 = MAC_REG_R32(R_AX_LTR_CTRL_0);
1716
1717 if (val32 & B_AX_LTR_HW_EN) {
1718 PLTFM_MSG_ERR("[ERR]LTR HW mode running\n");
1719 return MACPROCERR;
1720 } else if (!(val32 & B_AX_LTR_EN)) {
1721 PLTFM_MSG_ERR("[ERR]LTR not enable\n");
1722 return MACHWNOTEN;
1723 }
1724
1725 switch (ctrl) {
1726 case MAC_AX_PCIE_LTR_SW_ACT:
1727 MAC_REG_W32(R_AX_LTR_CTRL_0, val32 | B_AX_APP_LTR_ACT);
1728 break;
1729 case MAC_AX_PCIE_LTR_SW_IDLE:
1730 MAC_REG_W32(R_AX_LTR_CTRL_0, val32 | B_AX_APP_LTR_IDLE);
1731 break;
1732 default:
1733 PLTFM_MSG_ERR("Invalid input for %s\n", __func__);
1734 return MACFUNCINPUT;
1735 }
1736
1737 return MACSUCCESS;
1738 }
1739
pcie_set_sic(struct mac_ax_adapter * adapter)1740 static u32 pcie_set_sic(struct mac_ax_adapter *adapter)
1741 {
1742 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1743
1744 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
1745 return MACSUCCESS;
1746
1747 MAC_REG_W32(R_AX_PCIE_EXP_CTRL, MAC_REG_R32(R_AX_PCIE_EXP_CTRL) &
1748 ~B_AX_SIC_EN_FORCE_CLKREQ);
1749
1750 return MACSUCCESS;
1751 }
1752
pcie_set_lbc(struct mac_ax_adapter * adapter,enum mac_ax_pcie_func_ctrl ctrl,enum mac_ax_lbc_tmr tmr)1753 static u32 pcie_set_lbc(struct mac_ax_adapter *adapter,
1754 enum mac_ax_pcie_func_ctrl ctrl,
1755 enum mac_ax_lbc_tmr tmr)
1756 {
1757 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1758 struct mac_ax_intf_info *intf_info_def;
1759 u32 val32;
1760
1761 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
1762 intf_info_def = &intf_info_def_8852a;
1763 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
1764 intf_info_def = &intf_info_def_8852b;
1765 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
1766 intf_info_def = &intf_info_def_8852c;
1767 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
1768 intf_info_def = &intf_info_def_8192xb;
1769 } else {
1770 PLTFM_MSG_ERR("Chip ID is undefined\n");
1771 return MACCHIPID;
1772 }
1773
1774 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
1775 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
1776 val32 = MAC_REG_R32(R_AX_LBC_WATCHDOG);
1777 if (ctrl == MAC_AX_PCIE_ENABLE ||
1778 (ctrl == MAC_AX_PCIE_DEFAULT &&
1779 intf_info_def->lbc_en == MAC_AX_PCIE_ENABLE)) {
1780 val32 = SET_CLR_WORD(val32, tmr == MAC_AX_LBC_TMR_DEF ?
1781 intf_info_def->lbc_tmr : tmr,
1782 B_AX_LBC_TIMER);
1783 val32 |= B_AX_LBC_FLAG | B_AX_LBC_EN;
1784 } else {
1785 val32 &= ~B_AX_LBC_EN;
1786 }
1787 MAC_REG_W32(R_AX_LBC_WATCHDOG, val32);
1788 }
1789
1790 return MACSUCCESS;
1791 }
1792
pcie_set_dbg(struct mac_ax_adapter * adapter)1793 static u32 pcie_set_dbg(struct mac_ax_adapter *adapter)
1794 {
1795 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1796
1797 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
1798 return MACSUCCESS;
1799
1800 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, MAC_REG_R32(R_AX_PCIE_DBG_CTRL) |
1801 B_AX_ASFF_FULL_NO_STK |
1802 B_AX_EN_STUCK_DBG);
1803 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
1804 MAC_REG_W32(R_AX_PCIE_EXP_CTRL,
1805 MAC_REG_R32(R_AX_PCIE_EXP_CTRL) |
1806 B_AX_EN_CHKDSC_NO_RX_STUCK);
1807
1808 return MACSUCCESS;
1809 }
1810
pcie_set_keep_reg(struct mac_ax_adapter * adapter)1811 static u32 pcie_set_keep_reg(struct mac_ax_adapter *adapter)
1812 {
1813 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1814
1815 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, MAC_REG_R32(R_AX_PCIE_INIT_CFG1) |
1816 B_AX_PCIE_TXRST_KEEP_REG |
1817 B_AX_PCIE_RXRST_KEEP_REG);
1818
1819 return MACSUCCESS;
1820 }
1821
pcie_set_io_rcy(struct mac_ax_adapter * adapter,enum mac_ax_pcie_func_ctrl ctrl,enum mac_ax_io_rcy_tmr tmr)1822 static u32 pcie_set_io_rcy(struct mac_ax_adapter *adapter,
1823 enum mac_ax_pcie_func_ctrl ctrl,
1824 enum mac_ax_io_rcy_tmr tmr)
1825 {
1826 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1827 struct mac_ax_intf_info *intf_info_def;
1828 u32 val32;
1829
1830 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
1831 intf_info_def = &intf_info_def_8852a;
1832 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
1833 intf_info_def = &intf_info_def_8852b;
1834 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
1835 intf_info_def = &intf_info_def_8852c;
1836 } else {
1837 PLTFM_MSG_ERR("Chip ID is undefined\n");
1838 return MACCHIPID;
1839 }
1840
1841 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
1842 val32 = 0;
1843 if (ctrl == MAC_AX_PCIE_ENABLE ||
1844 (ctrl == MAC_AX_PCIE_DEFAULT &&
1845 intf_info_def->io_rcy_en == MAC_AX_PCIE_ENABLE)) {
1846 val32 = SET_CLR_WORD(val32,
1847 tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?
1848 intf_info_def->io_rcy_tmr : tmr,
1849 B_AX_PCIE_WDT_TIMER_M1);
1850 MAC_REG_W32(R_AX_PCIE_WDT_TIMER_M1, val32);
1851 MAC_REG_W32(R_AX_PCIE_WDT_TIMER_M2, val32);
1852 MAC_REG_W32(R_AX_PCIE_WDT_TIMER_E0, val32);
1853 MAC_REG_W32(R_AX_PCIE_WDT_TIMER_S1, val32);
1854
1855 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M1);
1856 val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_M1;
1857 MAC_REG_W32(R_AX_PCIE_IO_RCY_M1, val32);
1858
1859 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M2);
1860 val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_M2;
1861 MAC_REG_W32(R_AX_PCIE_IO_RCY_M2, val32);
1862
1863 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_E0);
1864 val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_E0;
1865 MAC_REG_W32(R_AX_PCIE_IO_RCY_E0, val32);
1866
1867 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_S1);
1868 val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_S1;
1869 MAC_REG_W32(R_AX_PCIE_IO_RCY_S1, val32);
1870 } else {
1871 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M1);
1872 val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_M1;
1873 MAC_REG_W32(R_AX_PCIE_IO_RCY_M1, val32);
1874
1875 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M2);
1876 val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_M2;
1877 MAC_REG_W32(R_AX_PCIE_IO_RCY_M2, val32);
1878
1879 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_E0);
1880 val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_E0;
1881 MAC_REG_W32(R_AX_PCIE_IO_RCY_E0, val32);
1882
1883 val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_S1);
1884 val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_S1;
1885 MAC_REG_W32(R_AX_PCIE_IO_RCY_S1, val32);
1886 }
1887 }
1888
1889 return MACSUCCESS;
1890 }
1891
ctrl_hci_dma_en_pcie(struct mac_ax_adapter * adapter,enum mac_ax_func_sw en)1892 static void ctrl_hci_dma_en_pcie(struct mac_ax_adapter *adapter,
1893 enum mac_ax_func_sw en)
1894 {
1895 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1896
1897 if (en == MAC_AX_FUNC_EN)
1898 MAC_REG_W32(R_AX_HCI_FUNC_EN,
1899 MAC_REG_R32(R_AX_HCI_FUNC_EN) | B_AX_HCI_TXDMA_EN |
1900 B_AX_HCI_RXDMA_EN);
1901 else
1902 MAC_REG_W32(R_AX_HCI_FUNC_EN,
1903 MAC_REG_R32(R_AX_HCI_FUNC_EN) &
1904 ~(B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN));
1905 }
1906
poll_io_idle_pcie(struct mac_ax_adapter * adapter)1907 static u32 poll_io_idle_pcie(struct mac_ax_adapter *adapter)
1908 {
1909 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
1910 u32 val32;
1911 u32 cnt;
1912
1913 cnt = PCIE_POLL_IO_IDLE_CNT;
1914 val32 = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY;
1915 while (cnt && (MAC_REG_R32(R_AX_PCIE_DMA_BUSY1) & val32)) {
1916 cnt--;
1917 PLTFM_DELAY_US(PCIE_POLL_IO_IDLE_DLY_US);
1918 }
1919
1920 if (!cnt) {
1921 PLTFM_MSG_ERR("[ERR]PCIE dmach busy1 0x%X\n",
1922 MAC_REG_R32(R_AX_PCIE_DMA_BUSY1));
1923 return MACPOLLTO;
1924 }
1925
1926 return MACSUCCESS;
1927 }
1928
get_txbd_desc_reg(struct mac_ax_adapter * adapter,u8 dma_ch,u32 * addr_l,u32 * addr_h)1929 static u32 get_txbd_desc_reg(struct mac_ax_adapter *adapter, u8 dma_ch,
1930 u32 *addr_l, u32 *addr_h)
1931 {
1932 u8 c_id = adapter->hw_info->chip_id;
1933
1934 if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
1935 ((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
1936 (dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
1937 PLTFM_MSG_ERR("[ERR] TXBD desc CH%d not support in 8852B\n",
1938 dma_ch);
1939 return MACHWNOSUP;
1940 }
1941
1942 switch (dma_ch) {
1943 case MAC_AX_DMA_ACH0:
1944 *addr_l = ach0_txbd_desa_l_reg[c_id];
1945 *addr_h = ach0_txbd_desa_h_reg[c_id];
1946 break;
1947 case MAC_AX_DMA_ACH1:
1948 *addr_l = ach1_txbd_desa_l_reg[c_id];
1949 *addr_h = ach1_txbd_desa_h_reg[c_id];
1950 break;
1951 case MAC_AX_DMA_ACH2:
1952 *addr_l = ach2_txbd_desa_l_reg[c_id];
1953 *addr_h = ach2_txbd_desa_h_reg[c_id];
1954 break;
1955 case MAC_AX_DMA_ACH3:
1956 *addr_l = ach3_txbd_desa_l_reg[c_id];
1957 *addr_h = ach3_txbd_desa_h_reg[c_id];
1958 break;
1959 case MAC_AX_DMA_ACH4:
1960 *addr_l = ach4_txbd_desa_l_reg[c_id];
1961 *addr_h = ach4_txbd_desa_h_reg[c_id];
1962 break;
1963 case MAC_AX_DMA_ACH5:
1964 *addr_l = ach5_txbd_desa_l_reg[c_id];
1965 *addr_h = ach5_txbd_desa_h_reg[c_id];
1966 break;
1967 case MAC_AX_DMA_ACH6:
1968 *addr_l = ach6_txbd_desa_l_reg[c_id];
1969 *addr_h = ach6_txbd_desa_h_reg[c_id];
1970 break;
1971 case MAC_AX_DMA_ACH7:
1972 *addr_l = ach7_txbd_desa_l_reg[c_id];
1973 *addr_h = ach7_txbd_desa_h_reg[c_id];
1974 break;
1975 case MAC_AX_DMA_B0MG:
1976 *addr_l = ch8_txbd_desa_l_reg[c_id];
1977 *addr_h = ch8_txbd_desa_h_reg[c_id];
1978 break;
1979 case MAC_AX_DMA_B0HI:
1980 *addr_l = ch9_txbd_desa_l_reg[c_id];
1981 *addr_h = ch9_txbd_desa_h_reg[c_id];
1982 break;
1983 case MAC_AX_DMA_B1MG:
1984 *addr_l = ch10_txbd_desa_l_reg[c_id];
1985 *addr_h = ch10_txbd_desa_h_reg[c_id];
1986 break;
1987 case MAC_AX_DMA_B1HI:
1988 *addr_l = ch11_txbd_desa_l_reg[c_id];
1989 *addr_h = ch11_txbd_desa_h_reg[c_id];
1990 break;
1991 case MAC_AX_DMA_H2C:
1992 *addr_l = ch12_txbd_desa_l_reg[c_id];
1993 *addr_h = ch12_txbd_desa_h_reg[c_id];
1994 break;
1995 default:
1996 PLTFM_MSG_ERR("[ERR] TXBD desc CH%d invalid\n", dma_ch);
1997 return MACFUNCINPUT;
1998 }
1999 return MACSUCCESS;
2000 }
2001
get_rxbd_desc_reg(struct mac_ax_adapter * adapter,u8 dma_ch,u32 * addr_l,u32 * addr_h)2002 static u32 get_rxbd_desc_reg(struct mac_ax_adapter *adapter, u8 dma_ch,
2003 u32 *addr_l, u32 *addr_h)
2004 {
2005 u8 c_id = adapter->hw_info->chip_id;
2006
2007 switch (dma_ch) {
2008 case MAC_AX_RX_CH_RXQ:
2009 *addr_l = rxq_rxbd_desa_l_reg[c_id];
2010 *addr_h = rxq_rxbd_desa_h_reg[c_id];
2011 break;
2012 case MAC_AX_RX_CH_RPQ:
2013 *addr_l = rpq_rxbd_desa_l_reg[c_id];
2014 *addr_h = rpq_rxbd_desa_h_reg[c_id];
2015 break;
2016 default:
2017 PLTFM_MSG_ERR("[ERR] RXBD desc CH%d invalid\n", dma_ch);
2018 return MACFUNCINPUT;
2019 }
2020 return MACSUCCESS;
2021 }
2022
get_txbd_num_reg(struct mac_ax_adapter * adapter,u8 dma_ch,u32 * reg)2023 static u32 get_txbd_num_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
2024 {
2025 u8 c_id = adapter->hw_info->chip_id;
2026
2027 if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
2028 ((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
2029 (dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
2030 PLTFM_MSG_ERR("[ERR] TXBD num CH%d not support in 8852B\n",
2031 dma_ch);
2032 return MACHWNOSUP;
2033 }
2034
2035 switch (dma_ch) {
2036 case MAC_AX_DMA_ACH0:
2037 *reg = R_AX_ACH0_TXBD_NUM;
2038 break;
2039 case MAC_AX_DMA_ACH1:
2040 *reg = R_AX_ACH1_TXBD_NUM;
2041 break;
2042 case MAC_AX_DMA_ACH2:
2043 *reg = R_AX_ACH2_TXBD_NUM;
2044 break;
2045 case MAC_AX_DMA_ACH3:
2046 *reg = R_AX_ACH3_TXBD_NUM;
2047 break;
2048 case MAC_AX_DMA_ACH4:
2049 *reg = R_AX_ACH4_TXBD_NUM;
2050 break;
2051 case MAC_AX_DMA_ACH5:
2052 *reg = R_AX_ACH5_TXBD_NUM;
2053 break;
2054 case MAC_AX_DMA_ACH6:
2055 *reg = R_AX_ACH6_TXBD_NUM;
2056 break;
2057 case MAC_AX_DMA_ACH7:
2058 *reg = R_AX_ACH7_TXBD_NUM;
2059 break;
2060 case MAC_AX_DMA_B0MG:
2061 *reg = R_AX_CH8_TXBD_NUM;
2062 break;
2063 case MAC_AX_DMA_B0HI:
2064 *reg = R_AX_CH9_TXBD_NUM;
2065 break;
2066 case MAC_AX_DMA_B1MG:
2067 *reg = ch10_txbd_num_reg[c_id];
2068 break;
2069 case MAC_AX_DMA_B1HI:
2070 *reg = ch11_txbd_num_reg[c_id];
2071 break;
2072 case MAC_AX_DMA_H2C:
2073 *reg = R_AX_CH12_TXBD_NUM;
2074 break;
2075 default:
2076 PLTFM_MSG_ERR("[ERR] TXBD num CH%d invalid\n", dma_ch);
2077 return MACFUNCINPUT;
2078 }
2079
2080 return MACSUCCESS;
2081 }
2082
get_txbd_idx_reg(struct mac_ax_adapter * adapter,u8 dma_ch,u32 * reg)2083 static u32 get_txbd_idx_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
2084 {
2085 if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
2086 ((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
2087 (dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
2088 PLTFM_MSG_ERR("[ERR] TXBD idx CH%d not support in 8852B\n",
2089 dma_ch);
2090 return MACHWNOSUP;
2091 }
2092
2093 switch (dma_ch) {
2094 case MAC_AX_DMA_ACH0:
2095 *reg = R_AX_ACH0_TXBD_IDX;
2096 break;
2097 case MAC_AX_DMA_ACH1:
2098 *reg = R_AX_ACH1_TXBD_IDX;
2099 break;
2100 case MAC_AX_DMA_ACH2:
2101 *reg = R_AX_ACH2_TXBD_IDX;
2102 break;
2103 case MAC_AX_DMA_ACH3:
2104 *reg = R_AX_ACH3_TXBD_IDX;
2105 break;
2106 case MAC_AX_DMA_ACH4:
2107 *reg = R_AX_ACH4_TXBD_IDX;
2108 break;
2109 case MAC_AX_DMA_ACH5:
2110 *reg = R_AX_ACH5_TXBD_IDX;
2111 break;
2112 case MAC_AX_DMA_ACH6:
2113 *reg = R_AX_ACH6_TXBD_IDX;
2114 break;
2115 case MAC_AX_DMA_ACH7:
2116 *reg = R_AX_ACH7_TXBD_IDX;
2117 break;
2118 case MAC_AX_DMA_B0MG:
2119 *reg = R_AX_CH8_TXBD_IDX;
2120 break;
2121 case MAC_AX_DMA_B0HI:
2122 *reg = R_AX_CH9_TXBD_IDX;
2123 break;
2124 case MAC_AX_DMA_B1MG:
2125 *reg = R_AX_CH10_TXBD_IDX;
2126 break;
2127 case MAC_AX_DMA_B1HI:
2128 *reg = R_AX_CH11_TXBD_IDX;
2129 break;
2130 case MAC_AX_DMA_H2C:
2131 *reg = R_AX_CH12_TXBD_IDX;
2132 break;
2133 default:
2134 PLTFM_MSG_ERR("[ERR] TXBD idx CH%d invalid\n", dma_ch);
2135 return MACFUNCINPUT;
2136 }
2137
2138 return MACSUCCESS;
2139 }
2140
get_rxbd_num_reg(struct mac_ax_adapter * adapter,u8 dma_ch,u32 * reg)2141 static u32 get_rxbd_num_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
2142 {
2143 u8 c_id = adapter->hw_info->chip_id;
2144
2145 switch (dma_ch) {
2146 case MAC_AX_RX_CH_RXQ:
2147 *reg = rxq_rxbd_num_reg[c_id];
2148 break;
2149 case MAC_AX_RX_CH_RPQ:
2150 *reg = rpq_rxbd_num_reg[c_id];
2151 break;
2152 default:
2153 PLTFM_MSG_ERR("[ERR] RXBD num CH%d invalid\n", dma_ch);
2154 return MACFUNCINPUT;
2155 }
2156
2157 return MACSUCCESS;
2158 }
2159
get_txbd_ram_reg(struct mac_ax_adapter * adapter,u8 dma_ch,u32 * reg)2160 static u32 get_txbd_ram_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
2161 {
2162 u8 c_id = adapter->hw_info->chip_id;
2163
2164 if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
2165 ((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
2166 (dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
2167 PLTFM_MSG_ERR("[ERR] TXBD ram CH%d not support in 8852B\n",
2168 dma_ch);
2169 return MACHWNOSUP;
2170 }
2171
2172 switch (dma_ch) {
2173 case MAC_AX_DMA_ACH0:
2174 *reg = ach0_bdram_ctrl_reg[c_id];
2175 break;
2176 case MAC_AX_DMA_ACH1:
2177 *reg = ach1_bdram_ctrl_reg[c_id];
2178 break;
2179 case MAC_AX_DMA_ACH2:
2180 *reg = ach2_bdram_ctrl_reg[c_id];
2181 break;
2182 case MAC_AX_DMA_ACH3:
2183 *reg = ach3_bdram_ctrl_reg[c_id];
2184 break;
2185 case MAC_AX_DMA_ACH4:
2186 *reg = ach4_bdram_ctrl_reg[c_id];
2187 break;
2188 case MAC_AX_DMA_ACH5:
2189 *reg = ach5_bdram_ctrl_reg[c_id];
2190 break;
2191 case MAC_AX_DMA_ACH6:
2192 *reg = ach6_bdram_ctrl_reg[c_id];
2193 break;
2194 case MAC_AX_DMA_ACH7:
2195 *reg = ach7_bdram_ctrl_reg[c_id];
2196 break;
2197 case MAC_AX_DMA_B0MG:
2198 *reg = ch8_bdram_ctrl_reg[c_id];
2199 break;
2200 case MAC_AX_DMA_B0HI:
2201 *reg = ch9_bdram_ctrl_reg[c_id];
2202 break;
2203 case MAC_AX_DMA_B1MG:
2204 *reg = ch10_bdram_ctrl_reg[c_id];
2205 break;
2206 case MAC_AX_DMA_B1HI:
2207 *reg = ch11_bdram_ctrl_reg[c_id];
2208 break;
2209 case MAC_AX_DMA_H2C:
2210 *reg = ch12_bdram_ctrl_reg[c_id];
2211 break;
2212 default:
2213 PLTFM_MSG_ERR("[ERR] TXBD ram CH%d invalid\n", dma_ch);
2214 return MACFUNCINPUT;
2215 }
2216
2217 return MACSUCCESS;
2218 }
2219
mode_op(struct mac_ax_adapter * adapter,struct mac_ax_intf_info * intf_info)2220 static u32 mode_op(struct mac_ax_adapter *adapter,
2221 struct mac_ax_intf_info *intf_info)
2222 {
2223 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2224 u8 c_id = adapter->hw_info->chip_id;
2225 u32 val32;
2226 struct tx_base_desc *txbd = (struct tx_base_desc *)intf_info->txbd_buf;
2227 struct rx_base_desc *rxbd = (struct rx_base_desc *)intf_info->rxbd_buf;
2228 enum mac_ax_bd_trunc_mode *txbd_trunc_mode =
2229 (&intf_info->txbd_trunc_mode);
2230 enum mac_ax_bd_trunc_mode *rxbd_trunc_mode =
2231 (&intf_info->rxbd_trunc_mode);
2232 enum mac_ax_rxbd_mode *rxbd_mode = (&intf_info->rxbd_mode);
2233 enum mac_ax_tag_mode *tag_mode = (&intf_info->tag_mode);
2234 enum mac_ax_multi_tag_num *multi_tag_num = (&intf_info->multi_tag_num);
2235 enum mac_ax_wd_dma_intvl *wd_dma_idle_intvl =
2236 (&intf_info->wd_dma_idle_intvl);
2237 enum mac_ax_wd_dma_intvl *wd_dma_act_intvl =
2238 (&intf_info->wd_dma_act_intvl);
2239 enum mac_ax_tx_burst *tx_burst = &intf_info->tx_burst;
2240 enum mac_ax_rx_burst *rx_burst = &intf_info->rx_burst;
2241 struct mac_ax_intf_info *intf_info_def;
2242
2243 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
2244 intf_info_def = &intf_info_def_8852a;
2245 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2246 intf_info_def = &intf_info_def_8852b;
2247 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
2248 intf_info_def = &intf_info_def_8852c;
2249 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
2250 intf_info_def = &intf_info_def_8192xb;
2251 } else {
2252 PLTFM_MSG_ERR("Chip ID is undefined\n");
2253 return MACCHIPID;
2254 }
2255
2256 if (intf_info->txbd_trunc_mode == MAC_AX_BD_DEF)
2257 txbd_trunc_mode = (&intf_info_def->txbd_trunc_mode);
2258
2259 if (intf_info->rxbd_trunc_mode == MAC_AX_BD_DEF)
2260 rxbd_trunc_mode = (&intf_info_def->rxbd_trunc_mode);
2261
2262 if ((*txbd_trunc_mode) == MAC_AX_BD_TRUNC) {
2263 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
2264 is_cv(adapter, CBV)) {
2265 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_TX_TRUNC_MODE;
2266 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2267 MAC_REG_W32(R_AX_TXDMA_ADDR_H, txbd->phy_addr_h);
2268 }
2269 } else if ((*txbd_trunc_mode) == MAC_AX_BD_NORM) {
2270 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
2271 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2272 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_TX_TRUNC_MODE;
2273 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2274 }
2275 }
2276
2277 if ((*rxbd_trunc_mode) == MAC_AX_BD_TRUNC) {
2278 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
2279 is_cv(adapter, CBV)) {
2280 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_RX_TRUNC_MODE;
2281 PLTFM_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2282 PLTFM_REG_W32(R_AX_RXDMA_ADDR_H, rxbd->phy_addr_h);
2283 }
2284 } else if ((*rxbd_trunc_mode) == MAC_AX_BD_NORM) {
2285 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
2286 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2287 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_RX_TRUNC_MODE;
2288 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2289 }
2290 }
2291
2292 if (intf_info->rxbd_mode == MAC_AX_RXBD_DEF)
2293 rxbd_mode = (&intf_info_def->rxbd_mode);
2294
2295 if ((*rxbd_mode) == MAC_AX_RXBD_PKT) {
2296 val32 = MAC_REG_R32(init_cfg_reg[c_id]) & ~rxbd_mode_bit[c_id];
2297 MAC_REG_W32(init_cfg_reg[c_id], val32);
2298 } else if ((*rxbd_mode) == MAC_AX_RXBD_SEP) {
2299 val32 = MAC_REG_R32(init_cfg_reg[c_id]) | rxbd_mode_bit[c_id];
2300 MAC_REG_W32(init_cfg_reg[c_id], val32);
2301
2302 if (intf_info->rx_sep_append_len > 0x3FFF) {
2303 PLTFM_MSG_ERR("rx sep app len %d\n",
2304 intf_info->rx_sep_append_len);
2305 return MACFUNCINPUT;
2306 }
2307 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
2308 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2309 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG2);
2310 val32 = SET_CLR_WORD(val32, intf_info->rx_sep_append_len,
2311 B_AX_PCIE_RX_APPLEN);
2312 MAC_REG_W32(R_AX_PCIE_INIT_CFG2, val32);
2313 }
2314 }
2315
2316 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
2317 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2318 if (intf_info->tx_burst == MAC_AX_TX_BURST_DEF)
2319 tx_burst = &intf_info_def->tx_burst;
2320 if (intf_info->rx_burst == MAC_AX_RX_BURST_DEF)
2321 rx_burst = &intf_info_def->rx_burst;
2322 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
2323 val32 = SET_CLR_WORD(val32, *tx_burst, B_AX_PCIE_MAX_TXDMA);
2324 val32 = SET_CLR_WORD(val32, *rx_burst, B_AX_PCIE_MAX_RXDMA);
2325 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2326 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
2327 is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
2328 if (intf_info->tx_burst == MAC_AX_TX_BURST_DEF)
2329 tx_burst = &intf_info_def->tx_burst;
2330 if (intf_info->rx_burst == MAC_AX_RX_BURST_DEF)
2331 rx_burst = &intf_info_def->rx_burst;
2332 val32 = MAC_REG_R32(R_AX_HAXI_INIT_CFG1);
2333 val32 = SET_CLR_WORD(val32, *tx_burst, B_AX_HAXI_MAX_TXDMA);
2334 val32 = SET_CLR_WORD(val32, *rx_burst, B_AX_HAXI_MAX_RXDMA);
2335 MAC_REG_W32(R_AX_HAXI_INIT_CFG1, val32);
2336 } else {
2337 PLTFM_MSG_ERR("Chip ID is undefined\n");
2338 return MACCHIPID;
2339 }
2340
2341 if (intf_info->tag_mode == MAC_AX_TAG_DEF)
2342 tag_mode = (&intf_info_def->tag_mode);
2343 if (intf_info->multi_tag_num == MAC_AX_TAG_NUM_DEF)
2344 multi_tag_num = (&intf_info_def->multi_tag_num);
2345 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
2346 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2347 if ((*tag_mode) == MAC_AX_TAG_SGL) {
2348 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) &
2349 ~B_AX_LATENCY_CONTROL;
2350 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2351 } else if ((*tag_mode) == MAC_AX_TAG_MULTI) {
2352 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) |
2353 B_AX_LATENCY_CONTROL;
2354 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
2355 }
2356 }
2357
2358 val32 = MAC_REG_R32(exp_ctrl_reg[c_id]);
2359 val32 = SET_CLR_WOR2(val32, *multi_tag_num, max_tag_num_sh[c_id],
2360 max_tag_num_msk[c_id]);
2361 MAC_REG_W32(exp_ctrl_reg[c_id], val32);
2362
2363 if (intf_info->wd_dma_act_intvl == MAC_AX_WD_DMA_INTVL_DEF)
2364 wd_dma_act_intvl = (&intf_info_def->wd_dma_act_intvl);
2365 if (intf_info->wd_dma_idle_intvl == MAC_AX_WD_DMA_INTVL_DEF)
2366 wd_dma_idle_intvl = (&intf_info_def->wd_dma_idle_intvl);
2367 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
2368 is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2369 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG2);
2370 val32 = SET_CLR_WORD(val32, *wd_dma_idle_intvl,
2371 B_AX_WD_ITVL_IDLE);
2372 val32 = SET_CLR_WORD(val32, *wd_dma_act_intvl,
2373 B_AX_WD_ITVL_ACT);
2374 MAC_REG_W32(R_AX_PCIE_INIT_CFG2, val32);
2375 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
2376 is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
2377 val32 = MAC_REG_R32(R_AX_HAXI_INIT_CFG1);
2378 val32 = SET_CLR_WORD(val32, *wd_dma_idle_intvl,
2379 B_AX_WD_ITVL_IDLE_V1);
2380 val32 = SET_CLR_WORD(val32, *wd_dma_act_intvl,
2381 B_AX_WD_ITVL_ACT_V1);
2382 MAC_REG_W32(R_AX_HAXI_INIT_CFG1, val32);
2383 } else {
2384 PLTFM_MSG_ERR("Chip ID is undefined\n");
2385 return MACCHIPID;
2386 }
2387
2388 return MACSUCCESS;
2389 }
2390
trx_init_bd(struct mac_ax_adapter * adapter,struct mac_ax_intf_info * intf_info)2391 static u32 trx_init_bd(struct mac_ax_adapter *adapter,
2392 struct mac_ax_intf_info *intf_info)
2393 {
2394 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2395 struct tx_base_desc *txbd = (struct tx_base_desc *)intf_info->txbd_buf;
2396 struct rx_base_desc *rxbd = (struct rx_base_desc *)intf_info->rxbd_buf;
2397 enum mac_ax_bd_trunc_mode *txbd_trunc_mode =
2398 (&intf_info->txbd_trunc_mode);
2399 enum mac_ax_bd_trunc_mode *rxbd_trunc_mode =
2400 (&intf_info->rxbd_trunc_mode);
2401 enum mac_ax_rxbd_mode *rxbd_mode = (&intf_info->rxbd_mode);
2402 struct txbd_ram *bdram_tbl;
2403 struct mac_ax_intf_info *intf_info_def;
2404 u32 reg_addr_l, reg_addr_h, reg32, val32, bd_num;
2405 u16 val16;
2406 u8 ch, bdram_idx;
2407 u32 ret = MACSUCCESS;
2408
2409 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
2410 bdram_tbl = mac_bdram_tbl_8852a;
2411 intf_info_def = &intf_info_def_8852a;
2412 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2413 bdram_tbl = mac_bdram_tbl_8852b;
2414 intf_info_def = &intf_info_def_8852b;
2415 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
2416 bdram_tbl = mac_bdram_tbl_8852c;
2417 intf_info_def = &intf_info_def_8852c;
2418 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
2419 bdram_tbl = mac_bdram_tbl_8192xb;
2420 intf_info_def = &intf_info_def_8192xb;
2421 } else {
2422 PLTFM_MSG_ERR("Chip ID is undefined\n");
2423 return MACCHIPID;
2424 }
2425
2426 if (intf_info->txbd_trunc_mode == MAC_AX_BD_DEF)
2427 txbd_trunc_mode = (&intf_info_def->txbd_trunc_mode);
2428
2429 if (intf_info->rxbd_trunc_mode == MAC_AX_BD_DEF)
2430 rxbd_trunc_mode = (&intf_info_def->rxbd_trunc_mode);
2431
2432 if (intf_info->rxbd_mode == MAC_AX_RXBD_DEF)
2433 rxbd_mode = (&intf_info_def->rxbd_mode);
2434
2435 if (*txbd_trunc_mode == MAC_AX_BD_TRUNC) {
2436 val32 = MAC_REG_R32(R_AX_TX_ADDRESS_INFO_MODE_SETTING) |
2437 B_AX_HOST_ADDR_INFO_8B_SEL;
2438 MAC_REG_W32(R_AX_TX_ADDRESS_INFO_MODE_SETTING, val32);
2439
2440 val32 = MAC_REG_R32(R_AX_PKTIN_SETTING) &
2441 ~B_AX_WD_ADDR_INFO_LENGTH;
2442 MAC_REG_W32(R_AX_PKTIN_SETTING, val32);
2443 } else if (*txbd_trunc_mode == MAC_AX_BD_NORM) {
2444 val32 = MAC_REG_R32(R_AX_TX_ADDRESS_INFO_MODE_SETTING) &
2445 ~B_AX_HOST_ADDR_INFO_8B_SEL;
2446 MAC_REG_W32(R_AX_TX_ADDRESS_INFO_MODE_SETTING, val32);
2447
2448 val32 = MAC_REG_R32(R_AX_PKTIN_SETTING) |
2449 B_AX_WD_ADDR_INFO_LENGTH;
2450 MAC_REG_W32(R_AX_PKTIN_SETTING, val32);
2451 } else {
2452 PLTFM_MSG_ERR("pcie init txbd_trunc_mode %d illegal\n",
2453 intf_info->txbd_trunc_mode);
2454 return MACFUNCINPUT;
2455 }
2456
2457 bdram_idx = 0;
2458 for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_CH_NUM; ch++) {
2459 if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
2460 ((ch >= MAC_AX_DMA_ACH4 && ch <= MAC_AX_DMA_ACH7) ||
2461 (ch >= MAC_AX_DMA_B1MG && ch <= MAC_AX_DMA_B1HI)))
2462 continue;
2463 if (txbd[ch].phy_addr_l % TXBD_BYTE_ALIGN) {
2464 PLTFM_MSG_ERR("[ERR]ch%d txbd phyaddr 0x%X not %dB align\n",
2465 ch, txbd[ch].phy_addr_l, TXBD_BYTE_ALIGN);
2466 return MACBADDR;
2467 }
2468
2469 ret = get_txbd_desc_reg(adapter, ch, ®_addr_l, ®_addr_h);
2470 if (ret != MACSUCCESS) {
2471 PLTFM_MSG_ERR("[ERR]get_txbd_desc_reg\n");
2472 return ret;
2473 }
2474 MAC_REG_W32(reg_addr_l, txbd[ch].phy_addr_l);
2475 MAC_REG_W32(reg_addr_h, txbd[ch].phy_addr_h);
2476
2477 bd_num = (*txbd_trunc_mode == MAC_AX_BD_TRUNC) ?
2478 (txbd[ch].buf_len / BD_TRUNC_SIZE) :
2479 (txbd[ch].buf_len / BD_NORM_SIZE);
2480 if (bd_num > BD_MAX_NUM) {
2481 PLTFM_MSG_ERR("ch%d txbd num %d\n", ch, bd_num);
2482 return MACFUNCINPUT;
2483 }
2484
2485 ret = get_txbd_num_reg(adapter, ch, ®32);
2486 if (ret != MACSUCCESS) {
2487 PLTFM_MSG_ERR("[ERR]get_txbd_num_reg\n");
2488 return ret;
2489 }
2490
2491 val16 = SET_CLR_WORD(MAC_REG_R16(reg32), bd_num,
2492 B_AX_ACH0_DESC_NUM);
2493 MAC_REG_W16(reg32, val16);
2494
2495 ret = get_txbd_ram_reg(adapter, ch, ®32);
2496 if (ret != MACSUCCESS) {
2497 PLTFM_MSG_ERR("[ERR]get_txbd_ram_reg\n");
2498 return ret;
2499 }
2500
2501 val32 = MAC_REG_R32(reg32);
2502 val32 = SET_CLR_WORD(val32, bdram_tbl[bdram_idx].sidx,
2503 B_AX_ACH0_BDRAM_SIDX);
2504 val32 = SET_CLR_WORD(val32, bdram_tbl[bdram_idx].max,
2505 B_AX_ACH0_BDRAM_MAX);
2506 val32 = SET_CLR_WORD(val32, bdram_tbl[bdram_idx].min,
2507 B_AX_ACH0_BDRAM_MIN);
2508 MAC_REG_W32(reg32, val32);
2509 bdram_idx++;
2510 }
2511
2512 for (ch = MAC_AX_RX_CH_RXQ; ch < MAC_AX_RX_CH_NUM; ch++) {
2513 if (rxbd[ch].phy_addr_l % RXBD_BYTE_ALIGN) {
2514 PLTFM_MSG_ERR("[ERR]ch%d rxbd phyaddr 0x%X not %dB align\n",
2515 ch, rxbd[ch].phy_addr_l, RXBD_BYTE_ALIGN);
2516 return MACBADDR;
2517 }
2518
2519 ret = get_rxbd_desc_reg(adapter, ch, ®_addr_l, ®_addr_h);
2520 if (ret != MACSUCCESS) {
2521 PLTFM_MSG_ERR("[ERR]get_rxbd_desc_reg\n");
2522 return ret;
2523 }
2524
2525 MAC_REG_W32(reg_addr_l, rxbd[ch].phy_addr_l);
2526 MAC_REG_W32(reg_addr_h, rxbd[ch].phy_addr_h);
2527
2528 ret = get_rxbd_num_reg(adapter, ch, ®32);
2529 if (ret != MACSUCCESS) {
2530 PLTFM_MSG_ERR("[ERR]get_rxbd_num_reg\n");
2531 return ret;
2532 }
2533
2534 if (ch == MAC_AX_RX_CH_RXQ) {
2535 bd_num = (*rxbd_mode == MAC_AX_RXBD_PKT) ?
2536 (rxbd[ch].buf_len / BD_TRUNC_SIZE) :
2537 (rxbd[ch].buf_len / RXBD_SEP_TRUNC_NEW_SIZE);
2538 } else {
2539 bd_num = (*rxbd_trunc_mode == MAC_AX_BD_TRUNC) ?
2540 (rxbd[ch].buf_len / BD_TRUNC_SIZE) :
2541 (rxbd[ch].buf_len / BD_NORM_SIZE);
2542 }
2543
2544 if (bd_num > BD_MAX_NUM) {
2545 PLTFM_MSG_ERR("ch%d rxbd num %d\n", ch, bd_num);
2546 return MACFUNCINPUT;
2547 }
2548
2549 val16 = SET_CLR_WORD(MAC_REG_R16(reg32), bd_num,
2550 B_AX_RXQ_DESC_NUM);
2551 MAC_REG_W16(reg32, val16);
2552 }
2553
2554 return MACSUCCESS;
2555 }
2556
_patch_pcie_power_wake(struct mac_ax_adapter * adapter,u8 pwr_state)2557 static u32 _patch_pcie_power_wake(struct mac_ax_adapter *adapter, u8 pwr_state)
2558 {
2559 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2560
2561 if (pwr_state == PC_POWER_UP) {
2562 MAC_REG_W32(R_AX_HCI_OPT_CTRL, MAC_REG_R32(R_AX_HCI_OPT_CTRL)
2563 | BIT_WAKE_CTRL);
2564 } else if (pwr_state == PC_POWER_DOWN) {
2565 MAC_REG_W32(R_AX_HCI_OPT_CTRL, MAC_REG_R32(R_AX_HCI_OPT_CTRL)
2566 & ~BIT_WAKE_CTRL);
2567 } else {
2568 PLTFM_MSG_ERR("[ERR] patch power wake input: %d\n", pwr_state);
2569 return MACFUNCINPUT;
2570 }
2571
2572 return MACSUCCESS;
2573 }
2574
_patch_pcie_dphy_delay(struct mac_ax_adapter * adapter)2575 static u32 _patch_pcie_dphy_delay(struct mac_ax_adapter *adapter)
2576 {
2577 u16 val16;
2578 u32 ret = MACSUCCESS;
2579
2580 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
2581 return MACSUCCESS;
2582
2583 ret = mdio_r16_pcie(adapter, RAC_REG_REV2, MAC_AX_PCIE_PHY_GEN1,
2584 &val16);
2585 if (ret != MACSUCCESS)
2586 return ret;
2587 val16 = SET_CLR_WOR2(val16, PCIE_DPHY_DLY_25US, BAC_CMU_EN_DLY_SH,
2588 BAC_CMU_EN_DLY_MSK);
2589 ret = mdio_w16_pcie(adapter, RAC_REG_REV2, val16,
2590 MAC_AX_PCIE_PHY_GEN1);
2591 if (ret != MACSUCCESS)
2592 return ret;
2593
2594 return MACSUCCESS;
2595 }
2596
_patch_pcie_autok_x(struct mac_ax_adapter * adapter)2597 static u32 _patch_pcie_autok_x(struct mac_ax_adapter *adapter)
2598 {
2599 u16 val16;
2600 u32 ret = MACSUCCESS;
2601
2602 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
2603 return MACSUCCESS;
2604
2605 ret = mdio_r16_pcie(adapter, RAC_REG_FLD_0, MAC_AX_PCIE_PHY_GEN1,
2606 &val16);
2607 if (ret != MACSUCCESS)
2608 return ret;
2609 val16 = SET_CLR_WOR2(val16, PCIE_AUTOK_4, BAC_AUTOK_N_SH,
2610 BAC_AUTOK_N_MSK);
2611 ret = mdio_w16_pcie(adapter, RAC_REG_FLD_0, val16,
2612 MAC_AX_PCIE_PHY_GEN1);
2613 if (ret != MACSUCCESS)
2614 return ret;
2615
2616 return MACSUCCESS;
2617 }
2618
_patch_pcie_refclk_autok(struct mac_ax_adapter * adapter,struct mac_ax_intf_info * intf_info)2619 static u32 _patch_pcie_refclk_autok(struct mac_ax_adapter *adapter,
2620 struct mac_ax_intf_info *intf_info)
2621 {
2622 u32 ret;
2623 struct mac_ax_intf_info *intf_info_def;
2624
2625 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
2626 if (is_cv(adapter, CBV))
2627 return MACSUCCESS;
2628 } else if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2629 return MACSUCCESS;
2630 } else {
2631 //cut_ver_checker
2632 }
2633
2634 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
2635 intf_info_def = &intf_info_def_8852a;
2636 } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2637 intf_info_def = &intf_info_def_8852b;
2638 } else {
2639 PLTFM_MSG_ERR("[ERR] Invalid IC\n");
2640 return MACNOTSUP;
2641 }
2642
2643 if (intf_info->autok_en == MAC_AX_PCIE_DEFAULT)
2644 intf_info->autok_en = intf_info_def->autok_en;
2645
2646 if (intf_info->autok_en != MAC_AX_PCIE_IGNORE) {
2647 ret = mac_auto_refclk_cal_pcie(adapter, intf_info->autok_en);
2648 if (ret != MACSUCCESS) {
2649 PLTFM_MSG_ERR("[ERR] pcie autok fail %d\n", ret);
2650 return ret;
2651 }
2652 }
2653
2654 return MACSUCCESS;
2655 }
2656
_patch_pcie_deglitch(struct mac_ax_adapter * adapter)2657 static u32 _patch_pcie_deglitch(struct mac_ax_adapter *adapter)
2658 {
2659 u32 ret;
2660 u16 val16, bit_set;
2661
2662 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
2663 return MACSUCCESS;
2664
2665 bit_set = BIT11 | BIT10 | BIT9 | BIT8;
2666
2667 ret = mdio_r16_pcie(adapter, RAC_ANA24, MAC_AX_PCIE_PHY_GEN1, &val16);
2668 if (ret != MACSUCCESS)
2669 return ret;
2670 val16 &= ~bit_set;
2671 ret = mdio_w16_pcie(adapter, RAC_ANA24, val16, MAC_AX_PCIE_PHY_GEN1);
2672 if (ret != MACSUCCESS)
2673 return ret;
2674
2675 ret = mdio_r16_pcie(adapter, RAC_ANA24, MAC_AX_PCIE_PHY_GEN2, &val16);
2676 if (ret != MACSUCCESS)
2677 return ret;
2678 val16 &= ~bit_set;
2679 ret = mdio_w16_pcie(adapter, RAC_ANA24, val16, MAC_AX_PCIE_PHY_GEN2);
2680 if (ret != MACSUCCESS)
2681 return ret;
2682
2683 return MACSUCCESS;
2684 }
2685
_patch_pcie_l2_rxen_lat(struct mac_ax_adapter * adapter)2686 static u32 _patch_pcie_l2_rxen_lat(struct mac_ax_adapter *adapter)
2687 {
2688 u32 ret;
2689 u16 val16, bit_set;
2690
2691 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
2692 return MACSUCCESS;
2693
2694 bit_set = BIT15 | BIT14;
2695
2696 ret = mdio_r16_pcie(adapter, RAC_ANA26, MAC_AX_PCIE_PHY_GEN1, &val16);
2697 if (ret != MACSUCCESS)
2698 return ret;
2699 val16 &= ~bit_set;
2700 ret = mdio_w16_pcie(adapter, RAC_ANA26, val16, MAC_AX_PCIE_PHY_GEN1);
2701 if (ret != MACSUCCESS)
2702 return ret;
2703
2704 ret = mdio_r16_pcie(adapter, RAC_ANA26, MAC_AX_PCIE_PHY_GEN2, &val16);
2705 if (ret != MACSUCCESS)
2706 return ret;
2707 val16 &= ~bit_set;
2708 ret = mdio_w16_pcie(adapter, RAC_ANA26, val16, MAC_AX_PCIE_PHY_GEN2);
2709 if (ret != MACSUCCESS)
2710 return ret;
2711
2712 return MACSUCCESS;
2713 }
2714
_patch_pcie_l1off_pwroff(struct mac_ax_adapter * adapter)2715 static u32 _patch_pcie_l1off_pwroff(struct mac_ax_adapter *adapter)
2716 {
2717 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2718
2719 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
2720 return MACSUCCESS;
2721
2722 MAC_REG_W32(R_AX_PCIE_PS_CTRL,
2723 MAC_REG_R32(R_AX_PCIE_PS_CTRL) & ~B_AX_L1OFF_PWR_OFF_EN);
2724
2725 return MACSUCCESS;
2726 }
2727
_patch_pcie_aphy_pwrcut(struct mac_ax_adapter * adapter)2728 static u32 _patch_pcie_aphy_pwrcut(struct mac_ax_adapter *adapter)
2729 {
2730 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2731
2732 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
2733 return MACSUCCESS;
2734
2735 MAC_REG_W32(R_AX_SYS_PW_CTRL,
2736 MAC_REG_R32(R_AX_SYS_PW_CTRL) & ~B_AX_PSUS_OFF_CAPC_EN);
2737
2738 return MACSUCCESS;
2739 }
2740
_patch_pcie_hci_ldo(struct mac_ax_adapter * adapter)2741 static u32 _patch_pcie_hci_ldo(struct mac_ax_adapter *adapter)
2742 {
2743 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2744 u32 val32;
2745
2746 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
2747 return MACSUCCESS;
2748
2749 val32 = MAC_REG_R32(R_AX_SYS_SDIO_CTRL);
2750 val32 |= B_AX_PCIE_DIS_L2_CTRL_LDO_HCI;
2751 val32 &= ~B_AX_PCIE_DIS_WLSUS_AFT_PDN;
2752 MAC_REG_W32(R_AX_SYS_SDIO_CTRL, val32);
2753
2754 return MACSUCCESS;
2755 }
2756
_patch_pcie_l2_hci_ldo(struct mac_ax_adapter * adapter)2757 static u32 _patch_pcie_l2_hci_ldo(struct mac_ax_adapter *adapter)
2758 {
2759 u32 ret;
2760 u16 bit_set;
2761 u8 val8;
2762
2763 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
2764 return MACSUCCESS;
2765
2766 bit_set = BIT0;
2767
2768 ret = dbi_r8_pcie(adapter, CFG_RST_MSTATE, &val8);
2769 if (ret != MACSUCCESS)
2770 return ret;
2771 val8 |= bit_set;
2772 ret = dbi_w8_pcie(adapter, CFG_RST_MSTATE, val8);
2773 if (ret != MACSUCCESS)
2774 return ret;
2775
2776 ret = dbi_r8_pcie(adapter, CFG_RST_MSTATE, &val8);
2777 if (ret != MACSUCCESS)
2778 return ret;
2779 val8 |= bit_set;
2780 ret = dbi_w8_pcie(adapter, CFG_RST_MSTATE, val8);
2781 if (ret != MACSUCCESS)
2782 return ret;
2783
2784 return MACSUCCESS;
2785 }
2786
_patch_pcie_rxdma_prefth(struct mac_ax_adapter * adapter)2787 static u32 _patch_pcie_rxdma_prefth(struct mac_ax_adapter *adapter)
2788 {
2789 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2790
2791 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
2792 return MACSUCCESS;
2793
2794 MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
2795 MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_DIS_RXDMA_PRE);
2796
2797 return MACSUCCESS;
2798 }
2799
_patch_pcie_sw_ltr_setparm(struct mac_ax_adapter * adapter,struct mac_ax_pcie_ltr_param * param)2800 static u32 _patch_pcie_sw_ltr_setparm(struct mac_ax_adapter *adapter,
2801 struct mac_ax_pcie_ltr_param *param)
2802 {
2803 if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
2804 is_cv(adapter, CBV)))
2805 return MACSUCCESS;
2806
2807 param->ltr_hw_ctrl = MAC_AX_PCIE_DISABLE;
2808
2809 return MACSUCCESS;
2810 }
2811
_patch_pcie_sw_ltr(struct mac_ax_adapter * adapter,enum mac_ax_pcie_ltr_sw_ctrl ctrl)2812 static u32 _patch_pcie_sw_ltr(struct mac_ax_adapter *adapter,
2813 enum mac_ax_pcie_ltr_sw_ctrl ctrl)
2814 {
2815 u32 ret;
2816
2817 if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
2818 is_cv(adapter, CBV)))
2819 return MACSUCCESS;
2820
2821 ret = ltr_sw_trigger(adapter, ctrl);
2822 if (ret != MACSUCCESS) {
2823 PLTFM_MSG_ERR("[ERR]pcie ltr sw trig %d %d\n", ctrl, ret);
2824 return ret;
2825 }
2826
2827 return MACSUCCESS;
2828 }
2829
ctrl_dma_all_pcie(struct mac_ax_adapter * adapter,enum mac_ax_func_sw en)2830 void ctrl_dma_all_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
2831 {
2832 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2833 u8 c_id = adapter->hw_info->chip_id;
2834
2835 if (en == MAC_AX_FUNC_EN) {
2836 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
2837 MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
2838 MAC_REG_R32(R_AX_PCIE_DMA_STOP1) &
2839 ~B_AX_STOP_PCIEIO);
2840 }
2841 MAC_REG_W32(init_cfg_reg[adapter->hw_info->chip_id],
2842 MAC_REG_R32(init_cfg_reg[c_id]) |
2843 txhci_en_bit[c_id] | rxhci_en_bit[c_id]);
2844 } else {
2845 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
2846 MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
2847 MAC_REG_R32(R_AX_PCIE_DMA_STOP1) |
2848 B_AX_STOP_PCIEIO);
2849 }
2850 MAC_REG_W32(init_cfg_reg[adapter->hw_info->chip_id],
2851 MAC_REG_R32(init_cfg_reg[c_id]) &
2852 ~(txhci_en_bit[c_id] | rxhci_en_bit[c_id]));
2853 }
2854 }
2855
clr_idx_all_pcie(struct mac_ax_adapter * adapter)2856 u32 clr_idx_all_pcie(struct mac_ax_adapter *adapter)
2857 {
2858 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2859 u8 c_id = adapter->hw_info->chip_id;
2860 u32 val32;
2861
2862 val32 = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX |
2863 B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX |
2864 B_AX_CLR_CH12_IDX;
2865
2866 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
2867 val32 |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX |
2868 B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX;
2869
2870 MAC_REG_W32(R_AX_TXBD_RWPTR_CLR1, val32);
2871
2872 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2873 val32 = B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX;
2874 MAC_REG_W32(txbd_rwptr_clr2_reg[c_id], val32);
2875 }
2876
2877 val32 = B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX;
2878 MAC_REG_W32(rxbd_rwptr_clr_reg[c_id], val32);
2879
2880 PLTFM_MSG_ALWAYS("Clear all bd index done.\n");
2881
2882 return MACSUCCESS;
2883 }
2884
clr_idx_ch_pcie(struct mac_ax_adapter * adapter,struct mac_ax_txdma_ch_map * txch_map,struct mac_ax_rxdma_ch_map * rxch_map)2885 static u32 clr_idx_ch_pcie(struct mac_ax_adapter *adapter,
2886 struct mac_ax_txdma_ch_map *txch_map,
2887 struct mac_ax_rxdma_ch_map *rxch_map)
2888 {
2889 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2890 u32 reg_clr_tx1 = R_AX_TXBD_RWPTR_CLR1;
2891 u32 reg_clr_tx2 = R_AX_TXBD_RWPTR_CLR2;
2892 u32 reg_clr_rx = R_AX_RXBD_RWPTR_CLR;
2893 u32 val32 = 0;
2894
2895 if (txch_map->ch0 == MAC_AX_PCIE_ENABLE)
2896 val32 |= B_AX_CLR_ACH0_IDX;
2897
2898 if (txch_map->ch1 == MAC_AX_PCIE_ENABLE)
2899 val32 |= B_AX_CLR_ACH1_IDX;
2900
2901 if (txch_map->ch2 == MAC_AX_PCIE_ENABLE)
2902 val32 |= B_AX_CLR_ACH2_IDX;
2903
2904 if (txch_map->ch3 == MAC_AX_PCIE_ENABLE)
2905 val32 |= B_AX_CLR_ACH3_IDX;
2906
2907 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
2908 if (txch_map->ch4 == MAC_AX_PCIE_ENABLE)
2909 val32 |= B_AX_CLR_ACH4_IDX;
2910
2911 if (txch_map->ch5 == MAC_AX_PCIE_ENABLE)
2912 val32 |= B_AX_CLR_ACH5_IDX;
2913
2914 if (txch_map->ch6 == MAC_AX_PCIE_ENABLE)
2915 val32 |= B_AX_CLR_ACH6_IDX;
2916
2917 if (txch_map->ch7 == MAC_AX_PCIE_ENABLE)
2918 val32 |= B_AX_CLR_ACH7_IDX;
2919 }
2920
2921 if (txch_map->ch8 == MAC_AX_PCIE_ENABLE)
2922 val32 |= B_AX_CLR_CH8_IDX;
2923
2924 if (txch_map->ch9 == MAC_AX_PCIE_ENABLE)
2925 val32 |= B_AX_CLR_CH9_IDX;
2926
2927 if (txch_map->ch12 == MAC_AX_PCIE_ENABLE)
2928 val32 |= B_AX_CLR_CH12_IDX;
2929
2930 MAC_REG_W32(reg_clr_tx1, val32);
2931
2932 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
2933 val32 = 0;
2934 if (txch_map->ch10 == MAC_AX_PCIE_ENABLE)
2935 val32 |= B_AX_CLR_CH10_IDX;
2936
2937 if (txch_map->ch11 == MAC_AX_PCIE_ENABLE)
2938 val32 |= B_AX_CLR_CH11_IDX;
2939
2940 MAC_REG_W32(reg_clr_tx2, val32);
2941 }
2942
2943 val32 = 0;
2944 if (rxch_map->rxq == MAC_AX_PCIE_ENABLE)
2945 val32 |= B_AX_CLR_RXQ_IDX;
2946 if (rxch_map->rpq == MAC_AX_PCIE_ENABLE)
2947 val32 |= B_AX_CLR_RPQ_IDX;
2948
2949 MAC_REG_W32(reg_clr_rx, val32);
2950
2951 return MACSUCCESS;
2952 }
2953
ctrl_txdma_ch_pcie(struct mac_ax_adapter * adapter,struct mac_ax_txdma_ch_map * ch_map)2954 u32 ctrl_txdma_ch_pcie(struct mac_ax_adapter *adapter,
2955 struct mac_ax_txdma_ch_map *ch_map)
2956 {
2957 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
2958 u8 c_id = adapter->hw_info->chip_id;
2959 u32 val32;
2960
2961 val32 = MAC_REG_R32(dma_stop1_reg[c_id]);
2962 if (ch_map->ch0 == MAC_AX_PCIE_ENABLE)
2963 val32 &= ~B_AX_STOP_ACH0;
2964 else if (ch_map->ch0 == MAC_AX_PCIE_DISABLE)
2965 val32 |= B_AX_STOP_ACH0;
2966
2967 if (ch_map->ch1 == MAC_AX_PCIE_ENABLE)
2968 val32 &= ~B_AX_STOP_ACH1;
2969 else if (ch_map->ch1 == MAC_AX_PCIE_DISABLE)
2970 val32 |= B_AX_STOP_ACH1;
2971
2972 if (ch_map->ch2 == MAC_AX_PCIE_ENABLE)
2973 val32 &= ~B_AX_STOP_ACH2;
2974 else if (ch_map->ch2 == MAC_AX_PCIE_DISABLE)
2975 val32 |= B_AX_STOP_ACH2;
2976
2977 if (ch_map->ch3 == MAC_AX_PCIE_ENABLE)
2978 val32 &= ~B_AX_STOP_ACH3;
2979 else if (ch_map->ch3 == MAC_AX_PCIE_DISABLE)
2980 val32 |= B_AX_STOP_ACH3;
2981 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
2982 if (ch_map->ch4 == MAC_AX_PCIE_ENABLE)
2983 val32 &= ~B_AX_STOP_ACH4;
2984 else if (ch_map->ch4 == MAC_AX_PCIE_DISABLE)
2985 val32 |= B_AX_STOP_ACH4;
2986
2987 if (ch_map->ch5 == MAC_AX_PCIE_ENABLE)
2988 val32 &= ~B_AX_STOP_ACH5;
2989 else if (ch_map->ch5 == MAC_AX_PCIE_DISABLE)
2990 val32 |= B_AX_STOP_ACH5;
2991
2992 if (ch_map->ch6 == MAC_AX_PCIE_ENABLE)
2993 val32 &= ~B_AX_STOP_ACH6;
2994 else if (ch_map->ch6 == MAC_AX_PCIE_DISABLE)
2995 val32 |= B_AX_STOP_ACH6;
2996
2997 if (ch_map->ch7 == MAC_AX_PCIE_ENABLE)
2998 val32 &= ~B_AX_STOP_ACH7;
2999 else if (ch_map->ch7 == MAC_AX_PCIE_DISABLE)
3000 val32 |= B_AX_STOP_ACH7;
3001 }
3002 if (ch_map->ch8 == MAC_AX_PCIE_ENABLE)
3003 val32 &= ~B_AX_STOP_CH8;
3004 else if (ch_map->ch8 == MAC_AX_PCIE_DISABLE)
3005 val32 |= B_AX_STOP_CH8;
3006
3007 if (ch_map->ch9 == MAC_AX_PCIE_ENABLE)
3008 val32 &= ~B_AX_STOP_CH9;
3009 else if (ch_map->ch9 == MAC_AX_PCIE_DISABLE)
3010 val32 |= B_AX_STOP_CH9;
3011
3012 if (ch_map->ch12 == MAC_AX_PCIE_ENABLE)
3013 val32 &= ~B_AX_STOP_CH12;
3014 else if (ch_map->ch12 == MAC_AX_PCIE_DISABLE)
3015 val32 |= B_AX_STOP_CH12;
3016 MAC_REG_W32(dma_stop1_reg[c_id], val32);
3017
3018 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
3019 val32 = MAC_REG_R32(dma_stop2_reg[c_id]);
3020 if (ch_map->ch10 == MAC_AX_PCIE_ENABLE)
3021 val32 &= ~B_AX_STOP_CH10;
3022 else if (ch_map->ch10 == MAC_AX_PCIE_DISABLE)
3023 val32 |= B_AX_STOP_CH10;
3024
3025 if (ch_map->ch11 == MAC_AX_PCIE_ENABLE)
3026 val32 &= ~B_AX_STOP_CH11;
3027 else if (ch_map->ch11 == MAC_AX_PCIE_DISABLE)
3028 val32 |= B_AX_STOP_CH11;
3029 MAC_REG_W32(dma_stop2_reg[c_id], val32);
3030 }
3031
3032 return MACSUCCESS;
3033 }
3034
poll_txdma_ch_idle_pcie(struct mac_ax_adapter * adapter,struct mac_ax_txdma_ch_map * ch_map)3035 u32 poll_txdma_ch_idle_pcie(struct mac_ax_adapter *adapter,
3036 struct mac_ax_txdma_ch_map *ch_map)
3037 {
3038 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3039 u8 c_id = adapter->hw_info->chip_id;
3040 u32 val32;
3041 u32 cnt;
3042
3043 val32 = 0;
3044 if (ch_map->ch0 == MAC_AX_PCIE_ENABLE)
3045 val32 |= B_AX_ACH0_BUSY;
3046
3047 if (ch_map->ch1 == MAC_AX_PCIE_ENABLE)
3048 val32 |= B_AX_ACH1_BUSY;
3049
3050 if (ch_map->ch2 == MAC_AX_PCIE_ENABLE)
3051 val32 |= B_AX_ACH2_BUSY;
3052
3053 if (ch_map->ch3 == MAC_AX_PCIE_ENABLE)
3054 val32 |= B_AX_ACH3_BUSY;
3055
3056 if (ch_map->ch8 == MAC_AX_PCIE_ENABLE)
3057 val32 |= B_AX_CH8_BUSY;
3058
3059 if (ch_map->ch9 == MAC_AX_PCIE_ENABLE)
3060 val32 |= B_AX_CH9_BUSY;
3061
3062 if (ch_map->ch12 == MAC_AX_PCIE_ENABLE)
3063 val32 |= B_AX_CH12_BUSY;
3064 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
3065 if (ch_map->ch4 == MAC_AX_PCIE_ENABLE)
3066 val32 |= B_AX_ACH4_BUSY;
3067
3068 if (ch_map->ch5 == MAC_AX_PCIE_ENABLE)
3069 val32 |= B_AX_ACH5_BUSY;
3070
3071 if (ch_map->ch6 == MAC_AX_PCIE_ENABLE)
3072 val32 |= B_AX_ACH6_BUSY;
3073
3074 if (ch_map->ch7 == MAC_AX_PCIE_ENABLE)
3075 val32 |= B_AX_ACH7_BUSY;
3076 }
3077
3078 cnt = PCIE_POLL_DMACH_IDLE_CNT;
3079 while (cnt && (MAC_REG_R32(dma_busy1_reg[c_id]) & val32)) {
3080 cnt--;
3081 PLTFM_DELAY_US(PCIE_POLL_DMACH_IDLE_DLY_US);
3082 }
3083
3084 if (!cnt) {
3085 PLTFM_MSG_ERR("[ERR]PCIE dmach busy1 0x%X\n",
3086 MAC_REG_R32(dma_busy1_reg[c_id]));
3087 return MACPOLLTO;
3088 }
3089
3090 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
3091 val32 = 0;
3092 if (ch_map->ch10 == MAC_AX_PCIE_ENABLE)
3093 val32 |= B_AX_CH10_BUSY;
3094
3095 if (ch_map->ch11 == MAC_AX_PCIE_ENABLE)
3096 val32 |= B_AX_CH11_BUSY;
3097
3098 cnt = PCIE_POLL_DMACH_IDLE_CNT;
3099 while (cnt && (MAC_REG_R32(dma_busy2_reg[c_id]) & val32)) {
3100 cnt--;
3101 PLTFM_DELAY_US(PCIE_POLL_DMACH_IDLE_DLY_US);
3102 }
3103
3104 if (!cnt) {
3105 PLTFM_MSG_ERR("[ERR]PCIE dmach busy2 0x%X\n",
3106 MAC_REG_R32(dma_busy2_reg[c_id]));
3107 return MACPOLLTO;
3108 }
3109 }
3110
3111 return MACSUCCESS;
3112 }
3113
poll_rxdma_ch_idle_pcie(struct mac_ax_adapter * adapter,struct mac_ax_rxdma_ch_map * ch_map)3114 u32 poll_rxdma_ch_idle_pcie(struct mac_ax_adapter *adapter,
3115 struct mac_ax_rxdma_ch_map *ch_map)
3116 {
3117 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3118 u8 c_id = adapter->hw_info->chip_id;
3119 u32 val32;
3120 u32 cnt;
3121
3122 val32 = 0;
3123 if (ch_map->rxq == MAC_AX_PCIE_ENABLE)
3124 val32 |= B_AX_RXQ_BUSY;
3125 if (ch_map->rpq == MAC_AX_PCIE_ENABLE)
3126 val32 |= B_AX_RPQ_BUSY;
3127
3128 cnt = PCIE_POLL_DMACH_IDLE_CNT;
3129 while (cnt && (MAC_REG_R32(dma_busy3_reg[c_id]) & val32)) {
3130 cnt--;
3131 PLTFM_DELAY_US(PCIE_POLL_DMACH_IDLE_DLY_US);
3132 }
3133
3134 if (!cnt) {
3135 PLTFM_MSG_ERR("[ERR]PCIE dmach busy1 0x%X\n",
3136 MAC_REG_R32(dma_busy3_reg[c_id]));
3137 return MACPOLLTO;
3138 }
3139
3140 return MACSUCCESS;
3141 }
3142
poll_dma_all_idle_pcie(struct mac_ax_adapter * adapter)3143 u32 poll_dma_all_idle_pcie(struct mac_ax_adapter *adapter)
3144 {
3145 struct mac_ax_txdma_ch_map txch_map;
3146 struct mac_ax_rxdma_ch_map rxch_map;
3147 u32 ret;
3148
3149 txch_map.ch0 = MAC_AX_PCIE_ENABLE;
3150 txch_map.ch1 = MAC_AX_PCIE_ENABLE;
3151 txch_map.ch2 = MAC_AX_PCIE_ENABLE;
3152 txch_map.ch3 = MAC_AX_PCIE_ENABLE;
3153 txch_map.ch4 = MAC_AX_PCIE_ENABLE;
3154 txch_map.ch5 = MAC_AX_PCIE_ENABLE;
3155 txch_map.ch6 = MAC_AX_PCIE_ENABLE;
3156 txch_map.ch7 = MAC_AX_PCIE_ENABLE;
3157 txch_map.ch8 = MAC_AX_PCIE_ENABLE;
3158 txch_map.ch9 = MAC_AX_PCIE_ENABLE;
3159 txch_map.ch10 = MAC_AX_PCIE_ENABLE;
3160 txch_map.ch11 = MAC_AX_PCIE_ENABLE;
3161 txch_map.ch12 = MAC_AX_PCIE_ENABLE;
3162 ret = poll_txdma_ch_idle_pcie(adapter, &txch_map);
3163 if (ret) {
3164 PLTFM_MSG_ERR("[ERR]PCIE poll txdma all ch idle\n");
3165 return ret;
3166 }
3167
3168 rxch_map.rxq = MAC_AX_PCIE_ENABLE;
3169 rxch_map.rpq = MAC_AX_PCIE_ENABLE;
3170 ret = poll_rxdma_ch_idle_pcie(adapter, &rxch_map);
3171 if (ret) {
3172 PLTFM_MSG_ERR("[ERR]PCIE poll rxdma all ch idle\n");
3173 return ret;
3174 }
3175
3176 return ret;
3177 }
3178
ctrl_txhci_pcie(struct mac_ax_adapter * adapter,enum mac_ax_func_sw en)3179 u32 ctrl_txhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
3180 {
3181 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3182
3183 if (en == MAC_AX_FUNC_EN) {
3184 MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
3185 MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_TXHCI_EN);
3186 } else if (en == MAC_AX_FUNC_DIS) {
3187 MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
3188 MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_TXHCI_EN);
3189 } else {
3190 PLTFM_MSG_ERR("[ERR]Wrong Input for Ctrl TX HCI\n");
3191 return MACFUNCINPUT;
3192 }
3193
3194 return MACSUCCESS;
3195 }
3196
ctrl_rxhci_pcie(struct mac_ax_adapter * adapter,enum mac_ax_func_sw en)3197 u32 ctrl_rxhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
3198 {
3199 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3200
3201 if (en == MAC_AX_FUNC_EN) {
3202 MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
3203 MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_RXHCI_EN);
3204 } else if (en == MAC_AX_FUNC_DIS) {
3205 MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
3206 MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_RXHCI_EN);
3207 } else {
3208 PLTFM_MSG_ERR("[ERR]Wrong Input for Ctrl RX HCI\n");
3209 return MACFUNCINPUT;
3210 }
3211
3212 return MACSUCCESS;
3213 }
3214
ctrl_dma_io_pcie(struct mac_ax_adapter * adapter,enum mac_ax_func_sw en)3215 u32 ctrl_dma_io_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
3216 {
3217 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3218
3219 if (en == MAC_AX_FUNC_EN) {
3220 MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
3221 MAC_REG_R32(R_AX_PCIE_DMA_STOP1)
3222 & ~B_AX_STOP_PCIEIO);
3223 } else if (en == MAC_AX_FUNC_DIS) {
3224 MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
3225 MAC_REG_R32(R_AX_PCIE_DMA_STOP1)
3226 | B_AX_STOP_PCIEIO);
3227 } else {
3228 PLTFM_MSG_ERR("[ERR]Wrong Input for DMA IO\n");
3229 return MACFUNCINPUT;
3230 }
3231
3232 return MACSUCCESS;
3233 }
3234
pcie_pre_init(struct mac_ax_adapter * adapter,void * param)3235 u32 pcie_pre_init(struct mac_ax_adapter *adapter, void *param)
3236 {
3237 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3238 struct mac_ax_intf_info *intf_info = (struct mac_ax_intf_info *)param;
3239 struct mac_ax_txdma_ch_map ch_map;
3240 u32 ret = MACSUCCESS;
3241
3242 ret = _patch_pcie_rxdma_prefth(adapter);
3243 if (ret != MACSUCCESS) {
3244 PLTFM_MSG_ERR("[ERR]patch pcie dis rxdma prefth %d\n", ret);
3245 return ret;
3246 }
3247
3248 ret = _patch_pcie_l1off_pwroff(adapter);
3249 if (ret != MACSUCCESS) {
3250 PLTFM_MSG_ERR("[ERR]patch pcie dis l1off pwroff %d\n", ret);
3251 return ret;
3252 }
3253
3254 ret = _patch_pcie_deglitch(adapter);
3255 if (ret != MACSUCCESS) {
3256 PLTFM_MSG_ERR("[ERR]patch pcie deglitch %d\n", ret);
3257 return ret;
3258 }
3259
3260 ret = _patch_pcie_l2_rxen_lat(adapter);
3261 if (ret != MACSUCCESS) {
3262 PLTFM_MSG_ERR("[ERR]patch pcie l2 rxen latency %d\n", ret);
3263 return ret;
3264 }
3265
3266 ret = _patch_pcie_aphy_pwrcut(adapter);
3267 if (ret != MACSUCCESS) {
3268 PLTFM_MSG_ERR("[ERR]patch pcie aphy pwrcut %d\n", ret);
3269 return ret;
3270 }
3271
3272 ret = _patch_pcie_hci_ldo(adapter);
3273 if (ret != MACSUCCESS) {
3274 PLTFM_MSG_ERR("[ERR]patch pcie hci ldo %d\n", ret);
3275 return ret;
3276 }
3277
3278 ret = _patch_pcie_dphy_delay(adapter);
3279 if (ret != MACSUCCESS) {
3280 PLTFM_MSG_ERR("[ERR]patch pcie dphy delay %d\n", ret);
3281 return ret;
3282 }
3283
3284 ret = _patch_pcie_autok_x(adapter);
3285 if (ret != MACSUCCESS) {
3286 PLTFM_MSG_ERR("[ERR]patch pcie autok_x %d\n", ret);
3287 return ret;
3288 }
3289
3290 ret = _patch_pcie_refclk_autok(adapter, intf_info);
3291 if (ret) {
3292 PLTFM_MSG_ERR("[ERR]patch pcie refclk autok %d\n", ret);
3293 return ret;
3294 }
3295
3296 ret = _patch_pcie_power_wake(adapter, PC_POWER_UP);
3297 if (ret) {
3298 PLTFM_MSG_ERR("[ERR]patch pcie power wake %d\n", ret);
3299 return ret;
3300 }
3301
3302 ret = pcie_set_sic(adapter);
3303 if (ret != MACSUCCESS) {
3304 PLTFM_MSG_ERR("[ERR]patch pcie sic %d\n", ret);
3305 return ret;
3306 }
3307
3308 ret = pcie_set_lbc(adapter, intf_info->lbc_en, intf_info->lbc_tmr);
3309 if (ret != MACSUCCESS) {
3310 PLTFM_MSG_ERR("[ERR]pcie set lbc %d\n", ret);
3311 return ret;
3312 }
3313
3314 ret = pcie_set_io_rcy(adapter, intf_info->io_rcy_en,
3315 intf_info->io_rcy_tmr);
3316 if (ret != MACSUCCESS) {
3317 PLTFM_MSG_ERR("[ERR]pcie set io rcy %d\n", ret);
3318 return ret;
3319 }
3320
3321 ret = pcie_set_dbg(adapter);
3322 if (ret != MACSUCCESS) {
3323 PLTFM_MSG_ERR("[ERR]pcie set dbg %d\n", ret);
3324 return ret;
3325 }
3326
3327 ret = pcie_set_keep_reg(adapter);
3328 if (ret != MACSUCCESS) {
3329 PLTFM_MSG_ERR("[ERR]pcie set keep reg %d\n", ret);
3330 return ret;
3331 }
3332
3333 if (intf_info->skip_all)
3334 return ret;
3335
3336 if (!intf_info->txbd_buf || !intf_info->rxbd_buf ||
3337 !intf_info->txch_map)
3338 return MACNPTR;
3339
3340 MAC_REG_W32(dma_stop1_reg[adapter->hw_info->chip_id],
3341 MAC_REG_R32(dma_stop1_reg[adapter->hw_info->chip_id]) |
3342 B_AX_STOP_WPDMA);
3343
3344 ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
3345
3346 ret = clr_idx_all_pcie(adapter);
3347 if (ret)
3348 return ret;
3349
3350 ret = poll_dma_all_idle_pcie(adapter);
3351 if (ret)
3352 return ret;
3353
3354 ret = mode_op(adapter, intf_info);
3355 if (ret)
3356 return ret;
3357
3358 ret = trx_init_bd(adapter, intf_info);
3359 if (ret)
3360 return ret;
3361
3362 ret = rst_bdram_pcie(adapter, 0);
3363 if (ret)
3364 return ret;
3365
3366 ch_map.ch0 = MAC_AX_PCIE_DISABLE;
3367 ch_map.ch1 = MAC_AX_PCIE_DISABLE;
3368 ch_map.ch2 = MAC_AX_PCIE_DISABLE;
3369 ch_map.ch3 = MAC_AX_PCIE_DISABLE;
3370 ch_map.ch4 = MAC_AX_PCIE_DISABLE;
3371 ch_map.ch5 = MAC_AX_PCIE_DISABLE;
3372 ch_map.ch6 = MAC_AX_PCIE_DISABLE;
3373 ch_map.ch7 = MAC_AX_PCIE_DISABLE;
3374 ch_map.ch8 = MAC_AX_PCIE_DISABLE;
3375 ch_map.ch9 = MAC_AX_PCIE_DISABLE;
3376 ch_map.ch10 = MAC_AX_PCIE_DISABLE;
3377 ch_map.ch11 = MAC_AX_PCIE_DISABLE;
3378 ch_map.ch12 = MAC_AX_PCIE_ENABLE;
3379 ret = ctrl_txdma_ch_pcie(adapter, &ch_map);
3380 if (ret)
3381 return ret;
3382
3383 ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_EN);
3384
3385 return MACSUCCESS;
3386 }
3387
pcie_init(struct mac_ax_adapter * adapter,void * param)3388 u32 pcie_init(struct mac_ax_adapter *adapter, void *param)
3389 {
3390 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3391 struct mac_ax_intf_info *intf_info = (struct mac_ax_intf_info *)param;
3392 u8 c_id = adapter->hw_info->chip_id;
3393 u32 val32, ret = MACSUCCESS;
3394 struct mac_ax_pcie_ltr_param ltr_param = {
3395 1,
3396 0,
3397 MAC_AX_PCIE_DEFAULT,
3398 MAC_AX_PCIE_DEFAULT,
3399 MAC_AX_PCIE_LTR_SPC_DEF,
3400 MAC_AX_PCIE_LTR_IDLE_TIMER_DEF,
3401 {MAC_AX_PCIE_DEFAULT, 0},
3402 {MAC_AX_PCIE_DEFAULT, 0},
3403 {MAC_AX_PCIE_DEFAULT, 0},
3404 {MAC_AX_PCIE_DEFAULT, 0}
3405 };
3406
3407 if (intf_info->skip_all)
3408 return MACSUCCESS;
3409
3410 ret = _patch_pcie_sw_ltr_setparm(adapter, <r_param);
3411 if (ret != MACSUCCESS) {
3412 PLTFM_MSG_ERR("[ERR]patch pcie sw ltr set param %d\n", ret);
3413 return ret;
3414 }
3415
3416 ret = ltr_set_pcie(adapter, <r_param);
3417 if (ret != MACSUCCESS) {
3418 PLTFM_MSG_ERR("[ERR]pcie ltr set fail %d\n", ret);
3419 return ret;
3420 }
3421
3422 ret = _patch_pcie_sw_ltr(adapter, MAC_AX_PCIE_LTR_SW_ACT);
3423 if (ret != MACSUCCESS) {
3424 PLTFM_MSG_ERR("[ERR]patch pcie sw ltr act %d\n", ret);
3425 return ret;
3426 }
3427
3428 if (!intf_info->txch_map) {
3429 PLTFM_MSG_ERR("[ERR] pcie init no txch map\n");
3430 return MACNPTR;
3431 }
3432
3433 val32 = MAC_REG_R32(dma_stop1_reg[c_id]) &
3434 ~(B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO);
3435 MAC_REG_W32(dma_stop1_reg[c_id], val32);
3436
3437 ret = ctrl_txdma_ch_pcie(adapter, intf_info->txch_map);
3438 if (ret)
3439 return ret;
3440
3441 return MACSUCCESS;
3442 }
3443
pcie_deinit(struct mac_ax_adapter * adapter,void * param)3444 u32 pcie_deinit(struct mac_ax_adapter *adapter, void *param)
3445 {
3446 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3447 u32 val32, ret = MACSUCCESS;
3448 struct mac_ax_pcie_ltr_param ltr_param = {
3449 1,
3450 0,
3451 MAC_AX_PCIE_DISABLE,
3452 MAC_AX_PCIE_DISABLE,
3453 MAC_AX_PCIE_LTR_SPC_DEF,
3454 MAC_AX_PCIE_LTR_IDLE_TIMER_DEF,
3455 {MAC_AX_PCIE_DEFAULT, 0},
3456 {MAC_AX_PCIE_DEFAULT, 0},
3457 {MAC_AX_PCIE_DEFAULT, 0},
3458 {MAC_AX_PCIE_DEFAULT, 0}
3459 };
3460
3461 ret = _patch_pcie_power_wake(adapter, PC_POWER_DOWN);
3462 if (ret) {
3463 PLTFM_MSG_ERR("[ERR]patch pcie power wake %d\n", ret);
3464 return ret;
3465 }
3466
3467 val32 = MAC_REG_R32(R_AX_IC_PWR_STATE);
3468 val32 = GET_FIELD(val32, B_AX_WLMAC_PWR_STE);
3469 if (val32 == MAC_AX_MAC_OFF) {
3470 PLTFM_MSG_WARN("PCIe deinit when MAC off\n");
3471 return MACSUCCESS;
3472 }
3473
3474 ret = ltr_set_pcie(adapter, <r_param);
3475 if (ret != MACSUCCESS) {
3476 PLTFM_MSG_ERR("[ERR]pcie ltr set fail %d\n", ret);
3477 return ret;
3478 }
3479
3480 ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
3481 ret = clr_idx_all_pcie(adapter);
3482 if (ret)
3483 return ret;
3484
3485 return ret;
3486 }
3487
rst_bdram_pcie(struct mac_ax_adapter * adapter,u8 val)3488 u32 rst_bdram_pcie(struct mac_ax_adapter *adapter, u8 val)
3489 {
3490 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3491 u32 cnt, val32;
3492
3493 MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
3494 MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM);
3495
3496 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
3497 MAC_REG_W32(R_AX_PCIE_PS_CTRL, MAC_REG_R32(R_AX_PCIE_PS_CTRL) |
3498 B_AX_PCIE_FORCE_L0);
3499
3500 cnt = PCIE_POLL_BDRAM_RST_CNT;
3501 do {
3502 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
3503 if (!(val32 & B_AX_RST_BDRAM))
3504 break;
3505 cnt--;
3506 PLTFM_DELAY_US(PCIE_POLL_BDRAM_RST_DLY_US);
3507 } while (cnt);
3508
3509 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
3510 MAC_REG_W32(R_AX_PCIE_PS_CTRL, MAC_REG_R32(R_AX_PCIE_PS_CTRL) &
3511 ~B_AX_PCIE_FORCE_L0);
3512
3513 if (!cnt) {
3514 PLTFM_MSG_ERR("[ERR]rst bdram timeout 0x%X\n", val32);
3515 return MACPOLLTO;
3516 }
3517
3518 return MACSUCCESS;
3519 }
3520
lv1rst_stop_dma_pcie(struct mac_ax_adapter * adapter,u8 val)3521 u32 lv1rst_stop_dma_pcie(struct mac_ax_adapter *adapter, u8 val)
3522 {
3523 u32 ret, reg32, dma_rst = 0;
3524 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3525
3526 ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
3527 ret = poll_io_idle_pcie(adapter);
3528 if (ret != MACSUCCESS) {
3529 reg32 = MAC_REG_R32(R_AX_DBG_ERR_FLAG);
3530 if ((reg32 & B_AX_TX_STUCK) ||
3531 (reg32 & B_AX_PCIE_TXBD_LEN0))
3532 dma_rst |= B_AX_HCI_TXDMA_EN;
3533 if (reg32 & B_AX_RX_STUCK)
3534 dma_rst |= B_AX_HCI_RXDMA_EN;
3535 reg32 = MAC_REG_R32(R_AX_HCI_FUNC_EN);
3536 MAC_REG_W32(R_AX_HCI_FUNC_EN, reg32 & ~dma_rst);
3537 MAC_REG_W32(R_AX_HCI_FUNC_EN, reg32 | dma_rst);
3538 ret = poll_io_idle_pcie(adapter);
3539 }
3540
3541 return ret;
3542 }
3543
lv1rst_start_dma_pcie(struct mac_ax_adapter * adapter,u8 val)3544 u32 lv1rst_start_dma_pcie(struct mac_ax_adapter *adapter, u8 val)
3545 {
3546 u32 ret;
3547
3548 ctrl_hci_dma_en_pcie(adapter, MAC_AX_FUNC_DIS);
3549 ctrl_hci_dma_en_pcie(adapter, MAC_AX_FUNC_EN);
3550 ret = clr_idx_all_pcie(adapter);
3551 if (ret)
3552 return ret;
3553
3554 ret = rst_bdram_pcie(adapter, 0);
3555 if (ret) {
3556 PLTFM_MSG_ERR("[ERR]rst bdram %d\n", ret);
3557 return ret;
3558 }
3559
3560 ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_EN);
3561 return ret;
3562 }
3563
pcie_pwr_switch(void * vadapter,u8 pre_switch,u8 on)3564 u32 pcie_pwr_switch(void *vadapter, u8 pre_switch, u8 on)
3565 {
3566 struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
3567
3568 if (pre_switch == PWR_PRE_SWITCH)
3569 adapter->mac_pwr_info.pwr_seq_proc = 1;
3570 else if (pre_switch == PWR_POST_SWITCH)
3571 adapter->mac_pwr_info.pwr_seq_proc = 0;
3572
3573 return MACSUCCESS;
3574 }
3575
pcie_trx_mit(struct mac_ax_adapter * adapter,struct mac_ax_pcie_trx_mitigation * mit_info)3576 u32 pcie_trx_mit(struct mac_ax_adapter *adapter,
3577 struct mac_ax_pcie_trx_mitigation *mit_info)
3578 {
3579 u8 tmr_unit = 0;
3580 u32 value32 = 0;
3581 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3582
3583 if (mit_info->txch_map->ch0 == MAC_AX_PCIE_ENABLE)
3584 value32 |= B_AX_TXMIT_ACH0_SEL;
3585 else if (mit_info->txch_map->ch0 == MAC_AX_PCIE_DISABLE)
3586 value32 &= ~B_AX_TXMIT_ACH0_SEL;
3587
3588 if (mit_info->txch_map->ch1 == MAC_AX_PCIE_ENABLE)
3589 value32 |= B_AX_TXMIT_ACH1_SEL;
3590 else if (mit_info->txch_map->ch1 == MAC_AX_PCIE_DISABLE)
3591 value32 &= ~B_AX_TXMIT_ACH1_SEL;
3592
3593 if (mit_info->txch_map->ch2 == MAC_AX_PCIE_ENABLE)
3594 value32 |= B_AX_TXMIT_ACH2_SEL;
3595 else if (mit_info->txch_map->ch2 == MAC_AX_PCIE_DISABLE)
3596 value32 &= ~B_AX_TXMIT_ACH2_SEL;
3597
3598 if (mit_info->txch_map->ch3 == MAC_AX_PCIE_ENABLE)
3599 value32 |= B_AX_TXMIT_ACH3_SEL;
3600 else if (mit_info->txch_map->ch3 == MAC_AX_PCIE_DISABLE)
3601 value32 &= ~B_AX_TXMIT_ACH3_SEL;
3602
3603 if (mit_info->txch_map->ch8 == MAC_AX_PCIE_ENABLE)
3604 value32 |= B_AX_TXMIT_CH8_SEL;
3605 else if (mit_info->txch_map->ch8 == MAC_AX_PCIE_DISABLE)
3606 value32 &= ~B_AX_TXMIT_CH8_SEL;
3607
3608 if (mit_info->txch_map->ch9 == MAC_AX_PCIE_ENABLE)
3609 value32 |= B_AX_TXMIT_CH9_SEL;
3610 else if (mit_info->txch_map->ch9 == MAC_AX_PCIE_DISABLE)
3611 value32 &= ~B_AX_TXMIT_CH9_SEL;
3612
3613 if (mit_info->txch_map->ch12 == MAC_AX_PCIE_ENABLE)
3614 value32 |= B_AX_TXMIT_CH12_SEL;
3615 else if (mit_info->txch_map->ch12 == MAC_AX_PCIE_DISABLE)
3616 value32 &= ~B_AX_TXMIT_CH12_SEL;
3617
3618 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
3619 if (mit_info->txch_map->ch4 == MAC_AX_PCIE_ENABLE)
3620 value32 |= B_AX_TXMIT_ACH4_SEL;
3621 else if (mit_info->txch_map->ch4 == MAC_AX_PCIE_DISABLE)
3622 value32 &= ~B_AX_TXMIT_ACH4_SEL;
3623
3624 if (mit_info->txch_map->ch5 == MAC_AX_PCIE_ENABLE)
3625 value32 |= B_AX_TXMIT_ACH5_SEL;
3626 else if (mit_info->txch_map->ch5 == MAC_AX_PCIE_DISABLE)
3627 value32 &= ~B_AX_TXMIT_ACH5_SEL;
3628
3629 if (mit_info->txch_map->ch6 == MAC_AX_PCIE_ENABLE)
3630 value32 |= B_AX_TXMIT_ACH6_SEL;
3631 else if (mit_info->txch_map->ch6 == MAC_AX_PCIE_DISABLE)
3632 value32 &= ~B_AX_TXMIT_ACH6_SEL;
3633
3634 if (mit_info->txch_map->ch7 == MAC_AX_PCIE_ENABLE)
3635 value32 |= B_AX_TXMIT_ACH7_SEL;
3636 else if (mit_info->txch_map->ch7 == MAC_AX_PCIE_DISABLE)
3637 value32 &= ~B_AX_TXMIT_ACH7_SEL;
3638
3639 if (mit_info->txch_map->ch10 == MAC_AX_PCIE_ENABLE)
3640 value32 |= B_AX_TXMIT_CH10_SEL;
3641 else if (mit_info->txch_map->ch10 == MAC_AX_PCIE_DISABLE)
3642 value32 &= ~B_AX_TXMIT_CH10_SEL;
3643
3644 if (mit_info->txch_map->ch11 == MAC_AX_PCIE_ENABLE)
3645 value32 |= B_AX_TXMIT_CH11_SEL;
3646 else if (mit_info->txch_map->ch11 == MAC_AX_PCIE_DISABLE)
3647 value32 &= ~B_AX_TXMIT_CH11_SEL;
3648 }
3649
3650 switch (mit_info->tx_timer_unit) {
3651 case MAC_AX_MIT_64US:
3652 tmr_unit = 0;
3653 break;
3654 case MAC_AX_MIT_128US:
3655 tmr_unit = 1;
3656 break;
3657 case MAC_AX_MIT_256US:
3658 tmr_unit = 2;
3659 break;
3660 case MAC_AX_MIT_512US:
3661 tmr_unit = 3;
3662 break;
3663 default:
3664 PLTFM_MSG_WARN("[WARN]Set TX MIT timer unit fail\n");
3665 break;
3666 }
3667
3668 value32 = SET_CLR_WOR2(value32, tmr_unit,
3669 B_AX_TXTIMER_UNIT_SH,
3670 B_AX_TXTIMER_UNIT_MSK);
3671
3672 value32 = SET_CLR_WOR2(value32, mit_info->tx_counter,
3673 B_AX_TXCOUNTER_MATCH_SH,
3674 B_AX_TXCOUNTER_MATCH_MSK);
3675
3676 value32 = SET_CLR_WOR2(value32, mit_info->tx_timer,
3677 B_AX_TXTIMER_MATCH_SH,
3678 B_AX_TXTIMER_MATCH_MSK);
3679
3680 MAC_REG_W32(R_AX_INT_MIT_TX, value32);
3681
3682 value32 = 0;
3683 if (mit_info->rxch_map->rxq == MAC_AX_PCIE_ENABLE)
3684 value32 |= B_AX_RXMIT_RXP2_SEL;
3685 else if (mit_info->rxch_map->rxq == MAC_AX_PCIE_DISABLE)
3686 value32 &= ~B_AX_RXMIT_RXP2_SEL;
3687
3688 if (mit_info->rxch_map->rpq == MAC_AX_PCIE_ENABLE)
3689 value32 |= B_AX_RXMIT_RXP1_SEL;
3690 else if (mit_info->rxch_map->rpq == MAC_AX_PCIE_DISABLE)
3691 value32 &= ~B_AX_RXMIT_RXP1_SEL;
3692
3693 switch (mit_info->rx_timer_unit) {
3694 case MAC_AX_MIT_64US:
3695 tmr_unit = 0;
3696 break;
3697 case MAC_AX_MIT_128US:
3698 tmr_unit = 1;
3699 break;
3700 case MAC_AX_MIT_256US:
3701 tmr_unit = 2;
3702 break;
3703 case MAC_AX_MIT_512US:
3704 tmr_unit = 3;
3705 break;
3706 default:
3707 PLTFM_MSG_WARN("[WARN]Set RX MIT timer unit fail\n");
3708 break;
3709 }
3710
3711 value32 = SET_CLR_WOR2(value32, tmr_unit,
3712 B_AX_RXTIMER_UNIT_SH,
3713 B_AX_RXTIMER_UNIT_MSK);
3714
3715 value32 = SET_CLR_WOR2(value32, mit_info->rx_counter,
3716 B_AX_RXCOUNTER_MATCH_SH,
3717 B_AX_RXCOUNTER_MATCH_MSK);
3718
3719 value32 = SET_CLR_WOR2(value32, mit_info->rx_timer,
3720 B_AX_RXTIMER_MATCH_SH,
3721 B_AX_RXTIMER_MATCH_MSK);
3722
3723 MAC_REG_W32(R_AX_INT_MIT_RX, value32);
3724
3725 return MACSUCCESS;
3726 }
3727
set_pcie_wowlan(struct mac_ax_adapter * adapter,enum mac_ax_wow_ctrl w_c)3728 u32 set_pcie_wowlan(struct mac_ax_adapter *adapter, enum mac_ax_wow_ctrl w_c)
3729 {
3730 u32 val32, ret;
3731 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3732
3733 if (w_c == MAC_AX_WOW_ENTER) {
3734 MAC_REG_W32(R_AX_SYS_SDIO_CTRL,
3735 MAC_REG_R32(R_AX_SYS_SDIO_CTRL) &
3736 ~B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
3737
3738 MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
3739 B_AX_WLOCK_1C_B6);
3740 MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
3741 B_AX_R_DIS_PRST);
3742 MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
3743 ~B_AX_WLOCK_1C_B6);
3744
3745 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
3746 val32 |= B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG;
3747 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
3748 } else if (w_c == MAC_AX_WOW_LEAVE) {
3749 MAC_REG_W32(R_AX_SYS_SDIO_CTRL,
3750 MAC_REG_R32(R_AX_SYS_SDIO_CTRL) |
3751 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
3752
3753 MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
3754 B_AX_WLOCK_1C_B6);
3755 MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
3756 ~B_AX_R_DIS_PRST);
3757 MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
3758 ~B_AX_WLOCK_1C_B6);
3759
3760 val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
3761 val32 &= (~B_AX_PCIE_PERST_KEEP_REG &
3762 ~B_AX_PCIE_TRAIN_KEEP_REG);
3763 MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
3764
3765 ret = _patch_pcie_l2_hci_ldo(adapter);
3766 if (ret != MACSUCCESS) {
3767 PLTFM_MSG_ERR("[ERR]patch pcie l2 hci ldo %d\n", ret);
3768 return ret;
3769 }
3770 } else {
3771 PLTFM_MSG_ERR("[ERR] Invalid WoWLAN input.\n");
3772 return MACFUNCINPUT;
3773 }
3774
3775 return MACSUCCESS;
3776 }
3777
set_pcie_l2_leave(struct mac_ax_adapter * adapter,u8 set)3778 u32 set_pcie_l2_leave(struct mac_ax_adapter *adapter, u8 set)
3779 {
3780 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3781
3782 if (set) {
3783 /* fix WoWLAN Power Consumption */
3784 MAC_REG_W32(R_AX_SYS_SDIO_CTRL,
3785 MAC_REG_R32(R_AX_SYS_SDIO_CTRL) &
3786 ~B_AX_PCIE_CALIB_EN_V1);
3787 }
3788
3789 return MACSUCCESS;
3790 }
3791
get_io_stat_pcie(struct mac_ax_adapter * adapter,struct mac_ax_io_stat * out_st)3792 u32 get_io_stat_pcie(struct mac_ax_adapter *adapter,
3793 struct mac_ax_io_stat *out_st)
3794 {
3795 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3796 u32 val32, to_addr;
3797
3798 val32 = MAC_REG_R32(R_AX_LBC_WATCHDOG);
3799 if (val32 & B_AX_LBC_FLAG) {
3800 adapter->sm.io_st = MAC_AX_IO_ST_HANG;
3801 to_addr = GET_FIELD(val32, B_AX_LBC_ADDR);
3802 PLTFM_MSG_ERR("[ERR]pcie io timeout addr 0x%X\n", to_addr);
3803 if (out_st) {
3804 out_st->to_flag = 1;
3805 out_st->io_st = adapter->sm.io_st;
3806 out_st->addr = to_addr;
3807 }
3808 MAC_REG_W32(R_AX_LBC_WATCHDOG, val32);
3809 } else if (out_st) {
3810 out_st->to_flag = 0;
3811 out_st->io_st = adapter->sm.io_st;
3812 out_st->addr = 0;
3813 }
3814
3815 return MACSUCCESS;
3816 }
3817
pcie_get_txagg_num(struct mac_ax_adapter * adapter,u8 band)3818 u32 pcie_get_txagg_num(struct mac_ax_adapter *adapter, u8 band)
3819 {
3820 return PCIE_DEFAULT_AGG_NUM;
3821 }
3822
pcie_autok_counter_avg(struct mac_ax_adapter * adapter)3823 u32 pcie_autok_counter_avg(struct mac_ax_adapter *adapter)
3824 {
3825 u8 bdr_ori, val8, l1_flag = 0;
3826 u16 tar16, hw_tar16, tmp16;
3827 u32 ret = MACSUCCESS;
3828 enum mac_ax_pcie_phy phy_rate = MAC_AX_PCIE_PHY_GEN1;
3829
3830 #if MAC_AX_FEATURE_HV
3831 if (adapter->env == HV_AX_FPGA)
3832 return MACSUCCESS;
3833 #endif
3834 if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
3835 return MACSUCCESS;
3836
3837 ret = dbi_r8_pcie(adapter, PCIE_PHY_RATE, &val8);
3838 if (ret != MACSUCCESS) {
3839 PLTFM_MSG_ERR("[ERR]dbi_r8_pcie 0x%x\n", PCIE_PHY_RATE);
3840 return ret;
3841 }
3842
3843 if ((val8 & (BIT1 | BIT0)) == 0x1) {
3844 phy_rate = MAC_AX_PCIE_PHY_GEN1;
3845 } else if ((val8 & (BIT1 | BIT0)) == 0x2) {
3846 phy_rate = MAC_AX_PCIE_PHY_GEN2;
3847 } else {
3848 PLTFM_MSG_ERR("[ERR]PCIe PHY rate not support\n");
3849 return MACHWNOSUP;
3850 }
3851
3852 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &hw_tar16);
3853 if (ret != MACSUCCESS) {
3854 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
3855 return ret;
3856 }
3857 PLTFM_MSG_TRACE("PCIe PHY %X: %X\n", RAC_CTRL_PPR_V1, hw_tar16);
3858
3859 if (!(hw_tar16 & BAC_AUTOK_EN)) {
3860 PLTFM_MSG_ERR("[ERR]PCIe autok is not enabled\n: %X", hw_tar16);
3861 return MACPROCERR;
3862 }
3863
3864 ret = mdio_r16_pcie(adapter, RAC_SET_PPR_V1, phy_rate, &tar16);
3865 if (ret != MACSUCCESS) {
3866 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_SET_PPR_V1);
3867 return ret;
3868 }
3869 PLTFM_MSG_TRACE("PCIe PHY %X: %X\n", RAC_SET_PPR_V1, tar16);
3870
3871 hw_tar16 = GET_FIELD(hw_tar16, BAC_AUTOK_HW_TAR);
3872 tar16 = GET_FIELD(tar16, BAC_AUTOK_TAR);
3873
3874 if (tar16 > hw_tar16)
3875 tmp16 = tar16 - hw_tar16;
3876 else
3877 tmp16 = hw_tar16 - tar16;
3878
3879 if (!(tmp16 < PCIE_AUTOK_MGN_2048)) {
3880 PLTFM_MSG_WARN("autok target is different from origin\n");
3881 return MACSUCCESS;
3882 }
3883
3884 adapter->pcie_info.autok_total += hw_tar16;
3885 adapter->pcie_info.autok_2s_cnt++;
3886
3887 if (adapter->pcie_info.autok_2s_cnt >= PCIE_AUTOK_UD_CNT) {
3888 /* Disable L1BD */
3889 ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &bdr_ori);
3890 if (ret != MACSUCCESS) {
3891 PLTFM_MSG_ERR("[ERR]dbi_r8_pcie 0x%X\n", PCIE_L1_CTRL);
3892 return ret;
3893 }
3894
3895 if (bdr_ori & PCIE_BIT_L1) {
3896 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL,
3897 bdr_ori & ~(PCIE_BIT_L1));
3898 if (ret != MACSUCCESS) {
3899 PLTFM_MSG_ERR("[ERR]dbi_w8_pcie 0x%X\n", PCIE_L1_CTRL);
3900 return ret;
3901 }
3902 l1_flag = 1;
3903 }
3904
3905 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &hw_tar16);
3906 if (ret != MACSUCCESS) {
3907 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
3908 goto end;
3909 }
3910
3911 hw_tar16 &= ~BAC_AUTOK_EN;
3912
3913 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, hw_tar16, phy_rate);
3914 if (ret != MACSUCCESS) {
3915 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
3916 goto end;
3917 }
3918
3919 ret = mdio_r16_pcie(adapter, RAC_SET_PPR_V1, phy_rate, &tar16);
3920 if (ret != MACSUCCESS) {
3921 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_SET_PPR_V1);
3922 goto end;
3923 }
3924
3925 tmp16 = adapter->pcie_info.autok_total / adapter->pcie_info.autok_2s_cnt;
3926 PLTFM_MSG_TRACE("Autok 30 times avg tar: %X\n", tmp16);
3927
3928 tar16 = SET_CLR_WOR2(tar16, tmp16, BAC_AUTOK_TAR_SH,
3929 BAC_AUTOK_TAR_MSK);
3930
3931 ret = mdio_w16_pcie(adapter, RAC_SET_PPR_V1, tar16, phy_rate);
3932 if (ret != MACSUCCESS) {
3933 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_SET_PPR_V1);
3934 goto end;
3935 }
3936
3937 ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &hw_tar16);
3938 if (ret != MACSUCCESS) {
3939 PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
3940 goto end;
3941 }
3942
3943 hw_tar16 |= BAC_AUTOK_EN;
3944
3945 ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, hw_tar16, phy_rate);
3946 if (ret != MACSUCCESS) {
3947 PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
3948 goto end;
3949 }
3950
3951 end:
3952 if (l1_flag == 1) {
3953 ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, bdr_ori);
3954 if (ret != MACSUCCESS) {
3955 PLTFM_MSG_ERR("[ERR]dbi_w8_pcie 0x%X\n", PCIE_L1_CTRL);
3956 return ret;
3957 }
3958 }
3959
3960 adapter->pcie_info.autok_total = 0;
3961 adapter->pcie_info.autok_2s_cnt = 0;
3962 }
3963
3964 return ret;
3965 }
3966
dbcc_hci_ctrl_pcie(struct mac_ax_adapter * adapter,struct mac_ax_dbcc_hci_ctrl * info)3967 u32 dbcc_hci_ctrl_pcie(struct mac_ax_adapter *adapter,
3968 struct mac_ax_dbcc_hci_ctrl *info)
3969 {
3970 struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
3971 struct mac_ax_dbcc_pcie_ctrl *ctrl;
3972 struct mac_ax_txdma_ch_map pause_txmap;
3973 struct mac_ax_rxdma_ch_map clr_rxch_map;
3974 enum mac_ax_band band;
3975 u32 ret, reg, val32;
3976 u8 ch, pause;
3977
3978 if (!info)
3979 return MACNPTR;
3980
3981 band = info->band;
3982 pause = info->pause;
3983 ctrl = &info->u.pcie_ctrl;
3984
3985 if (pause) {
3986 pause_txmap.ch0 = MAC_AX_PCIE_DISABLE;
3987 pause_txmap.ch1 = MAC_AX_PCIE_DISABLE;
3988 pause_txmap.ch2 = MAC_AX_PCIE_DISABLE;
3989 pause_txmap.ch3 = MAC_AX_PCIE_DISABLE;
3990 pause_txmap.ch4 = MAC_AX_PCIE_DISABLE;
3991 pause_txmap.ch5 = MAC_AX_PCIE_DISABLE;
3992 pause_txmap.ch6 = MAC_AX_PCIE_DISABLE;
3993 pause_txmap.ch7 = MAC_AX_PCIE_DISABLE;
3994 pause_txmap.ch8 = MAC_AX_PCIE_DISABLE;
3995 pause_txmap.ch9 = MAC_AX_PCIE_DISABLE;
3996 pause_txmap.ch10 = MAC_AX_PCIE_DISABLE;
3997 pause_txmap.ch11 = MAC_AX_PCIE_DISABLE;
3998 } else {
3999 pause_txmap.ch0 = MAC_AX_PCIE_ENABLE;
4000 pause_txmap.ch1 = MAC_AX_PCIE_ENABLE;
4001 pause_txmap.ch2 = MAC_AX_PCIE_ENABLE;
4002 pause_txmap.ch3 = MAC_AX_PCIE_ENABLE;
4003 pause_txmap.ch4 = MAC_AX_PCIE_ENABLE;
4004 pause_txmap.ch5 = MAC_AX_PCIE_ENABLE;
4005 pause_txmap.ch6 = MAC_AX_PCIE_ENABLE;
4006 pause_txmap.ch7 = MAC_AX_PCIE_ENABLE;
4007 pause_txmap.ch8 = MAC_AX_PCIE_ENABLE;
4008 pause_txmap.ch9 = MAC_AX_PCIE_ENABLE;
4009 pause_txmap.ch10 = MAC_AX_PCIE_ENABLE;
4010 pause_txmap.ch11 = MAC_AX_PCIE_ENABLE;
4011 }
4012 pause_txmap.ch12 = MAC_AX_PCIE_IGNORE;
4013
4014 ret = ops->ctrl_txdma_ch(adapter, &pause_txmap);
4015 if (ret != MACSUCCESS) {
4016 PLTFM_MSG_ERR("dbcc%d ctrl%d txdma ch pcie %d\n", band, pause, ret);
4017 return ret;
4018 }
4019
4020 if (!pause)
4021 return MACSUCCESS;
4022
4023 pause_txmap.ch0 = MAC_AX_PCIE_ENABLE;
4024 pause_txmap.ch1 = MAC_AX_PCIE_ENABLE;
4025 pause_txmap.ch2 = MAC_AX_PCIE_ENABLE;
4026 pause_txmap.ch3 = MAC_AX_PCIE_ENABLE;
4027 pause_txmap.ch4 = MAC_AX_PCIE_ENABLE;
4028 pause_txmap.ch5 = MAC_AX_PCIE_ENABLE;
4029 pause_txmap.ch6 = MAC_AX_PCIE_ENABLE;
4030 pause_txmap.ch7 = MAC_AX_PCIE_ENABLE;
4031 pause_txmap.ch8 = MAC_AX_PCIE_ENABLE;
4032 pause_txmap.ch9 = MAC_AX_PCIE_ENABLE;
4033 pause_txmap.ch10 = MAC_AX_PCIE_ENABLE;
4034 pause_txmap.ch11 = MAC_AX_PCIE_ENABLE;
4035 pause_txmap.ch12 = MAC_AX_PCIE_IGNORE;
4036 ret = ops->poll_txdma_ch_idle(adapter, &pause_txmap);
4037 if (ret != MACSUCCESS) {
4038 PLTFM_MSG_ERR("dbcc%d poll txdma ch pcie %d\n", band, ret);
4039 return ret;
4040 }
4041
4042 for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_CH_NUM; ch++) {
4043 if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
4044 ((ch >= MAC_AX_DMA_ACH4 && ch <= MAC_AX_DMA_ACH7) ||
4045 (ch >= MAC_AX_DMA_B1MG && ch <= MAC_AX_DMA_B1HI))) {
4046 ctrl->out_host_idx_l[ch] = BD_IDX_INVALID;
4047 ctrl->out_hw_idx_l[ch] = BD_IDX_INVALID;
4048 continue;
4049 }
4050
4051 ret = get_txbd_idx_reg(adapter, ch, ®);
4052 if (ret != MACSUCCESS) {
4053 PLTFM_MSG_ERR("get ch%d idx reg pcie %d\n", ch, ret);
4054 return ret;
4055 }
4056
4057 val32 = MAC_REG_R32(reg);
4058 ctrl->out_host_idx_l[ch] = GET_FIELD(val32, B_AX_ACH0_HOST_IDX);
4059 ctrl->out_hw_idx_l[ch] = GET_FIELD(val32, B_AX_ACH0_HW_IDX);
4060 }
4061
4062 clr_rxch_map.rxq = MAC_AX_PCIE_IGNORE;
4063 clr_rxch_map.rpq = MAC_AX_PCIE_IGNORE;
4064 ret = clr_idx_ch_pcie(adapter, &ctrl->clr_txch_map, &clr_rxch_map);
4065 if (ret != MACSUCCESS) {
4066 PLTFM_MSG_ERR("dbcc%d clear ch idx pcie %d\n", band, ret);
4067 return ret;
4068 }
4069
4070 return MACSUCCESS;
4071 }
4072 #endif /* #if MAC_AX_PCIE_SUPPORT */
4073
4074