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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #ifdef MSOS_TYPE_LINUX_KERNEL
108 #include <linux/string.h>
109 #else
110 #include <string.h>
111 #include <stdio.h>
112 #include <math.h>
113 #endif
114 #include "MsCommon.h"
115 #include "MsVersion.h"
116 #include "MsOS.h"
117
118 // Internal Definition
119 //#include "regCHIP.h"
120 //#include "regAVD.h"
121 //#include "mapi_tuner.h"
122 #include "drvSYS.h"
123 #include "drvDMD_VD_MBX.h"
124 #include "drvDMD_INTERN_DVBT2_v2.h"
125 #include "halDMD_INTERN_DVBT2.h"
126 #include "halDMD_INTERN_common.h"
127 #include "drvSAR.h" // for Utopia2
128 #include "utopia.h"
129 #include "utopia_dapi.h"
130 #include "../../utopia_core/utopia_driver_id.h"
131 #include "ULog.h"
132 //-------------------------------------------------------------------------------------------------
133 // Driver Compiler Options
134 //-------------------------------------------------------------------------------------------------
135
136
137 //-------------------------------------------------------------------------------------------------
138 // Local Defines
139 //-------------------------------------------------------------------------------------------------
140
141
142 //-------------------------------------------------------------------------------------------------
143 // Local Structurs
144 //-------------------------------------------------------------------------------------------------
145
146
147 //-------------------------------------------------------------------------------------------------
148 // Local Variables
149 //-------------------------------------------------------------------------------------------------
150 MS_BOOL bIsDVBT2 = FALSE; // Usage for STR
151
152
153 //-------------------------------------------------------------------------------------------------
154 // Local Functions
155 //-------------------------------------------------------------------------------------------------
156 typedef MS_BOOL (*IOCTL_DVBT2_Init)(DMD_DVBT2_InitData_Transform *pDMD_DVBT2_InitData, MS_U32 u32InitDataLen);
157 typedef MS_BOOL (*IOCTL_DVBT2_Exit)(void);
158 typedef MS_BOOL (*IOCTL_DVBT2_SetDbgLevel)(DMD_T2_DbgLv u8DbgLevel);
159 typedef DMD_DVBT2_Info* (*IOCTL_DVBT2_GetInfo)(DMD_DVBT2_INFO_TYPE eInfoType);
160 typedef MS_BOOL (*IOCTL_DVBT2_GetLibVer)(const MSIF_Version **ppVersion);
161 typedef MS_BOOL (*IOCTL_DVBT2_GetFWVer)(MS_U16 *ver);
162 typedef MS_BOOL (*IOCTL_DVBT2_GetReg)(MS_U16 u16Addr, MS_U8 *pu8Data);
163 typedef MS_BOOL (*IOCTL_DVBT2_SetReg)(MS_U16 u16Addr, MS_U8 u8Data);
164 typedef MS_BOOL (*IOCTL_DVBT2_SetSerialControl)(MS_BOOL bEnable);
165 typedef MS_BOOL (*IOCTL_DVBT2_SetReset)(void);
166 typedef MS_BOOL (*IOCTL_DVBT2_SetConfig)(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8PlpID);
167 typedef MS_BOOL (*IOCTL_DVBT2_SetActive)(MS_BOOL bEnable);
168 typedef MS_BOOL (*IOCTL_DVBT2_GetLock)(DMD_DVBT2_GETLOCK_TYPE eType, DMD_T2_LOCK_STATUS *eLockStatus);
169 //typedef MS_BOOL (*IOCTL_DVBT2_GetSignalStrength)(MS_U16 *u16Strength);
170 //typedef MS_BOOL (*IOCTL_DVBT2_GetSignalStrengthWithRFPower)(MS_U16 *u16Strength, float fRFPowerDbm);
171 //typedef MS_BOOL (*IOCTL_DVBT2_GetSignalQuality)(MS_U16 *u16Quality);
172 //typedef MS_BOOL (*IOCTL_DVBT2_GetSignalQualityWithRFPower)(MS_U16 *u16Quality, float fRFPowerDbm);
173 typedef MS_BOOL (*IOCTL_DVBT2_GetSNR)(MS_U16 *u16_snr100, MS_U8 *snr_cali, MS_U8 *u8_gi);
174 typedef MS_BOOL (*IOCTL_DVBT2_GetPostLdpcBer)(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType);
175 typedef MS_BOOL (*IOCTL_DVBT2_GetPreLdpcBer)(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType);
176 typedef MS_BOOL (*IOCTL_DVBT2_GetPacketErr)(MS_U16 *pktErr);
177 typedef MS_BOOL (*IOCTL_DVBT2_GetL1Info)(MS_U16 *u16Info, DMD_DVBT2_SIGNAL_INFO eSignalType);
178 typedef MS_BOOL (*IOCTL_DVBT2_GetFreqOffset)(MS_U32 *CfoTd_reg, MS_U32 *CfoFd_reg, MS_U32 *Icfo_reg, MS_U8 *fft_reg);
179 //typedef MS_BOOL (*IOCTL_DVBT2_NORDIG_SSI_Table_Write)(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value);
180 //typedef MS_BOOL (*IOCTL_DVBT2_NORDIG_SSI_Table_Read)(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value);
181 typedef MS_U32 (*IOCTL_DVBT2_SetPowerState)(EN_POWER_MODE u16PowerState);
182 typedef MS_BOOL (*IOCTL_DVBT2_GetPlpBitMap)(MS_U8* u8PlpBitMap);
183 typedef MS_BOOL (*IOCTL_DVBT2_GetPlpGroupID)(MS_U8 u8PlpID, MS_U8* u8GroupID);
184 typedef MS_BOOL (*IOCTL_DVBT2_SetPlpID)(MS_U8 u8PlpID, MS_U8 u8GroupID);
185
186
187 typedef struct DVBT2_INSTANT_PRIVATE
188 {
189 IOCTL_DVBT2_Init fpDVBT2_Init ;
190 IOCTL_DVBT2_Exit fpDVBT2_Exit;
191 IOCTL_DVBT2_SetDbgLevel fpDVBT2_SetDbgLevel;
192 IOCTL_DVBT2_GetInfo fpDVBT2_GetInfo;
193 IOCTL_DVBT2_GetLibVer fpDVBT2_GetLibVer;
194 IOCTL_DVBT2_GetFWVer fpDVBT2_GetFWVer;
195 IOCTL_DVBT2_GetReg fpDVBT2_GetReg;
196 IOCTL_DVBT2_SetReg fpDVBT2_SetReg;
197 IOCTL_DVBT2_SetSerialControl fpDVBT2_SetSerialControl;
198 IOCTL_DVBT2_SetReset fpDVBT2_SetReset;
199 IOCTL_DVBT2_SetConfig fpDVBT2_SetConfig;
200 IOCTL_DVBT2_SetActive fpDVBT2_SetActive;
201 IOCTL_DVBT2_GetLock fpDVBT2_GetLock;
202 // IOCTL_DVBT2_GetSignalStrength fpDVBT2_GetSignalStrength;
203 // IOCTL_DVBT2_GetSignalStrengthWithRFPower fpDVBT2_GetSignalStrengthWithRFPower;
204 // IOCTL_DVBT2_GetSignalQuality fpDVBT2_GetSignalQuality;
205 // IOCTL_DVBT2_GetSignalQualityWithRFPower fpDVBT2_GetSignalQualityWithRFPower ;
206 IOCTL_DVBT2_GetSNR fpDVBT2_GetSNR;
207 IOCTL_DVBT2_GetPostLdpcBer fpDVBT2_GetPostLdpcBer;
208 IOCTL_DVBT2_GetPreLdpcBer fpDVBT2_GetPreLdpcBer;
209 IOCTL_DVBT2_GetPacketErr fpDVBT2_GetPacketErr;
210 IOCTL_DVBT2_GetL1Info fpDVBT2_GetL1Info;
211 IOCTL_DVBT2_GetFreqOffset fpDVBT2_GetFreqOffset;
212 // IOCTL_DVBT2_NORDIG_SSI_Table_Write fpDVBT2_NORDIG_SSI_Table_Write;
213 // IOCTL_DVBT2_NORDIG_SSI_Table_Read fpDVBT2_NORDIG_SSI_Table_Read;
214 IOCTL_DVBT2_SetPowerState fpDVBT2_SetPowerState;
215 IOCTL_DVBT2_GetPlpBitMap fpDVBT2_GetPlpBitMap;
216 IOCTL_DVBT2_GetPlpGroupID fpDVBT2_GetPlpGroupID;
217 IOCTL_DVBT2_SetPlpID fpDVBT2_SetPlpID;
218 } DVBT2_INSTANT_PRIVATE;
219
220
221 //-------------------------------------------------------------------------------------------------
222 // Global Variables
223 //-------------------------------------------------------------------------------------------------
224 #define DMD_LOCK() \
225 do{ \
226 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
227 if (_s32DMD_DVBT2_Mutex == -1) return FALSE; \
228 if (_u8DMDDbgLevel == DMD_T2_DBGLV_DEBUG) printf("%s lock mutex\n", __FUNCTION__);\
229 MsOS_ObtainMutex(_s32DMD_DVBT2_Mutex, MSOS_WAIT_FOREVER);\
230 }while(0)
231
232 #define DMD_UNLOCK() \
233 do{ \
234 MsOS_ReleaseMutex(_s32DMD_DVBT2_Mutex);\
235 if (_u8DMDDbgLevel == DMD_T2_DBGLV_DEBUG) printf("%s unlock mutex\n", __FUNCTION__); \
236 }while(0)
237
238 //-------------------------------------------------------------------------------------------------
239 // Local Variables
240 //-------------------------------------------------------------------------------------------------
241 #if 1
242 static MSIF_Version _drv_dmd_dvbt2_intern_version = {
243 .MW = { DMD_DVBT2_INTERN_VER, },
244 };
245 #else
246 static MSIF_Version _drv_dmd_dvbt_intern_version;
247 #endif
248
249 static DMD_DVBT2_InitData_Transform _sDMD_DVBT2_InitData;
250 static DMD_T2_DbgLv _u8DMDDbgLevel=DMD_T2_DBGLV_NONE;
251 static MS_S32 _s32DMD_DVBT2_Mutex=-1;
252 static DMD_DVBT2_Info sDMD_DVBT2_Info;
253 //static MS_U16 u16DMD_DVBT2_P1_Timeout = 600, u16DMD_DVBT2_FEC_Timeout=6000;
254 static MS_U16 u16DMD_DVBT2_P1_Timeout = 1000, u16DMD_DVBT2_FEC_Timeout=6000;
255 static MS_U32 u32DMD_DVBT2_IfFrequency = 5000L, u32DMD_DVBT2_FsFrequency = 24000L;
256 //static MS_U8 u8DMD_DVBT2_IQSwap=0;
257 static DMD_DVBT2_RF_CHANNEL_BANDWIDTH eDMD_DVBT2_BandWidth=E_DMD_T2_RF_BAND_8MHz;
258 MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
259 MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
260 MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
261 MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
262 MS_U32 u32DMD_DVBT2_FW_START_ADDR;
263 //-------------------------------------------------------------------------------------------------
264 // Debug Functions
265 //-------------------------------------------------------------------------------------------------
266 #ifdef MS_DEBUG
267 #define DMD_DBG(x) (x)
268 #else
269 #define DMD_DBG(x) //(x)
270 #endif
271
272
273 //-------------------------------------------------------------------------------------------------
274 // Global Functions
275 //-------------------------------------------------------------------------------------------------
DMD_DVBT2_Init(DMD_DVBT2_InitData_Transform * pDMD_DVBT2_InitData,MS_U32 u32InitDataLen)276 MS_BOOL DMD_DVBT2_Init(DMD_DVBT2_InitData_Transform *pDMD_DVBT2_InitData, MS_U32 u32InitDataLen)
277 {
278 char pDMD_DVBT2_MutexString[16];
279 MS_U8 u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
280 MS_BOOL bRFAGCTristateEnable = 1;
281 MS_BOOL bIFAGCTristateEnable = 0;
282
283 bIsDVBT2 = TRUE;
284
285 if (_s32DMD_DVBT2_Mutex != -1)
286 {
287 DMD_DBG(printf("MDrv_DMD_DVBT2_Init more than once\n"));
288 return FALSE;
289 }
290
291 if (NULL == strncpy(pDMD_DVBT2_MutexString,"Mutex DMD DVBT2",16))
292 {
293 DMD_DBG(printf("MDrv_DMD_DVBT2_Init strcpy Fail\n"));
294 return FALSE;
295 }
296 _s32DMD_DVBT2_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBT2_MutexString, MSOS_PROCESS_SHARED);
297 if (_s32DMD_DVBT2_Mutex == -1)
298 {
299 DMD_DBG(printf("MDrv_DMD_DVBT2_Init Create Mutex Fail\n"));
300 return FALSE;
301 }
302 //_u8DMDDbgLevel = DMD_DBGLV_DEBUG;
303 #ifdef MS_DEBUG
304 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_INFO)
305 {
306 printf("MDrv_DMD_DVBT2_Init\n");
307 }
308 #endif
309
310 if ( sizeof(_sDMD_DVBT2_InitData) == u32InitDataLen)
311 {
312 memcpy(&_sDMD_DVBT2_InitData, pDMD_DVBT2_InitData, u32InitDataLen);
313 }
314 else
315 {
316 DMD_DBG(printf("MDrv_DMD_DVBT2_Init input data structure incorrect\n"));
317 return FALSE;
318 }
319
320 if (_sDMD_DVBT2_InitData.u8SarChannel != 0xFF)
321 {
322 // MDrv_SAR_Adc_Config(_sDMD_DVBT2_InitData.u8SarChannel, TRUE);
323 }
324
325 DMD_LOCK();
326 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBT2);
327 HAL_DMD_RegInit();
328
329 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
330 {
331 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=2)
332 {
333 bRFAGCTristateEnable = (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[3] & (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
334 bIFAGCTristateEnable = (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[3] & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
335 }
336 else
337 {
338 bRFAGCTristateEnable = 1;
339 bIFAGCTristateEnable = 0;
340 }
341 }
342 else
343 {
344 bRFAGCTristateEnable = 1;
345 bIFAGCTristateEnable = 0;
346 }
347
348 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
349 {
350 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=3)
351 {
352 u32DMD_DVBT2_IfFrequency = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[4]; // IF frequency
353 u32DMD_DVBT2_IfFrequency = (u32DMD_DVBT2_IfFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[5]; // IF frequency
354 u32DMD_DVBT2_IfFrequency = (u32DMD_DVBT2_IfFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[6]; // IF frequency
355 u32DMD_DVBT2_IfFrequency = (u32DMD_DVBT2_IfFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[7]; // IF frequency
356 u32DMD_DVBT2_FsFrequency = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[8]; // FS frequency
357 u32DMD_DVBT2_FsFrequency = (u32DMD_DVBT2_FsFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[9]; // FS frequency
358 u32DMD_DVBT2_FsFrequency = (u32DMD_DVBT2_FsFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[10]; // FS frequency
359 u32DMD_DVBT2_FsFrequency = (u32DMD_DVBT2_FsFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[11]; // FS frequency
360 //u8DMD_DVBT2_IQSwap = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[12]; // IQ Swap
361
362 u8ADCIQMode = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[13]; // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
363 u8PadSel = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[14]; // u8PadSel : 0=Normal, 1=analog pad
364 bPGAEnable = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[15]; // bPGAEnable : 0=disable, 1=enable
365 u8PGAGain = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[16]; // u8PGAGain : default 5
366 }
367 else
368 {
369
370 }
371 }
372 else
373 {
374
375 }
376 #ifdef MS_DEBUG
377 printf("u32DMD_DVBT2_IfFrequency %ld\n",u32DMD_DVBT2_IfFrequency);
378 printf("u32DMD_DVBT2_FsFrequency %ld\n",u32DMD_DVBT2_FsFrequency);
379 #endif
380
381 u16DMD_DVBT2_P1_Timeout = 1000; //600;
382 u16DMD_DVBT2_FEC_Timeout = 6000;
383 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
384 {
385 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=4)
386 {
387 u16DMD_DVBT2_P1_Timeout = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[17]; // P1 timeout in ms
388 u16DMD_DVBT2_P1_Timeout = (u16DMD_DVBT2_P1_Timeout<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[18];
389 if (u16DMD_DVBT2_P1_Timeout < 600) u16DMD_DVBT2_P1_Timeout=600;
390 //printf("u16DMD_DVBT2_P1_Timeout %d\n",u16DMD_DVBT2_P1_Timeout);
391
392 u16DMD_DVBT2_FEC_Timeout = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[19]; // FEC timeout in ms
393 u16DMD_DVBT2_FEC_Timeout = (u16DMD_DVBT2_FEC_Timeout<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[20];
394 if (u16DMD_DVBT2_FEC_Timeout < 6000) u16DMD_DVBT2_FEC_Timeout=6000;
395 //printf("u16DMD_DVBT2_FEC_Timeout %d\n",u16DMD_DVBT2_FEC_Timeout);
396 }
397 else
398 {
399 }
400 }
401 else
402 {
403 }
404
405 //u32DMD_DVBT2_DRAM_START_ADDR = _sDMD_DVBT2_InitData.u32DramStartAddr;
406 u32DMD_DVBT2_EQ_START_ADDR = _sDMD_DVBT2_InitData.u32EqStartAddr; //0x14B23000;
407 u32DMD_DVBT2_TDI_START_ADDR = _sDMD_DVBT2_InitData.u32TdiStartAddr; //0x14610000;
408 u32DMD_DVBT2_DJB_START_ADDR = _sDMD_DVBT2_InitData.u32DjbStartAddr; //0x14BB9000;
409 u32DMD_DVBT2_FW_START_ADDR = _sDMD_DVBT2_InitData.u32FwStartAddr; //0x14608000;
410
411 if (bIFAGCTristateEnable)
412 {
413 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
414 }
415 else
416 {
417 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
418 }
419
420 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitExt != NULL)
421 {
422 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitExt[0]>=1)
423 {
424 INTERN_DVBT2_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, _sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitExt, _sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitSize);
425 }
426 else
427 {
428 printf("u8DMD_DVBT2_DSPRegInitExt Error\n");
429 }
430 }
431 else
432 {
433 INTERN_DVBT2_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, NULL, 0);
434 }
435
436 INTERN_DVBT2_Version(&sDMD_DVBT2_Info.u16Version);
437 DMD_UNLOCK();
438 #ifdef MS_DEBUG
439 printf("firmware version: %x\n",sDMD_DVBT2_Info.u16Version);
440 #endif
441 return TRUE;
442 }
443
444
DMD_DVBT2_Exit(void)445 MS_BOOL DMD_DVBT2_Exit(void)
446 {
447 MS_BOOL bRet;
448
449 #ifdef MS_DEBUG
450 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
451 {
452 printf("MDrv_DMD_DVBT2_Exit\n");
453 }
454 #endif
455 bIsDVBT2 = FALSE;
456 DMD_LOCK();
457 bRet = INTERN_DVBT2_Exit();
458 DMD_UNLOCK();
459 MsOS_DeleteMutex(_s32DMD_DVBT2_Mutex);
460 _s32DMD_DVBT2_Mutex= -1;
461 return bRet;
462 }
463
DMD_DVBT2_SetDbgLevel(DMD_T2_DbgLv u8DbgLevel)464 MS_BOOL DMD_DVBT2_SetDbgLevel(DMD_T2_DbgLv u8DbgLevel)
465 {
466 DMD_LOCK();
467 _u8DMDDbgLevel = u8DbgLevel;
468 DMD_UNLOCK();
469 return TRUE;
470 }
471
DMD_DVBT2_GetInfo(DMD_DVBT2_INFO_TYPE eInfoType)472 DMD_DVBT2_Info* DMD_DVBT2_GetInfo(DMD_DVBT2_INFO_TYPE eInfoType)
473 {
474 DMD_LOCK();
475 switch (eInfoType)
476 {
477 case E_DMD_DVBT2_MODULATION_INFO:
478 INTERN_DVBT2_Show_Modulation_info();
479 break;
480 case E_DMD_DVBT2_DEMOD_INFO:
481 INTERN_DVBT2_Show_Demod_Info();
482 break;
483 case E_DMD_DVBT2_LOCK_INFO:
484 INTERN_DVBT2_Show_Lock_Info();
485 break;
486 case E_DMD_DVBT2_PRESFO_INFO:
487 INTERN_DVBT2_Show_PRESFO_Info();
488 break;
489 case E_DMD_DVBT2_LOCK_TIME_INFO:
490 INTERN_DVBT2_Show_Lock_Time_Info();
491 break;
492 case E_DMD_DVBT2_BER_INFO:
493 INTERN_DVBT2_Show_BER_Info();
494 break;
495 case E_DMD_DVBT2_AGC_INFO:
496 INTERN_DVBT2_Show_AGC_Info();
497 break;
498 default:
499 #ifdef MS_DEBUG
500 printf("MDrv_DMD_DVBT2_GetInfo %d Error\n", eInfoType);
501 #endif
502 break;
503 }
504 DMD_UNLOCK();
505 return &sDMD_DVBT2_Info;
506 }
507
DMD_DVBT2_GetLibVer(const MSIF_Version ** ppVersion)508 MS_BOOL DMD_DVBT2_GetLibVer(const MSIF_Version **ppVersion)
509 {
510 DMD_LOCK();
511 if (!ppVersion)
512 {
513 return FALSE;
514 }
515
516 *ppVersion = &_drv_dmd_dvbt2_intern_version;
517 DMD_UNLOCK();
518 return TRUE;
519 }
520
DMD_DVBT2_GetFWVer(MS_U16 * ver)521 MS_BOOL DMD_DVBT2_GetFWVer(MS_U16 *ver)
522 {
523
524 MS_BOOL bRet;
525
526 DMD_LOCK();
527
528 bRet = INTERN_DVBT2_Version(ver);
529 //printf("MDrv_DMD_DVBT2_GetFWVer %x\n",*ver);
530 DMD_UNLOCK();
531
532 return bRet;
533
534 }
535
DMD_DVBT2_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)536 MS_BOOL DMD_DVBT2_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
537 {
538 MS_BOOL bRet;
539
540 DMD_LOCK();
541 bRet=MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, pu8Data);
542 DMD_UNLOCK();
543
544 #ifdef MS_DEBUG
545 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
546 {
547 printf("MDrv_DMD_DVBT2_GetReg %x %x\n", u16Addr, *pu8Data);
548 }
549 #endif
550
551 return bRet;
552 }
553
DMD_DVBT2_SetReg(MS_U16 u16Addr,MS_U8 u8Data)554 MS_BOOL DMD_DVBT2_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
555 {
556 MS_BOOL bRet;
557
558 #ifdef MS_DEBUG
559 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
560 {
561 printf("MDrv_DMD_DVBT2_SetReg %x %x\n", u16Addr, u8Data);
562 }
563 #endif
564
565 DMD_LOCK();
566 bRet=MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, u8Data);
567 DMD_UNLOCK();
568 return bRet;
569 }
570
DMD_DVBT2_SetSerialControl(MS_BOOL bEnable)571 MS_BOOL DMD_DVBT2_SetSerialControl(MS_BOOL bEnable)
572 {
573 MS_BOOL bRet;
574 MS_U8 u8TSClk;
575
576 #ifdef MS_DEBUG
577 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
578 {
579 printf("MDrv_DMD_DVBT2_SetSerialControl %x\n", bEnable);
580 }
581 #endif
582
583 DMD_LOCK();
584 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
585 {
586 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=1)
587 {
588 u8TSClk = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[2]; // TS_CLK
589 }
590 else
591 {
592 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
593 }
594 }
595 else
596 {
597 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
598 }
599 bRet=INTERN_DVBT2_Serial_Control(bEnable, u8TSClk);
600 DMD_UNLOCK();
601 return bRet;
602 }
603
DMD_DVBT2_SetReset(void)604 MS_BOOL DMD_DVBT2_SetReset(void)
605 {
606 MS_BOOL bRet;
607
608 DMD_LOCK();
609 bRet = INTERN_DVBT2_SoftReset();
610 DMD_UNLOCK();
611
612 return bRet;
613 }
614
DMD_DVBT2_SetConfig(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8PlpID)615 MS_BOOL DMD_DVBT2_SetConfig(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8PlpID)
616 {
617 //return MDrv_DMD_DVBT2_SetConfigHPLPSetIF(BW, bSerialTS, bPalBG, 0, u32DMD_DVBT2_IfFrequency, u32DMD_DVBT2_FsFrequency, u8DMD_DVBT2_IQSwap);
618 MS_BOOL bRet;
619 MS_U8 u8TSClk;
620
621 #ifdef MS_DEBUG
622 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
623 {
624 printf("MDrv_DMD_DVBT2_SetConfig %d %d %d\n", BW, bSerialTS, u8PlpID);
625 }
626 #endif
627
628 DMD_LOCK();
629 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
630 {
631 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=1)
632 {
633 u8TSClk = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[2]; // TS_CLK
634 }
635 else
636 {
637 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
638 }
639 }
640 else
641 {
642 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
643 }
644
645 bRet=INTERN_DVBT2_Config(BW, bSerialTS, u8TSClk, u32DMD_DVBT2_IfFrequency, u8PlpID);
646 eDMD_DVBT2_BandWidth=BW;
647 DMD_UNLOCK();
648 return bRet;
649 }
650
651
DMD_DVBT2_SetActive(MS_BOOL bEnable)652 MS_BOOL DMD_DVBT2_SetActive(MS_BOOL bEnable)
653 {
654 MS_BOOL bRet;
655
656 #ifdef MS_DEBUG
657 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
658 {
659 printf("MDrv_DMD_DVBT2_SetActive %d\n", bEnable);
660 }
661 #endif
662
663 DMD_LOCK();
664 bRet=INTERN_DVBT2_Active(bEnable);
665 DMD_UNLOCK();
666 return bRet;
667 }
668
DMD_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eType,DMD_T2_LOCK_STATUS * eLockStatus)669 MS_BOOL DMD_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eType, DMD_T2_LOCK_STATUS *eLockStatus)
670 {
671 MS_BOOL bRet=TRUE;
672 DMD_LOCK();
673
674 if ( eType == E_DMD_DVBT2_GETLOCK ) // for channel scan
675 {
676 *eLockStatus = INTERN_DVBT2_Lock(u16DMD_DVBT2_P1_Timeout, u16DMD_DVBT2_FEC_Timeout);
677 }
678 else
679 {
680 if (INTERN_DVBT2_GetLock(eType) == TRUE)
681 {
682 *eLockStatus = E_DMD_T2_LOCK;
683 }
684 else
685 {
686 *eLockStatus = E_DMD_T2_UNLOCK;
687 }
688 }
689 DMD_UNLOCK();
690
691 #ifdef MS_DEBUG
692 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
693 {
694 printf("MDrv_DMD_DVBT2_GetLock %d\n", bRet);
695 }
696 #endif
697 return bRet;
698 }
699
700 /* implement in drv layer
701 MS_BOOL MDrv_DMD_DVBT2_GetSignalStrength(MS_U16 *u16Strength)
702 {
703 return MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(u16Strength, 200.0f);
704 }
705 */
706
707 #if 0
708 MS_BOOL DMD_DVBT2_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm)
709 {
710 MS_U8 u8SarValue;
711 MS_BOOL bRet;
712
713 DMD_LOCK();
714 if (_sDMD_DVBT2_InitData.u8SarChannel != 0xFF)
715 {
716 u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBT2_InitData.u8SarChannel);
717 }
718 else
719 {
720 u8SarValue=0xFF;
721 }
722 bRet=INTERN_DVBT2_GetSignalStrength(u16Strength, (const DMD_DVBT2_InitData *)(&_sDMD_DVBT2_InitData), u8SarValue, fRFPowerDbm);
723 DMD_UNLOCK();
724
725 #ifdef MS_DEBUG
726 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
727 {
728 printf("MDrv_DMD_DVBT2_GetSignalStrength %d\n", *u16Strength);
729 }
730 #endif
731 return bRet;
732 }
733 #endif
734
735 /* implement in drv layer
736 MS_BOOL DMD_DVBT2_GetSignalQuality(MS_U16 *u16Quality)
737 {
738 return MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(u16Quality, 200.0f);
739 }
740 */
741
742 #if 0
743 MS_BOOL DMD_DVBT2_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm)
744 {
745 MS_U8 u8SarValue=0;
746 MS_BOOL bRet=0;
747
748 DMD_LOCK();
749 if (_sDMD_DVBT2_InitData.u8SarChannel != 0xFF)
750 {
751 u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBT2_InitData.u8SarChannel);
752 }
753 else
754 {
755 u8SarValue=0xFF;
756 }
757 bRet=INTERN_DVBT2_GetSignalQuality(u16Quality, (const DMD_DVBT2_InitData *)(&_sDMD_DVBT2_InitData), u8SarValue, fRFPowerDbm);
758 DMD_UNLOCK();
759
760 #ifdef MS_DEBUG
761 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
762 {
763 printf("MDrv_DMD_DVBT2_GetSignalQuality %d\n", *u16Quality);
764 }
765 #endif
766 return bRet;
767 }
768 #endif
769
770 #if 0
771 MS_BOOL DMD_DVBT2_GetSNR(float *fSNR)
772 {
773 DMD_LOCK();
774 *fSNR=INTERN_DVBT2_GetSNR();
775 DMD_UNLOCK();
776
777 return TRUE;
778 }
779
780 MS_BOOL DMD_DVBT2_GetPostLdpcBer(float *ber)
781 {
782 MS_BOOL bRet;
783
784 DMD_LOCK();
785 bRet=INTERN_DVBT2_GetPostLdpcBer(ber);
786 DMD_UNLOCK();
787
788 return bRet;
789 }
790 #else
DMD_DVBT2_GetSNR(MS_U16 * u16_snr100,MS_U8 * snr_cali,MS_U8 * u8_gi)791 MS_BOOL DMD_DVBT2_GetSNR (MS_U16 *u16_snr100, MS_U8 *snr_cali, MS_U8 *u8_gi)
792 {
793 MS_BOOL bRet;
794
795 DMD_LOCK();
796 bRet=INTERN_DVBT2_GetSNR (u16_snr100, snr_cali, u8_gi);
797 DMD_UNLOCK();
798
799 return TRUE;
800 }
801
DMD_DVBT2_GetPostLdpcBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg,MS_U16 * FecType)802 MS_BOOL DMD_DVBT2_GetPostLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType)
803 {
804 MS_BOOL bRet;
805
806 DMD_LOCK();
807 bRet=INTERN_DVBT2_GetPostLdpcBer(BitErr_reg, BitErrPeriod_reg, FecType);
808 DMD_UNLOCK();
809
810 return bRet;
811 }
812 #endif
813
DMD_DVBT2_GetPreLdpcBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg,MS_U16 * FecType)814 MS_BOOL DMD_DVBT2_GetPreLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType)
815 {
816 MS_BOOL bRet;
817
818 DMD_LOCK();
819 bRet=INTERN_DVBT2_GetPreLdpcBer(BitErr_reg, BitErrPeriod_reg, FecType);
820 DMD_UNLOCK();
821
822 return bRet;
823 }
824
DMD_DVBT2_GetPacketErr(MS_U16 * pktErr)825 MS_BOOL DMD_DVBT2_GetPacketErr(MS_U16 *pktErr)
826 {
827 MS_BOOL bRet;
828 // float fBER;
829
830 DMD_LOCK();
831 // INTERN_DVBT2_GetPostLdpcBer(&fBER);
832 bRet=INTERN_DVBT2_GetPacketErr(pktErr);
833 // if ((*pktErr ==1) && (fBER<= 0.000001)) // for no signal case, from Oga
834 // {
835 // *pktErr = 0x3FF;
836 // }
837 #ifdef MS_DEBUG
838 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
839 {
840 printf("MDrv_DMD_DVBT2_GetPacketErr %d\n", *pktErr);
841 }
842 #endif
843 DMD_UNLOCK();
844
845 return bRet;
846 }
847
848
849
DMD_DVBT2_GetL1Info(MS_U16 * u16Info,DMD_DVBT2_SIGNAL_INFO eSignalType)850 MS_BOOL DMD_DVBT2_GetL1Info(MS_U16 *u16Info, DMD_DVBT2_SIGNAL_INFO eSignalType)
851 {
852 MS_BOOL bRet;
853
854 DMD_LOCK();
855 bRet=INTERN_DVBT2_Get_L1_Parameter(u16Info, eSignalType );
856 DMD_UNLOCK();
857
858 return bRet;
859 }
860
DMD_DVBT2_GetFreqOffset(MS_U32 * CfoTd_reg,MS_U32 * CfoFd_reg,MS_U32 * Icfo_reg,MS_U8 * fft_reg)861 MS_BOOL DMD_DVBT2_GetFreqOffset(MS_U32 *CfoTd_reg, MS_U32 *CfoFd_reg, MS_U32 *Icfo_reg, MS_U8 *fft_reg)
862 {
863 MS_BOOL bRet;
864
865 DMD_LOCK();
866 bRet=INTERN_DVBT2_Get_FreqOffset(CfoTd_reg, CfoFd_reg, Icfo_reg, fft_reg);
867 DMD_UNLOCK();
868
869 return bRet;
870 }
871
872
873 #if 0
874 MS_BOOL DMD_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
875 {
876 return INTERN_DVBT2_NORDIG_SSI_Table_Write(constel, code_rate, write_value);
877 }
878
879 MS_BOOL DMD_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
880 {
881 return INTERN_DVBT2_NORDIG_SSI_Table_Read(constel, code_rate, read_value);
882 }
883 #endif
884
DMD_DVBT2_SetPowerState(EN_POWER_MODE u16PowerState)885 MS_U32 DMD_DVBT2_SetPowerState(EN_POWER_MODE u16PowerState)
886 {
887 static EN_POWER_MODE _prev_u16PowerState = E_POWER_MECHANICAL;
888 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
889 u32Return = u32Return;
890
891 if(bIsDVBT2 == TRUE)
892 {
893
894 if (u16PowerState == E_POWER_SUSPEND)
895 {
896 DMD_DVBT2_Exit();
897 _prev_u16PowerState = u16PowerState;
898 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
899 }
900 else if (u16PowerState == E_POWER_RESUME)
901 {
902 if (_prev_u16PowerState == E_POWER_SUSPEND)
903 {
904 DMD_DVBT2_Init(&_sDMD_DVBT2_InitData, sizeof(_sDMD_DVBT2_InitData));
905 _prev_u16PowerState = u16PowerState;
906 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
907 }
908 else
909 {
910 printf("[%s,%5d]It is not suspended yet. We shouldn't resume\n",__FUNCTION__,__LINE__);
911 u32Return = UTOPIA_STATUS_FAIL;//SUSPEND_FAILED;
912 }
913 }
914 else
915 {
916 printf("[%s,%5d]Do Nothing: %d\n",__FUNCTION__,__LINE__,u16PowerState);
917 u32Return = FALSE;
918 }
919
920 }
921 else
922 {
923 ULOGD("DEMOD","\r\n ====== DVBT2 doesn't need to Suspend/Resume at Non-DVBT2 mode ====== \r\n");
924 u32Return = FALSE;
925 }
926 return UTOPIA_STATUS_SUCCESS;
927 }
928
929
DMD_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)930 MS_BOOL DMD_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
931 {
932 return INTERN_DVBT2_GetPlpBitMap(u8PlpBitMap);
933 }
934
DMD_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)935 MS_BOOL DMD_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
936 {
937 return INTERN_DVBT2_GetPlpGroupID(u8PlpID, u8GroupID);
938 }
939
DMD_DVBT2_SetPlpID(MS_U8 u8PlpID,MS_U8 u8GroupID)940 MS_BOOL DMD_DVBT2_SetPlpID(MS_U8 u8PlpID, MS_U8 u8GroupID)
941 {
942 MS_BOOL bRet = FALSE;
943
944 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
945 {
946 if (u8PlpID != 0xFF)
947 {
948 MS_U16 u16Retry = 0;
949 MS_U8 u8GroupId = 0;
950 MsOS_DelayTask(500);
951
952 bRet = INTERN_DVBT2_GetPlpGroupID(u8PlpID, &u8GroupId);
953 while ((bRet == FALSE) && (u16Retry < 60))
954 {
955 u16Retry++;
956 printf("DoSet_DVBT2 get groupid retry %d \n", u16Retry);
957 MsOS_DelayTask(100);
958 bRet = INTERN_DVBT2_GetPlpGroupID(u8PlpID, &u8GroupId);
959 }
960 if (bRet == FALSE)
961 {
962 printf("DoSet_DVBT2() INTERN_DVBT2_GetPlpGroupID(%d) Error \n", u8PlpID);
963 return FALSE;
964 }
965
966 bRet = INTERN_DVBT2_SetPlpGroupID(u8PlpID, u8GroupId);
967 if (bRet == FALSE)
968 {
969 printf("DoSet_DVBT2() INTERN_DVBT2_SetPlpGroupID(%d,%d) Error", u8PlpID, u8GroupId);
970 return FALSE;
971 }
972 }
973 }
974 else
975 {
976 return FALSE;
977 }
978
979 return TRUE;
980 }
981
982
983 //-------------------------------------------------------------------------------------------------
984 // Global Functions
985 //-------------------------------------------------------------------------------------------------
DVBT2Open(void ** ppInstance,MS_U32 u32ModuleVersion,void * pAttribute)986 MS_U32 DVBT2Open(void** ppInstance, MS_U32 u32ModuleVersion, void* pAttribute)
987 {
988 DVBT2_INSTANT_PRIVATE *pDvbt2Pri= NULL;
989
990 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c]DVBT2Open\n"));
991
992 // void *pDvbtPriVoid = NULL;
993
994 UtopiaInstanceCreate(sizeof(DVBT2_INSTANT_PRIVATE), ppInstance);
995 UtopiaInstanceGetPrivate(*ppInstance, (void*)&pDvbt2Pri);
996 // pDvbtPri = (DVBT_INSTANT_PRIVATE*)pDvbtPriVoid;
997
998
999 pDvbt2Pri->fpDVBT2_Init =DMD_DVBT2_Init;
1000 pDvbt2Pri->fpDVBT2_Exit =DMD_DVBT2_Exit;
1001 pDvbt2Pri->fpDVBT2_SetDbgLevel =DMD_DVBT2_SetDbgLevel;
1002 pDvbt2Pri->fpDVBT2_GetInfo =DMD_DVBT2_GetInfo;
1003 pDvbt2Pri->fpDVBT2_GetLibVer =DMD_DVBT2_GetLibVer;
1004 pDvbt2Pri->fpDVBT2_GetFWVer =DMD_DVBT2_GetFWVer;
1005 pDvbt2Pri->fpDVBT2_GetReg =DMD_DVBT2_GetReg;
1006 pDvbt2Pri->fpDVBT2_SetReg =DMD_DVBT2_SetReg;
1007 pDvbt2Pri->fpDVBT2_SetSerialControl =DMD_DVBT2_SetSerialControl;
1008 pDvbt2Pri->fpDVBT2_SetReset =DMD_DVBT2_SetReset;
1009 pDvbt2Pri->fpDVBT2_SetConfig =DMD_DVBT2_SetConfig;
1010 pDvbt2Pri->fpDVBT2_SetActive =DMD_DVBT2_SetActive;
1011 pDvbt2Pri->fpDVBT2_GetLock =DMD_DVBT2_GetLock;
1012 // pDvbt2Pri->fpDVBT2_GetSignalStrengthWithRFPower =DMD_DVBT2_GetSignalStrengthWithRFPower;
1013 // pDvbt2Pri->fpDVBT2_GetSignalQualityWithRFPower =DMD_DVBT2_GetSignalQualityWithRFPower;
1014 pDvbt2Pri->fpDVBT2_GetSNR =DMD_DVBT2_GetSNR;
1015 pDvbt2Pri->fpDVBT2_GetPostLdpcBer =DMD_DVBT2_GetPostLdpcBer;
1016 pDvbt2Pri->fpDVBT2_GetPreLdpcBer =DMD_DVBT2_GetPreLdpcBer;
1017 pDvbt2Pri->fpDVBT2_GetPacketErr =DMD_DVBT2_GetPacketErr;
1018 pDvbt2Pri->fpDVBT2_GetL1Info =DMD_DVBT2_GetL1Info;
1019 pDvbt2Pri->fpDVBT2_GetFreqOffset =DMD_DVBT2_GetFreqOffset;
1020 // pDvbt2Pri->fpDVBT2_NORDIG_SSI_Table_Write =DMD_DVBT2_NORDIG_SSI_Table_Write;
1021 // pDvbt2Pri->fpDVBT2_NORDIG_SSI_Table_Read =DMD_DVBT2_NORDIG_SSI_Table_Read;
1022 pDvbt2Pri->fpDVBT2_SetPowerState =DMD_DVBT2_SetPowerState;
1023 pDvbt2Pri->fpDVBT2_GetPlpBitMap =DMD_DVBT2_GetPlpBitMap;
1024 pDvbt2Pri->fpDVBT2_GetPlpGroupID =DMD_DVBT2_GetPlpGroupID;
1025 pDvbt2Pri->fpDVBT2_SetPlpID =DMD_DVBT2_SetPlpID;
1026
1027 //return TRUE;
1028 return UTOPIA_STATUS_SUCCESS;
1029 }
1030
DVBT2Ioctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)1031 MS_U32 DVBT2Ioctl(void* pInstance, MS_U32 u32Cmd, void* pArgs)
1032 {
1033
1034 void* pModule = NULL;
1035 UtopiaInstanceGetModule(pInstance, &pModule);
1036
1037 //void* pResource = NULL;
1038
1039 DVBT2_INSTANT_PRIVATE* psDVBT2InstPri = NULL;
1040 void* psDVBT2InstPriVoid = NULL;
1041 UtopiaInstanceGetPrivate(pInstance, (void**)&psDVBT2InstPriVoid);
1042 psDVBT2InstPri = (DVBT2_INSTANT_PRIVATE*)psDVBT2InstPriVoid;
1043
1044 MS_BOOL bRet = FALSE;
1045
1046 #if 0
1047 if (UtopiaResourceObtain(pModule, DVBT_POOL_ID_DMD0, &pResource) != 0)
1048 {
1049 DMD_DBG(ULOGD("DEMOD","UtopiaResourceObtainToInstant fail\n"));
1050 return UTOPIA_STATUS_ERR_RESOURCE;
1051 }
1052
1053 psDMD_DVBT_ResData = ((PDVBT_RESOURCE_PRIVATE)pResource)->sDMD_DVBT_ResData;
1054 #endif
1055
1056
1057
1058 switch (u32Cmd)
1059 {
1060 case DMD_DVBT2_DRV_CMD_Init:
1061 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c]DVBT2Ioctl - MDrv_DMD_DVBT2_Init\n"));
1062 bRet = psDVBT2InstPri->fpDVBT2_Init( (((PDVBT2_INIT_PARAM)pArgs)->pDMD_DVBT2_InitData), ((PDVBT2_INIT_PARAM)pArgs)->u32InitDataLen);
1063 ((PDVBT2_INIT_PARAM)pArgs)->ret=bRet;
1064 break;
1065 case DMD_DVBT2_DRV_CMD_Exit :
1066 bRet = psDVBT2InstPri->fpDVBT2_Exit();
1067 ((PDVBT2_EXIT_PARAM)pArgs)->ret=bRet;
1068 break;
1069 case DMD_DVBT2_DRV_CMD_SetDbgLevel:
1070 bRet = psDVBT2InstPri->fpDVBT2_SetDbgLevel(((PDVBT2_SETDBGLEVEL_PARAM)pArgs)->u8DbgLevel);
1071 ((PDVBT2_SETDBGLEVEL_PARAM)pArgs)->ret=bRet;
1072 break;
1073 case DMD_DVBT2_DRV_CMD_GetInfo:
1074 ((PDVBT2_GETINFO_PARAM)pArgs)->pInfo=psDVBT2InstPri->fpDVBT2_GetInfo(((PDVBT2_GETINFO_PARAM)pArgs)->eInfoType);
1075 bRet=true;
1076 break;
1077 case DMD_DVBT2_DRV_CMD_GetLibVer:
1078 bRet=psDVBT2InstPri->fpDVBT2_GetLibVer(((PDVBT2_GETLIBVER_PARAM)pArgs)->ppVersion);
1079 ((PDVBT2_GETLIBVER_PARAM)pArgs)->ret=bRet;
1080 break;
1081 case DMD_DVBT2_DRV_CMD_GetFWVer:
1082 bRet=psDVBT2InstPri->fpDVBT2_GetFWVer(((PDVBT2_GETFWVER_PARAM)pArgs)->ver);
1083 ((PDVBT2_GETFWVER_PARAM)pArgs)->ret=bRet;
1084 break;
1085 case DMD_DVBT2_DRV_CMD_GetReg:
1086 bRet=psDVBT2InstPri ->fpDVBT2_GetReg(((PDVBT2_GETREG_PARAM)pArgs)->u16Addr,((PDVBT2_GETREG_PARAM)pArgs)->pu8Data);
1087 ((PDVBT2_GETREG_PARAM)pArgs)->ret=bRet;
1088 break;
1089 case DMD_DVBT2_DRV_CMD_SetReg:
1090 bRet=psDVBT2InstPri->fpDVBT2_SetReg(((PDVBT2_SETREG_PARAM)pArgs)->u16Addr,((PDVBT2_SETREG_PARAM)pArgs)->u8Data);
1091 ((PDVBT2_SETREG_PARAM)pArgs)->ret=bRet;
1092 break;
1093 case DMD_DVBT2_DRV_CMD_SetSerialControl:
1094 bRet=psDVBT2InstPri->fpDVBT2_SetSerialControl(((PDVBT2_SETSERIALCONTROL_PARAM)pArgs)->bEnable);
1095 ((PDVBT2_SETSERIALCONTROL_PARAM)pArgs)->ret=bRet;
1096 break;
1097 case DMD_DVBT2_DRV_CMD_SetReset:
1098 bRet=psDVBT2InstPri->fpDVBT2_SetReset();
1099 break;
1100 case DMD_DVBT2_DRV_CMD_SetConfig:
1101 bRet=psDVBT2InstPri->fpDVBT2_SetConfig(((PDVBT2_SETCONFIG_PARAM)pArgs)->BW,((PDVBT2_SETCONFIG_PARAM)pArgs)->bSerialTS,((PDVBT2_SETCONFIG_PARAM)pArgs)->u8PlpID);
1102 ((PDVBT2_SETCONFIG_PARAM)pArgs)->ret=bRet;
1103 break;
1104 case DMD_DVBT2_DRV_CMD_SetActive:
1105 bRet=psDVBT2InstPri->fpDVBT2_SetActive(((PDVBT2_SETACTIVE_PARAM)pArgs)->bEnable);
1106 ((PDVBT2_SETACTIVE_PARAM)pArgs)->ret=bRet;
1107 break;
1108 case DMD_DVBT2_DRV_CMD_GetLock:
1109 bRet=psDVBT2InstPri->fpDVBT2_GetLock(((PDVBT2_GETLOCK_PARAM)pArgs)->eType,((PDVBT2_GETLOCK_PARAM)pArgs)->eLockStatus);
1110 ((PDVBT2_GETLOCK_PARAM)pArgs)->ret=bRet;
1111 break;
1112 case DMD_DVBT2_DRV_CMD_GetSNR:
1113 bRet=psDVBT2InstPri->fpDVBT2_GetSNR(((PDVBT2_GETSNR_PARAM)pArgs)->u16_snr100, ((PDVBT2_GETSNR_PARAM)pArgs)->snr_cali, ((PDVBT2_GETSNR_PARAM)pArgs)->u8_gi);
1114 ((PDVBT2_GETSNR_PARAM)pArgs)->ret=bRet;
1115 break;
1116 case DMD_DVBT2_DRV_CMD_GetPostLdpcBer:
1117 bRet=psDVBT2InstPri->fpDVBT2_GetPostLdpcBer(((PDVBT2_GETPOSTLDPCBER_PARAM)pArgs)->BitErr_reg, ((PDVBT2_GETPOSTLDPCBER_PARAM)pArgs)->BitErrPeriod_reg, ((PDVBT2_GETPOSTLDPCBER_PARAM)pArgs)->FecType);
1118 ((PDVBT2_GETPOSTLDPCBER_PARAM)pArgs)->ret=bRet;
1119 break;
1120 case DMD_DVBT2_DRV_CMD_GetPreLdpcBer:
1121 bRet=psDVBT2InstPri->fpDVBT2_GetPreLdpcBer(((PDVBT2_GETPRELDPCBERPARAM)pArgs)->BitErr_reg, ((PDVBT2_GETPRELDPCBERPARAM)pArgs)->BitErrPeriod_reg, ((PDVBT2_GETPRELDPCBERPARAM)pArgs)->FecType);
1122 ((PDVBT2_GETPRELDPCBERPARAM)pArgs)->ret=bRet;
1123 break;
1124 case DMD_DVBT2_DRV_CMD_GetPacketErr:
1125 bRet=psDVBT2InstPri->fpDVBT2_GetPacketErr(((PDVBT2_GETPACKETERRPARAM)pArgs)->pktErr);
1126 ((PDVBT2_GETPACKETERRPARAM)pArgs)->ret=bRet;
1127 break;
1128 case DMD_DVBT2_DRV_CMD_GetL1Info:
1129 bRet=psDVBT2InstPri->fpDVBT2_GetL1Info(((PDVBT2_GETL1INFO_PARAM)pArgs)->u16Info,((PDVBT2_GETL1INFO_PARAM)pArgs)->eSignalType);
1130 ((PDVBT2_GETL1INFO_PARAM)pArgs)->ret=bRet;
1131 break;
1132 case DMD_DVBT2_DRV_CMD_GetFreqOffset:
1133 bRet=psDVBT2InstPri->fpDVBT2_GetFreqOffset(((PDVBT2_GETFREQOFFSET_PARAM)pArgs)->CfoTd_reg, ((PDVBT2_GETFREQOFFSET_PARAM)pArgs)->CfoFd_reg, ((PDVBT2_GETFREQOFFSET_PARAM)pArgs)->Icfo_reg, ((PDVBT2_GETFREQOFFSET_PARAM)pArgs)->fft_reg);
1134 ((PDVBT2_GETFREQOFFSET_PARAM)pArgs)->ret=bRet;
1135 break;
1136 case DMD_DVBT2_DRV_CMD_SetPowerState:
1137 ((PDVBT2_SETPOWERSTATE_PARAM)pArgs)->ret=psDVBT2InstPri->fpDVBT2_SetPowerState(((PDVBT2_SETPOWERSTATE_PARAM)pArgs)->u16PowerState);
1138 bRet=TRUE;
1139 break;
1140 case DMD_DVBT2_DRV_CMD_GetPlpBitMap:
1141 bRet=psDVBT2InstPri->fpDVBT2_GetPlpBitMap(((PDVBT2_GETPLPBITMAP_PARAM)pArgs)->u8PlpBitMap);
1142 ((PDVBT2_GETPLPBITMAP_PARAM)pArgs)->ret=bRet;
1143 break;
1144 case DMD_DVBT2_DRV_CMD_GetPlpGroupID:
1145 bRet=psDVBT2InstPri->fpDVBT2_GetPlpGroupID(((PDVBT2_GETPLPGROUPID_PARAM)pArgs)->u8PlpID,((PDVBT2_GETPLPGROUPID_PARAM)pArgs)->u8GroupID);
1146 ((PDVBT2_GETPLPGROUPID_PARAM)pArgs)->ret=bRet;
1147 break;
1148 case DMD_DVBT2_DRV_CMD_SetPlpID:
1149 bRet=psDVBT2InstPri->fpDVBT2_SetPlpID(((PDMD_DVBT2_SETPLPID_PARAM)pArgs)->u8PlpID,((PDMD_DVBT2_SETPLPID_PARAM)pArgs)->u8GroupID);
1150 ((PDMD_DVBT2_SETPLPID_PARAM)pArgs)->ret=bRet;
1151 break;
1152 default:
1153 break;
1154 }
1155
1156 //jway suggest UtopiaResourceRelease(pResource);
1157
1158 return (bRet ? UTOPIA_STATUS_SUCCESS : UTOPIA_STATUS_FAIL);
1159 }
1160
DVBT2Close(void * pInstance)1161 MS_U32 DVBT2Close(void* pInstance)
1162 {
1163 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c]DVBT2Close\n"));
1164
1165 UtopiaInstanceDelete(pInstance);
1166
1167 return UTOPIA_STATUS_SUCCESS;
1168 }
1169
DVBT2Str(MS_U32 u32PowerState,void * pModule)1170 MS_U32 DVBT2Str(MS_U32 u32PowerState, void* pModule)
1171 {
1172 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1173 MS_U32 u32Ret = 0;
1174
1175 //UtopiaModuleGetSTRPrivate(pModule, (void**));
1176 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c]DVBT2Str\n"));
1177
1178 printf("[YPDEBUG][drvDMD_INTERN_DVBT2_v2.c] DVBT2Str\n");
1179
1180 if (u32PowerState == E_POWER_SUSPEND)
1181 {
1182 /* Please Implement Module Suspend Flow Here. */
1183 u32Ret = DMD_DVBT2_SetPowerState(E_POWER_SUSPEND);
1184
1185 if(u32Ret == TRUE)
1186 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1187 else
1188 u32Return = UTOPIA_STATUS_FAIL;
1189
1190 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c][DVBT2Str] SUSPEND !\n"));
1191 }
1192 else if (u32PowerState == E_POWER_RESUME)
1193 {
1194 /* Please Implement Module Resume Flow Here. */
1195 u32Ret = DMD_DVBT2_SetPowerState(E_POWER_RESUME);
1196
1197 if(u32Ret == TRUE)
1198 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1199 else
1200 u32Return = UTOPIA_STATUS_FAIL;
1201
1202 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c][DVBT2Str] RESUME !\n"));
1203 }
1204 else
1205 {
1206 u32Return = UTOPIA_STATUS_FAIL;
1207 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c][DVBT2Str] OTHERS !\n"));
1208 }
1209
1210 return u32Return;// for success
1211 }
1212
DVBT2RegisterToUtopia(void)1213 void DVBT2RegisterToUtopia(void)
1214 {
1215 // 1. deal with module
1216
1217 void* pUtopiaModule = NULL;
1218 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c]DVBT2RegisterToUtopia\n"));
1219 // UtopiaModuleCreate(MODULE_DVBT, 8, &pUtopiaModule); //bryan: why this was taken out
1220 UtopiaModuleCreate(MODULE_DVBT2, 8, &pUtopiaModule);
1221 UtopiaModuleRegister(pUtopiaModule);
1222 UtopiaModuleSetupFunctionPtr(pUtopiaModule, (FUtopiaOpen)DVBT2Open, (FUtopiaClose)DVBT2Close, (FUtopiaIOctl)DVBT2Ioctl);
1223
1224 printf("[YPDEBUG][drvDMD_INTERN_DVBT2_v2.c] DVBT2RegisterToUtopia\n");
1225 // Utopia2K STR
1226 #if defined(MSOS_TYPE_LINUX_KERNEL)
1227 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2_v2.c][DVBT2RegisterToUtopia] KERNEL DVBT2Str!\n"));
1228 UtopiaModuleSetupSTRFunctionPtr(pUtopiaModule,(FUtopiaSTR)DVBT2Str);
1229 #endif
1230 }