xref: /rk3399_ARM-atf/plat/mediatek/drivers/mminfra/mt8196/mminfra.h (revision 02309a84fbfb8b3469aa7dba52ea15c9bf2a768d)
1 /*
2  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MMINFRA_H
8 #define MMINFRA_H
9 
10 #include <lib/spinlock.h>
11 
12 #include "../mminfra_common.h"
13 #include <platform_def.h>
14 
15 #define VLP_AO_RSVD6			(MTK_VLP_TRACER_MON_BASE + 0x918)
16 #define MMINFRA_DONE			(1U << 0)
17 
18 #define SPM_SEMA_MMINFRA                (1U << 5)
19 #define SPM_SEMA_MMINFRA_NR             (8)
20 
21 #define SEMA_RETRY_CNT			(500)
22 
23 #define SPM_SEMAPHORE_M0		(0x69C)
24 #define SPM_SEMAPHORE_M1		(0x6A0)
25 #define SPM_SEMAPHORE_M2		(0x6A4)
26 #define SPM_SEMAPHORE_M3		(0x6A8)
27 #define SPM_SEMAPHORE_M4		(0x6AC)
28 #define SPM_SEMAPHORE_M5		(0x6B0)
29 #define SPM_SEMAPHORE_M6		(0x6B4)
30 #define SPM_SEMAPHORE_M7		(0x6B8)
31 
32 #define MMINFRA_HW_VOTER_BASE		(0x31A80000)
33 #define MTK_POLL_HWV_VOTE_US		(2)
34 #define MTK_POLL_HWV_VOTE_CNT		(2500)
35 #define MTK_POLL_DONE_DELAY_US		(1)
36 #define MTK_POLL_DONE_RETRY		(3000)
37 
38 struct mminfra_hw_sema {
39 	uint32_t base;
40 	uint32_t offset;
41 	uint32_t offset_all[SPM_SEMA_MMINFRA_NR];
42 	uint32_t set_val;
43 };
44 
45 struct mminfra_hw_voter {
46 	uint32_t base;
47 	uint32_t set_ofs;
48 	uint32_t clr_ofs;
49 	uint32_t en_ofs;
50 	uint32_t en_shift;
51 	uint32_t done_bits;
52 };
53 
54 struct mtk_mminfra_pwr_ctrl {
55 	spinlock_t lock;
56 	struct mminfra_hw_voter hw_voter;
57 	struct mminfra_hw_sema hw_sema;
58 	uint32_t ref_cnt;
59 	bool active;
60 };
61 
62 #endif
63