1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19 #include "mp_precomp.h"
20 #include "phydm_precomp.h"
21
22
23 boolean
phydm_dig_go_up_check(void * p_dm_void)24 phydm_dig_go_up_check(
25 void *p_dm_void
26 )
27 {
28 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
29 struct _CCX_INFO *ccx_info = &p_dm->dm_ccx_info;
30 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
31 u8 cur_ig_value = p_dig_t->cur_ig_value;
32 u8 max_cover_bond;
33 u8 rx_gain_range_max = p_dig_t->rx_gain_range_max;
34 u8 i = 0, j = 0;
35 u8 total_nhm_cnt = ccx_info->nhm_result_total;
36 u32 dig_cover_cnt = 0;
37 u32 over_dig_cover_cnt = 0;
38 boolean ret = true;
39
40 if (*p_dm->p_bb_op_mode == PHYDM_PERFORMANCE_MODE)
41 return ret;
42
43 max_cover_bond = DIG_MAX_BALANCE_MODE - p_dig_t->dig_upcheck_initial_value;
44
45 if (cur_ig_value < max_cover_bond - 6)
46 p_dig_t->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_0;
47 else if (cur_ig_value <= DIG_MAX_BALANCE_MODE)
48 p_dig_t->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_1;
49 else /* cur_ig_value > DM_DIG_MAX_AP, foolproof */
50 p_dig_t->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_2;
51
52
53 PHYDM_DBG(p_dm, DBG_DIG, ("check_lv = %d, max_cover_bond = 0x%x\n",
54 p_dig_t->dig_go_up_check_level,
55 max_cover_bond));
56
57 if (total_nhm_cnt != 0) {
58 if (p_dig_t->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_0) {
59 for (i = 3; i<=11; i++)
60 dig_cover_cnt += ccx_info->nhm_result[i];
61 ret = ((p_dig_t->dig_level0_ratio_reciprocal * dig_cover_cnt) >= total_nhm_cnt) ? true : false;
62 } else if (p_dig_t->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_1) {
63
64 /* search index */
65 for (i = 0; i<=10; i++) {
66 if ((max_cover_bond * 2) == ccx_info->nhm_th[i]) {
67 for(j =(i+1); j <= 11; j++)
68 over_dig_cover_cnt += ccx_info->nhm_result[j];
69 break;
70 }
71 }
72 ret = (p_dig_t->dig_level1_ratio_reciprocal * over_dig_cover_cnt < total_nhm_cnt) ? true : false;
73
74 if (!ret) {
75 /* update p_dig_t->rx_gain_range_max */
76 p_dig_t->rx_gain_range_max = (rx_gain_range_max >= max_cover_bond - 6) ? (max_cover_bond - 6) : rx_gain_range_max;
77
78 PHYDM_DBG(p_dm, DBG_DIG,
79 ("Noise pwr over DIG can filter, lock rx_gain_range_max to 0x%x\n",
80 p_dig_t->rx_gain_range_max));
81 }
82 } else if (p_dig_t->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_2) {
83 /* cur_ig_value > DM_DIG_MAX_AP, foolproof */
84 ret = true;
85 }
86 } else
87 ret = true;
88
89 return ret;
90 }
91
92 void
odm_fa_threshold_check(void * p_dm_void,boolean is_dfs_band,boolean is_performance)93 odm_fa_threshold_check(
94 void *p_dm_void,
95 boolean is_dfs_band,
96 boolean is_performance
97 )
98 {
99 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
100 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
101
102 if (p_dig_t->is_dbg_fa_th == true)
103 return;
104
105 if (p_dm->is_linked && (is_performance || is_dfs_band)) {
106 if ((p_dm->rx_tp >> 2) > p_dm->tx_tp && p_dm->rx_tp < 10 && p_dm->rx_tp > 1) { /*10Mbps & 1Mbps*/
107 p_dig_t->fa_th[0] = 125;
108 p_dig_t->fa_th[1] = 250;
109 p_dig_t->fa_th[2] = 500;
110 } else {
111 p_dig_t->fa_th[0] = 250;
112 p_dig_t->fa_th[1] = 500;
113 p_dig_t->fa_th[2] = 750;
114 }
115 } else {
116
117 if (is_dfs_band) { /* For DFS band and no link */
118
119 p_dig_t->fa_th[0] = 250;
120 p_dig_t->fa_th[1] = 1000;
121 p_dig_t->fa_th[2] = 2000;
122 } else {
123 p_dig_t->fa_th[0] = 2000;
124 p_dig_t->fa_th[1] = 4000;
125 p_dig_t->fa_th[2] = 5000;
126 }
127 }
128
129 PHYDM_DBG(p_dm, DBG_DIG,
130 ("FA_th={%d,%d,%d}\n",
131 p_dig_t->fa_th[0],
132 p_dig_t->fa_th[1],
133 p_dig_t->fa_th[2]));
134
135 }
136
137 void
phydm_set_big_jump_step(void * p_dm_void,u8 current_igi)138 phydm_set_big_jump_step(
139 void *p_dm_void,
140 u8 current_igi
141 )
142 {
143 #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
144 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
145 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
146 u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
147 u8 i;
148
149 if (p_dig_t->enable_adjust_big_jump == 0)
150 return;
151
152 for (i = 0; i <= p_dig_t->big_jump_step1; i++) {
153 if ((current_igi + step1[i]) > p_dig_t->big_jump_lmt[p_dig_t->agc_table_idx]) {
154 if (i != 0)
155 i = i - 1;
156 break;
157 } else if (i == p_dig_t->big_jump_step1)
158 break;
159 }
160 if (p_dm->support_ic_type & ODM_RTL8822B)
161 odm_set_bb_reg(p_dm, 0x8c8, 0xe, i);
162 else if (p_dm->support_ic_type & ODM_RTL8197F)
163 odm_set_bb_reg(p_dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
164
165 PHYDM_DBG(p_dm, DBG_DIG,
166 ("phydm_set_big_jump_step(): bigjump = %d (ori = 0x%x), LMT=0x%x\n",
167 i, p_dig_t->big_jump_step1, p_dig_t->big_jump_lmt[p_dig_t->agc_table_idx]));
168 #endif
169 }
170
171 void
odm_write_dig(void * p_dm_void,u8 current_igi)172 odm_write_dig(
173 void *p_dm_void,
174 u8 current_igi
175 )
176 {
177 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
178 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
179 struct phydm_adaptivity_struct *p_adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
180
181 PHYDM_DBG(p_dm, DBG_DIG, ("odm_write_dig===>\n"));
182
183 /* 1 Check IGI by upper bound */
184 if (p_adaptivity->igi_lmt_en &&
185 (current_igi > p_adaptivity->adapt_igi_up) && p_dm->is_linked) {
186
187 current_igi = p_adaptivity->adapt_igi_up;
188
189 PHYDM_DBG(p_dm, DBG_DIG,
190 ("Force to Adaptivity Upper bound=((0x%x))\n", current_igi));
191 }
192
193 if (p_dig_t->cur_ig_value != current_igi) {
194
195 #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
196 /* Modify big jump step for 8822B and 8197F */
197 if (p_dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F))
198 phydm_set_big_jump_step(p_dm, current_igi);
199 #endif
200
201 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
202 /* Set IGI value of CCK for new CCK AGC */
203 if (p_dm->cck_new_agc && (p_dm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE))
204 odm_set_bb_reg(p_dm, 0xa0c, 0x3f00, (current_igi >> 1));
205 #endif
206
207 /*Add by YuChen for USB IO too slow issue*/
208 if ((p_dm->support_ability & ODM_BB_ADAPTIVITY) && (current_igi > p_dig_t->cur_ig_value)) {
209 p_dig_t->cur_ig_value = current_igi;
210 phydm_adaptivity(p_dm);
211 }
212
213 /* Set IGI value */
214 odm_set_bb_reg(p_dm, ODM_REG(IGI_A, p_dm), ODM_BIT(IGI, p_dm), current_igi);
215
216 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
217 if (p_dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
218 odm_set_bb_reg(p_dm, ODM_REG(IGI_B, p_dm), ODM_BIT(IGI, p_dm), current_igi);
219 #endif
220
221 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
222 if (p_dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
223 odm_set_bb_reg(p_dm, ODM_REG(IGI_C, p_dm), ODM_BIT(IGI, p_dm), current_igi);
224 odm_set_bb_reg(p_dm, ODM_REG(IGI_D, p_dm), ODM_BIT(IGI, p_dm), current_igi);
225 }
226 #endif
227
228 p_dig_t->cur_ig_value = current_igi;
229 }
230
231 PHYDM_DBG(p_dm, DBG_DIG, ("New_igi=((0x%x))\n\n", current_igi));
232 }
233
234 void
phydm_set_dig_val(void * p_dm_void,u32 * val_buf,u8 val_len)235 phydm_set_dig_val(
236 void *p_dm_void,
237 u32 *val_buf,
238 u8 val_len
239 )
240 {
241 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
242
243 if (val_len != 1) {
244 PHYDM_DBG(p_dm, ODM_COMP_API, ("[Error][DIG]Need val_len=1\n"));
245 return;
246 }
247
248 odm_write_dig(p_dm, (u8)(*val_buf));
249 }
250
251 void
odm_pause_dig(void * p_dm_void,enum phydm_pause_type pause_type,enum phydm_pause_level pause_level,u8 igi_value)252 odm_pause_dig(
253 void *p_dm_void,
254 enum phydm_pause_type pause_type,
255 enum phydm_pause_level pause_level,
256 u8 igi_value
257 )
258 {
259 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
260 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
261 u8 i = 0;
262 s8 max_level;
263
264 PHYDM_DBG(p_dm, DBG_DIG, ("%s ======>\n", __func__));
265
266 if ((p_dig_t->pause_lv_bitmap == 0) &&
267 (!(p_dm->support_ability & (ODM_BB_DIG | ODM_BB_FA_CNT)))) {
268
269 PHYDM_DBG(p_dm, DBG_DIG, ("Return: DIG or FA is disabled\n"));
270 return;
271 }
272
273 if (pause_level >= PHYDM_PAUSE_MAX_NUM) {
274 PHYDM_DBG(p_dm, DBG_DIG, ("Return: Wrong Lv\n"));
275 return;
276 }
277
278 PHYDM_DBG(p_dm, DBG_DIG, ("Set pause {type, lv, IGI}={%d, %d, 0x%x}\n",
279 pause_type, pause_level, igi_value));
280
281 for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) {
282 PHYDM_DBG(p_dm, DBG_DIG, ("pause val[%d]=0x%x\n",
283 i, p_dig_t->pause_dig_value[i]));
284 }
285
286 switch (pause_type) {
287
288 case PHYDM_PAUSE:
289 {
290 PHYDM_DBG(p_dm, DBG_DIG, ("Pause DIG\n"));
291
292 p_dm->support_ability &= ~ODM_BB_DIG;
293
294 if (p_dig_t->pause_lv_bitmap == 0) {
295 p_dig_t->igi_backup = p_dig_t->cur_ig_value; /* Backup IGI value */
296 PHYDM_DBG(p_dm, DBG_DIG, ("Backup IGI=0x%x\n",
297 p_dig_t->igi_backup));
298 }
299
300 p_dig_t->pause_dig_value[pause_level] = igi_value; /* Record IGI value */
301 p_dig_t->pause_lv_bitmap |= BIT(pause_level); /* Update pause level bit-map*/
302
303 if (BIT(pause_level + 1) > p_dig_t->pause_lv_bitmap) {
304 PHYDM_DBG(p_dm, DBG_DIG, ("[SUCCESS ]Pause DIG\n"));
305 odm_write_dig(p_dm, igi_value);
306 } else {
307 PHYDM_DBG(p_dm, DBG_DIG,
308 ("[FAIL] Pause DIG, pause_bitmap=0x%x\n", p_dig_t->pause_lv_bitmap));
309 }
310 break;
311 }
312
313 case PHYDM_RESUME:
314 {
315 PHYDM_DBG(p_dm, DBG_DIG, ("Resume DIG\n"));
316
317 /* check if the level is illegal or not */
318 if ((p_dig_t->pause_lv_bitmap & (BIT(pause_level))) != 0) {
319
320 p_dig_t->pause_lv_bitmap &= ~(BIT(pause_level));
321 p_dig_t->pause_dig_value[pause_level] = 0;
322 } else {
323
324 PHYDM_DBG(p_dm, DBG_DIG, ("Wrong resume Lv\n"));
325 break;
326 }
327
328 PHYDM_DBG(p_dm, DBG_DIG, ("Pause_bitmap =0x%x\n",
329 p_dig_t->pause_lv_bitmap));
330
331 /* Resume DIG */
332 if (p_dig_t->pause_lv_bitmap == 0) {
333
334 PHYDM_DBG(p_dm, DBG_DIG, ("Revert ori_IGI\n"));
335 odm_write_dig(p_dm, p_dig_t->igi_backup); /* Revert IGI*/
336 p_dig_t->is_ignore_dig = true;
337 p_dm->support_ability |= ODM_BB_DIG;/* Enable DIG */
338 break;
339 }
340
341 if (BIT(pause_level) > p_dig_t->pause_lv_bitmap) {
342
343 /* Calculate the maximum level now */
344 for (max_level = (pause_level - 1); max_level >= 0; max_level--) {
345 if (p_dig_t->pause_lv_bitmap & BIT(max_level))
346 break;
347 }
348
349 /* write IGI to lower level */
350 PHYDM_DBG(p_dm, DBG_DIG, ("Pause @ IGI{Lv=0x%x}=%d)\n",
351 max_level, p_dig_t->pause_dig_value[max_level]));
352
353 odm_write_dig(p_dm, p_dig_t->pause_dig_value[max_level]);
354
355 break;
356 }
357 break;
358 }
359 default:
360 PHYDM_DBG(p_dm, DBG_DIG, ("Wrong pause type\n"));
361 break;
362 }
363
364 PHYDM_DBG(p_dm, DBG_DIG, ("New pause bitmap = 0x%x\n",
365 p_dig_t->pause_lv_bitmap));
366
367 for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) {
368 PHYDM_DBG(p_dm, DBG_DIG, ("pause val[%d]=0x%x\n",
369 i, p_dig_t->pause_dig_value[i]));
370 }
371
372 }
373
374 boolean
odm_dig_abort(void * p_dm_void)375 odm_dig_abort(
376 void *p_dm_void
377 )
378 {
379 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
380 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
381 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
382 struct _ADAPTER *p_adapter = p_dm->adapter;
383 #endif
384
385 /* support_ability */
386 if ((!(p_dm->support_ability & ODM_BB_FA_CNT)) ||
387 (!(p_dm->support_ability & ODM_BB_DIG)) ||
388 (*(p_dm->p_is_scan_in_process))) {
389 PHYDM_DBG(p_dm, DBG_DIG, ("Not Support\n"));
390 return true;
391 }
392
393 if (p_dm->pause_ability & ODM_BB_DIG) {
394
395 PHYDM_DBG(p_dm, DBG_DIG, ("Return: Pause DIG in LV=%d\n", p_dm->pause_lv_table.lv_dig));
396 return true;
397 }
398
399 if (p_dig_t->is_ignore_dig) {
400 p_dig_t->is_ignore_dig = false;
401 PHYDM_DBG(p_dm, DBG_DIG, ("Return: Ignore DIG\n"));
402 return true;
403 }
404
405 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
406 #if OS_WIN_FROM_WIN7(OS_VERSION)
407 if (IsAPModeExist(p_adapter) && p_adapter->bInHctTest) {
408 PHYDM_DBG(p_dm, DBG_DIG, (" Return: Is AP mode or In HCT Test\n"));
409 return true;
410 }
411 #endif
412 #endif
413
414 return false;
415 }
416
417 void
phydm_dig_init(void * p_dm_void)418 phydm_dig_init(
419 void *p_dm_void
420 )
421 {
422 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
423 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
424 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
425 struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(p_dm, PHYDM_FALSEALMCNT);
426 #endif
427 u32 ret_value = 0;
428 u8 i;
429
430 p_dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
431 p_dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
432 p_dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
433
434 p_dig_t->is_ignore_dig = false;
435 p_dig_t->cur_ig_value = (u8) odm_get_bb_reg(p_dm, ODM_REG(IGI_A, p_dm), ODM_BIT(IGI, p_dm));
436 p_dig_t->is_media_connect = false;
437
438 p_dig_t->fa_th[0] = 250;
439 p_dig_t->fa_th[1] = 500;
440 p_dig_t->fa_th[2] = 750;
441 p_dig_t->is_dbg_fa_th = false;
442 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
443 /* For RTL8881A */
444 false_alm_cnt->cnt_ofdm_fail_pre = 0;
445 #endif
446
447 odm_memory_set(p_dm, p_dig_t->pause_dig_value, 0, PHYDM_PAUSE_MAX_NUM);
448 p_dig_t->pause_lv_bitmap = 0;
449
450 p_dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
451 p_dig_t->rx_gain_range_min = p_dig_t->cur_ig_value;
452
453 #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
454 p_dig_t->enable_adjust_big_jump = 1;
455 if (p_dm->support_ic_type & ODM_RTL8822B)
456 ret_value = odm_get_bb_reg(p_dm, 0x8c8, MASKLWORD);
457 else if (p_dm->support_ic_type & ODM_RTL8197F)
458 ret_value = odm_get_bb_reg(p_dm, 0xc74, MASKLWORD);
459
460 p_dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
461 p_dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
462 p_dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
463
464 if (p_dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) {
465 for (i = 0; i < sizeof(p_dig_t->big_jump_lmt); i++) {
466 if (p_dig_t->big_jump_lmt[i] == 0)
467 p_dig_t->big_jump_lmt[i] = 0x64; /* Set -10dBm as default value */
468 }
469 }
470 #endif
471
472 p_dm->pre_rssi_min = 0;
473
474 #ifdef PHYDM_TDMA_DIG_SUPPORT
475 p_dm->original_dig_restore = 1;
476 #endif
477 }
478
479 boolean
phydm_dig_performance_mode_decision(struct PHY_DM_STRUCT * p_dm)480 phydm_dig_performance_mode_decision(
481 struct PHY_DM_STRUCT *p_dm
482 )
483 {
484 boolean is_performance = true;
485
486 #ifdef PHYDM_DIG_MODE_DECISION_SUPPORT
487 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
488
489 switch (p_dig_t->dig_mode_decision) {
490 case PHYDM_DIG_PERFORAMNCE_MODE:
491 is_performance = true;
492 break;
493 case PHYDM_DIG_COVERAGE_MODE:
494 is_performance = false;
495 break;
496 default:
497 is_performance = true;
498 break;
499 }
500 #endif
501
502 return is_performance;
503 }
504
505 void
phydm_dig_abs_boundary_decision(struct PHY_DM_STRUCT * p_dm,boolean is_performance,boolean is_dfs_band)506 phydm_dig_abs_boundary_decision(
507 struct PHY_DM_STRUCT *p_dm,
508 boolean is_performance,
509 boolean is_dfs_band
510 )
511 {
512 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
513
514 if (!p_dm->is_linked) {
515 p_dig_t->dm_dig_max = DIG_MAX_COVERAGR;
516 p_dig_t->dm_dig_min = DIG_MIN_COVERAGE;
517 } else if (is_dfs_band == true) {
518 if (*p_dm->p_band_width == CHANNEL_WIDTH_20)
519 p_dig_t->dm_dig_min = DIG_MIN_DFS + 2;
520 else
521 p_dig_t->dm_dig_min = DIG_MIN_DFS;
522
523 p_dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
524 p_dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
525
526 } else if (!is_performance) {
527 p_dig_t->dm_dig_max = DIG_MAX_COVERAGR;
528 p_dig_t->dm_dig_min = DIG_MIN_COVERAGE;
529 #if (DIG_HW == 1)
530 p_dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
531 #else
532 p_dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE;
533 #endif
534 } else {
535 if (*p_dm->p_bb_op_mode == PHYDM_BALANCE_MODE) { /*service > 2 devices*/
536 p_dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
537 #if (DIG_HW == 1)
538 p_dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
539 #else
540 p_dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
541 #endif
542 } else if (*p_dm->p_bb_op_mode == PHYDM_PERFORMANCE_MODE) { /*service 1 devices*/
543 p_dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
544 p_dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
545 }
546
547 if (p_dm->support_ic_type &
548 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
549 p_dig_t->dm_dig_min = 0x1c;
550 else if (p_dm->support_ic_type & ODM_RTL8197F)
551 p_dig_t->dm_dig_min = 0x1e; /*For HW setting*/
552 else
553 p_dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
554 }
555
556 PHYDM_DBG(p_dm, DBG_DIG,
557 ("Abs-bound{Max, Min}={0x%x, 0x%x}, Max_of_min = 0x%x\n",
558 p_dig_t->dm_dig_max,
559 p_dig_t->dm_dig_min,
560 p_dig_t->dig_max_of_min));
561
562 }
563
564 void
phydm_dig_dym_boundary_decision(struct PHY_DM_STRUCT * p_dm,boolean is_performance)565 phydm_dig_dym_boundary_decision(
566 struct PHY_DM_STRUCT *p_dm,
567 boolean is_performance
568 )
569 {
570 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
571 u8 offset = 15, tmp_max = 0;
572
573 PHYDM_DBG(p_dm, DBG_DIG,
574 ("Offset=((%d))\n", offset));
575
576 /* DIG lower bound */
577 if (p_dm->rssi_min > p_dig_t->dig_max_of_min)
578 p_dig_t->rx_gain_range_min = p_dig_t->dig_max_of_min;
579 else if (p_dm->rssi_min < p_dig_t->dm_dig_min)
580 p_dig_t->rx_gain_range_min = p_dig_t->dm_dig_min;
581 else
582 p_dig_t->rx_gain_range_min = p_dm->rssi_min;
583
584 /* DIG upper bound */
585 tmp_max = p_dig_t->rx_gain_range_min + offset;
586
587 if (tmp_max > p_dig_t->dm_dig_max)
588 p_dig_t->rx_gain_range_max = p_dig_t->dm_dig_max;
589 else
590 p_dig_t->rx_gain_range_max = tmp_max;
591
592 /* 1 Force Lower Bound for AntDiv */
593 if (!p_dm->is_one_entry_only) {
594 if ((p_dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_dm->support_ability & ODM_BB_ANT_DIV)) {
595 if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
596 if (p_dig_t->ant_div_rssi_max > p_dig_t->dig_max_of_min)
597 p_dig_t->rx_gain_range_min = p_dig_t->dig_max_of_min;
598 else
599 p_dig_t->rx_gain_range_min = (u8)p_dig_t->ant_div_rssi_max;
600
601 PHYDM_DBG(p_dm, DBG_DIG,
602 ("AntDiv: Force Dyn-Min = 0x%x, RSSI_max = 0x%x\n",
603 p_dig_t->rx_gain_range_min, p_dig_t->ant_div_rssi_max));
604 }
605 }
606 }
607 PHYDM_DBG(p_dm, DBG_DIG,
608 ("Dym-bound{Max, Min}={0x%x, 0x%x}\n",
609 p_dig_t->rx_gain_range_max, p_dig_t->rx_gain_range_min));
610 }
611
612 void
phydm_dig_abnormal_case(struct PHY_DM_STRUCT * p_dm,u8 current_igi,boolean is_performance,boolean is_dfs_band)613 phydm_dig_abnormal_case(
614 struct PHY_DM_STRUCT *p_dm,
615 u8 current_igi,
616 boolean is_performance,
617 boolean is_dfs_band
618 )
619 {
620 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
621 boolean first_connect = false, first_dis_connect = false;
622
623 first_connect = (p_dm->is_linked) && (p_dig_t->is_media_connect == false);
624 first_dis_connect = (!p_dm->is_linked) && (p_dig_t->is_media_connect == true);
625
626 /* Modify DIG lower bound, deal with abnormal case */
627 if (!p_dm->is_linked && is_dfs_band && is_performance) {
628 p_dig_t->rx_gain_range_max = DIG_MAX_DFS;
629 PHYDM_DBG(p_dm, DBG_DIG,
630 ("DFS band: Force max to 0x%x before link\n", p_dig_t->rx_gain_range_max));
631 }
632
633 if (is_dfs_band)
634 p_dig_t->rx_gain_range_min = p_dig_t->dm_dig_min;
635
636 /* Abnormal lower bound case */
637 if (p_dig_t->rx_gain_range_min > p_dig_t->rx_gain_range_max)
638 p_dig_t->rx_gain_range_min = p_dig_t->rx_gain_range_max;
639
640 PHYDM_DBG(p_dm, DBG_DIG,
641 ("Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
642 p_dig_t->rx_gain_range_max, p_dig_t->rx_gain_range_min));
643
644 }
645
646 u8
phydm_dig_current_igi_by_fa_th(struct PHY_DM_STRUCT * p_dm,u8 current_igi,u32 false_alm_cnt,u8 * step_size)647 phydm_dig_current_igi_by_fa_th(
648 struct PHY_DM_STRUCT *p_dm,
649 u8 current_igi,
650 u32 false_alm_cnt,
651 u8 *step_size
652 )
653 {
654 boolean dig_go_up_check = true;
655 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
656
657 dig_go_up_check = phydm_dig_go_up_check(p_dm);
658
659 if ((false_alm_cnt > p_dig_t->fa_th[2]) && dig_go_up_check)
660 current_igi = current_igi + step_size[0];
661 else if ((false_alm_cnt > p_dig_t->fa_th[1]) && dig_go_up_check)
662 current_igi = current_igi + step_size[1];
663 else if (false_alm_cnt < p_dig_t->fa_th[0])
664 current_igi = current_igi - step_size[2];
665
666 return current_igi;
667
668 }
669
670 u8
phydm_dig_igi_start_value(struct PHY_DM_STRUCT * p_dm,boolean is_performance,u8 current_igi,u32 false_alm_cnt,boolean is_dfs_band)671 phydm_dig_igi_start_value(
672 struct PHY_DM_STRUCT *p_dm,
673 boolean is_performance,
674 u8 current_igi,
675 u32 false_alm_cnt,
676 boolean is_dfs_band
677 )
678 {
679 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
680 u8 step_size[3] = {0};
681 boolean first_connect = false, first_dis_connect = false;
682
683 first_connect = (p_dm->is_linked) && (p_dig_t->is_media_connect == false);
684 first_dis_connect = (!p_dm->is_linked) && (p_dig_t->is_media_connect == true);
685
686 if (p_dm->is_linked) {
687 if (p_dm->pre_rssi_min <= p_dm->rssi_min) {
688 step_size[0] = 2;
689 step_size[1] = 1;
690 step_size[2] = 2;
691 } else {
692 step_size[0] = 4;
693 step_size[1] = 2;
694 step_size[2] = 2;
695 }
696 p_dm->pre_rssi_min = p_dm->rssi_min;
697 } else {
698 step_size[0] = 2;
699 step_size[1] = 1;
700 step_size[2] = 2;
701 }
702
703 PHYDM_DBG(p_dm, DBG_DIG,
704 ("step_size = {-%d, +%d, +%d}\n", step_size[2], step_size[1], step_size[0]));
705
706 PHYDM_DBG(p_dm, DBG_DIG,
707 ("rssi_min = %d, pre_rssi_min = %d\n", p_dm->rssi_min, p_dm->pre_rssi_min));
708
709 if (p_dm->is_linked && is_performance) {
710 /* 2 After link */
711 PHYDM_DBG(p_dm, DBG_DIG, ("Adjust IGI after link\n"));
712
713 if (first_connect && is_performance) {
714
715 if (is_dfs_band) {
716 if (p_dm->rssi_min > DIG_MAX_DFS)
717 current_igi = DIG_MAX_DFS;
718 else
719 current_igi = p_dm->rssi_min;
720 PHYDM_DBG(p_dm, DBG_DIG,
721 ("DFS band: one shot IGI to 0x%x most\n", p_dig_t->rx_gain_range_max));
722 } else
723 current_igi = p_dig_t->rx_gain_range_min;
724 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
725 #if (RTL8812A_SUPPORT == 1)
726 if (p_dm->support_ic_type == ODM_RTL8812)
727 odm_config_bb_with_header_file(p_dm, CONFIG_BB_AGC_TAB_DIFF);
728 #endif
729 #endif
730 PHYDM_DBG(p_dm, DBG_DIG,
731 ("First connect case: IGI does on-shot to 0x%x\n", current_igi));
732 } else {
733
734 /* 4 Abnormal # beacon case */
735 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
736 if ((p_dm->phy_dbg_info.num_qry_beacon_pkt < 5) &&
737 (false_alm_cnt < DM_DIG_FA_TH1) && (p_dm->bsta_state)) {
738 if (p_dm->support_ic_type != ODM_RTL8723D) {
739 p_dig_t->rx_gain_range_min = 0x1c;
740 current_igi = p_dig_t->rx_gain_range_min;
741 PHYDM_DBG(p_dm, DBG_DIG,
742 ("Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n",
743 p_dm->phy_dbg_info.num_qry_beacon_pkt, current_igi));
744 }
745 } else
746 #endif
747 current_igi = phydm_dig_current_igi_by_fa_th(p_dm,
748 current_igi, false_alm_cnt, step_size);
749 }
750 } else {
751 /* 2 Before link */
752 PHYDM_DBG(p_dm, DBG_DIG, ("Adjust IGI before link\n"));
753
754 if (first_dis_connect) {
755 current_igi = p_dig_t->dm_dig_min;
756 PHYDM_DBG(p_dm, DBG_DIG, ("First disconnect case: IGI does on-shot to lower bound\n"));
757 } else {
758 PHYDM_DBG(p_dm, DBG_DIG,
759 ("Pre_IGI=((0x%x)), FA=((%d))\n", current_igi, false_alm_cnt));
760
761 current_igi = phydm_dig_current_igi_by_fa_th(p_dm,
762 current_igi, false_alm_cnt, step_size);
763 }
764 }
765
766 return current_igi;
767
768 }
769
770 void
phydm_dig(void * p_dm_void)771 phydm_dig(
772 void *p_dm_void
773 )
774 {
775 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
776 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
777 struct phydm_fa_struct *p_falm_cnt = &p_dm->false_alm_cnt;
778 #ifdef PHYDM_TDMA_DIG_SUPPORT
779 struct phydm_fa_acc_struct *p_falm_cnt_acc = &p_dm->false_alm_cnt_acc;
780 #endif
781 boolean first_connect, first_dis_connect;
782 u8 current_igi = p_dig_t->cur_ig_value;
783 u32 false_alm_cnt= p_falm_cnt->cnt_all;
784 boolean is_dfs_band = false, is_performance = true;
785
786 #ifdef PHYDM_TDMA_DIG_SUPPORT
787 if (p_dm->original_dig_restore == 0) {
788 if (p_dig_t->cur_ig_value_tdma == 0)
789 p_dig_t->cur_ig_value_tdma = p_dig_t->cur_ig_value;
790
791 current_igi = p_dig_t->cur_ig_value_tdma;
792 false_alm_cnt = p_falm_cnt_acc->cnt_all_1sec;
793 }
794 #endif
795
796 if (odm_dig_abort(p_dm) == true)
797 return;
798
799 PHYDM_DBG(p_dm, DBG_DIG, ("%s Start===>\n", __func__));
800
801 /* 1 Update status */
802 first_connect = (p_dm->is_linked) && (p_dig_t->is_media_connect == false);
803 first_dis_connect = (!p_dm->is_linked) && (p_dig_t->is_media_connect == true);
804
805 PHYDM_DBG(p_dm, DBG_DIG,
806 ("is_linked = %d, RSSI = %d, 1stConnect = %d, 1stDisconnect = %d\n",
807 p_dm->is_linked, p_dm->rssi_min, first_connect, first_dis_connect));
808
809 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE))
810 /* Modify lower bound for DFS band */
811 if (p_dm->is_dfs_band) {
812 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
813 if (phydm_dfs_master_enabled(p_dm))
814 #endif
815 is_dfs_band = true;
816
817 PHYDM_DBG(p_dm, DBG_DIG, ("In DFS band\n"));
818 }
819 #endif
820
821 is_performance = phydm_dig_performance_mode_decision(p_dm);
822 PHYDM_DBG(p_dm, DBG_DIG,
823 ("DIG ((%s)) mode\n", (is_performance ? "Performance" : "Coverage")));
824
825 /* Boundary Decision */
826 phydm_dig_abs_boundary_decision(p_dm, is_performance, is_dfs_band);
827
828 /*init dym boundary*/
829 p_dig_t->rx_gain_range_max = p_dig_t->dig_max_of_min; /*if no link, always stay at lower bound*/
830 p_dig_t->rx_gain_range_min = p_dig_t->dm_dig_min;
831
832 /* Adjust boundary by RSSI */
833 if (p_dm->is_linked)
834 phydm_dig_dym_boundary_decision(p_dm, is_performance);
835
836 /*Abnormal case check*/
837 phydm_dig_abnormal_case(p_dm, current_igi, is_performance, is_dfs_band);
838
839 /* False alarm threshold decision */
840 odm_fa_threshold_check(p_dm, is_dfs_band, is_performance);
841
842 /* 1 Adjust initial gain by false alarm */
843 current_igi = phydm_dig_igi_start_value(p_dm,
844 is_performance, current_igi, false_alm_cnt, is_dfs_band);
845
846 /* 1 Check initial gain by upper/lower bound */
847 if (current_igi < p_dig_t->rx_gain_range_min)
848 current_igi = p_dig_t->rx_gain_range_min;
849
850 if (current_igi > p_dig_t->rx_gain_range_max)
851 current_igi = p_dig_t->rx_gain_range_max;
852
853 PHYDM_DBG(p_dm, DBG_DIG, ("New_IGI=((0x%x))\n", current_igi));
854
855 /* 1 Update status */
856 #ifdef PHYDM_TDMA_DIG_SUPPORT
857 if (p_dm->original_dig_restore == 0) {
858
859 p_dig_t->cur_ig_value_tdma = current_igi;
860 /*It is possible fa_acc_1sec_tsf >= */
861 /*1sec while tdma_dig_state == 0*/
862 if (p_dig_t->tdma_dig_state != 0)
863 odm_write_dig(p_dm, p_dig_t->cur_ig_value_tdma);
864 } else
865 #endif
866 odm_write_dig(p_dm, current_igi);
867
868 p_dig_t->is_media_connect = p_dm->is_linked;
869
870 PHYDM_DBG(p_dm, DBG_DIG, ("DIG end\n"));
871 }
872
873 void
phydm_dig_lps_32k(void * p_dm_void)874 phydm_dig_lps_32k(
875 void *p_dm_void
876 )
877 {
878 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
879 u8 current_igi = p_dm->rssi_min;
880
881
882 odm_write_dig(p_dm, current_igi);
883 }
884
885 void
phydm_dig_by_rssi_lps(void * p_dm_void)886 phydm_dig_by_rssi_lps(
887 void *p_dm_void
888 )
889 {
890 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
891 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
892 struct phydm_fa_struct *p_falm_cnt;
893
894 u8 rssi_lower = DIG_MIN_LPS; /* 0x1E or 0x1C */
895 u8 current_igi = p_dm->rssi_min;
896
897 p_falm_cnt = &p_dm->false_alm_cnt;
898 if (odm_dig_abort(p_dm) == true)
899 return;
900
901 current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
902 PHYDM_DBG(p_dm, DBG_DIG, ("%s==>\n", __func__));
903
904 /* Using FW PS mode to make IGI */
905 /* Adjust by FA in LPS MODE */
906 if (p_falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
907 current_igi = current_igi + 4;
908 else if (p_falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
909 current_igi = current_igi + 2;
910 else if (p_falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
911 current_igi = current_igi - 2;
912
913
914 /* Lower bound checking */
915
916 /* RSSI Lower bound check */
917 if ((p_dm->rssi_min - 10) > DIG_MIN_LPS)
918 rssi_lower = (p_dm->rssi_min - 10);
919 else
920 rssi_lower = DIG_MIN_LPS;
921
922 /* Upper and Lower Bound checking */
923 if (current_igi > DIG_MAX_LPS)
924 current_igi = DIG_MAX_LPS;
925 else if (current_igi < rssi_lower)
926 current_igi = rssi_lower;
927
928 PHYDM_DBG(p_dm, DBG_DIG,
929 ("%s p_falm_cnt->cnt_all = %d\n", __func__,
930 p_falm_cnt->cnt_all));
931 PHYDM_DBG(p_dm, DBG_DIG,
932 ("%s p_dm->rssi_min = %d\n", __func__,
933 p_dm->rssi_min));
934 PHYDM_DBG(p_dm, DBG_DIG,
935 ("%s current_igi = 0x%x\n", __func__,
936 current_igi));
937
938 /* odm_write_dig(p_dm, p_dig_t->cur_ig_value); */
939 odm_write_dig(p_dm, current_igi);
940 #endif
941 }
942
943 /* 3============================================================
944 * 3 FASLE ALARM CHECK
945 * 3============================================================ */
946 void
phydm_false_alarm_counter_reg_reset(void * p_dm_void)947 phydm_false_alarm_counter_reg_reset(
948 void *p_dm_void
949 )
950 {
951 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
952 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
953 struct phydm_fa_struct *p_falm_cnt = &p_dm->false_alm_cnt;
954 #ifdef PHYDM_TDMA_DIG_SUPPORT
955 struct phydm_fa_acc_struct *p_falm_cnt_acc = &p_dm->false_alm_cnt_acc;
956 #endif
957 u32 false_alm_cnt;
958
959 #ifdef PHYDM_TDMA_DIG_SUPPORT
960 if (p_dm->original_dig_restore == 0) {
961
962 if (p_dig_t->cur_ig_value_tdma == 0)
963 p_dig_t->cur_ig_value_tdma = p_dig_t->cur_ig_value;
964
965 false_alm_cnt = p_falm_cnt_acc->cnt_all_1sec;
966 } else
967 #endif
968 {
969 false_alm_cnt = p_falm_cnt->cnt_all;
970 }
971
972 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
973 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
974 /*reset false alarm counter registers*/
975 odm_set_bb_reg(p_dm, 0xC0C, BIT(31), 1);
976 odm_set_bb_reg(p_dm, 0xC0C, BIT(31), 0);
977 odm_set_bb_reg(p_dm, 0xD00, BIT(27), 1);
978 odm_set_bb_reg(p_dm, 0xD00, BIT(27), 0);
979
980 /*update ofdm counter*/
981 /*update page C counter*/
982 odm_set_bb_reg(p_dm, 0xD00, BIT(31), 0);
983 /*update page D counter*/
984 odm_set_bb_reg(p_dm, 0xD00, BIT(31), 0);
985
986 /*reset CCK CCA counter*/
987 odm_set_bb_reg(p_dm, 0xA2C, BIT(13) | BIT(12), 0);
988 odm_set_bb_reg(p_dm, 0xA2C, BIT(13) | BIT(12), 2);
989
990 /*reset CCK FA counter*/
991 odm_set_bb_reg(p_dm, 0xA2C, BIT(15) | BIT(14), 0);
992 odm_set_bb_reg(p_dm, 0xA2C, BIT(15) | BIT(14), 2);
993
994 /*reset CRC32 counter*/
995 odm_set_bb_reg(p_dm, 0xF14, BIT(16), 1);
996 odm_set_bb_reg(p_dm, 0xF14, BIT(16), 0);
997 }
998 #endif /* #if (ODM_IC_11N_SERIES_SUPPORT == 1) */
999
1000 #if (ODM_IC_11AC_SERIES_SUPPORT == 1)
1001 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
1002 #if (RTL8881A_SUPPORT == 1)
1003 /* Reset FA counter by enable/disable OFDM */
1004 if (false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
1005 /* reset OFDM */
1006 odm_set_bb_reg(p_dm, 0x808, BIT(29), 0);
1007 odm_set_bb_reg(p_dm, 0x808, BIT(29), 1);
1008 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1009 PHYDM_DBG(p_dm, DBG_FA_CNT, ("Reset FA_cnt\n"));
1010 }
1011 #endif /* #if (RTL8881A_SUPPORT == 1) */
1012 /* reset OFDM FA countner */
1013 odm_set_bb_reg(p_dm, 0x9A4, BIT(17), 1);
1014 odm_set_bb_reg(p_dm, 0x9A4, BIT(17), 0);
1015
1016 /* reset CCK FA counter */
1017 odm_set_bb_reg(p_dm, 0xA2C, BIT(15), 0);
1018 odm_set_bb_reg(p_dm, 0xA2C, BIT(15), 1);
1019
1020 /* reset CCA counter */
1021 odm_set_bb_reg(p_dm, 0xB58, BIT(0), 1);
1022 odm_set_bb_reg(p_dm, 0xB58, BIT(0), 0);
1023 }
1024 #endif /* #if (ODM_IC_11AC_SERIES_SUPPORT == 1) */
1025 }
1026
1027 void
phydm_false_alarm_counter_reg_hold(void * p_dm_void)1028 phydm_false_alarm_counter_reg_hold(
1029 void *p_dm_void
1030 )
1031 {
1032 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1033
1034 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
1035 /*hold ofdm counter*/
1036 /*hold page C counter*/
1037 odm_set_bb_reg(p_dm, 0xC00, BIT(31), 1);
1038 /*hold page D counter*/
1039 odm_set_bb_reg(p_dm, 0xD00, BIT(31), 1);
1040
1041 //hold cck counter
1042 odm_set_bb_reg(p_dm, 0xA2C, BIT(12), 1);
1043 odm_set_bb_reg(p_dm, 0xA2C, BIT(14), 1);
1044 }
1045 }
1046
1047 void
odm_false_alarm_counter_statistics(void * p_dm_void)1048 odm_false_alarm_counter_statistics(
1049 void *p_dm_void
1050 )
1051 {
1052 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1053 struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(p_dm, PHYDM_FALSEALMCNT);
1054 struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(p_dm, PHYDM_ADAPTIVITY);
1055 u32 ret_value;
1056
1057 if (!(p_dm->support_ability & ODM_BB_FA_CNT))
1058 return;
1059
1060 PHYDM_DBG(p_dm, DBG_FA_CNT, ("FA_Counter()======>\n"));
1061
1062 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
1063 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
1064
1065 /* hold ofdm & cck counter */
1066 phydm_false_alarm_counter_reg_hold(p_dm);
1067
1068 ret_value = odm_get_bb_reg(p_dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
1069 false_alm_cnt->cnt_fast_fsync = (ret_value & 0xffff);
1070 false_alm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
1071
1072 ret_value = odm_get_bb_reg(p_dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
1073 false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
1074 false_alm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
1075
1076 ret_value = odm_get_bb_reg(p_dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
1077 false_alm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
1078 false_alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
1079
1080 ret_value = odm_get_bb_reg(p_dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
1081 false_alm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
1082
1083 false_alm_cnt->cnt_ofdm_fail =
1084 false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal +
1085 false_alm_cnt->cnt_crc8_fail + false_alm_cnt->cnt_mcs_fail +
1086 false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail;
1087
1088 /* read CCK CRC32 counter */
1089 false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(p_dm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD);
1090 false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(p_dm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD);
1091
1092 /* read OFDM CRC32 counter */
1093 ret_value = odm_get_bb_reg(p_dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
1094 false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1095 false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1096
1097 /* read HT CRC32 counter */
1098 ret_value = odm_get_bb_reg(p_dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1099 false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1100 false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff;
1101
1102 /* read VHT CRC32 counter */
1103 false_alm_cnt->cnt_vht_crc32_error = 0;
1104 false_alm_cnt->cnt_vht_crc32_ok = 0;
1105
1106 #if (RTL8723D_SUPPORT == 1)
1107 if (p_dm->support_ic_type == ODM_RTL8723D) {
1108 /* read HT CRC32 agg counter */
1109 ret_value = odm_get_bb_reg(p_dm, ODM_REG_HT_CRC32_CNT_11N_AGG, MASKDWORD);
1110 false_alm_cnt->cnt_ht_crc32_error_agg = (ret_value & 0xffff0000) >> 16;
1111 false_alm_cnt->cnt_ht_crc32_ok_agg= ret_value & 0xffff;
1112 }
1113 #endif
1114
1115 #if (RTL8188E_SUPPORT == 1)
1116 if (p_dm->support_ic_type == ODM_RTL8188E) {
1117 ret_value = odm_get_bb_reg(p_dm, ODM_REG_SC_CNT_11N, MASKDWORD);
1118 false_alm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
1119 false_alm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
1120 }
1121 #endif
1122
1123 {
1124 ret_value = odm_get_bb_reg(p_dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
1125 false_alm_cnt->cnt_cck_fail = ret_value;
1126
1127 ret_value = odm_get_bb_reg(p_dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
1128 false_alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
1129
1130 ret_value = odm_get_bb_reg(p_dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
1131 false_alm_cnt->cnt_cck_cca = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8);
1132 }
1133
1134 false_alm_cnt->cnt_all_pre = false_alm_cnt->cnt_all;
1135
1136 false_alm_cnt->cnt_all = (false_alm_cnt->cnt_fast_fsync +
1137 false_alm_cnt->cnt_sb_search_fail +
1138 false_alm_cnt->cnt_parity_fail +
1139 false_alm_cnt->cnt_rate_illegal +
1140 false_alm_cnt->cnt_crc8_fail +
1141 false_alm_cnt->cnt_mcs_fail +
1142 false_alm_cnt->cnt_cck_fail);
1143
1144 false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca + false_alm_cnt->cnt_cck_cca;
1145
1146 PHYDM_DBG(p_dm, DBG_FA_CNT,
1147 ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n",
1148 false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail));
1149
1150 }
1151 #endif
1152
1153 #if (ODM_IC_11AC_SERIES_SUPPORT == 1)
1154 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
1155 u32 cck_enable;
1156
1157 /* read OFDM FA counter */
1158 false_alm_cnt->cnt_ofdm_fail = odm_get_bb_reg(p_dm, ODM_REG_OFDM_FA_11AC, MASKLWORD);
1159
1160 /* Read CCK FA counter */
1161 false_alm_cnt->cnt_cck_fail = odm_get_bb_reg(p_dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1162
1163 /* read CCK/OFDM CCA counter */
1164 ret_value = odm_get_bb_reg(p_dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1165 false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1166 false_alm_cnt->cnt_cck_cca = ret_value & 0xffff;
1167
1168 /* read CCK CRC32 counter */
1169 ret_value = odm_get_bb_reg(p_dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
1170 false_alm_cnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
1171 false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff;
1172
1173 /* read OFDM CRC32 counter */
1174 ret_value = odm_get_bb_reg(p_dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
1175 false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1176 false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1177
1178 /* read HT CRC32 counter */
1179 ret_value = odm_get_bb_reg(p_dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
1180 false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1181 false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff;
1182
1183 /* read VHT CRC32 counter */
1184 ret_value = odm_get_bb_reg(p_dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
1185 false_alm_cnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
1186 false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff;
1187
1188 #if (RTL8881A_SUPPORT == 1)
1189 /* For 8881A */
1190 if (p_dm->support_ic_type == ODM_RTL8881A) {
1191 u32 cnt_ofdm_fail_temp = 0;
1192
1193 if (false_alm_cnt->cnt_ofdm_fail >= false_alm_cnt->cnt_ofdm_fail_pre) {
1194 cnt_ofdm_fail_temp = false_alm_cnt->cnt_ofdm_fail_pre;
1195 false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail;
1196 false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_ofdm_fail - cnt_ofdm_fail_temp;
1197 } else
1198 false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail;
1199 PHYDM_DBG(p_dm, DBG_FA_CNT, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail=%d\n", false_alm_cnt->cnt_ofdm_fail_pre));
1200 PHYDM_DBG(p_dm, DBG_FA_CNT, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail_pre=%d\n", cnt_ofdm_fail_temp));
1201 }
1202 #endif
1203 cck_enable = odm_get_bb_reg(p_dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1204 if (cck_enable) { /* if(*p_dm->p_band_type == ODM_BAND_2_4G) */
1205 false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail + false_alm_cnt->cnt_cck_fail;
1206 false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_cck_cca + false_alm_cnt->cnt_ofdm_cca;
1207 } else {
1208 false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail;
1209 false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca;
1210 }
1211 }
1212 #endif
1213
1214 #if (RTL8723D_SUPPORT == 1)
1215 if (p_dm->support_ic_type != ODM_RTL8723D) {
1216 if (phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/
1217 false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm);
1218 phydm_release_bb_dbg_port(p_dm);
1219 }
1220
1221 if (phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) {
1222 if (p_dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
1223 false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm) & BIT(30)) >> 30);
1224 else
1225 false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm) & BIT(29)) >> 29);
1226 phydm_release_bb_dbg_port(p_dm);
1227 }
1228 }
1229 #endif
1230
1231 phydm_false_alarm_counter_reg_reset(p_dm_void);
1232
1233 false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error;
1234 false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok + false_alm_cnt->cnt_ht_crc32_ok + false_alm_cnt->cnt_ofdm_crc32_ok + false_alm_cnt->cnt_cck_crc32_ok;
1235
1236 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1237 false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all));
1238
1239 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1240 false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all));
1241
1242 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[CCK] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_cck_crc32_error, false_alm_cnt->cnt_cck_crc32_ok));
1243 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[OFDM]CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ofdm_crc32_error, false_alm_cnt->cnt_ofdm_crc32_ok));
1244 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[ HT ] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ht_crc32_error, false_alm_cnt->cnt_ht_crc32_ok));
1245 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_vht_crc32_error, false_alm_cnt->cnt_vht_crc32_ok));
1246 PHYDM_DBG(p_dm, DBG_FA_CNT, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_crc32_error_all, false_alm_cnt->cnt_crc32_ok_all));
1247 PHYDM_DBG(p_dm, DBG_FA_CNT, ("FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag));
1248 }
1249
1250 #ifdef PHYDM_TDMA_DIG_SUPPORT
1251 void
phydm_set_tdma_dig_timer(void * p_dm_void)1252 phydm_set_tdma_dig_timer(
1253 void *p_dm_void
1254 )
1255 {
1256 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1257 u32 delta_time_us = p_dm->tdma_dig_timer_ms * 1000;
1258 struct phydm_dig_struct *p_dig_t;
1259 u32 timeout;
1260 u32 current_time_stamp, diff_time_stamp, regb0;
1261
1262 p_dig_t = &p_dm->dm_dig_table;
1263 /*some IC has no FREERUN_CUNT register, like 92E*/
1264 if (p_dm->support_ic_type & ODM_RTL8197F)
1265 current_time_stamp = odm_get_bb_reg(p_dm, 0x568, bMaskDWord);
1266 else
1267 return;
1268
1269 timeout = current_time_stamp + delta_time_us;
1270
1271 diff_time_stamp = current_time_stamp - p_dig_t->cur_timestamp;
1272 p_dig_t->pre_timestamp = p_dig_t->cur_timestamp;
1273 p_dig_t->cur_timestamp = current_time_stamp;
1274
1275 /*HIMR0, it shows HW interrupt mask*/
1276 regb0 = odm_get_bb_reg(p_dm, 0xb0, bMaskDWord);
1277
1278 PHYDM_DBG(p_dm, DBG_DIG,
1279 ("Set next tdma_dig_timer\n"));
1280 PHYDM_DBG(p_dm, DBG_DIG,
1281 ("current_time_stamp=%d, delta_time_us=%d, timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
1282 current_time_stamp,
1283 delta_time_us,
1284 timeout,
1285 diff_time_stamp,
1286 regb0));
1287
1288 if (p_dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
1289 odm_set_bb_reg(p_dm, 0x588, bMaskDWord, timeout);
1290 else {
1291 PHYDM_DBG(p_dm, DBG_DIG,
1292 ("NOT 97F, TDMA-DIG timer does NOT start!\n"));
1293 return;
1294 }
1295 }
1296
1297 void
phydm_tdma_dig_timer_check(void * p_dm_void)1298 phydm_tdma_dig_timer_check(
1299 void *p_dm_void
1300 )
1301 {
1302 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1303 struct phydm_dig_struct *p_dig_t;
1304
1305 p_dig_t = &p_dm->dm_dig_table;
1306
1307 PHYDM_DBG(p_dm, DBG_DIG,
1308 ("tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
1309 p_dig_t->tdma_dig_cnt,
1310 p_dig_t->pre_tdma_dig_cnt));
1311
1312 if ((p_dig_t->tdma_dig_cnt == 0) ||
1313 (p_dig_t->tdma_dig_cnt == p_dig_t->pre_tdma_dig_cnt)) {
1314
1315 if (p_dm->support_ability & ODM_BB_DIG) {
1316 /*if interrupt mask info is got.*/
1317 /*Reg0xb0 is no longer needed*/
1318 /*regb0 = odm_get_bb_reg(p_dm, 0xb0, bMaskDWord);*/
1319 PHYDM_DBG(p_dm, DBG_DIG,
1320 ("Check fail, IntMask[0]=0x%x, restart tdma_dig_timer !!!\n",
1321 *p_dm->p_interrupt_mask));
1322
1323 phydm_tdma_dig_add_interrupt_mask_handler(p_dm);
1324 phydm_enable_rx_related_interrupt_handler(p_dm);
1325 phydm_set_tdma_dig_timer(p_dm);
1326 }
1327 } else
1328 PHYDM_DBG(p_dm, DBG_DIG,
1329 ("Check pass, update pre_tdma_dig_cnt\n"));
1330
1331 p_dig_t->pre_tdma_dig_cnt = p_dig_t->tdma_dig_cnt;
1332 }
1333
1334 /*different IC/team may use different timer for tdma-dig*/
1335 void
phydm_tdma_dig_add_interrupt_mask_handler(void * p_dm_void)1336 phydm_tdma_dig_add_interrupt_mask_handler(
1337 void *p_dm_void
1338 )
1339 {
1340 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1341
1342 #if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
1343 if (p_dm->support_ic_type & ODM_RTL8197F)
1344 phydm_add_interrupt_mask_handler(p_dm, HAL_INT_TYPE_PSTIMEOUT2); /*HAL_INT_TYPE_PSTIMEOUT2*/
1345 #elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
1346 #elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
1347 #endif
1348 }
1349
1350 void
phydm_tdma_dig(void * p_dm_void)1351 phydm_tdma_dig(
1352 void *p_dm_void
1353 )
1354 {
1355 struct PHY_DM_STRUCT *p_dm;
1356 struct phydm_dig_struct *p_dig_t;
1357 struct phydm_fa_struct *p_falm_cnt;
1358 u32 reg_c50;
1359
1360 p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1361 p_dig_t = &p_dm->dm_dig_table;
1362 p_falm_cnt = &p_dm->false_alm_cnt;
1363 reg_c50 = odm_get_bb_reg(p_dm, 0xc50, MASKBYTE0);
1364
1365 p_dig_t->tdma_dig_state =
1366 p_dig_t->tdma_dig_cnt % p_dm->tdma_dig_state_number;
1367
1368 PHYDM_DBG(p_dm, DBG_DIG,
1369 ("tdma_dig_state=%d, regc50=0x%x\n",
1370 p_dig_t->tdma_dig_state,
1371 reg_c50));
1372
1373 p_dig_t->tdma_dig_cnt++;
1374
1375 if (p_dig_t->tdma_dig_state == 1) {
1376 // update IGI from tdma_dig_state == 0
1377 if (p_dig_t->cur_ig_value_tdma == 0)
1378 p_dig_t->cur_ig_value_tdma = p_dig_t->cur_ig_value;
1379
1380 odm_write_dig(p_dm, p_dig_t->cur_ig_value_tdma);
1381 phydm_tdma_false_alarm_counter_check(p_dm);
1382 PHYDM_DBG(p_dm, DBG_DIG,
1383 ("tdma_dig_state=%d, reset FA counter !!!\n",
1384 p_dig_t->tdma_dig_state));
1385
1386 } else if (p_dig_t->tdma_dig_state == 0) {
1387 /* update p_dig_t->CurIGValue,*/
1388 /* it may different from p_dig_t->cur_ig_value_tdma */
1389 /* TDMA IGI upperbond @ L-state = */
1390 /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
1391
1392 if (p_dig_t->cur_ig_value >= p_dm->tdma_dig_low_upper_bond)
1393 p_dig_t->low_ig_value = p_dm->tdma_dig_low_upper_bond;
1394 else
1395 p_dig_t->low_ig_value = p_dig_t->cur_ig_value;
1396
1397 odm_write_dig(p_dm, p_dig_t->low_ig_value);
1398 phydm_tdma_false_alarm_counter_check(p_dm);
1399 } else
1400 phydm_tdma_false_alarm_counter_check(p_dm);
1401 }
1402
1403 /*============================================================*/
1404 /*FASLE ALARM CHECK*/
1405 /*============================================================*/
1406
1407 void
phydm_tdma_false_alarm_counter_check(void * p_dm_void)1408 phydm_tdma_false_alarm_counter_check(
1409 void *p_dm_void
1410 )
1411 {
1412 struct PHY_DM_STRUCT *p_dm;
1413 struct phydm_fa_struct *p_falm_cnt;
1414 struct phydm_fa_acc_struct *p_falm_cnt_acc;
1415 struct phydm_dig_struct *p_dig_t;
1416 boolean rssi_dump_en = 0;
1417 u32 timestamp;
1418 u8 tdma_dig_state_number;
1419
1420 p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1421 p_falm_cnt = &p_dm->false_alm_cnt;
1422 p_falm_cnt_acc = &p_dm->false_alm_cnt_acc;
1423 p_dig_t = &p_dm->dm_dig_table;
1424
1425 if (p_dig_t->tdma_dig_state == 1)
1426 phydm_false_alarm_counter_reset(p_dm);
1427 /* Reset FalseAlarmCounterStatistics */
1428 /* fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
1429 /* fa_end_tsf = fa_start_tsf = TSF */
1430 else {
1431 odm_false_alarm_counter_statistics(p_dm);
1432 if (p_dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
1433 timestamp = odm_get_bb_reg(p_dm, 0x568, bMaskDWord);
1434 else {
1435 PHYDM_DBG(p_dm, DBG_DIG,
1436 ("Caution! NOT 97F! TDMA-DIG timer does NOT start!!!\n"));
1437 return;
1438 }
1439 p_dig_t->fa_end_timestamp = timestamp;
1440 p_dig_t->fa_acc_1sec_timestamp +=
1441 (p_dig_t->fa_end_timestamp - p_dig_t->fa_start_timestamp);
1442
1443 /*prevent dumb*/
1444 if (p_dm->tdma_dig_state_number == 1)
1445 p_dm->tdma_dig_state_number = 2;
1446
1447 tdma_dig_state_number = p_dm->tdma_dig_state_number;
1448 p_dig_t->sec_factor =
1449 tdma_dig_state_number / (tdma_dig_state_number - 1);
1450
1451 /*1sec = 1000000us*/
1452 if (p_dig_t->fa_acc_1sec_timestamp >= (u32)(1000000 / p_dig_t->sec_factor)) {
1453 rssi_dump_en = 1;
1454 phydm_false_alarm_counter_acc(p_dm, rssi_dump_en);
1455 PHYDM_DBG(p_dm, DBG_DIG,
1456 ("sec_factor = %u, total FA = %u, is_linked=%u\n",
1457 p_dig_t->sec_factor,
1458 p_falm_cnt_acc->cnt_all,
1459 p_dm->is_linked));
1460
1461 phydm_noisy_detection(p_dm);
1462 phydm_cck_pd_th(p_dm);
1463 phydm_dig(p_dm);
1464 phydm_false_alarm_counter_acc_reset(p_dm);
1465
1466 /* Reset FalseAlarmCounterStatistics */
1467 /* fa_end_tsf = fa_start_tsf = TSF, keep */
1468 /* fa_acc_1sec_tsf = 0 */
1469 phydm_false_alarm_counter_reset(p_dm);
1470 } else
1471 phydm_false_alarm_counter_acc(p_dm, rssi_dump_en);
1472 }
1473 }
1474
1475 void
phydm_false_alarm_counter_acc(void * p_dm_void,boolean rssi_dump_en)1476 phydm_false_alarm_counter_acc(
1477 void *p_dm_void,
1478 boolean rssi_dump_en
1479 )
1480 {
1481 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1482 struct phydm_fa_struct *p_falm_cnt;
1483 struct phydm_fa_acc_struct *p_falm_cnt_acc;
1484 struct phydm_dig_struct *p_dig_t;
1485
1486 p_falm_cnt = &p_dm->false_alm_cnt;
1487 p_falm_cnt_acc = &p_dm->false_alm_cnt_acc;
1488 p_dig_t = &p_dm->dm_dig_table;
1489
1490 p_falm_cnt_acc->cnt_parity_fail += p_falm_cnt->cnt_parity_fail;
1491 p_falm_cnt_acc->cnt_rate_illegal += p_falm_cnt->cnt_rate_illegal;
1492 p_falm_cnt_acc->cnt_crc8_fail += p_falm_cnt->cnt_crc8_fail;
1493 p_falm_cnt_acc->cnt_mcs_fail += p_falm_cnt->cnt_mcs_fail;
1494 p_falm_cnt_acc->cnt_ofdm_fail += p_falm_cnt->cnt_ofdm_fail;
1495 p_falm_cnt_acc->cnt_cck_fail += p_falm_cnt->cnt_cck_fail;
1496 p_falm_cnt_acc->cnt_all += p_falm_cnt->cnt_all;
1497 p_falm_cnt_acc->cnt_fast_fsync += p_falm_cnt->cnt_fast_fsync;
1498 p_falm_cnt_acc->cnt_sb_search_fail += p_falm_cnt->cnt_sb_search_fail;
1499 p_falm_cnt_acc->cnt_ofdm_cca += p_falm_cnt->cnt_ofdm_cca;
1500 p_falm_cnt_acc->cnt_cck_cca += p_falm_cnt->cnt_cck_cca;
1501 p_falm_cnt_acc->cnt_cca_all += p_falm_cnt->cnt_cca_all;
1502 p_falm_cnt_acc->cnt_cck_crc32_error += p_falm_cnt->cnt_cck_crc32_error;
1503 p_falm_cnt_acc->cnt_cck_crc32_ok += p_falm_cnt->cnt_cck_crc32_ok;
1504 p_falm_cnt_acc->cnt_ofdm_crc32_error += p_falm_cnt->cnt_ofdm_crc32_error;
1505 p_falm_cnt_acc->cnt_ofdm_crc32_ok += p_falm_cnt->cnt_ofdm_crc32_ok;
1506 p_falm_cnt_acc->cnt_ht_crc32_error += p_falm_cnt->cnt_ht_crc32_error;
1507 p_falm_cnt_acc->cnt_ht_crc32_ok += p_falm_cnt->cnt_ht_crc32_ok;
1508 p_falm_cnt_acc->cnt_vht_crc32_error += p_falm_cnt->cnt_vht_crc32_error;
1509 p_falm_cnt_acc->cnt_vht_crc32_ok += p_falm_cnt->cnt_vht_crc32_ok;
1510 p_falm_cnt_acc->cnt_crc32_error_all += p_falm_cnt->cnt_crc32_error_all;
1511 p_falm_cnt_acc->cnt_crc32_ok_all += p_falm_cnt->cnt_crc32_ok_all;
1512
1513 if (rssi_dump_en == 1) {
1514 p_falm_cnt_acc->cnt_all_1sec =
1515 p_falm_cnt_acc->cnt_all * p_dig_t->sec_factor;
1516 p_falm_cnt_acc->cnt_cca_all_1sec =
1517 p_falm_cnt_acc->cnt_cca_all * p_dig_t->sec_factor;
1518 p_falm_cnt_acc->cnt_cck_fail_1sec =
1519 p_falm_cnt_acc->cnt_cck_fail * p_dig_t->sec_factor;
1520 }
1521 }
1522
1523 void
phydm_false_alarm_counter_acc_reset(void * p_dm_void)1524 phydm_false_alarm_counter_acc_reset(
1525 void *p_dm_void
1526 )
1527 {
1528 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1529 struct phydm_fa_acc_struct *p_falm_cnt_acc;
1530
1531 p_falm_cnt_acc = &p_dm->false_alm_cnt_acc;
1532
1533 /* Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
1534 /* do NOT need to be reset */
1535 odm_memory_set(p_dm, p_falm_cnt_acc, 0, sizeof(p_falm_cnt_acc));
1536 }
1537
1538 void
phydm_false_alarm_counter_reset(void * p_dm_void)1539 phydm_false_alarm_counter_reset(
1540 void *p_dm_void
1541 )
1542 {
1543 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1544 struct phydm_fa_struct *p_falm_cnt;
1545 struct phydm_dig_struct *p_dig_t;
1546 u32 timestamp;
1547
1548 p_falm_cnt = &p_dm->false_alm_cnt;
1549 p_dig_t = &p_dm->dm_dig_table;
1550
1551 memset(p_falm_cnt, 0, sizeof(p_dm->false_alm_cnt));
1552 phydm_false_alarm_counter_reg_reset(p_dm);
1553
1554 if (p_dig_t->tdma_dig_state != 1)
1555 p_dig_t->fa_acc_1sec_timestamp = 0;
1556 else
1557 p_dig_t->fa_acc_1sec_timestamp = p_dig_t->fa_acc_1sec_timestamp;
1558
1559 /*REG_FREERUN_CNT*/
1560 timestamp = odm_get_bb_reg(p_dm, 0x568, bMaskDWord);
1561 p_dig_t->fa_start_timestamp = timestamp;
1562 p_dig_t->fa_end_timestamp = timestamp;
1563 }
1564
1565 #endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
1566
1567 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1568 void
phydm_lna_sat_chk_init(void * p_dm_void)1569 phydm_lna_sat_chk_init(
1570 void *p_dm_void
1571 )
1572 {
1573 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1574
1575 struct phydm_lna_sat_info_struct *p_lna_info = &p_dm->dm_lna_sat_info;
1576
1577 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("%s ==>\n", __FUNCTION__));
1578
1579 p_lna_info->check_time = 0;
1580 p_lna_info->sat_cnt_acc_patha = 0;
1581 p_lna_info->sat_cnt_acc_pathb = 0;
1582 p_lna_info->cur_sat_status = 0;
1583 p_lna_info->pre_sat_status = 0;
1584 p_lna_info->cur_timer_check_cnt = 0;
1585 p_lna_info->pre_timer_check_cnt = 0;
1586 }
1587
1588 void
phydm_set_ofdm_agc_tab(void * p_dm_void,u8 tab_sel)1589 phydm_set_ofdm_agc_tab(
1590 void *p_dm_void,
1591 u8 tab_sel
1592 )
1593 {
1594 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1595
1596 /* table sel:0/2, 1 is used for CCK */
1597 if (tab_sel == OFDM_AGC_TAB_0)
1598 odm_set_bb_reg(p_dm, 0xc70, 0x1e00, OFDM_AGC_TAB_0);
1599 else if (tab_sel == OFDM_AGC_TAB_2)
1600 odm_set_bb_reg(p_dm, 0xc70, 0x1e00, OFDM_AGC_TAB_2);
1601 else
1602 odm_set_bb_reg(p_dm, 0xc70, 0x1e00, OFDM_AGC_TAB_0);
1603 }
1604
1605 u8
phydm_get_ofdm_agc_tab(void * p_dm_void)1606 phydm_get_ofdm_agc_tab(
1607 void *p_dm_void
1608 )
1609 {
1610 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1611
1612 return (u1Byte)odm_get_bb_reg(p_dm, 0xc70, 0x1e00);
1613 }
1614
1615 void
phydm_lna_sat_chk(void * p_dm_void)1616 phydm_lna_sat_chk(
1617 void *p_dm_void
1618 )
1619 {
1620 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1621 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
1622 struct phydm_lna_sat_info_struct *p_lna_info = &p_dm->dm_lna_sat_info;
1623
1624 u1Byte igi_rssi_min, rssi_min = p_dm->rssi_min;
1625 u4Byte sat_status_patha, sat_status_pathb;
1626 u1Byte igi_restore = p_dig_t->cur_ig_value;
1627 u1Byte i, lna_sat_chk_cnt = p_dm->lna_sat_chk_cnt;
1628 u4Byte lna_sat_cnt_thd = 0;
1629 u1Byte agc_tab;
1630 u4Byte max_check_time = 0;
1631
1632 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("\n%s ==>\n", __FUNCTION__));
1633
1634 if (!(p_dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
1635 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1636 ("support ability is disabled, return.\n"));
1637 return;
1638 }
1639
1640 if (p_dm->is_disable_lna_sat_chk) {
1641 phydm_lna_sat_chk_init(p_dm);
1642 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1643 ("is_disable_lna_sat_chk=%d, return.\n", p_dm->is_disable_lna_sat_chk));
1644 return;
1645 }
1646
1647 //func_start = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord);
1648
1649 // move igi to target pin of rssi_min
1650 if ((rssi_min == 0) || (rssi_min == 0xff)) {
1651 // adapt agc table 0
1652 phydm_set_ofdm_agc_tab(p_dm, OFDM_AGC_TAB_0);
1653 phydm_lna_sat_chk_init(p_dm);
1654 return;
1655 } else if (rssi_min % 2 != 0)
1656 igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1;
1657 else
1658 igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI;
1659
1660 if ((p_dm->lna_sat_chk_period_ms > 0) && (p_dm->lna_sat_chk_period_ms <= ONE_SEC_MS))
1661 max_check_time = lna_sat_chk_cnt*(ONE_SEC_MS/(p_dm->lna_sat_chk_period_ms))*5;
1662 else
1663 max_check_time = lna_sat_chk_cnt * 5;
1664
1665 lna_sat_cnt_thd = (max_check_time * p_dm->lna_sat_chk_duty_cycle)/100;
1666
1667 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1668 ("check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nlna_sat_chk_cnt=%d, lna_sat_chk_period_ms=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n",
1669 p_lna_info->check_time,
1670 rssi_min,
1671 igi_rssi_min,
1672 lna_sat_chk_cnt,
1673 p_dm->lna_sat_chk_period_ms,
1674 max_check_time,
1675 lna_sat_cnt_thd));
1676
1677 odm_write_dig(p_dm, igi_rssi_min);
1678
1679 // adapt agc table 0 check saturation status
1680 phydm_set_ofdm_agc_tab(p_dm, OFDM_AGC_TAB_0);
1681 // open rf power detection ckt & set detection range
1682 odm_set_rf_reg(p_dm, RF_PATH_A, 0x86, 0x1f, 0x10);
1683 odm_set_rf_reg(p_dm, RF_PATH_B, 0x86, 0x1f, 0x10);
1684
1685 // check saturation status
1686 for (i = 0; i < lna_sat_chk_cnt; i++) {
1687 sat_status_patha = odm_get_rf_reg(p_dm, RF_PATH_A, 0xae, 0xc0000);
1688 sat_status_pathb = odm_get_rf_reg(p_dm, RF_PATH_B, 0xae, 0xc0000);
1689 if (sat_status_patha != 0)
1690 p_lna_info->sat_cnt_acc_patha++;
1691 if (sat_status_pathb != 0)
1692 p_lna_info->sat_cnt_acc_pathb++;
1693
1694 if ((p_lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd) ||
1695 (p_lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd)) {
1696 p_lna_info->cur_sat_status = 1;
1697 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1698 ("cur_sat_status=%d, check_time=%d\n",
1699 p_lna_info->cur_sat_status,
1700 p_lna_info->check_time));
1701 break;
1702 } else
1703 p_lna_info->cur_sat_status = 0;
1704 }
1705
1706 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1707 ("cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n",
1708 p_lna_info->cur_sat_status,
1709 p_lna_info->pre_sat_status,
1710 p_lna_info->sat_cnt_acc_patha,
1711 p_lna_info->sat_cnt_acc_pathb));
1712
1713 // agc table decision
1714 if (p_lna_info->cur_sat_status) {
1715 if (!p_dm->is_disable_gain_table_switch)
1716 phydm_set_ofdm_agc_tab(p_dm, OFDM_AGC_TAB_2);
1717 p_lna_info->check_time = 0;
1718 p_lna_info->sat_cnt_acc_patha = 0;
1719 p_lna_info->sat_cnt_acc_pathb = 0;
1720 p_lna_info->pre_sat_status = p_lna_info->cur_sat_status;
1721
1722 } else if (p_lna_info->check_time <= (max_check_time - 1)) {
1723 if (p_lna_info->pre_sat_status && (!p_dm->is_disable_gain_table_switch))
1724 phydm_set_ofdm_agc_tab(p_dm, OFDM_AGC_TAB_2);
1725 p_lna_info->check_time++;
1726
1727 } else if (p_lna_info->check_time == max_check_time) {
1728 if (!p_dm->is_disable_gain_table_switch && (p_lna_info->pre_sat_status == 1))
1729 phydm_set_ofdm_agc_tab(p_dm, OFDM_AGC_TAB_0);
1730 p_lna_info->check_time = 0;
1731 p_lna_info->sat_cnt_acc_patha = 0;
1732 p_lna_info->sat_cnt_acc_pathb = 0;
1733 p_lna_info->pre_sat_status = p_lna_info->cur_sat_status;
1734 }
1735
1736 agc_tab = phydm_get_ofdm_agc_tab(p_dm);
1737
1738 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("use AGC tab %d\n", agc_tab));
1739 //func_end = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord);
1740
1741 //PHYDM_DBG(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("function process time=%d\n",
1742 // func_end - func_start));
1743
1744 // restore previous igi
1745 odm_write_dig(p_dm, igi_restore);
1746 p_lna_info->cur_timer_check_cnt++;
1747 odm_set_timer(p_dm, &p_lna_info->phydm_lna_sat_chk_timer, p_dm->lna_sat_chk_period_ms);
1748 }
1749
1750 void
phydm_lna_sat_chk_callback(void * p_dm_void)1751 phydm_lna_sat_chk_callback(
1752 void *p_dm_void
1753
1754 )
1755 {
1756 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1757
1758 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("\n%s ==>\n", __FUNCTION__));
1759 phydm_lna_sat_chk(p_dm);
1760 }
1761
1762 void
phydm_lna_sat_chk_timers(void * p_dm_void,u8 state)1763 phydm_lna_sat_chk_timers(
1764 void *p_dm_void,
1765 u8 state
1766 )
1767 {
1768 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1769 struct phydm_lna_sat_info_struct *p_lna_info = &p_dm->dm_lna_sat_info;
1770
1771 if (state == INIT_LNA_SAT_CHK_TIMMER) {
1772 odm_initialize_timer(p_dm, &(p_lna_info->phydm_lna_sat_chk_timer),
1773 (void *)phydm_lna_sat_chk_callback, NULL, "phydm_lna_sat_chk_timer");
1774 } else if (state == CANCEL_LNA_SAT_CHK_TIMMER) {
1775 odm_cancel_timer(p_dm, &(p_lna_info->phydm_lna_sat_chk_timer));
1776 } else if (state == RELEASE_LNA_SAT_CHK_TIMMER) {
1777 odm_release_timer(p_dm, &(p_lna_info->phydm_lna_sat_chk_timer));
1778 }
1779 }
1780
1781 void
phydm_lna_sat_chk_watchdog(void * p_dm_void)1782 phydm_lna_sat_chk_watchdog(
1783 void *p_dm_void
1784 )
1785 {
1786 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1787 struct phydm_lna_sat_info_struct *p_lna_info = &p_dm->dm_lna_sat_info;
1788
1789 u1Byte rssi_min = p_dm->rssi_min;
1790
1791 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("\n%s ==>\n", __FUNCTION__));
1792
1793 if (!(p_dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
1794 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1795 ("support ability is disabled, return.\n"));
1796 return;
1797 }
1798
1799 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n",
1800 p_lna_info->pre_timer_check_cnt,
1801 p_lna_info->cur_timer_check_cnt));
1802
1803 if (p_dm->is_disable_lna_sat_chk) {
1804 phydm_lna_sat_chk_init(p_dm);
1805 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1806 ("is_disable_lna_sat_chk=%d, return.\n", p_dm->is_disable_lna_sat_chk));
1807 return;
1808 }
1809
1810 if ((p_dm->support_ic_type & ODM_RTL8197F) == 0) {
1811 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1812 ("SupportICType != ODM_RTL8197F, return.\n"));
1813 return;
1814 }
1815
1816 if ((rssi_min == 0) || (rssi_min == 0xff)) {
1817 // adapt agc table 0
1818 phydm_set_ofdm_agc_tab(p_dm, OFDM_AGC_TAB_0);
1819 phydm_lna_sat_chk_init(p_dm);
1820 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK,
1821 ("rssi_min=%d, return.\n", rssi_min));
1822 return;
1823 }
1824
1825 if (p_lna_info->cur_timer_check_cnt == p_lna_info->pre_timer_check_cnt) {
1826 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("Timer check fail, restart timer.\n"));
1827 phydm_lna_sat_chk(p_dm);
1828 } else {
1829 PHYDM_DBG(p_dm, DBG_LNA_SAT_CHK, ("Timer check pass.\n"));
1830 }
1831 p_lna_info->pre_timer_check_cnt = p_lna_info->cur_timer_check_cnt;
1832 }
1833 #endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
1834
1835 void
phydm_dig_debug(void * p_dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len,u32 input_num)1836 phydm_dig_debug(
1837 void *p_dm_void,
1838 char input[][16],
1839 u32 *_used,
1840 char *output,
1841 u32 *_out_len,
1842 u32 input_num
1843 )
1844 {
1845 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1846 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
1847 char help[] = "-h";
1848 char monitor[] = "-m";
1849 u32 var1[10] = {0};
1850 u32 used = *_used;
1851 u32 out_len = *_out_len;
1852 u8 i;
1853
1854 if ((strcmp(input[1], help) == 0))
1855 PHYDM_SNPRINTF((output + used, out_len - used, "{0} fa[0] fa[1] fa[2]\n"));
1856 else if ((strcmp(input[1], monitor) == 0)) {
1857 PHYDM_SNPRINTF((output + used, out_len - used,
1858 "Read DIG fa_th[0:2]= {%d, %d, %d}\n",
1859 p_dig_t->fa_th[0], p_dig_t->fa_th[1], p_dig_t->fa_th[2]));
1860
1861 } else {
1862
1863 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
1864
1865 for (i = 1; i < 10; i++) {
1866 if (input[i + 1])
1867 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
1868 }
1869
1870 if (var1[0] == 0) {
1871 p_dig_t->is_dbg_fa_th = true;
1872 p_dig_t->fa_th[0] = (u16)var1[1];
1873 p_dig_t->fa_th[1] = (u16)var1[2];
1874 p_dig_t->fa_th[2] = (u16)var1[3];
1875
1876 PHYDM_SNPRINTF((output + used, out_len - used,
1877 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
1878 p_dig_t->fa_th[0], p_dig_t->fa_th[1], p_dig_t->fa_th[2]));
1879 } else
1880 p_dig_t->is_dbg_fa_th = false;
1881 }
1882 *_used = used;
1883 *_out_len = out_len;
1884 }
1885
1886