1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19 #include "mp_precomp.h"
20 #include "phydm_precomp.h"
21
22 void
phydm_dynamic_tx_power_init(void * p_dm_void)23 phydm_dynamic_tx_power_init(
24 void *p_dm_void
25 )
26 {
27 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
28 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
29 struct _ADAPTER *adapter = p_dm->adapter;
30 PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
31 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
32
33 /*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/
34 /* PHYDM_DBG(p_dm,DBG_DYN_TXPWR, */
35 /* ("phydm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/
36 /* return;*/
37 /*} else*/
38 {
39 p_mgnt_info->bDynamicTxPowerEnable = true;
40 PHYDM_DBG(p_dm, DBG_DYN_TXPWR,
41 ("phydm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable));
42 }
43
44 #if DEV_BUS_TYPE == RT_USB_INTERFACE
45 if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) {
46 odm_dynamic_tx_power_save_power_index(p_dm);
47 p_mgnt_info->bDynamicTxPowerEnable = true;
48 } else
49 #else
50 /* so 92c pci do not need dynamic tx power? vivi check it later */
51 p_mgnt_info->bDynamicTxPowerEnable = false;
52 #endif
53
54
55 p_hal_data->LastDTPLvl = tx_high_pwr_level_normal;
56 p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
57
58 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
59
60 p_dm->last_dtp_lvl = tx_high_pwr_level_normal;
61 p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
62 p_dm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
63
64 #endif
65
66 }
67
68 void
odm_dynamic_tx_power_save_power_index(void * p_dm_void)69 odm_dynamic_tx_power_save_power_index(
70 void *p_dm_void
71 )
72 {
73 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
74 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
75 u8 index;
76 u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
77
78 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
79 struct _ADAPTER *adapter = p_dm->adapter;
80 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
81 for (index = 0; index < 6; index++)
82 p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]);
83
84
85 #endif
86 #endif
87 }
88
89 void
odm_dynamic_tx_power_restore_power_index(void * p_dm_void)90 odm_dynamic_tx_power_restore_power_index(
91 void *p_dm_void
92 )
93 {
94 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
95 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
96 u8 index;
97 struct _ADAPTER *adapter = p_dm->adapter;
98 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
99 u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
100
101 for (index = 0; index < 6; index++)
102 PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]);
103
104
105
106 #endif
107 }
108
109 void
odm_dynamic_tx_power_write_power_index(void * p_dm_void,u8 value)110 odm_dynamic_tx_power_write_power_index(
111 void *p_dm_void,
112 u8 value)
113 {
114 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
115 u8 index;
116 u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
117
118 for (index = 0; index < 6; index++)
119 /* platform_efio_write_1byte(adapter, power_index_reg[index], value); */
120 odm_write_1byte(p_dm, power_index_reg[index], value);
121
122 }
123
124 void
odm_dynamic_tx_power_nic_ce(void * p_dm_void)125 odm_dynamic_tx_power_nic_ce(
126 void *p_dm_void
127 )
128 {
129 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
130 #if (RTL8821A_SUPPORT == 1)
131 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
132 u8 val;
133 u8 rssi_tmp = p_dm->rssi_min;
134
135 if (!(p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
136 return;
137
138 if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
139 p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2;
140 /**/
141 } else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
142 p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1;
143 /**/
144 } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
145 p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
146 /**/
147 }
148
149 if (p_dm->last_dtp_lvl != p_dm->dynamic_tx_high_power_lvl) {
150
151 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm->last_dtp_lvl, p_dm->dynamic_tx_high_power_lvl));
152
153 p_dm->last_dtp_lvl = p_dm->dynamic_tx_high_power_lvl;
154
155 if (p_dm->support_ic_type & (ODM_RTL8821)) {
156
157 if (p_dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) {
158
159 odm_set_mac_reg(p_dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
160
161 val = p_dm->tx_agc_ofdm_18_6 & 0xff;
162 if (val >= 0x20)
163 val -= 0x16;
164
165 odm_set_bb_reg(p_dm, 0xC24, 0xff, val);
166 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Set TX power: level 2\n"));
167 } else if (p_dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) {
168
169 odm_set_mac_reg(p_dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
170
171 val = p_dm->tx_agc_ofdm_18_6 & 0xff;
172 if (val >= 0x20)
173 val -= 0x10;
174
175 odm_set_bb_reg(p_dm, 0xC24, 0xff, val);
176 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Set TX power: level 1\n"));
177 } else if (p_dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) {
178
179 odm_set_mac_reg(p_dm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/
180 odm_set_bb_reg(p_dm, 0xC24, MASKDWORD, p_dm->tx_agc_ofdm_18_6);
181 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Set TX power: normal\n"));
182 }
183 }
184 }
185
186 #endif
187 #endif
188 }
189
190
191 void
odm_dynamic_tx_power(void * p_dm_void)192 odm_dynamic_tx_power(
193 void *p_dm_void
194 )
195 {
196 /* */
197 /* For AP/ADSL use struct rtl8192cd_priv* */
198 /* For CE/NIC use struct _ADAPTER* */
199 /* */
200 /* struct _ADAPTER* p_adapter = p_dm->adapter;
201 * struct rtl8192cd_priv* priv = p_dm->priv; */
202 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
203
204 if (!(p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
205 return;
206 /* */
207 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
208 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
209 /* HW dynamic mechanism. */
210 /* */
211 switch (p_dm->support_platform) {
212 case ODM_WIN:
213 odm_dynamic_tx_power_nic(p_dm);
214 break;
215 case ODM_CE:
216 odm_dynamic_tx_power_nic_ce(p_dm);
217 break;
218 default:
219 break;
220 }
221
222
223 }
224
225
226 void
odm_dynamic_tx_power_nic(void * p_dm_void)227 odm_dynamic_tx_power_nic(
228 void *p_dm_void
229 )
230 {
231 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
232
233 if (!(p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
234 return;
235
236 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
237
238 if (p_dm->support_ic_type == ODM_RTL8814A)
239 odm_dynamic_tx_power_8814a(p_dm);
240 else if (p_dm->support_ic_type & ODM_RTL8821) {
241 struct _ADAPTER *adapter = p_dm->adapter;
242 PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter);
243
244 if (p_mgnt_info->RegRspPwr == 1) {
245 if (p_dm->rssi_min > 60)
246 odm_set_mac_reg(p_dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/
247 else if (p_dm->rssi_min < 55)
248 odm_set_mac_reg(p_dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/
249 }
250 }
251 #endif
252 }
253
254
255 void
odm_dynamic_tx_power_8821(void * p_dm_void,u8 * p_desc,u8 mac_id)256 odm_dynamic_tx_power_8821(
257 void *p_dm_void,
258 u8 *p_desc,
259 u8 mac_id
260 )
261 {
262 #if (RTL8821A_SUPPORT == 1)
263 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
264 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
265 struct cmn_sta_info *p_entry;
266 u8 reg0xc56_byte;
267 u8 txpwr_offset = 0;
268
269 p_entry = p_dm->p_phydm_sta_info[mac_id];
270
271 reg0xc56_byte = odm_read_1byte(p_dm, 0xc56);
272
273 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("reg0xc56_byte=%d\n", reg0xc56_byte));
274
275 if (p_entry[mac_id].rssi_stat.rssi > 85) {
276
277 /* Avoid TXAGC error after TX power offset is applied.
278 For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
279 Total power = 6-11= -5( overflow!! ), PA may be burned !
280 so txpwr_offset should be adjusted by Reg0xc56*/
281
282 if (reg0xc56_byte < 7)
283 txpwr_offset = 1;
284 else if (reg0xc56_byte < 11)
285 txpwr_offset = 2;
286 else
287 txpwr_offset = 3;
288
289 SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
290 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.rssi, txpwr_offset));
291
292 } else {
293 SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
294 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.rssi, txpwr_offset));
295
296 }
297 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
298 #endif /*#if (RTL8821A_SUPPORT==1)*/
299 }
300
301 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
302 void
odm_dynamic_tx_power_8814a(void * p_dm_void)303 odm_dynamic_tx_power_8814a(
304 void *p_dm_void
305 )
306 {
307 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
308 struct _ADAPTER *adapter = p_dm->adapter;
309 PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
310 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
311 s32 undecorated_smoothed_pwdb;
312
313 PHYDM_DBG(p_dm, DBG_DYN_TXPWR,
314 ("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n",
315 p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable));
316
317 /*STA not connected and AP not connected*/
318 if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) {
319 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Not connected to any reset power lvl\n"));
320 p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
321 return;
322 }
323
324
325 if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
326 p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
327 else {
328 if (p_mgnt_info->bMediaConnect) { /*Default port*/
329 if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) {
330 undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
331 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb));
332 } else {
333 undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB;
334 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
335 }
336 } else {/*associated entry pwdb*/
337 undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
338 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
339 }
340
341 /*Should we separate as 2.4G/5G band?*/
342
343 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
344 p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2;
345 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n"));
346 } else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
347 (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
348 p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1;
349 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n"));
350 } else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
351 p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
352 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("tx_high_pwr_level_normal\n"));
353 }
354 }
355
356
357 if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) {
358 PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel));
359 odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl);
360 }
361
362
363 PHYDM_DBG(p_dm, DBG_DYN_TXPWR,
364 ("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n",
365 p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl));
366
367 p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl;
368
369 }
370
371
372
373 /**/
374 /*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
375 /**/
376 /**/
377 void
odm_set_tx_power_level8814(struct _ADAPTER * adapter,u8 channel,u8 pwr_lvl)378 odm_set_tx_power_level8814(
379 struct _ADAPTER *adapter,
380 u8 channel,
381 u8 pwr_lvl
382 )
383 {
384 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
385 u32 i, j, k = 0;
386 u32 value[264] = {0};
387 u32 path = 0, power_index, txagc_table_wd = 0x00801000;
388
389 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
390
391 u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
392 {MGN_6M, MGN_9M, MGN_12M, MGN_18M},
393 {MGN_24M, MGN_36M, MGN_48M, MGN_54M},
394 {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
395 {MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
396 {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
397 {MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
398 {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
399 {MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
400 {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
401 {MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
402 {MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
403 {MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
404 {MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
405 {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
406 {MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
407 {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0}
408 };
409
410 for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
411
412 u8 usb_host = UsbModeQueryHubUsbType(adapter);
413 u8 usb_rfset = UsbModeQueryRfSet(adapter);
414 u8 usb_rf_type = RT_GetRFType(adapter);
415
416 for (i = 0; i <= 16; i++) {
417 for (j = 0; j <= 3; j++) {
418 if (jaguar2_rates[i][j] == 0)
419 continue;
420
421 txagc_table_wd = 0x00801000;
422 power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel);
423
424 /*for Query bus type to recude tx power.*/
425 if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) {
426 if (channel <= 14) {
427 if (power_index >= 16)
428 power_index -= 16;
429 else
430 power_index = 0;
431 } else
432 power_index = 0;
433 }
434
435 if (pwr_lvl == tx_high_pwr_level_level1) {
436 if (power_index >= 0x10)
437 power_index -= 0x10;
438 else
439 power_index = 0;
440 } else if (pwr_lvl == tx_high_pwr_level_level2)
441 power_index = 0;
442
443 txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24);
444
445 PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]);
446
447 value[k++] = txagc_table_wd;
448 }
449 }
450 }
451
452 if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2)
453 HalDownloadTxPowerLevel8814(adapter, value);
454 #endif
455 }
456 #endif
457