1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #include "../phydm_precomp.h"
28
29 #if (RTL8822C_SUPPORT)
30
odm_config_rf_reg_8822c(struct dm_struct * dm,u32 addr,u32 data,enum rf_path rf_path,u32 reg_addr)31 void odm_config_rf_reg_8822c(struct dm_struct *dm, u32 addr, u32 data,
32 enum rf_path rf_path, u32 reg_addr)
33 {
34 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
35 if (addr == 0xffe)
36 phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_MS,
37 reg_addr, data, RFREG_MASK, rf_path,
38 50);
39 else if (addr == 0xfe)
40 phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US,
41 reg_addr, data, RFREG_MASK, rf_path,
42 100);
43 else {
44 phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_RF_W, reg_addr,
45 data, RFREG_MASK, rf_path, 0);
46 phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US,
47 reg_addr, data, RFREG_MASK, rf_path,
48 1);
49 }
50 } else {
51 if (addr == 0xffe) {
52 #ifdef CONFIG_LONG_DELAY_ISSUE
53 ODM_sleep_ms(50);
54 #else
55 ODM_delay_ms(50);
56 #endif
57 } else if (addr == 0xfe) {
58 #ifdef CONFIG_LONG_DELAY_ISSUE
59 ODM_sleep_us(100);
60 #else
61 ODM_delay_us(100);
62 #endif
63 } else if (addr == 0xffff) {
64 ODM_delay_us(1);
65 } else {
66 odm_set_rf_reg(dm, rf_path, reg_addr, RFREG_MASK, data);
67
68 /*Add 1us delay between BB/RF register setting.*/
69 ODM_delay_us(1);
70 }
71 }
72 }
73
odm_config_rf_radio_a_8822c(struct dm_struct * dm,u32 addr,u32 data)74 void odm_config_rf_radio_a_8822c(struct dm_struct *dm, u32 addr, u32 data)
75 {
76 u32 content = 0x1000; /* RF_Content: radioa_txt */
77 u32 maskfor_phy_set = (u32)(content & 0xE000);
78
79 odm_config_rf_reg_8822c(dm, addr, data, RF_PATH_A, addr |
80 maskfor_phy_set);
81
82 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioA] %08X %08X\n",
83 addr, data);
84 }
85
odm_config_rf_radio_b_8822c(struct dm_struct * dm,u32 addr,u32 data)86 void odm_config_rf_radio_b_8822c(struct dm_struct *dm, u32 addr, u32 data)
87 {
88 u32 content = 0x1001; /* RF_Content: radiob_txt */
89 u32 maskfor_phy_set = (u32)(content & 0xE000);
90
91 odm_config_rf_reg_8822c(dm, addr, data, RF_PATH_B, addr |
92 maskfor_phy_set);
93
94 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioB] %08X %08X\n",
95 addr, data);
96 }
97
phydm_agc_lower_bound_8822c(struct dm_struct * dm,u32 addr,u32 data)98 void phydm_agc_lower_bound_8822c(struct dm_struct *dm, u32 addr, u32 data)
99 {
100 u8 rxbb_gain = (u8)(data & 0x0000001f);
101 u8 mp_gain = (u8)((data & 0x003f0000) >> 16);
102 u8 tab = (u8)((data & 0x03c00000) >> 22);
103
104 if (addr != R_0x1d90)
105 return;
106
107 PHYDM_DBG(dm, ODM_COMP_INIT,
108 "data = 0x%x, mp_gain = 0x%x, tab = 0x%x, rxbb_gain = 0x%x\n",
109 data, mp_gain, tab, rxbb_gain);
110
111 if (!dm->l_bnd_detect[tab] && rxbb_gain == RXBB_MAX_GAIN_8822C) {
112 dm->ofdm_rxagc_l_bnd[tab] = mp_gain;
113 dm->l_bnd_detect[tab] = true;
114 }
115 }
116
phydm_agc_store_8822c(struct dm_struct * dm,u32 addr,u32 data)117 void phydm_agc_store_8822c(struct dm_struct *dm, u32 addr, u32 data)
118 {
119 u16 rf_gain = (u16)(data & 0x000003ff);
120 u8 mp_gain = (u8)((data & 0x003f0000) >> 16);
121 u8 tab = (u8)((data & 0x03c00000) >> 22);
122
123 if (addr != R_0x1d90)
124 return;
125
126 PHYDM_DBG(dm, ODM_COMP_INIT,
127 "data = 0x%x, mp_gain = 0x%x, tab = 0x%x, rxbb_gain = 0x%x\n",
128 data, mp_gain, tab, rf_gain);
129
130 dm->agc_rf_gain_ori[tab][mp_gain] = rf_gain;
131 dm->agc_rf_gain[tab][mp_gain] = rf_gain;
132 if (tab > dm->agc_table_cnt)
133 dm->agc_table_cnt = tab;
134 }
135
odm_config_bb_agc_8822c(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)136 void odm_config_bb_agc_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,
137 u32 data)
138 {
139 phydm_agc_lower_bound_8822c(dm, addr, data);
140 phydm_agc_store_8822c(dm, addr, data);
141
142 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
143 phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32, addr, data,
144 bitmask, (enum rf_path)0, 0);
145 else
146 odm_set_bb_reg(dm, addr, bitmask, data);
147
148 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n",
149 addr, data);
150 }
151
odm_config_bb_phy_reg_pg_8822c(struct dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)152 void odm_config_bb_phy_reg_pg_8822c(struct dm_struct *dm, u32 band, u32 rf_path,
153 u32 tx_num, u32 addr, u32 bitmask, u32 data)
154 {
155 if (addr == 0xfe || addr == 0xffe) {
156 #ifdef CONFIG_LONG_DELAY_ISSUE
157 ODM_sleep_ms(50);
158 #else
159 ODM_delay_ms(50);
160 #endif
161 } else {
162 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
163 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
164 addr, bitmask, data);
165 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
166 PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr,
167 bitmask, data);
168 #endif
169 }
170 PHYDM_DBG(dm, ODM_COMP_INIT,
171 "===> config_bb: [PHY_REG] %08X %08X %08X\n", addr, bitmask,
172 data);
173 }
174
odm_config_bb_phy_8822c(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)175 void odm_config_bb_phy_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,
176 u32 data)
177 {
178 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
179 u32 delay_time = 0;
180
181 if (addr >= 0xf9 && addr <= 0xfe) {
182 if (addr == 0xfe || addr == 0xfb)
183 delay_time = 50;
184 else if (addr == 0xfd || addr == 0xfa)
185 delay_time = 5;
186 else
187 delay_time = 1;
188
189 if (addr >= 0xfc && addr <= 0xfe)
190 phydm_set_reg_by_fw(dm,
191 PHYDM_HALMAC_CMD_DELAY_MS,
192 addr, data, bitmask,
193 (enum rf_path)0,
194 delay_time);
195 else
196 phydm_set_reg_by_fw(dm,
197 PHYDM_HALMAC_CMD_DELAY_US,
198 addr, data, bitmask,
199 (enum rf_path)0,
200 delay_time);
201 } else
202 phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32,
203 addr, data, bitmask,
204 (enum rf_path)0, 0);
205 } else {
206 if (addr == 0xfe)
207 #ifdef CONFIG_LONG_DELAY_ISSUE
208 ODM_sleep_ms(50);
209 #else
210 ODM_delay_ms(50);
211 #endif
212 else if (addr == 0xfd)
213 ODM_delay_ms(5);
214 else if (addr == 0xfc)
215 ODM_delay_ms(1);
216 else if (addr == 0xfb)
217 ODM_delay_us(50);
218 else if (addr == 0xfa)
219 ODM_delay_us(5);
220 else if (addr == 0xf9)
221 ODM_delay_us(1);
222 else
223 odm_set_bb_reg(dm, addr, bitmask, data);
224 }
225
226 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n",
227 addr, data);
228 }
229
odm_config_bb_txpwr_lmt_8822c_ex(struct dm_struct * dm,u8 regulation,u8 band,u8 bandwidth,u8 rate_section,u8 rf_path,u8 channel,s8 power_limit)230 void odm_config_bb_txpwr_lmt_8822c_ex(struct dm_struct *dm, u8 regulation,
231 u8 band, u8 bandwidth, u8 rate_section,
232 u8 rf_path, u8 channel, s8 power_limit)
233 {
234 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
235 phy_set_tx_power_limit_ex(dm, regulation, band, bandwidth, rate_section,
236 rf_path, channel, power_limit);
237 #endif
238 #if 0
239 PHY_SetTxPowerLimit_ex(dm, regulation, band, bandwidth, rate_section,
240 rf_path, channel, power_limit);
241 #endif
242 }
243
odm_config_bb_txpwr_lmt_8822c(struct dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)244 void odm_config_bb_txpwr_lmt_8822c(struct dm_struct *dm, u8 *regulation,
245 u8 *band, u8 *bandwidth, u8 *rate_section,
246 u8 *rf_path, u8 *channel, u8 *power_limit)
247 {
248 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
249 phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
250 rf_path, channel, power_limit);
251 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
252 PHY_SetTxPowerLimit(dm, regulation, band, bandwidth, rate_section,
253 rf_path, channel, power_limit);
254 #endif
255 }
256
257 #endif
258