1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #include "../phydm_precomp.h"
18
19 #if (RTL8723B_SUPPORT == 1)
20
21 void
odm_config_rf_reg_8723b(struct PHY_DM_STRUCT * p_dm,u32 addr,u32 data,enum rf_path RF_PATH,u32 reg_addr)22 odm_config_rf_reg_8723b(
23 struct PHY_DM_STRUCT *p_dm,
24 u32 addr,
25 u32 data,
26 enum rf_path RF_PATH,
27 u32 reg_addr
28 )
29 {
30 if (addr == 0xfe || addr == 0xffe) {
31 #ifdef CONFIG_LONG_DELAY_ISSUE
32 ODM_sleep_ms(50);
33 #else
34 ODM_delay_ms(50);
35 #endif
36 } else {
37 odm_set_rf_reg(p_dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
38 /* Add 1us delay between BB/RF register setting. */
39 ODM_delay_us(1);
40
41 /* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
42 if (addr == 0xb6) {
43 u32 getvalue = 0;
44 u8 count = 0;
45 getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
46
47 ODM_delay_us(1);
48
49 while ((getvalue >> 8) != (data >> 8)) {
50 count++;
51 odm_set_rf_reg(p_dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
52 ODM_delay_us(1);
53 getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
54 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [B6] getvalue 0x%x, data 0x%x, count %d\n", getvalue, data, count));
55 if (count > 5)
56 break;
57 }
58 }
59
60 if (addr == 0xb2) {
61 u32 getvalue = 0;
62 u8 count = 0;
63 getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
64
65 ODM_delay_us(1);
66
67 while (getvalue != data) {
68 count++;
69 odm_set_rf_reg(p_dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
70 ODM_delay_us(1);
71 /* Do LCK againg */
72 odm_set_rf_reg(p_dm, RF_PATH, 0x18, RFREGOFFSETMASK, 0x0fc07);
73 ODM_delay_us(1);
74 getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
75 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [B2] getvalue 0x%x, data 0x%x, count %d\n", getvalue, data, count));
76 if (count > 5)
77 break;
78 }
79 }
80 }
81 }
82
83
84 void
odm_config_rf_radio_a_8723b(struct PHY_DM_STRUCT * p_dm,u32 addr,u32 data)85 odm_config_rf_radio_a_8723b(
86 struct PHY_DM_STRUCT *p_dm,
87 u32 addr,
88 u32 data
89 )
90 {
91 u32 content = 0x1000; /* RF_Content: radioa_txt */
92 u32 maskfor_phy_set = (u32)(content & 0xE000);
93
94 odm_config_rf_reg_8723b(p_dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
95
96 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data));
97 }
98
99 void
odm_config_rf_radio_b_8723b(struct PHY_DM_STRUCT * p_dm,u32 addr,u32 data)100 odm_config_rf_radio_b_8723b(
101 struct PHY_DM_STRUCT *p_dm,
102 u32 addr,
103 u32 data
104 )
105 {
106 u32 content = 0x1001; /* RF_Content: radiob_txt */
107 u32 maskfor_phy_set = (u32)(content & 0xE000);
108
109 odm_config_rf_reg_8723b(p_dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
110
111 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data));
112
113 }
114
115 void
odm_config_mac_8723b(struct PHY_DM_STRUCT * p_dm,u32 addr,u8 data)116 odm_config_mac_8723b(
117 struct PHY_DM_STRUCT *p_dm,
118 u32 addr,
119 u8 data
120 )
121 {
122 odm_write_1byte(p_dm, addr, data);
123 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data));
124 }
125
126 void
odm_config_bb_agc_8723b(struct PHY_DM_STRUCT * p_dm,u32 addr,u32 bitmask,u32 data)127 odm_config_bb_agc_8723b(
128 struct PHY_DM_STRUCT *p_dm,
129 u32 addr,
130 u32 bitmask,
131 u32 data
132 )
133 {
134 odm_set_bb_reg(p_dm, addr, bitmask, data);
135 /* Add 1us delay between BB/RF register setting. */
136 ODM_delay_us(1);
137
138 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data));
139 }
140
141 void
odm_config_bb_phy_reg_pg_8723b(struct PHY_DM_STRUCT * p_dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)142 odm_config_bb_phy_reg_pg_8723b(
143 struct PHY_DM_STRUCT *p_dm,
144 u32 band,
145 u32 rf_path,
146 u32 tx_num,
147 u32 addr,
148 u32 bitmask,
149 u32 data
150 )
151 {
152 if (addr == 0xfe || addr == 0xffe)
153 #ifdef CONFIG_LONG_DELAY_ISSUE
154 ODM_sleep_ms(50);
155 #else
156 ODM_delay_ms(50);
157 #endif
158 else {
159 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
160 phy_store_tx_power_by_rate(p_dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
161 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
162 PHY_StoreTxPowerByRate(p_dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
163 #endif
164 }
165 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data));
166 }
167
168 void
odm_config_bb_phy_8723b(struct PHY_DM_STRUCT * p_dm,u32 addr,u32 bitmask,u32 data)169 odm_config_bb_phy_8723b(
170 struct PHY_DM_STRUCT *p_dm,
171 u32 addr,
172 u32 bitmask,
173 u32 data
174 )
175 {
176 if (addr == 0xfe)
177 #ifdef CONFIG_LONG_DELAY_ISSUE
178 ODM_sleep_ms(50);
179 #else
180 ODM_delay_ms(50);
181 #endif
182 else if (addr == 0xfd)
183 ODM_delay_ms(5);
184 else if (addr == 0xfc)
185 ODM_delay_ms(1);
186 else if (addr == 0xfb)
187 ODM_delay_us(50);
188 else if (addr == 0xfa)
189 ODM_delay_us(5);
190 else if (addr == 0xf9)
191 ODM_delay_us(1);
192 else
193 odm_set_bb_reg(p_dm, addr, bitmask, data);
194
195 /* Add 1us delay between BB/RF register setting. */
196 ODM_delay_us(1);
197 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data));
198 }
199
200 void
odm_config_bb_txpwr_lmt_8723b(struct PHY_DM_STRUCT * p_dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)201 odm_config_bb_txpwr_lmt_8723b(
202 struct PHY_DM_STRUCT *p_dm,
203 u8 *regulation,
204 u8 *band,
205 u8 *bandwidth,
206 u8 *rate_section,
207 u8 *rf_path,
208 u8 *channel,
209 u8 *power_limit
210 )
211 {
212 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
213 phy_set_tx_power_limit(p_dm, regulation, band,
214 bandwidth, rate_section, rf_path, channel, power_limit);
215 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
216 PHY_SetTxPowerLimit(p_dm, regulation, band,
217 bandwidth, rate_section, rf_path, channel, power_limit);
218 #endif
219 }
220
221 #endif
222