1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #include "../phydm_precomp.h"
28
29 #if (RTL8822B_SUPPORT == 1)
odm_config_rf_reg_8822b(struct dm_struct * dm,u32 addr,u32 data,enum rf_path rf_path,u32 reg_addr)30 void odm_config_rf_reg_8822b(struct dm_struct *dm, u32 addr, u32 data,
31 enum rf_path rf_path, u32 reg_addr)
32 {
33 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
34 if (addr == 0xffe) {
35 phydm_set_reg_by_fw(dm,
36 PHYDM_HALMAC_CMD_DELAY_MS,
37 reg_addr,
38 data,
39 RFREGOFFSETMASK,
40 rf_path,
41 50);
42 } else if (addr == 0xfe) {
43 phydm_set_reg_by_fw(dm,
44 PHYDM_HALMAC_CMD_DELAY_US,
45 reg_addr,
46 data,
47 RFREGOFFSETMASK,
48 rf_path,
49 100);
50 } else {
51 phydm_set_reg_by_fw(dm,
52 PHYDM_HALMAC_CMD_RF_W,
53 reg_addr,
54 data,
55 RFREGOFFSETMASK,
56 rf_path,
57 0);
58 phydm_set_reg_by_fw(dm,
59 PHYDM_HALMAC_CMD_DELAY_US,
60 reg_addr,
61 data,
62 RFREGOFFSETMASK,
63 rf_path,
64 1);
65 }
66 } else {
67 if (addr == 0xffe) {
68 #ifdef CONFIG_LONG_DELAY_ISSUE
69 ODM_sleep_ms(50);
70 #else
71 ODM_delay_ms(50);
72 #endif
73 } else if (addr == 0xfe) {
74 #ifdef CONFIG_LONG_DELAY_ISSUE
75 ODM_sleep_us(100);
76 #else
77 ODM_delay_us(100);
78 #endif
79 } else {
80 odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data);
81
82 /* @Add 1us delay between BB/RF register setting. */
83 ODM_delay_us(1);
84 }
85 }
86 }
87
odm_config_rf_radio_a_8822b(struct dm_struct * dm,u32 addr,u32 data)88 void odm_config_rf_radio_a_8822b(struct dm_struct *dm, u32 addr, u32 data)
89 {
90 u32 content = 0x1000; /* RF_Content: radioa_txt */
91 u32 maskfor_phy_set = (u32)(content & 0xE000);
92
93 odm_config_rf_reg_8822b(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
94
95 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioA] %08X %08X\n",
96 addr, data);
97 }
98
odm_config_rf_radio_b_8822b(struct dm_struct * dm,u32 addr,u32 data)99 void odm_config_rf_radio_b_8822b(struct dm_struct *dm, u32 addr, u32 data)
100 {
101 u32 content = 0x1001; /* RF_Content: radiob_txt */
102 u32 maskfor_phy_set = (u32)(content & 0xE000);
103
104 odm_config_rf_reg_8822b(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
105
106 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioB] %08X %08X\n",
107 addr, data);
108 }
109
odm_config_mac_8822b(struct dm_struct * dm,u32 addr,u8 data)110 void odm_config_mac_8822b(struct dm_struct *dm, u32 addr, u8 data)
111 {
112 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
113 phydm_set_reg_by_fw(dm,
114 PHYDM_HALMAC_CMD_MAC_W8,
115 addr,
116 data,
117 0,
118 (enum rf_path)0,
119 0);
120 else
121 odm_write_1byte(dm, addr, data);
122 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_mac: [MAC_REG] %08X %08X\n",
123 addr, data);
124 }
125
odm_update_agc_big_jump_lmt_8822b(struct dm_struct * dm,u32 addr,u32 data)126 void odm_update_agc_big_jump_lmt_8822b(struct dm_struct *dm, u32 addr, u32 data)
127 {
128 static boolean is_limit;
129 struct phydm_dig_struct *dig_tab = &dm->dm_dig_table;
130 u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
131 u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
132 u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
133
134 if (addr != 0x81c)
135 return;
136
137 #if 0
138 /*@dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/
139 /*@dbg_print("rf_gain_idx = 0x%x, dig_tab->rf_gain_idx = 0x%x\n", rf_gain_idx, dig_tab->rf_gain_idx);*/
140 #endif
141
142 if (bb_gain_idx > 0x3c) {
143 if (rf_gain_idx == dig_tab->rf_gain_idx && !is_limit) {
144 is_limit = true;
145 dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
146 PHYDM_DBG(dm, DBG_DIG,
147 "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
148 agc_table_idx,
149 dig_tab->big_jump_lmt[agc_table_idx]);
150 }
151 } else {
152 is_limit = false;
153 }
154
155 dig_tab->rf_gain_idx = rf_gain_idx;
156 }
157
odm_config_bb_agc_8822b(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)158 void odm_config_bb_agc_8822b(struct dm_struct *dm, u32 addr, u32 bitmask,
159 u32 data)
160 {
161 odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
162
163 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
164 phydm_set_reg_by_fw(dm,
165 PHYDM_HALMAC_CMD_BB_W32,
166 addr,
167 data,
168 bitmask,
169 (enum rf_path)0,
170 0);
171 else
172 odm_set_bb_reg(dm, addr, bitmask, data);
173
174 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n",
175 addr, data);
176 }
177
odm_config_bb_phy_reg_pg_8822b(struct dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)178 void odm_config_bb_phy_reg_pg_8822b(struct dm_struct *dm, u32 band, u32 rf_path,
179 u32 tx_num, u32 addr, u32 bitmask, u32 data)
180 {
181 if (addr == 0xfe || addr == 0xffe)
182 #ifdef CONFIG_LONG_DELAY_ISSUE
183 ODM_sleep_ms(50);
184 #else
185 ODM_delay_ms(50);
186 #endif
187 else
188 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
189 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
190 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
191 PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
192 #endif
193 PHYDM_DBG(dm, ODM_COMP_INIT,
194 "===> config_bb: [PHY_REG] %08X %08X %08X\n", addr, bitmask,
195 data);
196 }
197
odm_config_bb_phy_8822b(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)198 void odm_config_bb_phy_8822b(struct dm_struct *dm, u32 addr, u32 bitmask,
199 u32 data)
200 {
201 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
202 u32 delay_time = 0;
203
204 if (addr >= 0xf9 && addr <= 0xfe) {
205 if (addr == 0xfe || addr == 0xfb)
206 delay_time = 50;
207 else if (addr == 0xfd || addr == 0xfa)
208 delay_time = 5;
209 else
210 delay_time = 1;
211
212 if (addr >= 0xfc && addr <= 0xfe)
213 phydm_set_reg_by_fw(dm,
214 PHYDM_HALMAC_CMD_DELAY_MS,
215 addr,
216 data,
217 bitmask,
218 (enum rf_path)0,
219 delay_time);
220 else
221 phydm_set_reg_by_fw(dm,
222 PHYDM_HALMAC_CMD_DELAY_US,
223 addr,
224 data,
225 bitmask,
226 (enum rf_path)0,
227 delay_time);
228 } else {
229 phydm_set_reg_by_fw(dm,
230 PHYDM_HALMAC_CMD_BB_W32,
231 addr,
232 data,
233 bitmask,
234 (enum rf_path)0,
235 0);
236 }
237 } else {
238 if (addr == 0xfe)
239 #ifdef CONFIG_LONG_DELAY_ISSUE
240 ODM_sleep_ms(50);
241 #else
242 ODM_delay_ms(50);
243 #endif
244 else if (addr == 0xfd)
245 ODM_delay_ms(5);
246 else if (addr == 0xfc)
247 ODM_delay_ms(1);
248 else if (addr == 0xfb)
249 ODM_delay_us(50);
250 else if (addr == 0xfa)
251 ODM_delay_us(5);
252 else if (addr == 0xf9)
253 ODM_delay_us(1);
254 else
255 odm_set_bb_reg(dm, addr, bitmask, data);
256 }
257
258 PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n",
259 addr, data);
260 }
261
odm_config_bb_txpwr_lmt_8822b(struct dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)262 void odm_config_bb_txpwr_lmt_8822b(struct dm_struct *dm, u8 *regulation,
263 u8 *band, u8 *bandwidth, u8 *rate_section,
264 u8 *rf_path, u8 *channel, u8 *power_limit)
265 {
266 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
267 phy_set_tx_power_limit(dm, regulation, band,
268 bandwidth, rate_section, rf_path, channel, power_limit);
269 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
270 PHY_SetTxPowerLimit(dm, regulation, band,
271 bandwidth, rate_section, rf_path, channel, power_limit);
272 #endif
273 }
274
275 #endif
276