1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #include "../phydm_precomp.h"
18
19 #if (RTL8703B_SUPPORT == 1)
20
odm_config_rf_reg_8703b(struct dm_struct * dm,u32 addr,u32 data,enum rf_path RF_PATH,u32 reg_addr)21 void odm_config_rf_reg_8703b(struct dm_struct *dm, u32 addr, u32 data,
22 enum rf_path RF_PATH, u32 reg_addr)
23 {
24 if (addr == 0xfe || addr == 0xffe) {
25 #ifdef CONFIG_LONG_DELAY_ISSUE
26 ODM_sleep_ms(50);
27 #else
28 ODM_delay_ms(50);
29 #endif
30 } else {
31 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
32 /* Add 1us delay between BB/RF register setting. */
33 ODM_delay_us(1);
34 }
35 }
36
odm_config_rf_radio_a_8703b(struct dm_struct * dm,u32 addr,u32 data)37 void odm_config_rf_radio_a_8703b(struct dm_struct *dm, u32 addr, u32 data)
38 {
39 u32 content = 0x1000; /* RF_Content: radioa_txt */
40 u32 maskfor_phy_set = (u32)(content & 0xE000);
41
42 odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
43
44 PHYDM_DBG(dm, ODM_COMP_INIT,
45 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
46 addr, data);
47 }
48
odm_config_rf_radio_b_8703b(struct dm_struct * dm,u32 addr,u32 data)49 void odm_config_rf_radio_b_8703b(struct dm_struct *dm, u32 addr, u32 data)
50 {
51 u32 content = 0x1001; /* RF_Content: radiob_txt */
52 u32 maskfor_phy_set = (u32)(content & 0xE000);
53
54 odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
55
56 PHYDM_DBG(dm, ODM_COMP_INIT,
57 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
58 addr, data);
59 }
60
odm_config_rf_radio_c_8703b(struct dm_struct * dm,u32 addr,u32 data)61 void odm_config_rf_radio_c_8703b(struct dm_struct *dm, u32 addr, u32 data)
62 {
63 u32 content = 0x1001; /* RF_Content: radiob_txt */
64 u32 maskfor_phy_set = (u32)(content & 0xE000);
65
66 odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_C, addr | maskfor_phy_set);
67
68 PHYDM_DBG(dm, ODM_COMP_INIT,
69 "===> odm_config_rf_with_header_file: [RadioC] %08X %08X\n",
70 addr, data);
71 }
72
odm_config_rf_radio_d_8703b(struct dm_struct * dm,u32 addr,u32 data)73 void odm_config_rf_radio_d_8703b(struct dm_struct *dm, u32 addr, u32 data)
74 {
75 u32 content = 0x1001; /* RF_Content: radiob_txt */
76 u32 maskfor_phy_set = (u32)(content & 0xE000);
77
78 odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_D, addr | maskfor_phy_set);
79
80 PHYDM_DBG(dm, ODM_COMP_INIT,
81 "===> odm_config_rf_with_header_file: [RadioD] %08X %08X\n",
82 addr, data);
83 }
84
odm_config_mac_8703b(struct dm_struct * dm,u32 addr,u8 data)85 void odm_config_mac_8703b(struct dm_struct *dm, u32 addr, u8 data)
86 {
87 odm_write_1byte(dm, addr, data);
88 PHYDM_DBG(dm, ODM_COMP_INIT,
89 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
90 addr, data);
91 }
92
odm_config_bb_agc_8703b(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)93 void odm_config_bb_agc_8703b(struct dm_struct *dm, u32 addr, u32 bitmask,
94 u32 data)
95 {
96 odm_set_bb_reg(dm, addr, bitmask, data);
97 /* Add 1us delay between BB/RF register setting. */
98 ODM_delay_us(1);
99
100 PHYDM_DBG(dm, ODM_COMP_INIT,
101 "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
102 addr, data);
103 }
104
odm_config_bb_phy_reg_pg_8703b(struct dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)105 void odm_config_bb_phy_reg_pg_8703b(struct dm_struct *dm, u32 band, u32 rf_path,
106 u32 tx_num, u32 addr, u32 bitmask, u32 data)
107 {
108 if (addr == 0xfe || addr == 0xffe)
109 #ifdef CONFIG_LONG_DELAY_ISSUE
110 ODM_sleep_ms(50);
111 #else
112 ODM_delay_ms(50);
113 #endif
114 else {
115 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
116 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
117 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
118 PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
119 #endif
120 }
121 PHYDM_DBG(dm, ODM_COMP_INIT,
122 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
123 addr, bitmask, data);
124 }
125
odm_config_bb_phy_8703b(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)126 void odm_config_bb_phy_8703b(struct dm_struct *dm, u32 addr, u32 bitmask,
127 u32 data)
128 {
129 if (addr == 0xfe)
130 #ifdef CONFIG_LONG_DELAY_ISSUE
131 ODM_sleep_ms(50);
132 #else
133 ODM_delay_ms(50);
134 #endif
135 else if (addr == 0xfd)
136 ODM_delay_ms(5);
137 else if (addr == 0xfc)
138 ODM_delay_ms(1);
139 else if (addr == 0xfb)
140 ODM_delay_us(50);
141 else if (addr == 0xfa)
142 ODM_delay_us(5);
143 else if (addr == 0xf9)
144 ODM_delay_us(1);
145 else
146 odm_set_bb_reg(dm, addr, bitmask, data);
147
148 /* Add 1us delay between BB/RF register setting. */
149 ODM_delay_us(1);
150 PHYDM_DBG(dm, ODM_COMP_INIT,
151 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
152 addr, data);
153 }
154
odm_config_bb_txpwr_lmt_8703b(struct dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)155 void odm_config_bb_txpwr_lmt_8703b(struct dm_struct *dm, u8 *regulation,
156 u8 *band, u8 *bandwidth, u8 *rate_section,
157 u8 *rf_path, u8 *channel, u8 *power_limit)
158 {
159 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
160 phy_set_tx_power_limit(dm, regulation, band,
161 bandwidth, rate_section, rf_path, channel, power_limit);
162 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
163 PHY_SetTxPowerLimit(dm, regulation, band,
164 bandwidth, rate_section, rf_path, channel, power_limit);
165 #endif
166 }
167 #endif
168