1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16
17 #include "mp_precomp.h"
18
19 #include "../phydm_precomp.h"
20
21 #if (RTL8188E_SUPPORT == 1)
22
odm_config_rf_reg_8188e(struct dm_struct * dm,u32 addr,u32 data,enum rf_path RF_PATH,u32 reg_addr)23 void odm_config_rf_reg_8188e(struct dm_struct *dm, u32 addr, u32 data,
24 enum rf_path RF_PATH, u32 reg_addr)
25 {
26 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
27 #ifndef SMP_SYNC
28 unsigned long x;
29 #endif
30 struct rtl8192cd_priv *priv = dm->priv;
31 #endif
32
33 if (addr == 0xffe) {
34 #ifdef CONFIG_LONG_DELAY_ISSUE
35 ODM_sleep_ms(50);
36 #else
37 ODM_delay_ms(50);
38 #endif
39 } else if (addr == 0xfd)
40 ODM_delay_ms(5);
41 else if (addr == 0xfc)
42 ODM_delay_ms(1);
43 else if (addr == 0xfb)
44 ODM_delay_us(50);
45 else if (addr == 0xfa)
46 ODM_delay_us(5);
47 else if (addr == 0xf9)
48 ODM_delay_us(1);
49 else {
50 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
51 SAVE_INT_AND_CLI(x);
52 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
53 RESTORE_INT(x);
54 #else
55 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
56 #endif
57 /* Add 1us delay between BB/RF register setting. */
58 ODM_delay_us(1);
59 }
60 }
61
odm_config_rf_radio_a_8188e(struct dm_struct * dm,u32 addr,u32 data)62 void odm_config_rf_radio_a_8188e(struct dm_struct *dm, u32 addr, u32 data)
63 {
64 u32 content = 0x1000; /* RF_Content: radioa_txt */
65 u32 maskfor_phy_set = (u32)(content & 0xE000);
66
67 odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
68
69 PHYDM_DBG(dm, ODM_COMP_INIT,
70 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
71 addr, data);
72 }
73
odm_config_rf_radio_b_8188e(struct dm_struct * dm,u32 addr,u32 data)74 void odm_config_rf_radio_b_8188e(struct dm_struct *dm, u32 addr, u32 data)
75 {
76 u32 content = 0x1001; /* RF_Content: radiob_txt */
77 u32 maskfor_phy_set = (u32)(content & 0xE000);
78
79 odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
80
81 PHYDM_DBG(dm, ODM_COMP_INIT,
82 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
83 addr, data);
84 }
85
odm_config_mac_8188e(struct dm_struct * dm,u32 addr,u8 data)86 void odm_config_mac_8188e(struct dm_struct *dm, u32 addr, u8 data)
87 {
88 odm_write_1byte(dm, addr, data);
89 PHYDM_DBG(dm, ODM_COMP_INIT,
90 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
91 addr, data);
92 }
93
odm_config_bb_agc_8188e(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)94 void odm_config_bb_agc_8188e(struct dm_struct *dm, u32 addr, u32 bitmask,
95 u32 data)
96 {
97 odm_set_bb_reg(dm, addr, bitmask, data);
98 /* Add 1us delay between BB/RF register setting. */
99 ODM_delay_us(1);
100
101 PHYDM_DBG(dm, ODM_COMP_INIT,
102 "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
103 addr, data);
104 }
105
odm_config_bb_phy_reg_pg_8188e(struct dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)106 void odm_config_bb_phy_reg_pg_8188e(struct dm_struct *dm, u32 band, u32 rf_path,
107 u32 tx_num, u32 addr, u32 bitmask, u32 data)
108 {
109 if (addr == 0xfe) {
110 #ifdef CONFIG_LONG_DELAY_ISSUE
111 ODM_sleep_ms(50);
112 #else
113 ODM_delay_ms(50);
114 #endif
115 } else if (addr == 0xfd)
116 ODM_delay_ms(5);
117 else if (addr == 0xfc)
118 ODM_delay_ms(1);
119 else if (addr == 0xfb)
120 ODM_delay_us(50);
121 else if (addr == 0xfa)
122 ODM_delay_us(5);
123 else if (addr == 0xf9)
124 ODM_delay_us(1);
125 else {
126 PHYDM_DBG(dm, ODM_COMP_INIT,
127 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
128 addr, bitmask, data);
129
130 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
131 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
132 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
133 PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
134 #endif
135 }
136 }
137
odm_config_bb_txpwr_lmt_8188e(struct dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)138 void odm_config_bb_txpwr_lmt_8188e(struct dm_struct *dm, u8 *regulation,
139 u8 *band, u8 *bandwidth, u8 *rate_section,
140 u8 *rf_path, u8 *channel, u8 *power_limit)
141 {
142 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
143 phy_set_tx_power_limit(dm, regulation, band,
144 bandwidth, rate_section, rf_path, channel, power_limit);
145 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
146 PHY_SetTxPowerLimit(dm, regulation, band,
147 bandwidth, rate_section, rf_path, channel, power_limit);
148 #endif
149 }
150
odm_config_bb_phy_8188e(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)151 void odm_config_bb_phy_8188e(struct dm_struct *dm, u32 addr, u32 bitmask,
152 u32 data)
153 {
154 if (addr == 0xfe) {
155 #ifdef CONFIG_LONG_DELAY_ISSUE
156 ODM_sleep_ms(50);
157 #else
158 ODM_delay_ms(50);
159 #endif
160 } else if (addr == 0xfd)
161 ODM_delay_ms(5);
162 else if (addr == 0xfc)
163 ODM_delay_ms(1);
164 else if (addr == 0xfb)
165 ODM_delay_us(50);
166 else if (addr == 0xfa)
167 ODM_delay_us(5);
168 else if (addr == 0xf9)
169 ODM_delay_us(1);
170 else {
171 if (addr == 0xa24)
172 dm->rf_calibrate_info.rega24 = data;
173 odm_set_bb_reg(dm, addr, bitmask, data);
174
175 /* Add 1us delay between BB/RF register setting. */
176 ODM_delay_us(1);
177 PHYDM_DBG(dm, ODM_COMP_INIT,
178 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
179 addr, data);
180 }
181 }
182 #endif
183