1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19
20 #include "mp_precomp.h"
21 #include "phydm_precomp.h"
22
23 /* ******************************************************
24 * when antenna test utility is on or some testing need to disable antenna diversity
25 * call this function to disable all ODM related mechanisms which will switch antenna.
26 * ****************************************************** */
27 void
odm_stop_antenna_switch_dm(void * p_dm_void)28 odm_stop_antenna_switch_dm(
29 void *p_dm_void
30 )
31 {
32 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
33 /* disable ODM antenna diversity */
34 p_dm->support_ability &= ~ODM_BB_ANT_DIV;
35 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
36 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
37 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("STOP Antenna Diversity\n"));
38 }
39
40 void
phydm_enable_antenna_diversity(void * p_dm_void)41 phydm_enable_antenna_diversity(
42 void *p_dm_void
43 )
44 {
45 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
46
47 p_dm->support_ability |= ODM_BB_ANT_DIV;
48 p_dm->antdiv_select = 0;
49 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("AntDiv is enabled & Re-Init AntDiv\n"));
50 odm_antenna_diversity_init(p_dm);
51 }
52
53 void
odm_set_ant_config(void * p_dm_void,u8 ant_setting)54 odm_set_ant_config(
55 void *p_dm_void,
56 u8 ant_setting /* 0=A, 1=B, 2=C, .... */
57 )
58 {
59 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
60 if (p_dm->support_ic_type == ODM_RTL8723B) {
61 if (ant_setting == 0) /* ant A*/
62 odm_set_bb_reg(p_dm, 0x948, MASKDWORD, 0x00000000);
63 else if (ant_setting == 1)
64 odm_set_bb_reg(p_dm, 0x948, MASKDWORD, 0x00000280);
65 } else if (p_dm->support_ic_type == ODM_RTL8723D) {
66 if (ant_setting == 0) /* ant A*/
67 odm_set_bb_reg(p_dm, 0x948, MASKLWORD, 0x0000);
68 else if (ant_setting == 1)
69 odm_set_bb_reg(p_dm, 0x948, MASKLWORD, 0x0280);
70 }
71 }
72
73 /* ****************************************************** */
74
75
76 void
odm_sw_ant_div_rest_after_link(void * p_dm_void)77 odm_sw_ant_div_rest_after_link(
78 void *p_dm_void
79 )
80 {
81 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
82 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
83 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
84 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
85 u32 i;
86
87 if (p_dm->ant_div_type == S0S1_SW_ANTDIV) {
88
89 p_dm_swat_table->try_flag = SWAW_STEP_INIT;
90 p_dm_swat_table->rssi_trying = 0;
91 p_dm_swat_table->double_chk_flag = 0;
92 p_dm_fat_table->rx_idle_ant = MAIN_ANT;
93
94 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
95 phydm_antdiv_reset_statistic(p_dm, i);
96 }
97
98 #endif
99 }
100
101 void
odm_ant_div_on_off(void * p_dm_void,u8 swch)102 odm_ant_div_on_off(
103 void *p_dm_void,
104 u8 swch
105 )
106 {
107 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
108 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
109
110 if (p_dm_fat_table->ant_div_on_off != swch) {
111 if (p_dm->ant_div_type == S0S1_SW_ANTDIV)
112 return;
113
114 if (p_dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
115 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"));
116 odm_set_bb_reg(p_dm, 0xc50, BIT(7), swch);
117 odm_set_bb_reg(p_dm, 0xa00, BIT(15), swch);
118
119 #if (RTL8723D_SUPPORT == 1)
120 /*Mingzhi 2017-05-08*/
121 if (p_dm->support_ic_type == ODM_RTL8723D) {
122 if (swch == ANTDIV_ON) {
123 odm_set_bb_reg(p_dm, 0xce0, BIT(1), 1);
124 odm_set_bb_reg(p_dm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/
125 }
126 else{
127 odm_set_bb_reg(p_dm, 0xce0, BIT(1), 0);
128 odm_set_bb_reg(p_dm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/
129 }
130 }
131 #endif
132
133 } else if (p_dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
134 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"));
135 if (p_dm->support_ic_type & ODM_RTL8812) {
136 odm_set_bb_reg(p_dm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */
137 odm_set_bb_reg(p_dm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */
138 } else {
139 odm_set_bb_reg(p_dm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */
140
141 if ((p_dm->cut_version >= ODM_CUT_C) && (p_dm->support_ic_type == ODM_RTL8821) && (p_dm->ant_div_type != S0S1_SW_ANTDIV)) {
142 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"));
143 odm_set_bb_reg(p_dm, 0x800, BIT(25), swch);
144 odm_set_bb_reg(p_dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */
145 } else if (p_dm->support_ic_type == ODM_RTL8821C) {
146 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"));
147 odm_set_bb_reg(p_dm, 0x800, BIT(25), swch);
148 odm_set_bb_reg(p_dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */
149 }
150 }
151 }
152 }
153 p_dm_fat_table->ant_div_on_off = swch;
154
155 }
156
157 void
odm_tx_by_tx_desc_or_reg(void * p_dm_void,u8 swch)158 odm_tx_by_tx_desc_or_reg(
159 void *p_dm_void,
160 u8 swch
161 )
162 {
163 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
164 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
165 u8 enable;
166
167 if (p_dm_fat_table->b_fix_tx_ant == NO_FIX_TX_ANT)
168 enable = (swch == TX_BY_DESC) ? 1 : 0;
169 else
170 enable = 0;/*Force TX by Reg*/
171
172 if (p_dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
173 if (p_dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
174 odm_set_bb_reg(p_dm, 0x80c, BIT(21), enable);
175 else if (p_dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
176 odm_set_bb_reg(p_dm, 0x900, BIT(18), enable);
177
178 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG"));
179 }
180 }
181
182 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
183 void
phydm_antdiv_reset_statistic(void * p_dm_void,u32 macid)184 phydm_antdiv_reset_statistic(
185 void *p_dm_void,
186 u32 macid
187 )
188 {
189 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
190 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
191
192 p_dm_fat_table->main_ant_sum[macid] = 0;
193 p_dm_fat_table->aux_ant_sum[macid] = 0;
194 p_dm_fat_table->main_ant_cnt[macid] = 0;
195 p_dm_fat_table->aux_ant_cnt[macid] = 0;
196 p_dm_fat_table->main_ant_sum_cck[macid] = 0;
197 p_dm_fat_table->aux_ant_sum_cck[macid] = 0;
198 p_dm_fat_table->main_ant_cnt_cck[macid] = 0;
199 p_dm_fat_table->aux_ant_cnt_cck[macid] = 0;
200 }
201
202 void
phydm_fast_training_enable(void * p_dm_void,u8 swch)203 phydm_fast_training_enable(
204 void *p_dm_void,
205 u8 swch
206 )
207 {
208 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
209 u8 enable;
210
211 if (swch == FAT_ON)
212 enable = 1;
213 else
214 enable = 0;
215
216 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Fast ant Training_en = ((%d))\n", enable));
217
218 if (p_dm->support_ic_type == ODM_RTL8188E) {
219 odm_set_bb_reg(p_dm, 0xe08, BIT(16), enable); /*enable fast training*/
220 /**/
221 } else if (p_dm->support_ic_type == ODM_RTL8192E) {
222 odm_set_bb_reg(p_dm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/
223 /*odm_set_bb_reg(p_dm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/
224 } else if (p_dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
225 odm_set_bb_reg(p_dm, 0x900, BIT(19), enable); /*enable fast training */
226 /**/
227 }
228 }
229
230 void
phydm_keep_rx_ack_ant_by_tx_ant_time(void * p_dm_void,u32 time)231 phydm_keep_rx_ack_ant_by_tx_ant_time(
232 void *p_dm_void,
233 u32 time
234 )
235 {
236 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
237
238 /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
239 if (p_dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
240
241 odm_set_bb_reg(p_dm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
242 /**/
243 } else if (p_dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
244
245 odm_set_bb_reg(p_dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
246 /**/
247 }
248 }
249
250 void
odm_update_rx_idle_ant(void * p_dm_void,u8 ant)251 odm_update_rx_idle_ant(
252 void *p_dm_void,
253 u8 ant
254 )
255 {
256 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
257 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
258 u32 default_ant, optional_ant, value32, default_tx_ant;
259
260 if (p_dm_fat_table->rx_idle_ant != ant) {
261 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
262
263 if (!(p_dm->support_ic_type & ODM_RTL8723B))
264 p_dm_fat_table->rx_idle_ant = ant;
265
266 if (ant == MAIN_ANT) {
267 default_ant = ANT1_2G;
268 optional_ant = ANT2_2G;
269 } else {
270 default_ant = ANT2_2G;
271 optional_ant = ANT1_2G;
272 }
273
274 if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT)
275 default_tx_ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1;
276 else
277 default_tx_ant = default_ant;
278
279 if (p_dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
280 if (p_dm->support_ic_type == ODM_RTL8192E) {
281 odm_set_bb_reg(p_dm, 0xB38, BIT(5) | BIT(4) | BIT(3), default_ant); /* Default RX */
282 odm_set_bb_reg(p_dm, 0xB38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */
283 odm_set_bb_reg(p_dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* Default TX */
284 }
285 #if (RTL8723B_SUPPORT == 1)
286 else if (p_dm->support_ic_type == ODM_RTL8723B) {
287
288 value32 = odm_get_bb_reg(p_dm, 0x948, 0xFFF);
289
290 if (value32 != 0x280)
291 odm_update_rx_idle_ant_8723b(p_dm, ant, default_ant, optional_ant);
292 else
293 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"));
294 }
295 #endif
296
297 #if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/
298 else if (p_dm->support_ic_type == ODM_RTL8723D) {
299 phydm_set_tx_ant_pwr_8723d(p_dm, ant);
300 odm_update_rx_idle_ant_8723d(p_dm, ant, default_ant, optional_ant);
301
302 }
303 #endif
304
305 else { /*8188E & 8188F*/
306 /*
307 if (p_dm->support_ic_type == ODM_RTL8723D) {
308 #if (RTL8723D_SUPPORT == 1)
309 phydm_set_tx_ant_pwr_8723d(p_dm, ant);
310 #endif
311 }
312 */
313 #if (RTL8188F_SUPPORT == 1)
314 if (p_dm->support_ic_type == ODM_RTL8188F) {
315 phydm_update_rx_idle_antenna_8188F(p_dm, default_ant);
316 /**/
317 }
318 #endif
319
320 odm_set_bb_reg(p_dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
321 odm_set_bb_reg(p_dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
322 odm_set_bb_reg(p_dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*Default TX*/
323 }
324 } else if (p_dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
325 u16 value16 = odm_read_2byte(p_dm, ODM_REG_TRMUX_11AC + 2);
326 /* */
327 /* 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */
328 /* incorrect 0xc08 bit0-15 .We still not know why it is changed. */
329 /* */
330 value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3));
331 value16 |= ((u16)default_ant << 3);
332 value16 |= ((u16)optional_ant << 6);
333 value16 |= ((u16)default_ant << 9);
334 odm_write_2byte(p_dm, ODM_REG_TRMUX_11AC + 2, value16);
335 #if 0
336 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */
337 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */
338 odm_set_bb_reg(p_dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */
339 #endif
340 }
341
342 if (p_dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) {
343 odm_set_mac_reg(p_dm, 0x6D8, 0x7, default_tx_ant); /*PathA Resp Tx*/
344 /**/
345 } else if (p_dm->support_ic_type == ODM_RTL8188E) {
346 odm_set_mac_reg(p_dm, 0x6D8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/
347 /**/
348 } else {
349 odm_set_mac_reg(p_dm, 0x6D8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/
350 /**/
351 }
352
353 } else { /* p_dm_fat_table->rx_idle_ant == ant */
354 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
355 p_dm_fat_table->rx_idle_ant = ant;
356 }
357 }
358
359 void
phydm_set_antdiv_val(void * p_dm_void,u32 * val_buf,u8 val_len)360 phydm_set_antdiv_val(
361 void *p_dm_void,
362 u32 *val_buf,
363 u8 val_len
364 )
365 {
366 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
367
368 if (val_len != 1) {
369 PHYDM_DBG(p_dm, ODM_COMP_API, ("[Error][antdiv]Need val_len=1\n"));
370 return;
371 }
372
373 odm_update_rx_idle_ant(p_dm, (u8)(*val_buf));
374 }
375
376 void
odm_update_tx_ant(void * p_dm_void,u8 ant,u32 mac_id)377 odm_update_tx_ant(
378 void *p_dm_void,
379 u8 ant,
380 u32 mac_id
381 )
382 {
383 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
384 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
385 u8 tx_ant;
386
387 if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT)
388 ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT;
389
390 if (p_dm->ant_div_type == CG_TRX_SMART_ANTDIV)
391 tx_ant = ant;
392 else {
393 if (ant == MAIN_ANT)
394 tx_ant = ANT1_2G;
395 else
396 tx_ant = ANT2_2G;
397 }
398
399 p_dm_fat_table->antsel_a[mac_id] = tx_ant & BIT(0);
400 p_dm_fat_table->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
401 p_dm_fat_table->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
402
403 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
404 /* PHYDM_DBG(p_dm,DBG_ANT_DIV,("antsel_tr_mux=(( 3'b%d%d%d ))\n",p_dm_fat_table->antsel_c[mac_id] , p_dm_fat_table->antsel_b[mac_id] , p_dm_fat_table->antsel_a[mac_id] )); */
405
406 }
407
408 #ifdef BEAMFORMING_SUPPORT
409 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
410
411 void
odm_bdc_init(void * p_dm_void)412 odm_bdc_init(
413 void *p_dm_void
414 )
415 {
416 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
417 struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm->dm_bdc_table;
418
419 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("\n[ BDC Initialization......]\n"));
420 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
421 p_dm_bdc_table->bdc_mode = BDC_MODE_NULL;
422 p_dm_bdc_table->bdc_try_flag = 0;
423 p_dm_bdc_table->bd_ccoex_type_wbfer = 0;
424 p_dm->bdc_holdstate = 0xff;
425
426 if (p_dm->support_ic_type == ODM_RTL8192E) {
427 odm_set_bb_reg(p_dm, 0xd7c, 0x0FFFFFFF, 0x1081008);
428 odm_set_bb_reg(p_dm, 0xd80, 0x0FFFFFFF, 0);
429 } else if (p_dm->support_ic_type == ODM_RTL8812) {
430 odm_set_bb_reg(p_dm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */
431 odm_set_bb_reg(p_dm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */
432 }
433
434 }
435
436
437 void
odm_CSI_on_off(void * p_dm_void,u8 CSI_en)438 odm_CSI_on_off(
439 void *p_dm_void,
440 u8 CSI_en
441 )
442 {
443 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
444 if (CSI_en == CSI_ON) {
445 if (p_dm->support_ic_type == ODM_RTL8192E)
446 odm_set_mac_reg(p_dm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */
447 else if (p_dm->support_ic_type == ODM_RTL8812)
448 odm_set_mac_reg(p_dm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */
449
450 } else if (CSI_en == CSI_OFF) {
451 if (p_dm->support_ic_type == ODM_RTL8192E)
452 odm_set_mac_reg(p_dm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */
453 else if (p_dm->support_ic_type == ODM_RTL8812)
454 odm_set_mac_reg(p_dm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */
455 }
456 }
457
458 void
odm_bd_ccoex_type_with_bfer_client(void * p_dm_void,u8 swch)459 odm_bd_ccoex_type_with_bfer_client(
460 void *p_dm_void,
461 u8 swch
462 )
463 {
464 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
465 struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm->dm_bdc_table;
466 u8 bd_ccoex_type_wbfer;
467
468 if (swch == DIVON_CSIOFF) {
469 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[BDCcoexType: 1] {DIV,CSI} ={1,0}\n"));
470 bd_ccoex_type_wbfer = 1;
471
472 if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) {
473 odm_ant_div_on_off(p_dm, ANTDIV_ON);
474 odm_CSI_on_off(p_dm, CSI_OFF);
475 p_dm_bdc_table->bd_ccoex_type_wbfer = 1;
476 }
477 } else if (swch == DIVOFF_CSION) {
478 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n"));
479 bd_ccoex_type_wbfer = 2;
480
481 if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) {
482 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
483 odm_CSI_on_off(p_dm, CSI_ON);
484 p_dm_bdc_table->bd_ccoex_type_wbfer = 2;
485 }
486 }
487 }
488
489 void
odm_bf_ant_div_mode_arbitration(void * p_dm_void)490 odm_bf_ant_div_mode_arbitration(
491 void *p_dm_void
492 )
493 {
494 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
495 struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm->dm_bdc_table;
496 u8 current_bdc_mode;
497
498 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
499 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("\n"));
500
501 /* 2 mode 1 */
502 if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client == 0)) {
503 current_bdc_mode = BDC_MODE_1;
504
505 if (current_bdc_mode != p_dm_bdc_table->bdc_mode) {
506 p_dm_bdc_table->bdc_mode = BDC_MODE_1;
507 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
508 p_dm_bdc_table->bdc_rx_idle_update_counter = 1;
509 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Change to (( Mode1 ))\n"));
510 }
511
512 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Antdiv + BF coextance mode] : (( Mode1 ))\n"));
513 }
514 /* 2 mode 2 */
515 else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client != 0)) {
516 current_bdc_mode = BDC_MODE_2;
517
518 if (current_bdc_mode != p_dm_bdc_table->bdc_mode) {
519 p_dm_bdc_table->bdc_mode = BDC_MODE_2;
520 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
521 p_dm_bdc_table->bdc_try_flag = 0;
522 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Change to (( Mode2 ))\n"));
523
524 }
525 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Antdiv + BF coextance mode] : (( Mode2 ))\n"));
526 }
527 /* 2 mode 3 */
528 else if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client != 0)) {
529 current_bdc_mode = BDC_MODE_3;
530
531 if (current_bdc_mode != p_dm_bdc_table->bdc_mode) {
532 p_dm_bdc_table->bdc_mode = BDC_MODE_3;
533 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
534 p_dm_bdc_table->bdc_try_flag = 0;
535 p_dm_bdc_table->bdc_rx_idle_update_counter = 1;
536 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Change to (( Mode3 ))\n"));
537 }
538
539 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Antdiv + BF coextance mode] : (( Mode3 ))\n"));
540 }
541 /* 2 mode 4 */
542 else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client == 0)) {
543 current_bdc_mode = BDC_MODE_4;
544
545 if (current_bdc_mode != p_dm_bdc_table->bdc_mode) {
546 p_dm_bdc_table->bdc_mode = BDC_MODE_4;
547 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
548 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Change to (( Mode4 ))\n"));
549 }
550
551 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Antdiv + BF coextance mode] : (( Mode4 ))\n"));
552 }
553 #endif
554
555 }
556
557 void
odm_div_train_state_setting(void * p_dm_void)558 odm_div_train_state_setting(
559 void *p_dm_void
560 )
561 {
562 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
563 struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm->dm_bdc_table;
564
565 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n"));
566 p_dm_bdc_table->bdc_try_counter = 2;
567 p_dm_bdc_table->bdc_try_flag = 1;
568 p_dm_bdc_table->BDC_state = bdc_bfer_train_state;
569 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
570 }
571
572 void
odm_bd_ccoex_bfee_rx_div_arbitration(void * p_dm_void)573 odm_bd_ccoex_bfee_rx_div_arbitration(
574 void *p_dm_void
575 )
576 {
577 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
578 struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm->dm_bdc_table;
579 boolean stop_bf_flag;
580 u8 bdc_active_mode;
581
582
583 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
584
585 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", p_dm_bdc_table->num_txbfee_client, p_dm_bdc_table->num_txbfer_client, p_dm_bdc_table->num_client));
586 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", p_dm_bdc_table->num_bf_tar, p_dm_bdc_table->num_div_tar));
587
588 /* 2 [ MIB control ] */
589 if (p_dm->bdc_holdstate == 2) {
590 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
591 p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
592 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Force in [ BF STATE]\n"));
593 return;
594 } else if (p_dm->bdc_holdstate == 1) {
595 p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
596 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
597 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Force in [ DIV STATE]\n"));
598 return;
599 }
600
601 /* ------------------------------------------------------------ */
602
603
604
605 /* 2 mode 2 & 3 */
606 if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) {
607
608 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("\n{ Try_flag, Try_counter } = { %d , %d }\n", p_dm_bdc_table->bdc_try_flag, p_dm_bdc_table->bdc_try_counter));
609 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("BDCcoexType = (( %d ))\n\n", p_dm_bdc_table->bd_ccoex_type_wbfer));
610
611 /* All Client have Bfer-Cap------------------------------- */
612 if (p_dm_bdc_table->num_txbfer_client == p_dm_bdc_table->num_client) { /* BFer STA Only?: yes */
613 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("BFer STA only? (( Yes ))\n"));
614 p_dm_bdc_table->bdc_try_flag = 0;
615 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
616 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
617 return;
618 } else
619 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("BFer STA only? (( No ))\n"));
620 /* */
621 if (p_dm_bdc_table->is_all_bf_sta_idle == false && p_dm_bdc_table->is_all_div_sta_idle == true) {
622 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("All DIV-STA are idle, but BF-STA not\n"));
623 p_dm_bdc_table->bdc_try_flag = 0;
624 p_dm_bdc_table->BDC_state = bdc_bfer_train_state;
625 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
626 return;
627 } else if (p_dm_bdc_table->is_all_bf_sta_idle == true && p_dm_bdc_table->is_all_div_sta_idle == false) {
628 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("All BF-STA are idle, but DIV-STA not\n"));
629 p_dm_bdc_table->bdc_try_flag = 0;
630 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
631 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
632 return;
633 }
634
635 /* Select active mode-------------------------------------- */
636 if (p_dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */
637 if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
638 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Select active mode (( 1 ))\n"));
639 p_dm_bdc_table->bdc_active_mode = 1;
640 } else {
641 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Select active mode (( 2 ))\n"));
642 p_dm_bdc_table->bdc_active_mode = 2;
643 }
644 p_dm_bdc_table->bdc_try_flag = 0;
645 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
646 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
647 return;
648 } else { /* num_bf_tar > 0 */
649 if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
650 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Select active mode (( 3 ))\n"));
651 p_dm_bdc_table->bdc_active_mode = 3;
652 p_dm_bdc_table->bdc_try_flag = 0;
653 p_dm_bdc_table->BDC_state = bdc_bfer_train_state;
654 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
655 return;
656 } else { /* Selsect_4 */
657 bdc_active_mode = 4;
658 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Select active mode (( 4 ))\n"));
659
660 if (bdc_active_mode != p_dm_bdc_table->bdc_active_mode) {
661 p_dm_bdc_table->bdc_active_mode = 4;
662 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Change to active mode (( 4 )) & return!!!\n"));
663 return;
664 }
665 }
666 }
667
668 #if 1
669 if (p_dm->bdc_holdstate == 0xff) {
670 p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
671 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
672 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Force in [ DIV STATE]\n"));
673 return;
674 }
675 #endif
676
677 /* Does Client number changed ? ------------------------------- */
678 if (p_dm_bdc_table->num_client != p_dm_bdc_table->pre_num_client) {
679 p_dm_bdc_table->bdc_try_flag = 0;
680 p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
681 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n"));
682 }
683 p_dm_bdc_table->pre_num_client = p_dm_bdc_table->num_client;
684
685 if (p_dm_bdc_table->bdc_try_flag == 0) {
686 /* 2 DIV_TRAIN_STATE (mode 2-0) */
687 if (p_dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
688 odm_div_train_state_setting(p_dm);
689 /* 2 BFer_TRAIN_STATE (mode 2-1) */
690 else if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) {
691 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*****[2-1. BFer_TRAIN_STATE ]*****\n"));
692
693 /* if(p_dm_bdc_table->num_bf_tar==0) */
694 /* { */
695 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n")); */
696 /* odm_div_train_state_setting( p_dm); */
697 /* } */
698 /* else */ /* num_bf_tar != 0 */
699 /* { */
700 p_dm_bdc_table->bdc_try_counter = 2;
701 p_dm_bdc_table->bdc_try_flag = 1;
702 p_dm_bdc_table->BDC_state = BDC_DECISION_STATE;
703 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
704 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n"));
705 /* } */
706 }
707 /* 2 DECISION_STATE (mode 2-2) */
708 else if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
709 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*****[2-2. DECISION_STATE]*****\n"));
710 /* if(p_dm_bdc_table->num_bf_tar==0) */
711 /* { */
712 /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
713 /* odm_div_train_state_setting( p_dm); */
714 /* } */
715 /* else */ /* num_bf_tar != 0 */
716 /* { */
717 if (p_dm_bdc_table->BF_pass == false || p_dm_bdc_table->DIV_pass == false)
718 stop_bf_flag = true;
719 else
720 stop_bf_flag = false;
721
722 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", p_dm_bdc_table->BF_pass, p_dm_bdc_table->DIV_pass, stop_bf_flag));
723
724 if (stop_bf_flag == true) { /* DIV_en */
725 p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */
726 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
727 p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
728 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n"));
729 } else { /* BF_en */
730 p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */
731 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
732 p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
733 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n"));
734 }
735 /* } */
736 }
737 /* 2 BF-HOLD_STATE (mode 2-3) */
738 else if (p_dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
739 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*****[2-3. BF_HOLD_STATE ]*****\n"));
740
741 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter));
742
743 if (p_dm_bdc_table->bdc_hold_counter == 1) {
744 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"));
745 odm_div_train_state_setting(p_dm);
746 } else {
747 p_dm_bdc_table->bdc_hold_counter--;
748
749 /* if(p_dm_bdc_table->num_bf_tar==0) */
750 /* { */
751 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
752 /* odm_div_train_state_setting( p_dm); */
753 /* } */
754 /* else */ /* num_bf_tar != 0 */
755 /* { */
756 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("BF_tars exist? : (( Yes ))\n")); */
757 p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
758 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVOFF_CSION);
759 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n"));
760 /* } */
761 }
762
763 }
764 /* 2 DIV-HOLD_STATE (mode 2-4) */
765 else if (p_dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
766 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*****[2-4. DIV_HOLD_STATE ]*****\n"));
767
768 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter));
769
770 if (p_dm_bdc_table->bdc_hold_counter == 1) {
771 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"));
772 odm_div_train_state_setting(p_dm);
773 } else {
774 p_dm_bdc_table->bdc_hold_counter--;
775 p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
776 odm_bd_ccoex_type_with_bfer_client(p_dm, DIVON_CSIOFF);
777 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n"));
778 }
779
780 }
781
782 } else if (p_dm_bdc_table->bdc_try_flag == 1) {
783 /* 2 Set Training counter */
784 if (p_dm_bdc_table->bdc_try_counter > 1) {
785 p_dm_bdc_table->bdc_try_counter--;
786 if (p_dm_bdc_table->bdc_try_counter == 1)
787 p_dm_bdc_table->bdc_try_flag = 0;
788
789 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Training !!\n"));
790 /* return ; */
791 }
792
793 }
794
795 }
796
797 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("\n[end]\n"));
798
799 #endif /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
800
801
802
803
804
805
806 }
807
808 #endif
809 #endif /* #ifdef BEAMFORMING_SUPPORT */
810
811
812 #if (RTL8188E_SUPPORT == 1)
813
814
815 void
odm_rx_hw_ant_div_init_88e(void * p_dm_void)816 odm_rx_hw_ant_div_init_88e(
817 void *p_dm_void
818 )
819 {
820 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
821 u32 value32;
822 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
823
824 #if 0
825 if (*(p_dm->p_mp_mode) == true) {
826 odm_set_bb_reg(p_dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
827 odm_set_bb_reg(p_dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */
828 return;
829 }
830 #endif
831
832 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"));
833
834 /* MAC setting */
835 value32 = odm_get_mac_reg(p_dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
836 odm_set_mac_reg(p_dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
837 /* Pin Settings */
838 odm_set_bb_reg(p_dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
839 odm_set_bb_reg(p_dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
840 odm_set_bb_reg(p_dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
841 odm_set_bb_reg(p_dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */
842 /* OFDM Settings */
843 odm_set_bb_reg(p_dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
844 /* CCK Settings */
845 odm_set_bb_reg(p_dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
846 odm_set_bb_reg(p_dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
847
848 odm_set_bb_reg(p_dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */
849
850 p_dm_fat_table->enable_ctrl_frame_antdiv = 1;
851 }
852
853 void
odm_trx_hw_ant_div_init_88e(void * p_dm_void)854 odm_trx_hw_ant_div_init_88e(
855 void *p_dm_void
856 )
857 {
858 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
859 u32 value32;
860 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
861
862 #if 0
863 if (*(p_dm->p_mp_mode) == true) {
864 odm_set_bb_reg(p_dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
865 odm_set_bb_reg(p_dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */
866 return;
867 }
868 #endif
869
870 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n"));
871
872 /* MAC setting */
873 value32 = odm_get_mac_reg(p_dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
874 odm_set_mac_reg(p_dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
875 /* Pin Settings */
876 odm_set_bb_reg(p_dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
877 odm_set_bb_reg(p_dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
878 odm_set_bb_reg(p_dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
879 odm_set_bb_reg(p_dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */
880 /* OFDM Settings */
881 odm_set_bb_reg(p_dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
882 /* CCK Settings */
883 odm_set_bb_reg(p_dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
884 odm_set_bb_reg(p_dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
885
886 /* antenna mapping table */
887 if (!p_dm->is_mp_chip) { /* testchip */
888 odm_set_bb_reg(p_dm, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
889 odm_set_bb_reg(p_dm, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
890 } else /* MPchip */
891 odm_set_bb_reg(p_dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/
892
893 p_dm_fat_table->enable_ctrl_frame_antdiv = 1;
894 }
895
896
897 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
898 void
odm_smart_hw_ant_div_init_88e(void * p_dm_void)899 odm_smart_hw_ant_div_init_88e(
900 void *p_dm_void
901 )
902 {
903 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
904 u32 value32, i;
905 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
906
907 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"));
908
909 #if 0
910 if (*(p_dm->p_mp_mode) == true) {
911 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("p_dm->ant_div_type: %d\n", p_dm->ant_div_type));
912 return;
913 }
914 #endif
915
916 p_dm_fat_table->train_idx = 0;
917 p_dm_fat_table->fat_state = FAT_PREPARE_STATE;
918
919 p_dm->fat_comb_a = 5;
920 p_dm->antdiv_intvl = 0x64; /* 100ms */
921
922 for (i = 0; i < 6; i++)
923 p_dm_fat_table->bssid[i] = 0;
924 for (i = 0; i < (p_dm->fat_comb_a) ; i++) {
925 p_dm_fat_table->ant_sum_rssi[i] = 0;
926 p_dm_fat_table->ant_rssi_cnt[i] = 0;
927 p_dm_fat_table->ant_ave_rssi[i] = 0;
928 }
929
930 /* MAC setting */
931 value32 = odm_get_mac_reg(p_dm, 0x4c, MASKDWORD);
932 odm_set_mac_reg(p_dm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
933 value32 = odm_get_mac_reg(p_dm, 0x7B4, MASKDWORD);
934 odm_set_mac_reg(p_dm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
935 /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
936 /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */
937
938 /* Match MAC ADDR */
939 odm_set_mac_reg(p_dm, 0x7b4, 0xFFFF, 0);
940 odm_set_mac_reg(p_dm, 0x7b0, MASKDWORD, 0);
941
942 odm_set_bb_reg(p_dm, 0x870, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
943 odm_set_bb_reg(p_dm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
944 odm_set_bb_reg(p_dm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
945 odm_set_bb_reg(p_dm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */
946 odm_set_bb_reg(p_dm, 0xca4, MASKDWORD, 0x000000a0);
947
948 /* antenna mapping table */
949 if (p_dm->fat_comb_a == 2) {
950 if (!p_dm->is_mp_chip) { /* testchip */
951 odm_set_bb_reg(p_dm, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
952 odm_set_bb_reg(p_dm, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
953 } else { /* MPchip */
954 odm_set_bb_reg(p_dm, 0x914, MASKBYTE0, 1);
955 odm_set_bb_reg(p_dm, 0x914, MASKBYTE1, 2);
956 }
957 } else {
958 if (!p_dm->is_mp_chip) { /* testchip */
959 odm_set_bb_reg(p_dm, 0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
960 odm_set_bb_reg(p_dm, 0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
961 odm_set_bb_reg(p_dm, 0x878, BIT(16), 0);
962 odm_set_bb_reg(p_dm, 0x858, BIT(15) | BIT(14), 2); /* (Reg878[0],Reg858[14:15])=3'b010 */
963 odm_set_bb_reg(p_dm, 0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
964 odm_set_bb_reg(p_dm, 0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
965 odm_set_bb_reg(p_dm, 0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
966 odm_set_bb_reg(p_dm, 0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
967 odm_set_bb_reg(p_dm, 0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
968 } else { /* MPchip */
969 odm_set_bb_reg(p_dm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */
970 odm_set_bb_reg(p_dm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */
971 odm_set_bb_reg(p_dm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */
972 odm_set_bb_reg(p_dm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */
973 odm_set_bb_reg(p_dm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */
974 odm_set_bb_reg(p_dm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */
975 odm_set_bb_reg(p_dm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */
976 odm_set_bb_reg(p_dm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */
977 }
978 }
979
980 /* Default ant setting when no fast training */
981 odm_set_bb_reg(p_dm, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
982 odm_set_bb_reg(p_dm, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
983 odm_set_bb_reg(p_dm, 0x860, BIT(14) | BIT(13) | BIT(12), 0); /* Default TX */
984
985 /* Enter Traing state */
986 odm_set_bb_reg(p_dm, 0x864, BIT(2) | BIT(1) | BIT(0), (p_dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */
987
988 /* SW Control */
989 /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
990 /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
991 /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
992 /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
993 /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
994 /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
995 }
996 #endif
997
998 #endif /* #if (RTL8188E_SUPPORT == 1) */
999
1000
1001 #if (RTL8192E_SUPPORT == 1)
1002 void
odm_rx_hw_ant_div_init_92e(void * p_dm_void)1003 odm_rx_hw_ant_div_init_92e(
1004 void *p_dm_void
1005 )
1006 {
1007 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1008 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1009
1010 #if 0
1011 if (*(p_dm->p_mp_mode) == true) {
1012 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
1013 odm_set_bb_reg(p_dm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1014 odm_set_bb_reg(p_dm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */
1015 return;
1016 }
1017 #endif
1018
1019 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"));
1020
1021 /* Pin Settings */
1022 odm_set_bb_reg(p_dm, 0x870, BIT(8), 0);/* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */
1023 odm_set_bb_reg(p_dm, 0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */
1024
1025 /* Mapping table */
1026 odm_set_bb_reg(p_dm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */
1027
1028 /* OFDM Settings */
1029 odm_set_bb_reg(p_dm, 0xca4, 0x7FF, 0xA0); /* thershold */
1030 odm_set_bb_reg(p_dm, 0xca4, 0x7FF000, 0x0); /* bias */
1031
1032 /* CCK Settings */
1033 odm_set_bb_reg(p_dm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1034 odm_set_bb_reg(p_dm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1035 odm_set_bb_reg(p_dm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */
1036 odm_set_bb_reg(p_dm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
1037
1038 #ifdef ODM_EVM_ENHANCE_ANTDIV
1039 phydm_evm_sw_antdiv_init(p_dm);
1040 #endif
1041
1042 }
1043
1044 void
odm_trx_hw_ant_div_init_92e(void * p_dm_void)1045 odm_trx_hw_ant_div_init_92e(
1046 void *p_dm_void
1047 )
1048 {
1049 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1050
1051 #if 0
1052 if (*(p_dm->p_mp_mode) == true) {
1053 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
1054 odm_set_bb_reg(p_dm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1055 odm_set_bb_reg(p_dm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */
1056 return;
1057 }
1058 #endif
1059
1060 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n"));
1061
1062 /* 3 --RFE pin setting--------- */
1063 /* [MAC] */
1064 odm_set_mac_reg(p_dm, 0x38, BIT(11), 1); /* DBG PAD Driving control (GPIO 8) */
1065 odm_set_mac_reg(p_dm, 0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
1066 odm_set_mac_reg(p_dm, 0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
1067 /* [BB] */
1068 odm_set_bb_reg(p_dm, 0x944, BIT(3), 1); /* RFE_buffer */
1069 odm_set_bb_reg(p_dm, 0x944, BIT(8), 1);
1070 odm_set_bb_reg(p_dm, 0x940, BIT(7) | BIT(6), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */
1071 odm_set_bb_reg(p_dm, 0x940, BIT(17) | BIT(16), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */
1072 odm_set_bb_reg(p_dm, 0x944, BIT(31), 0); /* RFE_buffer */
1073 odm_set_bb_reg(p_dm, 0x92C, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */
1074 odm_set_bb_reg(p_dm, 0x92C, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */
1075 odm_set_bb_reg(p_dm, 0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
1076 odm_set_bb_reg(p_dm, 0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1077 /* 3 ------------------------- */
1078
1079 /* Pin Settings */
1080 odm_set_bb_reg(p_dm, 0xC50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */
1081
1082 #if 0
1083 /* Let it follows PHY_REG for bit9 setting */
1084 if (p_dm->priv->pshare->rf_ft_var.use_ext_pa || p_dm->priv->pshare->rf_ft_var.use_ext_lna)
1085 odm_set_bb_reg(p_dm, 0xC50, BIT(9), 1); /* path-A output at CS */
1086 else
1087 odm_set_bb_reg(p_dm, 0xC50, BIT(9), 0); /* path-A output at CG ->normal power */
1088 #endif
1089
1090 odm_set_bb_reg(p_dm, 0x870, BIT(9) | BIT(8), 0); /* path-A*/ /* antsel antselb by HW */
1091 odm_set_bb_reg(p_dm, 0xB38, BIT(10), 0); /* path-A */ /* antsel2 by HW */
1092
1093 /* Mapping table */
1094 odm_set_bb_reg(p_dm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */
1095
1096 /* OFDM Settings */
1097 odm_set_bb_reg(p_dm, 0xca4, 0x7FF, 0xA0); /* thershold */
1098 odm_set_bb_reg(p_dm, 0xca4, 0x7FF000, 0x0); /* bias */
1099
1100 /* CCK Settings */
1101 odm_set_bb_reg(p_dm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1102 odm_set_bb_reg(p_dm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1103 odm_set_bb_reg(p_dm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */
1104 odm_set_bb_reg(p_dm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
1105
1106 #ifdef ODM_EVM_ENHANCE_ANTDIV
1107 phydm_evm_sw_antdiv_init(p_dm);
1108 #endif
1109 }
1110
1111 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
1112 void
odm_smart_hw_ant_div_init_92e(void * p_dm_void)1113 odm_smart_hw_ant_div_init_92e(
1114 void *p_dm_void
1115 )
1116 {
1117 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1118
1119 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"));
1120 }
1121 #endif
1122
1123 #endif /* #if (RTL8192E_SUPPORT == 1) */
1124
1125 #if (RTL8723D_SUPPORT == 1)
1126 void
odm_trx_hw_ant_div_init_8723d(void * p_dm_void)1127 odm_trx_hw_ant_div_init_8723d(
1128 void *p_dm_void
1129 )
1130 {
1131 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1132
1133 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n"));
1134
1135 /*BT Coexistence*/
1136 /*keep antsel_map when GNT_BT = 1*/
1137 odm_set_bb_reg(p_dm, 0x864, BIT(12), 1);
1138 /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1139 odm_set_bb_reg(p_dm, 0x874, BIT(23), 0);
1140 /* Disable hw antsw & fast_train.antsw when BT TX/RX */
1141 odm_set_bb_reg(p_dm, 0xE64, 0xFFFF0000, 0x000c);
1142
1143
1144 odm_set_bb_reg(p_dm, 0x870, BIT(9) | BIT(8), 0);
1145 /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/
1146 /*odm_set_bb_reg(p_dm, 0x948, BIT6, 0);*/
1147 /*odm_set_bb_reg(p_dm, 0x948, BIT8, 0);*/
1148 /*GNT_WL tx*/
1149 odm_set_bb_reg(p_dm, 0x950, BIT(29), 0);
1150
1151
1152 /*Mapping Table*/
1153 odm_set_bb_reg(p_dm, 0x914, MASKBYTE0, 0);
1154 odm_set_bb_reg(p_dm, 0x914, MASKBYTE1, 3);
1155 /* odm_set_bb_reg(p_dm, 0x864, BIT5|BIT4|BIT3, 0); */
1156 /* odm_set_bb_reg(p_dm, 0x864, BIT8|BIT7|BIT6, 1); */
1157
1158 /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
1159 odm_set_bb_reg(p_dm, 0xCcc, BIT(12), 0);
1160 /* Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
1161 odm_set_bb_reg(p_dm, 0xCcc, 0x0F, 0x01);
1162 /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
1163 odm_set_bb_reg(p_dm, 0xCcc, 0xF0, 0x0);
1164 /* b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
1165 odm_set_bb_reg(p_dm, 0xAbc, 0xFF, 0x06);
1166 /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
1167 odm_set_bb_reg(p_dm, 0xAbc, 0xFF00, 0x00);
1168
1169
1170 /*OFDM HW AntDiv Parameters*/
1171 odm_set_bb_reg(p_dm, 0xCA4, 0x7FF, 0xa0);
1172 odm_set_bb_reg(p_dm, 0xCA4, 0x7FF000, 0x00);
1173 odm_set_bb_reg(p_dm, 0xC5C, BIT(20) | BIT(19) | BIT(18), 0x04);
1174
1175 /*CCK HW AntDiv Parameters*/
1176 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1);
1177 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1);
1178 odm_set_bb_reg(p_dm, 0xAA8, BIT(8), 0);
1179
1180 odm_set_bb_reg(p_dm, 0xA0C, 0x0F, 0xf);
1181 odm_set_bb_reg(p_dm, 0xA14, 0x1F, 0x8);
1182 odm_set_bb_reg(p_dm, 0xA10, BIT(13), 0x1);
1183 odm_set_bb_reg(p_dm, 0xA74, BIT(8), 0x0);
1184 odm_set_bb_reg(p_dm, 0xB34, BIT(30), 0x1);
1185
1186 /*disable antenna training */
1187 odm_set_bb_reg(p_dm, 0xE08, BIT(16), 0);
1188 odm_set_bb_reg(p_dm, 0xc50, BIT(8), 0);
1189
1190 }
1191 /*Mingzhi 2017-05-08*/
1192
1193 void
odm_update_rx_idle_ant_8723d(void * p_dm_void,u8 ant,u32 default_ant,u32 optional_ant)1194 odm_update_rx_idle_ant_8723d(
1195 void *p_dm_void,
1196 u8 ant,
1197 u32 default_ant,
1198 u32 optional_ant
1199 )
1200 {
1201 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1202 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1203 struct _ADAPTER *p_adapter = p_dm->adapter;
1204 u8 count = 0;
1205
1206
1207 /* odm_set_bb_reg(p_dm, 0x948, BIT(6), 0x1); */
1208 odm_set_bb_reg(p_dm, 0x948, BIT(7), default_ant);
1209 odm_set_bb_reg(p_dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
1210 odm_set_bb_reg(p_dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
1211 odm_set_bb_reg(p_dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/
1212 p_dm_fat_table->rx_idle_ant = ant;
1213
1214 }
1215
1216 void
phydm_set_tx_ant_pwr_8723d(void * p_dm_void,u8 ant)1217 phydm_set_tx_ant_pwr_8723d(
1218 void *p_dm_void,
1219 u8 ant
1220 )
1221 {
1222 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1223 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1224 struct _ADAPTER *p_adapter = p_dm->adapter;
1225
1226 p_dm_fat_table->rx_idle_ant = ant;
1227
1228 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1229 p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm->p_channel);
1230 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1231 rtw_hal_set_tx_power_level(p_adapter, *p_dm->p_channel);
1232 #endif
1233
1234 }
1235 #endif
1236
1237 #if (RTL8723B_SUPPORT == 1)
1238 void
odm_trx_hw_ant_div_init_8723b(void * p_dm_void)1239 odm_trx_hw_ant_div_init_8723b(
1240 void *p_dm_void
1241 )
1242 {
1243 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1244
1245 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n"));
1246
1247 /* Mapping Table */
1248 odm_set_bb_reg(p_dm, 0x914, MASKBYTE0, 0);
1249 odm_set_bb_reg(p_dm, 0x914, MASKBYTE1, 1);
1250
1251 /* OFDM HW AntDiv Parameters */
1252 odm_set_bb_reg(p_dm, 0xCA4, 0x7FF, 0xa0); /* thershold */
1253 odm_set_bb_reg(p_dm, 0xCA4, 0x7FF000, 0x00); /* bias */
1254
1255 /* CCK HW AntDiv Parameters */
1256 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1257 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1258
1259 /* BT Coexistence */
1260 odm_set_bb_reg(p_dm, 0x864, BIT(12), 0); /* keep antsel_map when GNT_BT = 1 */
1261 odm_set_bb_reg(p_dm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1262
1263 /* Output Pin Settings */
1264 odm_set_bb_reg(p_dm, 0x870, BIT(8), 0);
1265
1266 odm_set_bb_reg(p_dm, 0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */
1267 odm_set_bb_reg(p_dm, 0x948, BIT(7), 0);
1268
1269 odm_set_mac_reg(p_dm, 0x40, BIT(3), 1);
1270 odm_set_mac_reg(p_dm, 0x38, BIT(11), 1);
1271 odm_set_mac_reg(p_dm, 0x4C, BIT(24) | BIT(23), 2); /* select DPDT_P and DPDT_N as output pin */
1272
1273 odm_set_bb_reg(p_dm, 0x944, BIT(0) | BIT(1), 3); /* in/out */
1274 odm_set_bb_reg(p_dm, 0x944, BIT(31), 0);
1275
1276 odm_set_bb_reg(p_dm, 0x92C, BIT(1), 0); /* DPDT_P non-inverse */
1277 odm_set_bb_reg(p_dm, 0x92C, BIT(0), 1); /* DPDT_N inverse */
1278
1279 odm_set_bb_reg(p_dm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */
1280 odm_set_bb_reg(p_dm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */
1281
1282 /* 2 [--For HW Bug setting] */
1283 if (p_dm->ant_type == ODM_AUTO_ANT)
1284 odm_set_bb_reg(p_dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
1285
1286 }
1287
1288
1289
1290 void
odm_s0s1_sw_ant_div_init_8723b(void * p_dm_void)1291 odm_s0s1_sw_ant_div_init_8723b(
1292 void *p_dm_void
1293 )
1294 {
1295 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1296 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
1297 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1298
1299 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"));
1300
1301 /* Mapping Table */
1302 odm_set_bb_reg(p_dm, 0x914, MASKBYTE0, 0);
1303 odm_set_bb_reg(p_dm, 0x914, MASKBYTE1, 1);
1304
1305 /* Output Pin Settings */
1306 /* odm_set_bb_reg(p_dm, 0x948, BIT6, 0x1); */
1307 odm_set_bb_reg(p_dm, 0x870, BIT(9) | BIT(8), 0);
1308
1309 p_dm_fat_table->is_become_linked = false;
1310 p_dm_swat_table->try_flag = SWAW_STEP_INIT;
1311 p_dm_swat_table->double_chk_flag = 0;
1312
1313 /* 2 [--For HW Bug setting] */
1314 odm_set_bb_reg(p_dm, 0x80C, BIT(21), 0); /* TX ant by Reg */
1315
1316 }
1317
1318 void
odm_update_rx_idle_ant_8723b(void * p_dm_void,u8 ant,u32 default_ant,u32 optional_ant)1319 odm_update_rx_idle_ant_8723b(
1320 void *p_dm_void,
1321 u8 ant,
1322 u32 default_ant,
1323 u32 optional_ant
1324 )
1325 {
1326 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1327 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1328 struct _ADAPTER *p_adapter = p_dm->adapter;
1329 u8 count = 0;
1330 /*u8 u1_temp;*/
1331 /*u8 h2c_parameter;*/
1332
1333 if ((!p_dm->is_linked) && (p_dm->ant_type == ODM_AUTO_ANT)) {
1334 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n"));
1335 return;
1336 }
1337
1338 #if 0
1339 /* Send H2C command to FW */
1340 /* Enable wifi calibration */
1341 h2c_parameter = true;
1342 odm_fill_h2c_cmd(p_dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1343
1344 /* Check if H2C command sucess or not (0x1e6) */
1345 u1_temp = odm_read_1byte(p_dm, 0x1e6);
1346 while ((u1_temp != 0x1) && (count < 100)) {
1347 ODM_delay_us(10);
1348 u1_temp = odm_read_1byte(p_dm, 0x1e6);
1349 count++;
1350 }
1351 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", u1_temp, count));
1352
1353 if (u1_temp == 0x1) {
1354 /* Check if BT is doing IQK (0x1e7) */
1355 count = 0;
1356 u1_temp = odm_read_1byte(p_dm, 0x1e7);
1357 while ((!(u1_temp & BIT(0))) && (count < 100)) {
1358 ODM_delay_us(50);
1359 u1_temp = odm_read_1byte(p_dm, 0x1e7);
1360 count++;
1361 }
1362 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", u1_temp, count));
1363
1364 if (u1_temp & BIT(0)) {
1365 odm_set_bb_reg(p_dm, 0x948, BIT(6), 0x1);
1366 odm_set_bb_reg(p_dm, 0x948, BIT(9), default_ant);
1367 odm_set_bb_reg(p_dm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */
1368 odm_set_bb_reg(p_dm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */
1369 odm_set_bb_reg(p_dm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */
1370 p_dm_fat_table->rx_idle_ant = ant;
1371
1372 /* Set TX AGC by S0/S1 */
1373 /* Need to consider Linux driver */
1374 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1375 p_adapter->hal_func.set_tx_power_level_handler(p_adapter, *p_dm->p_channel);
1376 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1377 rtw_hal_set_tx_power_level(p_adapter, *p_dm->p_channel);
1378 #endif
1379
1380 /* Set IQC by S0/S1 */
1381 odm_set_iqc_by_rfpath(p_dm, default_ant);
1382 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"));
1383 } else
1384 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n"));
1385 } else
1386 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n"));
1387
1388 /* Send H2C command to FW */
1389 /* Disable wifi calibration */
1390 h2c_parameter = false;
1391 odm_fill_h2c_cmd(p_dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1392 #else
1393
1394 odm_set_bb_reg(p_dm, 0x948, BIT(6), 0x1);
1395 odm_set_bb_reg(p_dm, 0x948, BIT(9), default_ant);
1396 odm_set_bb_reg(p_dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
1397 odm_set_bb_reg(p_dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
1398 odm_set_bb_reg(p_dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/
1399 p_dm_fat_table->rx_idle_ant = ant;
1400
1401 /* Set TX AGC by S0/S1 */
1402 /* Need to consider Linux driver */
1403 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1404 p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm->p_channel);
1405 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1406 rtw_hal_set_tx_power_level(p_adapter, *p_dm->p_channel);
1407 #endif
1408
1409 /* Set IQC by S0/S1 */
1410 odm_set_iqc_by_rfpath(p_dm, default_ant);
1411 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"));
1412
1413 #endif
1414 }
1415
1416 boolean
phydm_is_bt_enable_8723b(void * p_dm_void)1417 phydm_is_bt_enable_8723b(
1418 void *p_dm_void
1419 )
1420 {
1421 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1422 u32 bt_state;
1423 /*u32 reg75;*/
1424
1425 /*reg75 = odm_get_bb_reg(p_dm, 0x74, BIT8);*/
1426 /*odm_set_bb_reg(p_dm, 0x74, BIT8, 0x0);*/
1427 odm_set_bb_reg(p_dm, 0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
1428 bt_state = odm_get_bb_reg(p_dm, 0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1429 /*odm_set_bb_reg(p_dm, 0x74, BIT8, reg75);*/
1430
1431 if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13))
1432 return true;
1433 else
1434 return false;
1435 }
1436 #endif /* #if (RTL8723B_SUPPORT == 1) */
1437
1438 #if (RTL8821A_SUPPORT == 1)
1439
1440 void
odm_trx_hw_ant_div_init_8821a(void * p_dm_void)1441 odm_trx_hw_ant_div_init_8821a(
1442 void *p_dm_void
1443 )
1444 {
1445 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1446
1447 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n"));
1448
1449 /* Output Pin Settings */
1450 odm_set_mac_reg(p_dm, 0x4C, BIT(25), 0);
1451
1452 odm_set_mac_reg(p_dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
1453 odm_set_mac_reg(p_dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
1454
1455 odm_set_bb_reg(p_dm, 0xCB8, BIT(16), 0);
1456
1457 odm_set_mac_reg(p_dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1458 odm_set_mac_reg(p_dm, 0x4C, BIT(24), 1); /* by WLAN control */
1459 odm_set_bb_reg(p_dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
1460 odm_set_bb_reg(p_dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
1461 odm_set_bb_reg(p_dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
1462 odm_set_bb_reg(p_dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
1463
1464 /* Mapping Table */
1465 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE0, 0);
1466 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE1, 1);
1467
1468 /* OFDM HW AntDiv Parameters */
1469 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
1470 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF000, 0x10); /* bias */
1471
1472 /* CCK HW AntDiv Parameters */
1473 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1474 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1475
1476 odm_set_bb_reg(p_dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
1477 odm_set_bb_reg(p_dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
1478
1479 /* BT Coexistence */
1480 odm_set_bb_reg(p_dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
1481 odm_set_bb_reg(p_dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1482
1483 odm_set_bb_reg(p_dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1484
1485 /* response TX ant by RX ant */
1486 odm_set_mac_reg(p_dm, 0x668, BIT(3), 1);
1487
1488 }
1489
1490 void
odm_s0s1_sw_ant_div_init_8821a(void * p_dm_void)1491 odm_s0s1_sw_ant_div_init_8821a(
1492 void *p_dm_void
1493 )
1494 {
1495 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1496 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
1497
1498 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"));
1499
1500 /* Output Pin Settings */
1501 odm_set_mac_reg(p_dm, 0x4C, BIT(25), 0);
1502
1503 odm_set_mac_reg(p_dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
1504 odm_set_mac_reg(p_dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
1505
1506 odm_set_bb_reg(p_dm, 0xCB8, BIT(16), 0);
1507
1508 odm_set_mac_reg(p_dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1509 odm_set_mac_reg(p_dm, 0x4C, BIT(24), 1); /* by WLAN control */
1510 odm_set_bb_reg(p_dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
1511 odm_set_bb_reg(p_dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
1512 odm_set_bb_reg(p_dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
1513 odm_set_bb_reg(p_dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
1514
1515 /* Mapping Table */
1516 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE0, 0);
1517 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE1, 1);
1518
1519 /* OFDM HW AntDiv Parameters */
1520 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
1521 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF000, 0x10); /* bias */
1522
1523 /* CCK HW AntDiv Parameters */
1524 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1525 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1526
1527 odm_set_bb_reg(p_dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
1528 odm_set_bb_reg(p_dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
1529
1530 /* BT Coexistence */
1531 odm_set_bb_reg(p_dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
1532 odm_set_bb_reg(p_dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1533
1534 odm_set_bb_reg(p_dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1535
1536 /* response TX ant by RX ant */
1537 odm_set_mac_reg(p_dm, 0x668, BIT(3), 1);
1538
1539
1540 odm_set_bb_reg(p_dm, 0x900, BIT(18), 0);
1541
1542 p_dm_swat_table->try_flag = SWAW_STEP_INIT;
1543 p_dm_swat_table->double_chk_flag = 0;
1544 p_dm_swat_table->cur_antenna = MAIN_ANT;
1545 p_dm_swat_table->pre_antenna = MAIN_ANT;
1546 p_dm_swat_table->swas_no_link_state = 0;
1547
1548 }
1549 #endif /* #if (RTL8821A_SUPPORT == 1) */
1550
1551 #if (RTL8821C_SUPPORT == 1)
1552 void
odm_trx_hw_ant_div_init_8821c(void * p_dm_void)1553 odm_trx_hw_ant_div_init_8821c(
1554 void *p_dm_void
1555 )
1556 {
1557 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1558
1559 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n"));
1560 /* Output Pin Settings */
1561 odm_set_mac_reg(p_dm, 0x4C, BIT(25), 0);
1562
1563 odm_set_mac_reg(p_dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
1564 odm_set_mac_reg(p_dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
1565
1566 odm_set_bb_reg(p_dm, 0xCB8, BIT(16), 0);
1567
1568 odm_set_mac_reg(p_dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1569 odm_set_mac_reg(p_dm, 0x4C, BIT(24), 1); /* by WLAN control */
1570 odm_set_bb_reg(p_dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
1571 odm_set_bb_reg(p_dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
1572 odm_set_bb_reg(p_dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
1573 odm_set_bb_reg(p_dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
1574
1575 /* Mapping Table */
1576 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE0, 0);
1577 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE1, 1);
1578
1579 /* OFDM HW AntDiv Parameters */
1580 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
1581 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF000, 0x10); /* bias */
1582
1583 /* CCK HW AntDiv Parameters */
1584 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1585 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1586
1587 odm_set_bb_reg(p_dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
1588 odm_set_bb_reg(p_dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
1589
1590 /* BT Coexistence */
1591 odm_set_bb_reg(p_dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
1592 odm_set_bb_reg(p_dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1593
1594 /* Timming issue */
1595 odm_set_bb_reg(p_dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
1596 odm_set_bb_reg(p_dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1597
1598 /* response TX ant by RX ant */
1599 odm_set_mac_reg(p_dm, 0x668, BIT(3), 1);
1600
1601 }
1602
1603 void
phydm_s0s1_sw_ant_div_init_8821c(void * p_dm_void)1604 phydm_s0s1_sw_ant_div_init_8821c(
1605 void *p_dm_void
1606 )
1607 {
1608 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1609 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
1610
1611 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8821C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"));
1612
1613 /* Output Pin Settings */
1614 odm_set_mac_reg(p_dm, 0x4C, BIT(25), 0);
1615
1616 odm_set_mac_reg(p_dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
1617 odm_set_mac_reg(p_dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
1618
1619 odm_set_bb_reg(p_dm, 0xCB8, BIT(16), 0);
1620
1621 odm_set_mac_reg(p_dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1622 odm_set_mac_reg(p_dm, 0x4C, BIT(24), 1); /* by WLAN control */
1623 odm_set_bb_reg(p_dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
1624 odm_set_bb_reg(p_dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
1625 odm_set_bb_reg(p_dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
1626 odm_set_bb_reg(p_dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
1627
1628 /* Mapping Table */
1629 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE0, 0);
1630 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE1, 1);
1631
1632 /* OFDM HW AntDiv Parameters */
1633 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
1634 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF000, 0x00); /* bias */
1635
1636 /* CCK HW AntDiv Parameters */
1637 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1638 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1639
1640 odm_set_bb_reg(p_dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
1641 odm_set_bb_reg(p_dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
1642
1643 /* BT Coexistence */
1644 odm_set_bb_reg(p_dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
1645 odm_set_bb_reg(p_dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1646
1647 odm_set_bb_reg(p_dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1648
1649 /* response TX ant by RX ant */
1650 odm_set_mac_reg(p_dm, 0x668, BIT(3), 1);
1651
1652
1653 odm_set_bb_reg(p_dm, 0x900, BIT(18), 0);
1654
1655 p_dm_swat_table->try_flag = SWAW_STEP_INIT;
1656 p_dm_swat_table->double_chk_flag = 0;
1657 p_dm_swat_table->cur_antenna = MAIN_ANT;
1658 p_dm_swat_table->pre_antenna = MAIN_ANT;
1659 p_dm_swat_table->swas_no_link_state = 0;
1660
1661 }
1662 #endif /* #if (RTL8821C_SUPPORT == 1) */
1663
1664
1665 #if (RTL8881A_SUPPORT == 1)
1666 void
odm_trx_hw_ant_div_init_8881a(void * p_dm_void)1667 odm_trx_hw_ant_div_init_8881a(
1668 void *p_dm_void
1669 )
1670 {
1671 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1672
1673 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n"));
1674
1675 /* Output Pin Settings */
1676 /* [SPDT related] */
1677 odm_set_mac_reg(p_dm, 0x4C, BIT(25), 0);
1678 odm_set_mac_reg(p_dm, 0x4C, BIT(26), 0);
1679 odm_set_bb_reg(p_dm, 0xCB4, BIT(31), 0); /* delay buffer */
1680 odm_set_bb_reg(p_dm, 0xCB4, BIT(22), 0);
1681 odm_set_bb_reg(p_dm, 0xCB4, BIT(24), 1);
1682 odm_set_bb_reg(p_dm, 0xCB0, 0xF00, 8); /* DPDT_P = ANTSEL[0] */
1683 odm_set_bb_reg(p_dm, 0xCB0, 0xF0000, 8); /* DPDT_N = ANTSEL[0] */
1684
1685 /* Mapping Table */
1686 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE0, 0);
1687 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE1, 1);
1688
1689 /* OFDM HW AntDiv Parameters */
1690 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
1691 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF000, 0x0); /* bias */
1692 odm_set_bb_reg(p_dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1693
1694 /* CCK HW AntDiv Parameters */
1695 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1696 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1697
1698 /* 2 [--For HW Bug setting] */
1699
1700 odm_set_bb_reg(p_dm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */
1701 }
1702
1703 #endif /* #if (RTL8881A_SUPPORT == 1) */
1704
1705
1706 #if (RTL8812A_SUPPORT == 1)
1707 void
odm_trx_hw_ant_div_init_8812a(void * p_dm_void)1708 odm_trx_hw_ant_div_init_8812a(
1709 void *p_dm_void
1710 )
1711 {
1712 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1713
1714 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n"));
1715
1716 /* 3 */ /* 3 --RFE pin setting--------- */
1717 /* [BB] */
1718 odm_set_bb_reg(p_dm, 0x900, BIT(10) | BIT(9) | BIT(8), 0x0); /* disable SW switch */
1719 odm_set_bb_reg(p_dm, 0x900, BIT(17) | BIT(16), 0x0);
1720 odm_set_bb_reg(p_dm, 0x974, BIT(7) | BIT(6), 0x3); /* in/out */
1721 odm_set_bb_reg(p_dm, 0xCB4, BIT(31), 0); /* delay buffer */
1722 odm_set_bb_reg(p_dm, 0xCB4, BIT(26), 0);
1723 odm_set_bb_reg(p_dm, 0xCB4, BIT(27), 1);
1724 odm_set_bb_reg(p_dm, 0xCB0, 0xF000000, 8); /* DPDT_P = ANTSEL[0] */
1725 odm_set_bb_reg(p_dm, 0xCB0, 0xF0000000, 8); /* DPDT_N = ANTSEL[0] */
1726 /* 3 ------------------------- */
1727
1728 /* Mapping Table */
1729 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE0, 0);
1730 odm_set_bb_reg(p_dm, 0xCA4, MASKBYTE1, 1);
1731
1732 /* OFDM HW AntDiv Parameters */
1733 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
1734 odm_set_bb_reg(p_dm, 0x8D4, 0x7FF000, 0x0); /* bias */
1735 odm_set_bb_reg(p_dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1736
1737 /* CCK HW AntDiv Parameters */
1738 odm_set_bb_reg(p_dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
1739 odm_set_bb_reg(p_dm, 0xA0C, BIT(4), 1); /* do 64 samples */
1740
1741 /* 2 [--For HW Bug setting] */
1742
1743 odm_set_bb_reg(p_dm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */
1744
1745 }
1746
1747 #endif /* #if (RTL8812A_SUPPORT == 1) */
1748
1749 #if (RTL8188F_SUPPORT == 1)
1750 void
odm_s0s1_sw_ant_div_init_8188f(void * p_dm_void)1751 odm_s0s1_sw_ant_div_init_8188f(
1752 void *p_dm_void
1753 )
1754 {
1755 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1756 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
1757 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1758
1759 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"));
1760
1761
1762 /*GPIO setting*/
1763 /*odm_set_mac_reg(p_dm, 0x64, BIT(18), 0); */
1764 /*odm_set_mac_reg(p_dm, 0x44, BIT(28)|BIT(27), 0);*/
1765 /*odm_set_mac_reg(p_dm, 0x44, BIT(20) | BIT(19), 0x3);*/ /*enable_output for P_GPIO[4:3]*/
1766 /*odm_set_mac_reg(p_dm, 0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
1767 /*odm_set_mac_reg(p_dm, 0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
1768
1769 if (p_dm->support_ic_type == ODM_RTL8188F) {
1770 if (p_dm->support_interface == ODM_ITRF_USB)
1771 odm_set_mac_reg(p_dm, 0x44, BIT(20) | BIT(19), 0x3); /*enable_output for P_GPIO[4:3]*/
1772 else if (p_dm->support_interface == ODM_ITRF_SDIO)
1773 odm_set_mac_reg(p_dm, 0x44, BIT(18), 0x1); /*enable_output for P_GPIO[2]*/
1774 }
1775
1776 p_dm_fat_table->is_become_linked = false;
1777 p_dm_swat_table->try_flag = SWAW_STEP_INIT;
1778 p_dm_swat_table->double_chk_flag = 0;
1779 }
1780
1781 void
phydm_update_rx_idle_antenna_8188F(void * p_dm_void,u32 default_ant)1782 phydm_update_rx_idle_antenna_8188F(
1783 void *p_dm_void,
1784 u32 default_ant
1785 )
1786 {
1787 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1788 u8 codeword;
1789
1790 if (p_dm->support_ic_type == ODM_RTL8188F) {
1791 if (p_dm->support_interface == ODM_ITRF_USB) {
1792 if (default_ant == ANT1_2G)
1793 codeword = 1; /*2'b01*/
1794 else
1795 codeword = 2;/*2'b10*/
1796 odm_set_mac_reg(p_dm, 0x44, (BIT(12) | BIT(11)), codeword); /*GPIO[4:3] output value*/
1797 } else if (p_dm->support_interface == ODM_ITRF_SDIO) {
1798 if (default_ant == ANT1_2G) {
1799 codeword = 0; /*1'b0*/
1800 odm_set_bb_reg(p_dm, 0x870, BIT(9)|BIT(8), 0x3);
1801 odm_set_bb_reg(p_dm, 0x860, BIT(9)|BIT(8), 0x1);
1802 } else {
1803 codeword = 1;/*1'b1*/
1804 odm_set_bb_reg(p_dm, 0x870, BIT(9)|BIT(8), 0x3);
1805 odm_set_bb_reg(p_dm, 0x860, BIT(9)|BIT(8), 0x2);
1806 }
1807 odm_set_mac_reg(p_dm, 0x44, BIT(10), codeword); /*GPIO[2] output value*/
1808 }
1809 }
1810 }
1811 #endif
1812
1813
1814
1815 #ifdef ODM_EVM_ENHANCE_ANTDIV
1816 void
phydm_evm_sw_antdiv_init(void * p_dm_void)1817 phydm_evm_sw_antdiv_init(
1818 void *p_dm_void
1819 )
1820 {
1821 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1822 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1823
1824 /*EVM enhance AntDiv method init----------------------------------------------------------------------*/
1825 p_dm_fat_table->EVM_method_enable = 0;
1826 p_dm_fat_table->fat_state = NORMAL_STATE_MIAN;
1827 p_dm_fat_table->fat_state_cnt = 0;
1828 p_dm_fat_table->pre_antdiv_rssi = 0;
1829
1830 p_dm->antdiv_intvl = 30;
1831 p_dm->antdiv_train_num = 2;
1832 odm_set_bb_reg(p_dm, 0x910, 0x3f, 0xf);
1833 p_dm->antdiv_evm_en = 1;
1834 /*p_dm->antdiv_period=1;*/
1835 p_dm->evm_antdiv_period = 3;
1836 p_dm->stop_antdiv_rssi_th = 3;
1837 p_dm->stop_antdiv_tp_th = 80;
1838 p_dm->antdiv_tp_period = 3;
1839 p_dm->stop_antdiv_tp_diff_th = 5;
1840 }
1841
1842 void
odm_evm_fast_ant_reset(void * p_dm_void)1843 odm_evm_fast_ant_reset(
1844 void *p_dm_void
1845 )
1846 {
1847 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1848 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1849
1850 p_dm_fat_table->EVM_method_enable = 0;
1851 odm_ant_div_on_off(p_dm, ANTDIV_ON);
1852 p_dm_fat_table->fat_state = NORMAL_STATE_MIAN;
1853 p_dm_fat_table->fat_state_cnt = 0;
1854 p_dm->antdiv_period = 0;
1855 odm_set_mac_reg(p_dm, 0x608, BIT(8), 0);
1856 }
1857
1858
1859 void
odm_evm_enhance_ant_div(void * p_dm_void)1860 odm_evm_enhance_ant_div(
1861 void *p_dm_void
1862 )
1863 {
1864 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1865 u32 main_rssi, aux_rssi ;
1866 u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
1867 u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
1868 u32 main_2ss_evm[2], aux_2ss_evm[2];
1869 u32 main_1ss_evm, aux_1ss_evm;
1870 u32 main_2ss_evm_sum, aux_2ss_evm_sum;
1871 u8 score_EVM = 0, score_CRC = 0;
1872 u8 rssi_larger_ant = 0;
1873 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
1874 u32 value32, i;
1875 boolean main_above1 = false, aux_above1 = false;
1876 boolean force_antenna = false;
1877 struct cmn_sta_info *p_sta;
1878 u32 antdiv_tp_main_avg, antdiv_tp_aux_avg;
1879 u8 curr_rssi, rssi_diff;
1880 u32 tp_diff;
1881 u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
1882 u8 target_ant_evm_1ss, target_ant_evm_2ss;
1883 u8 decision_evm_ss;
1884 u8 next_ant;
1885
1886 p_dm_fat_table->target_ant_enhance = 0xFF;
1887
1888 if ((p_dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) {
1889 if (p_dm->is_one_entry_only) {
1890 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("[One Client only]\n")); */
1891 i = p_dm->one_entry_macid;
1892 p_sta = p_dm->p_phydm_sta_info[i];
1893
1894 main_rssi = (p_dm_fat_table->main_ant_cnt[i] != 0) ? (p_dm_fat_table->main_ant_sum[i] / p_dm_fat_table->main_ant_cnt[i]) : 0;
1895 aux_rssi = (p_dm_fat_table->aux_ant_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_sum[i] / p_dm_fat_table->aux_ant_cnt[i]) : 0;
1896
1897 if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
1898 diff_rssi = FORCE_RSSI_DIFF;
1899 else if (main_rssi != 0 && aux_rssi != 0)
1900 diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
1901
1902 if (main_rssi >= aux_rssi)
1903 rssi_larger_ant = MAIN_ANT;
1904 else
1905 rssi_larger_ant = AUX_ANT;
1906
1907 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Main_Cnt=(( %d )), main_rssi=(( %d ))\n", p_dm_fat_table->main_ant_cnt[i], main_rssi));
1908 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", p_dm_fat_table->aux_ant_cnt[i], aux_rssi));
1909
1910 if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || (p_dm_fat_table->EVM_method_enable == 1))
1911 /* && (diff_rssi <= FORCE_RSSI_DIFF + 1) */
1912 ) {
1913 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("> TH_H || EVM_method_enable==1\n"));
1914
1915 if (((main_rssi >= evm_rssi_th_low) || (aux_rssi >= evm_rssi_th_low))) {
1916 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("> TH_L, fat_state_cnt =((%d))\n", p_dm_fat_table->fat_state_cnt));
1917
1918 /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
1919 if (p_dm_fat_table->fat_state_cnt < ((p_dm->antdiv_train_num)<<1)) {
1920
1921 if (p_dm_fat_table->fat_state_cnt == 0) {
1922 /*Reset EVM 1SS Method */
1923 p_dm_fat_table->main_ant_evm_sum[i] = 0;
1924 p_dm_fat_table->aux_ant_evm_sum[i] = 0;
1925 p_dm_fat_table->main_ant_evm_cnt[i] = 0;
1926 p_dm_fat_table->aux_ant_evm_cnt[i] = 0;
1927 /*Reset EVM 2SS Method */
1928 p_dm_fat_table->main_ant_evm_2ss_sum[i][0] = 0;
1929 p_dm_fat_table->main_ant_evm_2ss_sum[i][1] = 0;
1930 p_dm_fat_table->aux_ant_evm_2ss_sum[i][0] = 0;
1931 p_dm_fat_table->aux_ant_evm_2ss_sum[i][1] = 0;
1932 p_dm_fat_table->main_ant_evm_2ss_cnt[i] = 0;
1933 p_dm_fat_table->aux_ant_evm_2ss_cnt[i] = 0;
1934 #if 0
1935 /*Reset TP Method */
1936 p_dm_fat_table->antdiv_tp_main = 0;
1937 p_dm_fat_table->antdiv_tp_aux = 0;
1938 p_dm_fat_table->antdiv_tp_main_cnt = 0;
1939 p_dm_fat_table->antdiv_tp_aux_cnt = 0;
1940 #endif
1941 /*Reset CRC Method */
1942 p_dm_fat_table->main_crc32_ok_cnt = 0;
1943 p_dm_fat_table->main_crc32_fail_cnt = 0;
1944 p_dm_fat_table->aux_crc32_ok_cnt = 0;
1945 p_dm_fat_table->aux_crc32_fail_cnt = 0;
1946
1947 #ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
1948 if ((*p_dm->p_band_width == CHANNEL_WIDTH_20) && (p_sta->mimo_type == RF_2T2R)) {
1949 /*1. Skip training: RSSI*/
1950 /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, ("TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt));*/
1951 curr_rssi = (u8)((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
1952 rssi_diff = (curr_rssi > p_dm_fat_table->pre_antdiv_rssi) ? (curr_rssi - p_dm_fat_table->pre_antdiv_rssi) : (p_dm_fat_table->pre_antdiv_rssi - curr_rssi);
1953
1954 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, p_dm_fat_table->pre_antdiv_rssi));
1955
1956 p_dm_fat_table->pre_antdiv_rssi = curr_rssi;
1957 if ((rssi_diff < (p_dm->stop_antdiv_rssi_th)) && (curr_rssi != 0))
1958 rssi_return = 1;
1959
1960 /*2. Skip training: TP Diff*/
1961 tp_diff = (p_dm->rx_tp > p_dm_fat_table->pre_antdiv_tp) ? (p_dm->rx_tp - p_dm_fat_table->pre_antdiv_tp) : (p_dm_fat_table->pre_antdiv_tp - p_dm->rx_tp);
1962
1963 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", p_dm->rx_tp, p_dm_fat_table->pre_antdiv_tp));
1964 p_dm_fat_table->pre_antdiv_tp = p_dm->rx_tp;
1965 if ((tp_diff < (u32)(p_dm->stop_antdiv_tp_diff_th) && (p_dm->rx_tp != 0)))
1966 tp_diff_return = 1;
1967
1968 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[3] tp_return, curr_rx_tp=((%d))\n", p_dm->rx_tp));
1969 /*3. Skip training: TP*/
1970 if (p_dm->rx_tp >= (u32)(p_dm->stop_antdiv_tp_th))
1971 tp_return = 1;
1972
1973 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return));
1974 /*4. Joint Return Decision*/
1975 if (tp_return) {
1976 if (tp_diff_return || rssi_diff) {
1977
1978 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***Return EVM SW AntDiv\n"));
1979 return;
1980 }
1981 }
1982 }
1983 #endif
1984
1985 p_dm_fat_table->EVM_method_enable = 1;
1986 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
1987 p_dm->antdiv_period = p_dm->evm_antdiv_period;
1988 odm_set_mac_reg(p_dm, 0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
1989
1990 }
1991
1992
1993 p_dm_fat_table->fat_state_cnt++;
1994 next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
1995 odm_update_rx_idle_ant(p_dm, next_ant);
1996 odm_set_timer(p_dm, &p_dm->evm_fast_ant_training_timer, p_dm->antdiv_intvl); //ms
1997
1998 }
1999 /*Decision state: 4==============================================================*/
2000 else {
2001
2002 p_dm_fat_table->fat_state_cnt = 0;
2003 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Decisoin state ]\n"));
2004
2005 /* 3 [CRC32 statistic] */
2006 #if 0
2007 if ((p_dm_fat_table->main_crc32_ok_cnt > ((p_dm_fat_table->aux_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == MAIN_ANT))) {
2008 p_dm_fat_table->target_ant_crc32 = MAIN_ANT;
2009 force_antenna = true;
2010 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("CRC32 Force Main\n"));
2011 } else if ((p_dm_fat_table->aux_crc32_ok_cnt > ((p_dm_fat_table->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
2012 p_dm_fat_table->target_ant_crc32 = AUX_ANT;
2013 force_antenna = true;
2014 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("CRC32 Force Aux\n"));
2015 } else
2016 #endif
2017 {
2018 if (p_dm_fat_table->main_crc32_fail_cnt <= 5)
2019 p_dm_fat_table->main_crc32_fail_cnt = 5;
2020
2021 if (p_dm_fat_table->aux_crc32_fail_cnt <= 5)
2022 p_dm_fat_table->aux_crc32_fail_cnt = 5;
2023
2024 if (p_dm_fat_table->main_crc32_ok_cnt > p_dm_fat_table->main_crc32_fail_cnt)
2025 main_above1 = true;
2026
2027 if (p_dm_fat_table->aux_crc32_ok_cnt > p_dm_fat_table->aux_crc32_fail_cnt)
2028 aux_above1 = true;
2029
2030 if (main_above1 == true && aux_above1 == false) {
2031 force_antenna = true;
2032 p_dm_fat_table->target_ant_crc32 = MAIN_ANT;
2033 } else if (main_above1 == false && aux_above1 == true) {
2034 force_antenna = true;
2035 p_dm_fat_table->target_ant_crc32 = AUX_ANT;
2036 } else if (main_above1 == true && aux_above1 == true) {
2037 main_crc_utility = ((p_dm_fat_table->main_crc32_ok_cnt) << 7) / p_dm_fat_table->main_crc32_fail_cnt;
2038 aux_crc_utility = ((p_dm_fat_table->aux_crc32_ok_cnt) << 7) / p_dm_fat_table->aux_crc32_fail_cnt;
2039 p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
2040
2041 if (main_crc_utility != 0 && aux_crc_utility != 0) {
2042 if (main_crc_utility >= aux_crc_utility)
2043 utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
2044 else
2045 utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
2046 }
2047 } else if (main_above1 == false && aux_above1 == false) {
2048 if (p_dm_fat_table->main_crc32_ok_cnt == 0)
2049 p_dm_fat_table->main_crc32_ok_cnt = 1;
2050 if (p_dm_fat_table->aux_crc32_ok_cnt == 0)
2051 p_dm_fat_table->aux_crc32_ok_cnt = 1;
2052
2053 main_crc_utility = ((p_dm_fat_table->main_crc32_fail_cnt) << 7) / p_dm_fat_table->main_crc32_ok_cnt;
2054 aux_crc_utility = ((p_dm_fat_table->aux_crc32_fail_cnt) << 7) / p_dm_fat_table->aux_crc32_ok_cnt;
2055 p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
2056
2057 if (main_crc_utility != 0 && aux_crc_utility != 0) {
2058 if (main_crc_utility >= aux_crc_utility)
2059 utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
2060 else
2061 utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
2062 }
2063 }
2064 }
2065 odm_set_mac_reg(p_dm, 0x608, BIT(8), 0);/* NOT Accept CRC32 Error packets. */
2066 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", p_dm_fat_table->main_crc32_ok_cnt, p_dm_fat_table->main_crc32_fail_cnt, main_crc_utility));
2067 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", p_dm_fat_table->aux_crc32_ok_cnt, p_dm_fat_table->aux_crc32_fail_cnt, aux_crc_utility));
2068 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***1.TargetAnt_CRC32 = ((%s))\n", (p_dm_fat_table->target_ant_crc32 == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
2069
2070 /* 3 [EVM statistic] */
2071 /*1SS EVM*/
2072 main_1ss_evm = (p_dm_fat_table->main_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_sum[i] / p_dm_fat_table->main_ant_evm_cnt[i]) : 0;
2073 aux_1ss_evm = (p_dm_fat_table->aux_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_sum[i] / p_dm_fat_table->aux_ant_evm_cnt[i]) : 0;
2074 target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
2075
2076 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", p_dm_fat_table->main_ant_evm_cnt[i], main_1ss_evm));
2077 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", p_dm_fat_table->main_ant_evm_cnt[i], aux_1ss_evm));
2078
2079 /*2SS EVM*/
2080 main_2ss_evm[0] = (p_dm_fat_table->main_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_2ss_sum[i][0] / p_dm_fat_table->main_ant_evm_2ss_cnt[i]) : 0;
2081 main_2ss_evm[1] = (p_dm_fat_table->main_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_2ss_sum[i][1] / p_dm_fat_table->main_ant_evm_2ss_cnt[i]) : 0;
2082 main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
2083
2084 aux_2ss_evm[0] = (p_dm_fat_table->aux_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_2ss_sum[i][0] / p_dm_fat_table->aux_ant_evm_2ss_cnt[i]) : 0;
2085 aux_2ss_evm[1] = (p_dm_fat_table->aux_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_2ss_sum[i][1] / p_dm_fat_table->aux_ant_evm_2ss_cnt[i]) : 0;
2086 aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
2087
2088 target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
2089
2090 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
2091 p_dm_fat_table->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum));
2092 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
2093 p_dm_fat_table->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum));
2094
2095 if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
2096 decision_evm_ss = 2;
2097 main_evm = main_2ss_evm_sum;
2098 aux_evm = aux_2ss_evm_sum;
2099 p_dm_fat_table->target_ant_evm = target_ant_evm_2ss;
2100 } else {
2101 decision_evm_ss = 1;
2102 main_evm = main_1ss_evm;
2103 aux_evm = aux_1ss_evm;
2104 p_dm_fat_table->target_ant_evm = target_ant_evm_1ss;
2105 }
2106
2107 if ((main_evm == 0 || aux_evm == 0))
2108 diff_EVM = 100;
2109 else if (main_evm >= aux_evm)
2110 diff_EVM = main_evm - aux_evm;
2111 else
2112 diff_EVM = aux_evm - main_evm;
2113
2114 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (p_dm_fat_table->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
2115
2116
2117 //3 [TP statistic]
2118 antdiv_tp_main_avg = (p_dm_fat_table->antdiv_tp_main_cnt != 0) ? (p_dm_fat_table->antdiv_tp_main / p_dm_fat_table->antdiv_tp_main_cnt) : 0;
2119 antdiv_tp_aux_avg = (p_dm_fat_table->antdiv_tp_aux_cnt != 0) ? (p_dm_fat_table->antdiv_tp_aux / p_dm_fat_table->antdiv_tp_aux_cnt) : 0;
2120 p_dm_fat_table->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (p_dm_fat_table->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT);
2121
2122 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Cnt = ((%d)), Main_TP = ((%d))\n", p_dm_fat_table->antdiv_tp_main_cnt, antdiv_tp_main_avg));
2123 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Cnt = ((%d)), Aux_TP = ((%d))\n", p_dm_fat_table->antdiv_tp_aux_cnt, antdiv_tp_aux_avg));
2124 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***3.TargetAnt_TP = ((%s))\n", (p_dm_fat_table->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
2125
2126 /*Reset TP Method */
2127 p_dm_fat_table->antdiv_tp_main = 0;
2128 p_dm_fat_table->antdiv_tp_aux = 0;
2129 p_dm_fat_table->antdiv_tp_main_cnt = 0;
2130 p_dm_fat_table->antdiv_tp_aux_cnt = 0;
2131
2132 /* 2 [ Decision state ] */
2133 if (p_dm_fat_table->target_ant_evm == p_dm_fat_table->target_ant_crc32) {
2134 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
2135
2136 if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
2137 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance;
2138 else
2139 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm;
2140 }
2141 #if 0
2142 else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
2143 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
2144 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32;
2145 }
2146 #endif
2147 else if (diff_EVM >= 20) {
2148 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
2149 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm;
2150 } else if (utility_ratio >= 6 && force_antenna == false) {
2151 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
2152 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32;
2153 } else {
2154 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
2155
2156 if (force_antenna == true)
2157 score_CRC = 2;
2158 else if (utility_ratio >= 5) /*>2.5*/
2159 score_CRC = 2;
2160 else if (utility_ratio >= 4) /*>2*/
2161 score_CRC = 1;
2162 else
2163 score_CRC = 0;
2164
2165 if (diff_EVM >= 15)
2166 score_EVM = 3;
2167 else if (diff_EVM >= 10)
2168 score_EVM = 2;
2169 else if (diff_EVM >= 5)
2170 score_EVM = 1;
2171 else
2172 score_EVM = 0;
2173
2174 if (score_CRC > score_EVM)
2175 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32;
2176 else if (score_CRC < score_EVM)
2177 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm;
2178 else
2179 p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance;
2180 }
2181 p_dm_fat_table->pre_target_ant_enhance = p_dm_fat_table->target_ant_enhance;
2182
2183 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** 4.TargetAnt_enhance = (( %s ))******\n", (p_dm_fat_table->target_ant_enhance == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
2184
2185
2186 }
2187 } else { /* RSSI< = evm_rssi_th_low */
2188 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ <TH_L: escape from > TH_L ]\n"));
2189 odm_evm_fast_ant_reset(p_dm);
2190 }
2191 } else {
2192 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[escape from> TH_H || EVM_method_enable==1]\n"));
2193 odm_evm_fast_ant_reset(p_dm);
2194 }
2195 } else {
2196 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[multi-Client]\n"));
2197 odm_evm_fast_ant_reset(p_dm);
2198 }
2199 }
2200 }
2201
2202 void
odm_evm_fast_ant_training_callback(void * p_dm_void)2203 odm_evm_fast_ant_training_callback(
2204 void *p_dm_void
2205 )
2206 {
2207 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2208
2209 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("******AntDiv_Callback******\n"));
2210 odm_hw_ant_div(p_dm);
2211 }
2212 #endif
2213
2214 void
odm_hw_ant_div(void * p_dm_void)2215 odm_hw_ant_div(
2216 void *p_dm_void
2217 )
2218 {
2219 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2220 u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi;
2221 u32 main_rssi, aux_rssi, mian_cnt, aux_cnt;
2222 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
2223 u8 rx_idle_ant = p_dm_fat_table->rx_idle_ant, target_ant = 7;
2224 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
2225 struct cmn_sta_info *p_sta;
2226
2227 #if (BEAMFORMING_SUPPORT == 1)
2228 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2229 struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm->dm_bdc_table;
2230 u32 TH1 = 500000;
2231 u32 TH2 = 10000000;
2232 u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
2233 u8 monitor_rssi_threshold = 30;
2234
2235 p_dm_bdc_table->BF_pass = true;
2236 p_dm_bdc_table->DIV_pass = true;
2237 p_dm_bdc_table->is_all_div_sta_idle = true;
2238 p_dm_bdc_table->is_all_bf_sta_idle = true;
2239 p_dm_bdc_table->num_bf_tar = 0 ;
2240 p_dm_bdc_table->num_div_tar = 0;
2241 p_dm_bdc_table->num_client = 0;
2242 #endif
2243 #endif
2244
2245 if (!p_dm->is_linked) { /* is_linked==False */
2246 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[No Link!!!]\n"));
2247
2248 if (p_dm_fat_table->is_become_linked == true) {
2249 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
2250 odm_update_rx_idle_ant(p_dm, MAIN_ANT);
2251 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
2252 p_dm->antdiv_period = 0;
2253
2254 p_dm_fat_table->is_become_linked = p_dm->is_linked;
2255 }
2256 return;
2257 } else {
2258 if (p_dm_fat_table->is_become_linked == false) {
2259 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Linked !!!]\n"));
2260 odm_ant_div_on_off(p_dm, ANTDIV_ON);
2261 /*odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_DESC);*/
2262
2263 /* if(p_dm->support_ic_type == ODM_RTL8821 ) */
2264 /* odm_set_bb_reg(p_dm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */
2265
2266 /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
2267 /* else if(p_dm->support_ic_type == ODM_RTL8881A) */
2268 /* odm_set_bb_reg(p_dm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */
2269 /* #endif */
2270
2271 /* else if(p_dm->support_ic_type == ODM_RTL8723B ||p_dm->support_ic_type == ODM_RTL8812) */
2272 /* odm_set_bb_reg(p_dm, 0xA00, BIT(15), 0); */ /* CCK AntDiv function disable */
2273
2274 p_dm_fat_table->is_become_linked = p_dm->is_linked;
2275
2276 if (p_dm->support_ic_type == ODM_RTL8723B && p_dm->ant_div_type == CG_TRX_HW_ANTDIV) {
2277 odm_set_bb_reg(p_dm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ /* for 8723B AntDiv function patch. BB Dino 130412 */
2278 odm_set_bb_reg(p_dm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */
2279 }
2280
2281 /* 2 BDC Init */
2282 #if (BEAMFORMING_SUPPORT == 1)
2283 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2284 odm_bdc_init(p_dm);
2285 #endif
2286 #endif
2287
2288 #ifdef ODM_EVM_ENHANCE_ANTDIV
2289 odm_evm_fast_ant_reset(p_dm);
2290 #endif
2291 }
2292 }
2293
2294 if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) {
2295 if (p_dm->is_one_entry_only == true)
2296 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
2297 else
2298 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_DESC);
2299 }
2300
2301 #ifdef ODM_EVM_ENHANCE_ANTDIV
2302 if (p_dm->antdiv_evm_en == 1) {
2303 odm_evm_enhance_ant_div(p_dm);
2304 if (p_dm_fat_table->fat_state_cnt != 0)
2305 return;
2306 } else
2307 odm_evm_fast_ant_reset(p_dm);
2308 #endif
2309
2310 /* 2 BDC mode Arbitration */
2311 #if (BEAMFORMING_SUPPORT == 1)
2312 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2313 if (p_dm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0)
2314 odm_bf_ant_div_mode_arbitration(p_dm);
2315 #endif
2316 #endif
2317
2318 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2319 p_sta = p_dm->p_phydm_sta_info[i];
2320 if (is_sta_active(p_sta)) {
2321 /* 2 Caculate RSSI per Antenna */
2322 if ((p_dm_fat_table->main_ant_cnt[i] != 0) || (p_dm_fat_table->aux_ant_cnt[i] != 0)) {
2323 mian_cnt = p_dm_fat_table->main_ant_cnt[i];
2324 aux_cnt = p_dm_fat_table->aux_ant_cnt[i];
2325 main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum[i] / mian_cnt) : 0;
2326 aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum[i] / aux_cnt) : 0;
2327 target_ant = (mian_cnt == aux_cnt) ? p_dm_fat_table->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/
2328
2329 } else { /*CCK only case*/
2330 mian_cnt = p_dm_fat_table->main_ant_cnt_cck[i];
2331 aux_cnt = p_dm_fat_table->aux_ant_cnt_cck[i];
2332 main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum_cck[i] / mian_cnt) : 0;
2333 aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum_cck[i] / aux_cnt) : 0;
2334 target_ant = (main_rssi == aux_rssi) ? p_dm_fat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/
2335 }
2336
2337 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", i, p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->main_ant_cnt_cck[i], main_rssi));
2338 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", i, p_dm_fat_table->aux_ant_cnt[i], p_dm_fat_table->aux_ant_cnt_cck[i], aux_rssi));
2339 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); */
2340
2341 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
2342 /* 2 Select max_rssi for DIG */
2343 if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40))
2344 ant_div_max_rssi = local_max_rssi;
2345 if (local_max_rssi > max_rssi)
2346 max_rssi = local_max_rssi;
2347
2348 /* 2 Select RX Idle Antenna */
2349 if ((local_max_rssi != 0) && (local_max_rssi < min_max_rssi)) {
2350 rx_idle_ant = target_ant;
2351 min_max_rssi = local_max_rssi;
2352 }
2353
2354 #ifdef ODM_EVM_ENHANCE_ANTDIV
2355 if (p_dm->antdiv_evm_en == 1) {
2356 if (p_dm_fat_table->target_ant_enhance != 0xFF) {
2357 target_ant = p_dm_fat_table->target_ant_enhance;
2358 rx_idle_ant = p_dm_fat_table->target_ant_enhance;
2359 }
2360 }
2361 #endif
2362
2363 /* 2 Select TX Antenna */
2364 if (p_dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
2365 #if (BEAMFORMING_SUPPORT == 1)
2366 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2367 if (p_dm_bdc_table->w_bfee_client[i] == 0)
2368 #endif
2369 #endif
2370 {
2371 odm_update_tx_ant(p_dm, target_ant, i);
2372 }
2373 }
2374
2375 /* ------------------------------------------------------------ */
2376
2377 #if (BEAMFORMING_SUPPORT == 1)
2378 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2379
2380 p_dm_bdc_table->num_client++;
2381
2382 if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) {
2383 /* 2 Byte counter */
2384
2385 ma_rx_temp = p_sta->rx_moving_average_tp; /* RX TP ( bit /sec) */
2386
2387 if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state)
2388 p_dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp ;
2389 else
2390 p_dm_bdc_table->MA_rx_TP[i] = ma_rx_temp ;
2391
2392 if ((ma_rx_temp < TH2) && (ma_rx_temp > TH1) && (local_max_rssi <= monitor_rssi_threshold)) {
2393 if (p_dm_bdc_table->w_bfer_client[i] == 1) { /* Bfer_Target */
2394 p_dm_bdc_table->num_bf_tar++;
2395
2396 if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) {
2397 improve_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3 ; /* * 1.125 */
2398 p_dm_bdc_table->BF_pass = (p_dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
2399 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], improve_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->BF_pass));
2400 }
2401 } else { /* DIV_Target */
2402 p_dm_bdc_table->num_div_tar++;
2403
2404 if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) {
2405 degrade_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* * 0.625 */
2406 p_dm_bdc_table->DIV_pass = (p_dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
2407 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->DIV_pass));
2408 }
2409 }
2410 }
2411
2412 if (ma_rx_temp > TH1) {
2413 if (p_dm_bdc_table->w_bfer_client[i] == 1) /* Bfer_Target */
2414 p_dm_bdc_table->is_all_bf_sta_idle = false;
2415 else/* DIV_Target */
2416 p_dm_bdc_table->is_all_div_sta_idle = false;
2417 }
2418
2419 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", i, p_dm_bdc_table->w_bfee_client[i], p_dm_bdc_table->w_bfer_client[i]));
2420
2421 if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state)
2422 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP_DIV[i]));
2423
2424 else
2425 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP[i]));
2426
2427 }
2428 #endif
2429 #endif
2430
2431 }
2432
2433 #if (BEAMFORMING_SUPPORT == 1)
2434 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2435 if (p_dm_bdc_table->bdc_try_flag == 0)
2436 #endif
2437 #endif
2438 {
2439 phydm_antdiv_reset_statistic(p_dm, i);
2440 }
2441 }
2442
2443
2444
2445 /* 2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
2446 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2447 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** rx_idle_ant = (( %s ))\n", (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
2448
2449 #if (BEAMFORMING_SUPPORT == 1)
2450 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2451 if (p_dm_bdc_table->bdc_mode == BDC_MODE_1 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) {
2452 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** bdc_rx_idle_update_counter = (( %d ))\n", p_dm_bdc_table->bdc_rx_idle_update_counter));
2453
2454 if (p_dm_bdc_table->bdc_rx_idle_update_counter == 1) {
2455 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***Update RxIdle Antenna!!!\n"));
2456 p_dm_bdc_table->bdc_rx_idle_update_counter = 30;
2457 odm_update_rx_idle_ant(p_dm, rx_idle_ant);
2458 } else {
2459 p_dm_bdc_table->bdc_rx_idle_update_counter--;
2460 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n"));
2461 }
2462 } else
2463 #endif
2464 #endif
2465 odm_update_rx_idle_ant(p_dm, rx_idle_ant);
2466 #else
2467
2468 odm_update_rx_idle_ant(p_dm, rx_idle_ant);
2469
2470 #endif/* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
2471
2472
2473
2474 /* 2 BDC Main Algorithm */
2475 #if (BEAMFORMING_SUPPORT == 1)
2476 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2477 if (p_dm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0)
2478 odm_bd_ccoex_bfee_rx_div_arbitration(p_dm);
2479 #endif
2480 #endif
2481
2482 if (ant_div_max_rssi == 0)
2483 p_dig_t->ant_div_rssi_max = p_dm->rssi_min;
2484 else
2485 p_dig_t->ant_div_rssi_max = ant_div_max_rssi;
2486
2487 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***AntDiv End***\n\n"));
2488 }
2489
2490
2491
2492 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2493
2494 void
odm_s0s1_sw_ant_div_reset(void * p_dm_void)2495 odm_s0s1_sw_ant_div_reset(
2496 void *p_dm_void
2497 )
2498 {
2499 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2500 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
2501 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
2502
2503 p_dm_fat_table->is_become_linked = false;
2504 p_dm_swat_table->try_flag = SWAW_STEP_INIT;
2505 p_dm_swat_table->double_chk_flag = 0;
2506
2507 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("odm_s0s1_sw_ant_div_reset(): p_dm_fat_table->is_become_linked = %d\n", p_dm_fat_table->is_become_linked));
2508 }
2509
2510 void
odm_s0s1_sw_ant_div(void * p_dm_void,u8 step)2511 odm_s0s1_sw_ant_div(
2512 void *p_dm_void,
2513 u8 step
2514 )
2515 {
2516 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2517 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
2518 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
2519 u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
2520 u32 main_rssi, aux_rssi;
2521 u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp;
2522 u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
2523 u8 rx_idle_ant = p_dm_swat_table->pre_antenna, target_ant, next_ant = 0;
2524 struct cmn_sta_info *p_entry = NULL;
2525 u32 value32;
2526 u32 main_ant_sum;
2527 u32 aux_ant_sum;
2528 u32 main_ant_cnt;
2529 u32 aux_ant_cnt;
2530
2531
2532 if (!p_dm->is_linked) { /* is_linked==False */
2533 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[No Link!!!]\n"));
2534 if (p_dm_fat_table->is_become_linked == true) {
2535 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
2536 if (p_dm->support_ic_type == ODM_RTL8723B) {
2537
2538 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Set REG 948[9:6]=0x0\n"));
2539 odm_set_bb_reg(p_dm, 0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0);
2540 }
2541 p_dm_fat_table->is_become_linked = p_dm->is_linked;
2542 }
2543 return;
2544 } else {
2545 if (p_dm_fat_table->is_become_linked == false) {
2546 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Linked !!!]\n"));
2547
2548 if (p_dm->support_ic_type == ODM_RTL8723B) {
2549 value32 = odm_get_bb_reg(p_dm, 0x864, BIT(5) | BIT(4) | BIT(3));
2550
2551 #if (RTL8723B_SUPPORT == 1)
2552 if (value32 == 0x0)
2553 odm_update_rx_idle_ant_8723b(p_dm, MAIN_ANT, ANT1_2G, ANT2_2G);
2554 else if (value32 == 0x1)
2555 odm_update_rx_idle_ant_8723b(p_dm, AUX_ANT, ANT2_2G, ANT1_2G);
2556 #endif
2557
2558 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("8723B: First link! Force antenna to %s\n", (value32 == 0x0 ? "MAIN" : "AUX")));
2559 }
2560 p_dm_fat_table->is_become_linked = p_dm->is_linked;
2561 }
2562 }
2563
2564 if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) {
2565 if (p_dm->is_one_entry_only == true)
2566 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
2567 else
2568 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_DESC);
2569 }
2570
2571 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
2572 __LINE__, p_dm_swat_table->try_flag, step, p_dm_swat_table->double_chk_flag));
2573
2574 /* Handling step mismatch condition. */
2575 /* Peak step is not finished at last time. Recover the variable and check again. */
2576 if (step != p_dm_swat_table->try_flag) {
2577 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[step != try_flag] Need to Reset After Link\n"));
2578 odm_sw_ant_div_rest_after_link(p_dm);
2579 }
2580
2581 if (p_dm_swat_table->try_flag == SWAW_STEP_INIT) {
2582
2583 p_dm_swat_table->try_flag = SWAW_STEP_PEEK;
2584 p_dm_swat_table->train_time_flag = 0;
2585 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[set try_flag = 0] Prepare for peek!\n\n"));
2586 return;
2587
2588 } else {
2589
2590 /* 1 Normal state (Begin Trying) */
2591 if (p_dm_swat_table->try_flag == SWAW_STEP_PEEK) {
2592
2593 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", p_dm->cur_tx_ok_cnt, p_dm->cur_rx_ok_cnt, p_dm->traffic_load));
2594
2595 if (p_dm->traffic_load == TRAFFIC_HIGH) {
2596 train_time_temp = p_dm_swat_table->train_time ;
2597
2598 if (p_dm_swat_table->train_time_flag == 3) {
2599 high_traffic_train_time_l = 0xa;
2600
2601 if (train_time_temp <= 16)
2602 train_time_temp = high_traffic_train_time_l;
2603 else
2604 train_time_temp -= 16;
2605
2606 } else if (p_dm_swat_table->train_time_flag == 2) {
2607 train_time_temp -= 8;
2608 high_traffic_train_time_l = 0xf;
2609 } else if (p_dm_swat_table->train_time_flag == 1) {
2610 train_time_temp -= 4;
2611 high_traffic_train_time_l = 0x1e;
2612 } else if (p_dm_swat_table->train_time_flag == 0) {
2613 train_time_temp += 8;
2614 high_traffic_train_time_l = 0x28;
2615 }
2616
2617 if (p_dm->support_ic_type == ODM_RTL8188F) {
2618 if (p_dm->support_interface == ODM_ITRF_SDIO)
2619 high_traffic_train_time_l += 0xa;
2620 }
2621
2622 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("*** train_time_temp = ((%d))\n",train_time_temp)); */
2623
2624 /* -- */
2625 if (train_time_temp > high_traffic_train_time_u)
2626 train_time_temp = high_traffic_train_time_u;
2627
2628 else if (train_time_temp < high_traffic_train_time_l)
2629 train_time_temp = high_traffic_train_time_l;
2630
2631 p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/
2632
2633 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("train_time_flag=((%d)), train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time));
2634
2635 } else if ((p_dm->traffic_load == TRAFFIC_MID) || (p_dm->traffic_load == TRAFFIC_LOW)) {
2636
2637 train_time_temp = p_dm_swat_table->train_time ;
2638
2639 if (p_dm_swat_table->train_time_flag == 3) {
2640 low_traffic_train_time_l = 10;
2641 if (train_time_temp < 50)
2642 train_time_temp = low_traffic_train_time_l;
2643 else
2644 train_time_temp -= 50;
2645 } else if (p_dm_swat_table->train_time_flag == 2) {
2646 train_time_temp -= 30;
2647 low_traffic_train_time_l = 36;
2648 } else if (p_dm_swat_table->train_time_flag == 1) {
2649 train_time_temp -= 10;
2650 low_traffic_train_time_l = 40;
2651 } else {
2652
2653 train_time_temp += 10;
2654 low_traffic_train_time_l = 50;
2655 }
2656
2657 if (p_dm->support_ic_type == ODM_RTL8188F) {
2658 if (p_dm->support_interface == ODM_ITRF_SDIO)
2659 low_traffic_train_time_l += 10;
2660 }
2661
2662 /* -- */
2663 if (train_time_temp >= low_traffic_train_time_u)
2664 train_time_temp = low_traffic_train_time_u;
2665
2666 else if (train_time_temp <= low_traffic_train_time_l)
2667 train_time_temp = low_traffic_train_time_l;
2668
2669 p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/
2670
2671 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("train_time_flag=((%d)) , train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time));
2672
2673 } else {
2674 p_dm_swat_table->train_time = 0xc8; /*200ms*/
2675
2676 }
2677
2678 /* ----------------- */
2679
2680 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Current min_max_rssi is ((%d))\n", p_dm_fat_table->min_max_rssi));
2681
2682 /* ---reset index--- */
2683 if (p_dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
2684
2685 p_dm_fat_table->min_max_rssi = 0;
2686 p_dm_swat_table->reset_idx = 0;
2687 }
2688 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("reset_idx = (( %d ))\n", p_dm_swat_table->reset_idx));
2689
2690 p_dm_swat_table->reset_idx++;
2691
2692 /* ---double check flag--- */
2693 if ((p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) && (p_dm_swat_table->double_chk_flag == 0)) {
2694 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" min_max_rssi is ((%d)), and > %d\n",
2695 p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD));
2696
2697 p_dm_swat_table->double_chk_flag = 1;
2698 p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE;
2699 p_dm_swat_table->rssi_trying = 0;
2700
2701 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Test the current ant for (( %d )) ms again\n", p_dm_swat_table->train_time));
2702 odm_update_rx_idle_ant(p_dm, p_dm_fat_table->rx_idle_ant);
2703 odm_set_timer(p_dm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/
2704 return;
2705 }
2706
2707 next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
2708
2709 p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE;
2710
2711 if (p_dm_swat_table->reset_idx <= 1)
2712 p_dm_swat_table->rssi_trying = 2;
2713 else
2714 p_dm_swat_table->rssi_trying = 1;
2715
2716 odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm, SWAW_STEP_PEEK);
2717 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[set try_flag=1] Normal state: Begin Trying!!\n"));
2718
2719 } else if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->double_chk_flag == 0)) {
2720
2721 next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
2722 p_dm_swat_table->rssi_trying--;
2723 }
2724
2725 /* 1 Decision state */
2726 if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->rssi_trying == 0)) {
2727
2728 boolean is_by_ctrl_frame = false;
2729 u64 pkt_cnt_total = 0;
2730
2731 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2732 p_entry = p_dm->p_phydm_sta_info[i];
2733 if (is_sta_active(p_entry)) {
2734 /* 2 Caculate RSSI per Antenna */
2735
2736 main_ant_sum = (u32)p_dm_fat_table->main_ant_sum[i] + (u32)p_dm_fat_table->main_ant_sum_cck[i];
2737 aux_ant_sum = (u32)p_dm_fat_table->aux_ant_sum[i] + (u32)p_dm_fat_table->aux_ant_sum_cck[i];
2738 main_ant_cnt = (u32)p_dm_fat_table->main_ant_cnt[i] + (u32)p_dm_fat_table->main_ant_cnt_cck[i];
2739 aux_ant_cnt = (u32)p_dm_fat_table->aux_ant_cnt[i] + (u32)p_dm_fat_table->aux_ant_cnt_cck[i];
2740
2741 main_rssi = (main_ant_cnt != 0) ? (main_ant_sum / main_ant_cnt) : 0;
2742 aux_rssi = (aux_ant_cnt != 0) ? (aux_ant_sum / aux_ant_cnt) : 0;
2743
2744 if (p_dm_fat_table->main_ant_cnt[i] <= 1 && p_dm_fat_table->main_ant_cnt_cck[i] >= 1)
2745 main_rssi = 0;
2746
2747 if (p_dm_fat_table->aux_ant_cnt[i] <= 1 && p_dm_fat_table->aux_ant_cnt_cck[i] >= 1)
2748 aux_rssi = 0;
2749
2750 target_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT);
2751 local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
2752 local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
2753
2754 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt_cck[i], p_dm_fat_table->aux_ant_cnt_cck[i]));
2755 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->aux_ant_cnt[i]));
2756 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", main_ant_cnt, main_rssi));
2757 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", aux_ant_cnt, aux_rssi));
2758 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
2759
2760 /* 2 Select RX Idle Antenna */
2761
2762 if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
2763 rx_idle_ant = target_ant;
2764 min_max_rssi = local_max_rssi;
2765 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi)));
2766
2767 if ((local_max_rssi - local_min_rssi) > 8) {
2768 if (local_min_rssi != 0)
2769 p_dm_swat_table->train_time_flag = 3;
2770 else {
2771 if (min_max_rssi > RSSI_CHECK_THRESHOLD)
2772 p_dm_swat_table->train_time_flag = 0;
2773 else
2774 p_dm_swat_table->train_time_flag = 3;
2775 }
2776 } else if ((local_max_rssi - local_min_rssi) > 5)
2777 p_dm_swat_table->train_time_flag = 2;
2778 else if ((local_max_rssi - local_min_rssi) > 2)
2779 p_dm_swat_table->train_time_flag = 1;
2780 else
2781 p_dm_swat_table->train_time_flag = 0;
2782
2783 }
2784
2785 /* 2 Select TX Antenna */
2786 if (target_ant == MAIN_ANT)
2787 p_dm_fat_table->antsel_a[i] = ANT1_2G;
2788 else
2789 p_dm_fat_table->antsel_a[i] = ANT2_2G;
2790
2791 }
2792 phydm_antdiv_reset_statistic(p_dm, i);
2793 pkt_cnt_total += (main_ant_cnt + aux_ant_cnt);
2794 }
2795
2796 if (p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) {
2797 odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm, SWAW_STEP_DETERMINE);
2798 is_by_ctrl_frame = true;
2799 }
2800
2801 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Control frame packet counter = %d, data frame packet counter = %llu\n",
2802 p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total));
2803
2804 if (min_max_rssi == 0xff || ((pkt_cnt_total < (p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && p_dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
2805 min_max_rssi = 0;
2806 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Check RSSI of control frame because min_max_rssi == 0xff\n"));
2807 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("is_by_ctrl_frame = %d\n", is_by_ctrl_frame));
2808
2809 if (is_by_ctrl_frame) {
2810 main_rssi = (p_dm_fat_table->main_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->main_ant_ctrl_frame_sum / p_dm_fat_table->main_ant_ctrl_frame_cnt) : 0;
2811 aux_rssi = (p_dm_fat_table->aux_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->aux_ant_ctrl_frame_sum / p_dm_fat_table->aux_ant_ctrl_frame_cnt) : 0;
2812
2813 if (p_dm_fat_table->main_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_main >= 1)
2814 main_rssi = 0;
2815
2816 if (p_dm_fat_table->aux_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_aux >= 1)
2817 aux_rssi = 0;
2818
2819 if (main_rssi != 0 || aux_rssi != 0) {
2820 rx_idle_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT);
2821 local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
2822 local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
2823
2824 if ((local_max_rssi - local_min_rssi) > 8)
2825 p_dm_swat_table->train_time_flag = 3;
2826 else if ((local_max_rssi - local_min_rssi) > 5)
2827 p_dm_swat_table->train_time_flag = 2;
2828 else if ((local_max_rssi - local_min_rssi) > 2)
2829 p_dm_swat_table->train_time_flag = 1;
2830 else
2831 p_dm_swat_table->train_time_flag = 0;
2832
2833 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi));
2834 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX")));
2835 }
2836 }
2837 }
2838
2839 p_dm_fat_table->min_max_rssi = min_max_rssi;
2840 p_dm_swat_table->try_flag = SWAW_STEP_PEEK;
2841
2842 if (p_dm_swat_table->double_chk_flag == 1) {
2843 p_dm_swat_table->double_chk_flag = 0;
2844
2845 if (p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) {
2846
2847 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" [Double check] min_max_rssi ((%d)) > %d again!!\n",
2848 p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD));
2849
2850 odm_update_rx_idle_ant(p_dm, rx_idle_ant);
2851
2852 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n"));
2853 return;
2854 } else {
2855 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" [Double check] min_max_rssi ((%d)) <= %d !!\n",
2856 p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD));
2857
2858 next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
2859 p_dm_swat_table->try_flag = SWAW_STEP_PEEK;
2860 p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD;
2861 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[set try_flag=0] Normal state: Need to tryg again!!\n\n\n"));
2862 return;
2863 }
2864 } else {
2865 if (p_dm_fat_table->min_max_rssi < RSSI_CHECK_THRESHOLD)
2866 p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD;
2867
2868 p_dm_swat_table->pre_antenna = rx_idle_ant;
2869 odm_update_rx_idle_ant(p_dm, rx_idle_ant);
2870 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n"));
2871 return;
2872 }
2873
2874 }
2875
2876 }
2877
2878 /* 1 4.Change TRX antenna */
2879
2880 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n",
2881 p_dm_swat_table->rssi_trying, (p_dm_fat_table->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), (next_ant == MAIN_ANT ? "MAIN" : "AUX")));
2882
2883 odm_update_rx_idle_ant(p_dm, next_ant);
2884
2885 /* 1 5.Reset Statistics */
2886
2887 p_dm_fat_table->rx_idle_ant = next_ant;
2888
2889 if (p_dm->support_ic_type == ODM_RTL8188F) {
2890 if (p_dm->support_interface == ODM_ITRF_SDIO) {
2891
2892 ODM_delay_us(200);
2893
2894 if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) {
2895 p_dm_fat_table->main_ant_sum[0] = 0;
2896 p_dm_fat_table->main_ant_cnt[0] = 0;
2897 p_dm_fat_table->main_ant_sum_cck[0] = 0;
2898 p_dm_fat_table->main_ant_cnt_cck[0] = 0;
2899 } else {
2900 p_dm_fat_table->aux_ant_sum[0] = 0;
2901 p_dm_fat_table->aux_ant_cnt[0] = 0;
2902 p_dm_fat_table->aux_ant_sum_cck[0] = 0;
2903 p_dm_fat_table->aux_ant_cnt_cck[0] = 0;
2904 }
2905 }
2906 }
2907
2908 /* 1 6.Set next timer (Trying state) */
2909
2910 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" Test ((%s)) ant for (( %d )) ms\n", (next_ant == MAIN_ANT ? "MAIN" : "AUX"), p_dm_swat_table->train_time));
2911 odm_set_timer(p_dm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/
2912 }
2913
2914
2915 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2916 void
odm_sw_antdiv_callback(struct timer_list * p_timer)2917 odm_sw_antdiv_callback(
2918 struct timer_list *p_timer
2919 )
2920 {
2921 struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter;
2922 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
2923 struct _sw_antenna_switch_ *p_dm_swat_table = &p_hal_data->DM_OutSrc.dm_swat_table;
2924
2925 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2926 #if USE_WORKITEM
2927 odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem);
2928 #else
2929 {
2930 /* dbg_print("SW_antdiv_Callback"); */
2931 odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
2932 }
2933 #endif
2934 #else
2935 odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem);
2936 #endif
2937 }
2938 void
odm_sw_antdiv_workitem_callback(void * p_context)2939 odm_sw_antdiv_workitem_callback(
2940 void *p_context
2941 )
2942 {
2943 struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context;
2944 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
2945
2946 /* dbg_print("SW_antdiv_Workitem_Callback"); */
2947 odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
2948 }
2949
2950 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2951
2952 void
odm_sw_antdiv_workitem_callback(void * p_context)2953 odm_sw_antdiv_workitem_callback(
2954 void *p_context
2955 )
2956 {
2957 struct _ADAPTER *
2958 p_adapter = (struct _ADAPTER *)p_context;
2959 HAL_DATA_TYPE
2960 *p_hal_data = GET_HAL_DATA(p_adapter);
2961
2962 /*dbg_print("SW_antdiv_Workitem_Callback");*/
2963 odm_s0s1_sw_ant_div(&p_hal_data->odmpriv, SWAW_STEP_DETERMINE);
2964 }
2965
2966 void
odm_sw_antdiv_callback(void * function_context)2967 odm_sw_antdiv_callback(void *function_context)
2968 {
2969 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)function_context;
2970 struct _ADAPTER *padapter = p_dm->adapter;
2971 if (padapter->net_closed == true)
2972 return;
2973
2974 #if 0 /* Can't do I/O in timer callback*/
2975 odm_s0s1_sw_ant_div(p_dm, SWAW_STEP_DETERMINE);
2976 #else
2977 rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);
2978 #endif
2979 }
2980
2981
2982 #endif
2983
2984 void
odm_s0s1_sw_ant_div_by_ctrl_frame(void * p_dm_void,u8 step)2985 odm_s0s1_sw_ant_div_by_ctrl_frame(
2986 void *p_dm_void,
2987 u8 step
2988 )
2989 {
2990 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2991 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
2992 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
2993
2994 switch (step) {
2995 case SWAW_STEP_PEEK:
2996 p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
2997 p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = true;
2998 p_dm_fat_table->main_ant_ctrl_frame_cnt = 0;
2999 p_dm_fat_table->aux_ant_ctrl_frame_cnt = 0;
3000 p_dm_fat_table->main_ant_ctrl_frame_sum = 0;
3001 p_dm_fat_table->aux_ant_ctrl_frame_sum = 0;
3002 p_dm_fat_table->cck_ctrl_frame_cnt_main = 0;
3003 p_dm_fat_table->cck_ctrl_frame_cnt_aux = 0;
3004 p_dm_fat_table->ofdm_ctrl_frame_cnt_main = 0;
3005 p_dm_fat_table->ofdm_ctrl_frame_cnt_aux = 0;
3006 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n"));
3007 break;
3008 case SWAW_STEP_DETERMINE:
3009 p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false;
3010 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n"));
3011 break;
3012 default:
3013 p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false;
3014 break;
3015 }
3016 }
3017
3018 void
odm_antsel_statistics_of_ctrl_frame(void * p_dm_void,u8 antsel_tr_mux,u32 rx_pwdb_all)3019 odm_antsel_statistics_of_ctrl_frame(
3020 void *p_dm_void,
3021 u8 antsel_tr_mux,
3022 u32 rx_pwdb_all
3023
3024 )
3025 {
3026 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3027 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3028
3029 if (antsel_tr_mux == ANT1_2G) {
3030 p_dm_fat_table->main_ant_ctrl_frame_sum += rx_pwdb_all;
3031 p_dm_fat_table->main_ant_ctrl_frame_cnt++;
3032 } else {
3033 p_dm_fat_table->aux_ant_ctrl_frame_sum += rx_pwdb_all;
3034 p_dm_fat_table->aux_ant_ctrl_frame_cnt++;
3035 }
3036 }
3037
3038 void
odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void * p_dm_void,void * p_phy_info_void,void * p_pkt_info_void)3039 odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
3040 void *p_dm_void,
3041 void *p_phy_info_void,
3042 void *p_pkt_info_void
3043 /* struct phydm_phyinfo_struct* p_phy_info, */
3044 /* struct phydm_perpkt_info_struct* p_pktinfo */
3045 )
3046 {
3047 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3048 struct phydm_phyinfo_struct *p_phy_info = (struct phydm_phyinfo_struct *)p_phy_info_void;
3049 struct phydm_perpkt_info_struct *p_pktinfo = (struct phydm_perpkt_info_struct *)p_pkt_info_void;
3050 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
3051 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3052 boolean is_cck_rate;
3053
3054 if (!(p_dm->support_ability & ODM_BB_ANT_DIV))
3055 return;
3056
3057 if (p_dm->ant_div_type != S0S1_SW_ANTDIV)
3058 return;
3059
3060 /* In try state */
3061 if (!p_dm_swat_table->is_sw_ant_div_by_ctrl_frame)
3062 return;
3063
3064 /* No HW error and match receiver address */
3065 if (!p_pktinfo->is_to_self)
3066 return;
3067
3068 p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++;
3069 is_cck_rate = ((p_pktinfo->data_rate >= DESC_RATE1M) && (p_pktinfo->data_rate <= DESC_RATE11M)) ? true : false;
3070
3071 if (is_cck_rate) {
3072 p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
3073
3074 if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G)
3075 p_dm_fat_table->cck_ctrl_frame_cnt_main++;
3076 else
3077 p_dm_fat_table->cck_ctrl_frame_cnt_aux++;
3078
3079 odm_antsel_statistics_of_ctrl_frame(p_dm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_mimo_signal_strength[RF_PATH_A]);
3080 } else {
3081 p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
3082
3083 if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G)
3084 p_dm_fat_table->ofdm_ctrl_frame_cnt_main++;
3085 else
3086 p_dm_fat_table->ofdm_ctrl_frame_cnt_aux++;
3087
3088 odm_antsel_statistics_of_ctrl_frame(p_dm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_pwdb_all);
3089 }
3090 }
3091
3092 #endif /* #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
3093
3094
3095
3096
3097 void
odm_set_next_mac_addr_target(void * p_dm_void)3098 odm_set_next_mac_addr_target(
3099 void *p_dm_void
3100 )
3101 {
3102 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3103 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3104 struct cmn_sta_info *p_entry;
3105 u32 value32, i;
3106
3107 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("odm_set_next_mac_addr_target() ==>\n"));
3108
3109 if (p_dm->is_linked) {
3110 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3111
3112 if ((p_dm_fat_table->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
3113 p_dm_fat_table->train_idx = 0;
3114 else
3115 p_dm_fat_table->train_idx++;
3116
3117 p_entry = p_dm->p_phydm_sta_info[p_dm_fat_table->train_idx];
3118
3119 if (is_sta_active(p_entry)) {
3120
3121 /*Match MAC ADDR*/
3122 value32 = (p_entry->mac_addr[5] << 8) | p_entry->mac_addr[4];
3123
3124 odm_set_mac_reg(p_dm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/
3125
3126 value32 = (p_entry->mac_addr[3] << 24) | (p_entry->mac_addr[2] << 16) | (p_entry->mac_addr[1] << 8) | p_entry->mac_addr[0];
3127
3128 odm_set_mac_reg(p_dm, 0x7b0, MASKDWORD, value32);/*0x7b0~0x7b3*/
3129
3130 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("p_dm_fat_table->train_idx=%d\n", p_dm_fat_table->train_idx));
3131
3132 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n",
3133 p_entry->mac_addr[5], p_entry->mac_addr[4], p_entry->mac_addr[3], p_entry->mac_addr[2], p_entry->mac_addr[1], p_entry->mac_addr[0]));
3134
3135 break;
3136 }
3137 }
3138 }
3139
3140 }
3141
3142 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3143
3144 void
odm_fast_ant_training(void * p_dm_void)3145 odm_fast_ant_training(
3146 void *p_dm_void
3147 )
3148 {
3149 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3150 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3151
3152 u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
3153 u8 i, target_ant_path_a = 0;
3154 boolean is_pkt_filter_macth_path_a = false;
3155 #if (RTL8192E_SUPPORT == 1)
3156 u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
3157 u8 target_ant_path_b = 0;
3158 boolean is_pkt_filter_macth_path_b = false;
3159 #endif
3160
3161
3162 if (!p_dm->is_linked) { /* is_linked==False */
3163 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[No Link!!!]\n"));
3164
3165 if (p_dm_fat_table->is_become_linked == true) {
3166 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3167 phydm_fast_training_enable(p_dm, FAT_OFF);
3168 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
3169 p_dm_fat_table->is_become_linked = p_dm->is_linked;
3170 }
3171 return;
3172 } else {
3173 if (p_dm_fat_table->is_become_linked == false) {
3174 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Linked!!!]\n"));
3175 p_dm_fat_table->is_become_linked = p_dm->is_linked;
3176 }
3177 }
3178
3179 if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) {
3180 if (p_dm->is_one_entry_only == true)
3181 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
3182 else
3183 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_DESC);
3184 }
3185
3186
3187 if (p_dm->support_ic_type == ODM_RTL8188E)
3188 odm_set_bb_reg(p_dm, 0x864, BIT(2) | BIT(1) | BIT(0), ((p_dm->fat_comb_a) - 1));
3189 #if (RTL8192E_SUPPORT == 1)
3190 else if (p_dm->support_ic_type == ODM_RTL8192E) {
3191 odm_set_bb_reg(p_dm, 0xB38, BIT(2) | BIT(1) | BIT(0), ((p_dm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */
3192 odm_set_bb_reg(p_dm, 0xB38, BIT(18) | BIT(17) | BIT(16), ((p_dm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */
3193 }
3194 #endif
3195
3196 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("==>odm_fast_ant_training()\n"));
3197
3198 /* 1 TRAINING STATE */
3199 if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) {
3200 /* 2 Caculate RSSI per Antenna */
3201
3202 /* 3 [path-A]--------------------------- */
3203 for (i = 0; i < (p_dm->fat_comb_a); i++) { /* i : antenna index */
3204 if (p_dm_fat_table->ant_rssi_cnt[i] == 0)
3205 p_dm_fat_table->ant_ave_rssi[i] = 0;
3206 else {
3207 p_dm_fat_table->ant_ave_rssi[i] = p_dm_fat_table->ant_sum_rssi[i] / p_dm_fat_table->ant_rssi_cnt[i];
3208 is_pkt_filter_macth_path_a = true;
3209 }
3210
3211 if (p_dm_fat_table->ant_ave_rssi[i] > max_rssi_path_a) {
3212 max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i];
3213 pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i];
3214 target_ant_path_a = i ;
3215 } else if (p_dm_fat_table->ant_ave_rssi[i] == max_rssi_path_a) {
3216 if ((p_dm_fat_table->ant_rssi_cnt[i]) > pckcnt_path_a) {
3217 max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i];
3218 pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i];
3219 target_ant_path_a = i ;
3220 }
3221 }
3222
3223 PHYDM_DBG("*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", i, p_dm_fat_table->ant_rssi_cnt[i], p_dm_fat_table->ant_ave_rssi[i]);
3224 }
3225
3226
3227 #if 0
3228 #if (RTL8192E_SUPPORT == 1)
3229 /* 3 [path-B]--------------------------- */
3230 for (i = 0; i < (p_dm->fat_comb_b); i++) {
3231 if (p_dm_fat_table->antRSSIcnt_pathB[i] == 0)
3232 p_dm_fat_table->antAveRSSI_pathB[i] = 0;
3233 else { /* (ant_rssi_cnt[i] != 0) */
3234 p_dm_fat_table->antAveRSSI_pathB[i] = p_dm_fat_table->antSumRSSI_pathB[i] / p_dm_fat_table->antRSSIcnt_pathB[i];
3235 is_pkt_filter_macth_path_b = true;
3236 }
3237 if (p_dm_fat_table->antAveRSSI_pathB[i] > max_rssi_path_b) {
3238 max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i];
3239 pckcnt_path_b = p_dm_fat_table->antRSSIcnt_pathB[i];
3240 target_ant_path_b = (u8) i;
3241 }
3242 if (p_dm_fat_table->antAveRSSI_pathB[i] == max_rssi_path_b) {
3243 if (p_dm_fat_table->antRSSIcnt_pathB > pckcnt_path_b) {
3244 max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i];
3245 target_ant_path_b = (u8) i;
3246 }
3247 }
3248 if (p_dm->fat_print_rssi == 1) {
3249 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n",
3250 i, p_dm_fat_table->antSumRSSI_pathB[i], i, p_dm_fat_table->antRSSIcnt_pathB[i], i, p_dm_fat_table->antAveRSSI_pathB[i]));
3251 }
3252 }
3253 #endif
3254 #endif
3255
3256 /* 1 DECISION STATE */
3257
3258 /* 2 Select TRX Antenna */
3259
3260 phydm_fast_training_enable(p_dm, FAT_OFF);
3261
3262 /* 3 [path-A]--------------------------- */
3263 if (is_pkt_filter_macth_path_a == false) {
3264 /* PHYDM_DBG(p_dm,DBG_ANT_DIV, ("{path-A}: None Packet is matched\n")); */
3265 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("{path-A}: None Packet is matched\n"));
3266 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3267 } else {
3268 PHYDM_DBG("target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", target_ant_path_a, max_rssi_path_a);
3269
3270 /* 3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */
3271 if (p_dm->support_ic_type == ODM_RTL8188E)
3272 odm_set_bb_reg(p_dm, 0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
3273 else if (p_dm->support_ic_type == ODM_RTL8192E)
3274 odm_set_bb_reg(p_dm, 0xB38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
3275
3276 /* 3 [ update TX ant ] */
3277 odm_update_tx_ant(p_dm, target_ant_path_a, (p_dm_fat_table->train_idx));
3278
3279 if (target_ant_path_a == 0)
3280 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3281 }
3282 #if 0
3283 #if (RTL8192E_SUPPORT == 1)
3284 /* 3 [path-B]--------------------------- */
3285 if (is_pkt_filter_macth_path_b == false) {
3286 if (p_dm->fat_print_rssi == 1)
3287 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("***[%d]{path-B}: None Packet is matched\n\n\n", __LINE__));
3288 } else {
3289 if (p_dm->fat_print_rssi == 1) {
3290 PHYDM_DBG(p_dm, DBG_ANT_DIV,
3291 (" ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", target_ant_path_b, max_rssi_path_b));
3292 }
3293 odm_set_bb_reg(p_dm, 0xB38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* Default RX is Omni, Optional RX is the best decision by FAT */
3294 odm_set_bb_reg(p_dm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */
3295
3296 p_dm_fat_table->antsel_pathB[p_dm_fat_table->train_idx] = target_ant_path_b;
3297 }
3298 #endif
3299 #endif
3300
3301 /* 2 Reset counter */
3302 for (i = 0; i < (p_dm->fat_comb_a); i++) {
3303 p_dm_fat_table->ant_sum_rssi[i] = 0;
3304 p_dm_fat_table->ant_rssi_cnt[i] = 0;
3305 }
3306 /*
3307 #if (RTL8192E_SUPPORT == 1)
3308 for(i=0; i<=(p_dm->fat_comb_b); i++)
3309 {
3310 p_dm_fat_table->antSumRSSI_pathB[i] = 0;
3311 p_dm_fat_table->antRSSIcnt_pathB[i] = 0;
3312 }
3313 #endif
3314 */
3315
3316 p_dm_fat_table->fat_state = FAT_PREPARE_STATE;
3317 return;
3318 }
3319
3320 /* 1 NORMAL STATE */
3321 if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) {
3322 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Start Prepare state ]\n"));
3323
3324 odm_set_next_mac_addr_target(p_dm);
3325
3326 /* 2 Prepare Training */
3327 p_dm_fat_table->fat_state = FAT_TRAINING_STATE;
3328 phydm_fast_training_enable(p_dm, FAT_ON);
3329 odm_ant_div_on_off(p_dm, ANTDIV_ON); /* enable HW AntDiv */
3330 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Start Training state]\n"));
3331
3332 odm_set_timer(p_dm, &p_dm->fast_ant_training_timer, p_dm->antdiv_intvl); /* ms */
3333 }
3334
3335 }
3336
3337 void
odm_fast_ant_training_callback(void * p_dm_void)3338 odm_fast_ant_training_callback(
3339 void *p_dm_void
3340 )
3341 {
3342 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3343
3344 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3345 struct _ADAPTER *padapter = p_dm->adapter;
3346 if (padapter->net_closed == true)
3347 return;
3348 /* if(*p_dm->p_is_net_closed == true) */
3349 /* return; */
3350 #endif
3351
3352 #if USE_WORKITEM
3353 odm_schedule_work_item(&p_dm->fast_ant_training_workitem);
3354 #else
3355 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("******odm_fast_ant_training_callback******\n"));
3356 odm_fast_ant_training(p_dm);
3357 #endif
3358 }
3359
3360 void
odm_fast_ant_training_work_item_callback(void * p_dm_void)3361 odm_fast_ant_training_work_item_callback(
3362 void *p_dm_void
3363 )
3364 {
3365 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3366
3367 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("******odm_fast_ant_training_work_item_callback******\n"));
3368 odm_fast_ant_training(p_dm);
3369 }
3370
3371 #endif
3372
3373 void
odm_ant_div_init(void * p_dm_void)3374 odm_ant_div_init(
3375 void *p_dm_void
3376 )
3377 {
3378 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3379 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3380 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm->dm_swat_table;
3381
3382
3383 if (!(p_dm->support_ability & ODM_BB_ANT_DIV)) {
3384 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] Not Support Antenna Diversity Function\n"));
3385 return;
3386 }
3387 /* --- */
3388 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3389 if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) {
3390 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"));
3391 if (!(p_dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
3392 return;
3393 } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) {
3394 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"));
3395 if (!(p_dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
3396 return;
3397 } else if (p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
3398 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"));
3399
3400 #endif
3401 /* --- */
3402
3403 /* 2 [--General---] */
3404 p_dm->antdiv_period = 0;
3405
3406 p_dm_fat_table->is_become_linked = false;
3407 p_dm_fat_table->ant_div_on_off = 0xff;
3408
3409 /* 3 - AP - */
3410 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3411
3412 #if (BEAMFORMING_SUPPORT == 1)
3413 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3414 odm_bdc_init(p_dm);
3415 #endif
3416 #endif
3417
3418 /* 3 - WIN - */
3419 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3420 p_dm_swat_table->ant_5g = MAIN_ANT;
3421 p_dm_swat_table->ant_2g = MAIN_ANT;
3422 #endif
3423
3424 /* 2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
3425 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3426
3427 p_dm->ant_type = ODM_AUTO_ANT;
3428
3429 p_dm_fat_table->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/
3430 odm_update_rx_idle_ant(p_dm, MAIN_ANT);
3431 phydm_keep_rx_ack_ant_by_tx_ant_time(p_dm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/
3432
3433 /* 2 [---Set TX Antenna---] */
3434 if (p_dm_fat_table->p_force_tx_ant_by_desc == NULL) {
3435 p_dm_fat_table->force_tx_ant_by_desc = 0;
3436 p_dm_fat_table->p_force_tx_ant_by_desc = &(p_dm_fat_table->force_tx_ant_by_desc);
3437 }
3438 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("p_force_tx_ant_by_desc = %d\n", *p_dm_fat_table->p_force_tx_ant_by_desc));
3439
3440 if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == true)
3441 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_DESC);
3442 else
3443 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
3444
3445
3446 /* 2 [--88E---] */
3447 if (p_dm->support_ic_type == ODM_RTL8188E) {
3448 #if (RTL8188E_SUPPORT == 1)
3449 /* p_dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
3450 /* p_dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3451 /* p_dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
3452
3453 if ((p_dm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm->ant_div_type != CG_TRX_SMART_ANTDIV)) {
3454 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 88E Not Supprrt This AntDiv type\n"));
3455 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3456 return;
3457 }
3458
3459 if (p_dm->ant_div_type == CGCS_RX_HW_ANTDIV)
3460 odm_rx_hw_ant_div_init_88e(p_dm);
3461 else if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3462 odm_trx_hw_ant_div_init_88e(p_dm);
3463 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3464 else if (p_dm->ant_div_type == CG_TRX_SMART_ANTDIV)
3465 odm_smart_hw_ant_div_init_88e(p_dm);
3466 #endif
3467 #endif
3468 }
3469
3470 /* 2 [--92E---] */
3471 #if (RTL8192E_SUPPORT == 1)
3472 else if (p_dm->support_ic_type == ODM_RTL8192E) {
3473 /* p_dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
3474 /* p_dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3475 /* p_dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
3476
3477 if ((p_dm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm->ant_div_type != CG_TRX_SMART_ANTDIV)) {
3478 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8192E Not Supprrt This AntDiv type\n"));
3479 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3480 return;
3481 }
3482
3483 if (p_dm->ant_div_type == CGCS_RX_HW_ANTDIV)
3484 odm_rx_hw_ant_div_init_92e(p_dm);
3485 else if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3486 odm_trx_hw_ant_div_init_92e(p_dm);
3487 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3488 else if (p_dm->ant_div_type == CG_TRX_SMART_ANTDIV)
3489 odm_smart_hw_ant_div_init_92e(p_dm);
3490 #endif
3491
3492 }
3493 #endif
3494
3495 /* 2 [--8723B---] */
3496 #if (RTL8723B_SUPPORT == 1)
3497 else if (p_dm->support_ic_type == ODM_RTL8723B) {
3498 p_dm->ant_div_type = S0S1_SW_ANTDIV;
3499 /* p_dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3500
3501 if (p_dm->ant_div_type != S0S1_SW_ANTDIV && p_dm->ant_div_type != CG_TRX_HW_ANTDIV) {
3502 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8723B Not Supprrt This AntDiv type\n"));
3503 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3504 return;
3505 }
3506
3507 if (p_dm->ant_div_type == S0S1_SW_ANTDIV)
3508 odm_s0s1_sw_ant_div_init_8723b(p_dm);
3509 else if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3510 odm_trx_hw_ant_div_init_8723b(p_dm);
3511 }
3512 #endif
3513 /*2 [--8723D---]*/
3514 #if (RTL8723D_SUPPORT == 1)
3515 else if (p_dm->support_ic_type == ODM_RTL8723D) {
3516 if (p_dm_fat_table->p_default_s0_s1 == NULL) {
3517 p_dm_fat_table->default_s0_s1 = 1;
3518 p_dm_fat_table->p_default_s0_s1 = &(p_dm_fat_table->default_s0_s1);
3519 }
3520 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("default_s0_s1 = %d\n", *p_dm_fat_table->p_default_s0_s1));
3521
3522 if (*(p_dm_fat_table->p_default_s0_s1) == true)
3523 odm_update_rx_idle_ant(p_dm, MAIN_ANT);
3524 else
3525 odm_update_rx_idle_ant(p_dm, AUX_ANT);
3526
3527 if (p_dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
3528 odm_trx_hw_ant_div_init_8723d(p_dm);
3529 else {
3530 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8723D Not Supprrt This AntDiv type\n"));
3531 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3532 return;
3533 }
3534
3535 }
3536 #endif
3537 /* 2 [--8811A 8821A---] */
3538 #if (RTL8821A_SUPPORT == 1)
3539 else if (p_dm->support_ic_type == ODM_RTL8821) {
3540 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
3541 p_dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
3542
3543 if (p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
3544
3545 odm_trx_hw_ant_div_init_8821a(p_dm);
3546 phydm_hl_smart_ant_type1_init_8821a(p_dm);
3547 } else
3548 #endif
3549 {
3550 #ifdef ODM_CONFIG_BT_COEXIST
3551 p_dm->ant_div_type = S0S1_SW_ANTDIV;
3552 #else
3553 p_dm->ant_div_type = CG_TRX_HW_ANTDIV;
3554 #endif
3555
3556 if (p_dm->ant_div_type != CG_TRX_HW_ANTDIV && p_dm->ant_div_type != S0S1_SW_ANTDIV) {
3557 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n"));
3558 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3559 return;
3560 }
3561 if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3562 odm_trx_hw_ant_div_init_8821a(p_dm);
3563 else if (p_dm->ant_div_type == S0S1_SW_ANTDIV)
3564 odm_s0s1_sw_ant_div_init_8821a(p_dm);
3565 }
3566 }
3567 #endif
3568
3569 /* 2 [--8821C---] */
3570 #if (RTL8821C_SUPPORT == 1)
3571 else if (p_dm->support_ic_type == ODM_RTL8821C) {
3572 p_dm->ant_div_type = S0S1_SW_ANTDIV;
3573 if (p_dm->ant_div_type != S0S1_SW_ANTDIV) {
3574 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8821C Not Supprrt This AntDiv type\n"));
3575 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3576 return;
3577 }
3578 phydm_s0s1_sw_ant_div_init_8821c(p_dm);
3579 }
3580 #endif
3581
3582 /* 2 [--8881A---] */
3583 #if (RTL8881A_SUPPORT == 1)
3584 else if (p_dm->support_ic_type == ODM_RTL8881A) {
3585 /* p_dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
3586 /* p_dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3587
3588 if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV) {
3589
3590 odm_trx_hw_ant_div_init_8881a(p_dm);
3591 /**/
3592 } else {
3593
3594 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8881A Not Supprrt This AntDiv type\n"));
3595 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3596 return;
3597 }
3598
3599 odm_trx_hw_ant_div_init_8881a(p_dm);
3600 }
3601 #endif
3602
3603 /* 2 [--8812---] */
3604 #if (RTL8812A_SUPPORT == 1)
3605 else if (p_dm->support_ic_type == ODM_RTL8812) {
3606 /* p_dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3607
3608 if (p_dm->ant_div_type != CG_TRX_HW_ANTDIV) {
3609 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] 8812A Not Supprrt This AntDiv type\n"));
3610 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
3611 return;
3612 }
3613 odm_trx_hw_ant_div_init_8812a(p_dm);
3614 }
3615 #endif
3616
3617 /*[--8188F---]*/
3618 #if (RTL8188F_SUPPORT == 1)
3619 else if (p_dm->support_ic_type == ODM_RTL8188F) {
3620
3621 p_dm->ant_div_type = S0S1_SW_ANTDIV;
3622 odm_s0s1_sw_ant_div_init_8188f(p_dm);
3623 }
3624 #endif
3625
3626 /*[--8822B---]*/
3627 #if (RTL8822B_SUPPORT == 1)
3628 else if (p_dm->support_ic_type == ODM_RTL8822B) {
3629 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
3630 p_dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
3631
3632 if (p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
3633 phydm_hl_smart_ant_type2_init_8822b(p_dm);
3634 #endif
3635 }
3636 #endif
3637
3638 /*
3639 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** support_ic_type=[%lu]\n",p_dm->support_ic_type));
3640 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** AntDiv support_ability=[%lu]\n",(p_dm->support_ability & ODM_BB_ANT_DIV)>>6));
3641 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("*** AntDiv type=[%d]\n",p_dm->ant_div_type));
3642 */
3643 }
3644
3645 void
odm_ant_div(void * p_dm_void)3646 odm_ant_div(
3647 void *p_dm_void
3648 )
3649 {
3650 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3651 struct _ADAPTER *p_adapter = p_dm->adapter;
3652 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3653 #if (defined(CONFIG_HL_SMART_ANTENNA))
3654 struct smt_ant_honbo *pdm_sat_table = &(p_dm->dm_sat_table);
3655 #endif
3656
3657 #ifdef ODM_EVM_ENHANCE_ANTDIV
3658
3659 if (p_dm->is_linked) {
3660 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("tp_active_occur=((%d)), EVM_method_enable=((%d))\n",
3661 p_dm->tp_active_occur, p_dm_fat_table->EVM_method_enable));
3662
3663 if ((p_dm->tp_active_occur == 1) && (p_dm_fat_table->EVM_method_enable == 1)) {
3664
3665 p_dm_fat_table->idx_ant_div_counter_5g = p_dm->antdiv_period;
3666 p_dm_fat_table->idx_ant_div_counter_2g = p_dm->antdiv_period;
3667 }
3668 }
3669 #endif
3670
3671 if (*p_dm->p_band_type == ODM_BAND_5G) {
3672 if (p_dm_fat_table->idx_ant_div_counter_5g < p_dm->antdiv_period) {
3673 p_dm_fat_table->idx_ant_div_counter_5g++;
3674 return;
3675 } else
3676 p_dm_fat_table->idx_ant_div_counter_5g = 0;
3677 } else if (*p_dm->p_band_type == ODM_BAND_2_4G) {
3678 if (p_dm_fat_table->idx_ant_div_counter_2g < p_dm->antdiv_period) {
3679 p_dm_fat_table->idx_ant_div_counter_2g++;
3680 return;
3681 } else
3682 p_dm_fat_table->idx_ant_div_counter_2g = 0;
3683 }
3684
3685 /* ---------- */
3686
3687 /* ---------- */
3688 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
3689
3690 if (p_dm_fat_table->enable_ctrl_frame_antdiv) {
3691
3692 if ((p_dm->data_frame_num <= 10) && (p_dm->is_linked))
3693 p_dm_fat_table->use_ctrl_frame_antdiv = 1;
3694 else
3695 p_dm_fat_table->use_ctrl_frame_antdiv = 0;
3696
3697 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", p_dm_fat_table->use_ctrl_frame_antdiv, p_dm->data_frame_num));
3698 p_dm->data_frame_num = 0;
3699 }
3700
3701 if (p_adapter->MgntInfo.AntennaTest)
3702 return;
3703
3704 {
3705 #if (BEAMFORMING_SUPPORT == 1)
3706
3707 enum beamforming_cap beamform_cap = phydm_get_beamform_cap(p_dm);
3708
3709 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ AntDiv Beam Cap ] cap= ((%d))\n", beamform_cap));
3710
3711 if (beamform_cap & BEAMFORMEE_CAP) { /* BFmee On && Div On->Div Off */
3712 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ AntDiv : OFF ] BFmee ==1; cap= ((%d))\n", beamform_cap));
3713 if (p_dm_fat_table->fix_ant_bfee == 0) {
3714 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3715 p_dm_fat_table->fix_ant_bfee = 1;
3716 }
3717 return;
3718 } else { /* BFmee Off && Div Off->Div On */
3719 if ((p_dm_fat_table->fix_ant_bfee == 1) && p_dm->is_linked) {
3720 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ AntDiv : ON ] BFmee ==0; cap=((%d))\n", beamform_cap));
3721 if (p_dm->ant_div_type != S0S1_SW_ANTDIV)
3722 odm_ant_div_on_off(p_dm, ANTDIV_ON);
3723
3724 p_dm_fat_table->fix_ant_bfee = 0;
3725 }
3726 }
3727 #endif
3728 }
3729 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
3730 /* ----------just for fool proof */
3731
3732 if (p_dm->antdiv_rssi)
3733 p_dm->debug_components |= DBG_ANT_DIV;
3734 else
3735 p_dm->debug_components &= ~DBG_ANT_DIV;
3736
3737 if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) {
3738 /* PHYDM_DBG(p_dm, DBG_ANT_DIV,("[ 2G AntDiv Running ]\n")); */
3739 if (!(p_dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
3740 return;
3741 } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) {
3742 /* PHYDM_DBG(p_dm, DBG_ANT_DIV,("[ 5G AntDiv Running ]\n")); */
3743 if (!(p_dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
3744 return;
3745 }
3746 /* else if(p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */
3747 /* { */
3748 /* PHYDM_DBG(p_dm, DBG_ANT_DIV,("[ 2G & 5G AntDiv Running ]\n")); */
3749 /* } */
3750 #endif
3751
3752 /* ---------- */
3753
3754 if (p_dm->antdiv_select == 1)
3755 p_dm->ant_type = ODM_FIX_MAIN_ANT;
3756 else if (p_dm->antdiv_select == 2)
3757 p_dm->ant_type = ODM_FIX_AUX_ANT;
3758 else { /* if (p_dm->antdiv_select==0) */
3759 p_dm->ant_type = ODM_AUTO_ANT;
3760
3761 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3762 /*Stop Antenna diversity for CMW500 testing case*/
3763 if (p_dm->consecutive_idlel_time >= 10) {
3764 p_dm->ant_type = ODM_FIX_MAIN_ANT;
3765 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n", p_dm->consecutive_idlel_time));
3766 }
3767 #endif
3768 }
3769
3770 /* PHYDM_DBG(p_dm, DBG_ANT_DIV,("ant_type= (( %d )) , pre_ant_type= (( %d ))\n",p_dm->ant_type,p_dm->pre_ant_type)); */
3771
3772 if (p_dm->ant_type != ODM_AUTO_ANT) {
3773 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Fix Antenna at (( %s ))\n", (p_dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX"));
3774
3775 if (p_dm->ant_type != p_dm->pre_ant_type) {
3776 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3777 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_REG);
3778
3779 if (p_dm->ant_type == ODM_FIX_MAIN_ANT)
3780 odm_update_rx_idle_ant(p_dm, MAIN_ANT);
3781 else if (p_dm->ant_type == ODM_FIX_AUX_ANT)
3782 odm_update_rx_idle_ant(p_dm, AUX_ANT);
3783 }
3784 p_dm->pre_ant_type = p_dm->ant_type;
3785 return;
3786 } else {
3787 if (p_dm->ant_type != p_dm->pre_ant_type) {
3788 odm_ant_div_on_off(p_dm, ANTDIV_ON);
3789 odm_tx_by_tx_desc_or_reg(p_dm, TX_BY_DESC);
3790 }
3791 p_dm->pre_ant_type = p_dm->ant_type;
3792 }
3793
3794
3795 /* 3 ----------------------------------------------------------------------------------------------------------- */
3796 /* 2 [--88E---] */
3797 if (p_dm->support_ic_type == ODM_RTL8188E) {
3798 #if (RTL8188E_SUPPORT == 1)
3799 if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm->ant_div_type == CGCS_RX_HW_ANTDIV)
3800 odm_hw_ant_div(p_dm);
3801
3802 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3803 else if (p_dm->ant_div_type == CG_TRX_SMART_ANTDIV)
3804 odm_fast_ant_training(p_dm);
3805 #endif
3806
3807 #endif
3808
3809 }
3810 /* 2 [--92E---] */
3811 #if (RTL8192E_SUPPORT == 1)
3812 else if (p_dm->support_ic_type == ODM_RTL8192E) {
3813 if (p_dm->ant_div_type == CGCS_RX_HW_ANTDIV || p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3814 odm_hw_ant_div(p_dm);
3815
3816 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3817 else if (p_dm->ant_div_type == CG_TRX_SMART_ANTDIV)
3818 odm_fast_ant_training(p_dm);
3819 #endif
3820
3821 }
3822 #endif
3823
3824 #if (RTL8723B_SUPPORT == 1)
3825 /* 2 [--8723B---] */
3826 else if (p_dm->support_ic_type == ODM_RTL8723B) {
3827 if (phydm_is_bt_enable_8723b(p_dm)) {
3828 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[BT is enable!!!]\n"));
3829 if (p_dm_fat_table->is_become_linked == true) {
3830 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Set REG 948[9:6]=0x0\n"));
3831 if (p_dm->support_ic_type == ODM_RTL8723B)
3832 odm_set_bb_reg(p_dm, 0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0);
3833
3834 p_dm_fat_table->is_become_linked = false;
3835 }
3836 } else {
3837 if (p_dm->ant_div_type == S0S1_SW_ANTDIV) {
3838
3839 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3840 odm_s0s1_sw_ant_div(p_dm, SWAW_STEP_PEEK);
3841 #endif
3842 } else if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3843 odm_hw_ant_div(p_dm);
3844 }
3845 }
3846 #endif
3847 /*8723D*/
3848 #if (RTL8723D_SUPPORT == 1)
3849 else if (p_dm->support_ic_type == ODM_RTL8723D) {
3850
3851 odm_hw_ant_div(p_dm);
3852 /**/
3853 }
3854 #endif
3855
3856 /* 2 [--8821A---] */
3857 #if (RTL8821A_SUPPORT == 1)
3858 else if (p_dm->support_ic_type == ODM_RTL8821) {
3859 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
3860 if (p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
3861
3862 if (pdm_sat_table->fix_beam_pattern_en != 0) {
3863 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword));
3864 /*return;*/
3865 } else {
3866 /*PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n"));*/
3867 odm_fast_ant_training_hl_smart_antenna_type1(p_dm);
3868 }
3869
3870 } else
3871 #endif
3872 {
3873
3874 #ifdef ODM_CONFIG_BT_COEXIST
3875 if (!p_dm->bt_info_table.is_bt_enabled) { /*BT disabled*/
3876 if (p_dm->ant_div_type == S0S1_SW_ANTDIV) {
3877 p_dm->ant_div_type = CG_TRX_HW_ANTDIV;
3878 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n"));
3879 /*odm_set_bb_reg(p_dm, 0x8D4, BIT24, 1); */
3880 if (p_dm_fat_table->is_become_linked == true)
3881 odm_ant_div_on_off(p_dm, ANTDIV_ON);
3882 }
3883
3884 } else { /*BT enabled*/
3885
3886 if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV) {
3887 p_dm->ant_div_type = S0S1_SW_ANTDIV;
3888 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n"));
3889 /*odm_set_bb_reg(p_dm, 0x8D4, BIT24, 0);*/
3890 odm_ant_div_on_off(p_dm, ANTDIV_OFF);
3891 }
3892 }
3893 #endif
3894
3895 if (p_dm->ant_div_type == S0S1_SW_ANTDIV) {
3896
3897 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3898 odm_s0s1_sw_ant_div(p_dm, SWAW_STEP_PEEK);
3899 #endif
3900 } else if (p_dm->ant_div_type == CG_TRX_HW_ANTDIV)
3901 odm_hw_ant_div(p_dm);
3902 }
3903 }
3904 #endif
3905
3906 /* 2 [--8821C---] */
3907 #if (RTL8821C_SUPPORT == 1)
3908 else if (p_dm->support_ic_type == ODM_RTL8821C) {
3909 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3910 odm_s0s1_sw_ant_div(p_dm, SWAW_STEP_PEEK);
3911 #endif
3912 }
3913 #endif
3914
3915 /* 2 [--8881A---] */
3916 #if (RTL8881A_SUPPORT == 1)
3917 else if (p_dm->support_ic_type == ODM_RTL8881A)
3918 odm_hw_ant_div(p_dm);
3919 #endif
3920
3921 /* 2 [--8812A---] */
3922 #if (RTL8812A_SUPPORT == 1)
3923 else if (p_dm->support_ic_type == ODM_RTL8812)
3924 odm_hw_ant_div(p_dm);
3925 #endif
3926
3927 #if (RTL8188F_SUPPORT == 1)
3928 /* [--8188F---]*/
3929 else if (p_dm->support_ic_type == ODM_RTL8188F) {
3930
3931 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3932 odm_s0s1_sw_ant_div(p_dm, SWAW_STEP_PEEK);
3933 #endif
3934 }
3935 #endif
3936
3937 /* [--8822B---]*/
3938 #if (RTL8822B_SUPPORT == 1)
3939 else if (p_dm->support_ic_type == ODM_RTL8822B) {
3940 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
3941 if (p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
3942
3943 if (pdm_sat_table->fix_beam_pattern_en != 0)
3944 PHYDM_DBG(p_dm, DBG_ANT_DIV, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword));
3945 else
3946 phydm_fast_ant_training_hl_smart_antenna_type2(p_dm);
3947 }
3948 #endif
3949 }
3950 #endif
3951
3952
3953 }
3954
3955
3956 void
odm_antsel_statistics(void * p_dm_void,void * p_phy_info_void,u8 antsel_tr_mux,u32 mac_id,u32 utility,u8 method,u8 is_cck_rate)3957 odm_antsel_statistics(
3958 void *p_dm_void,
3959 void *p_phy_info_void,
3960 u8 antsel_tr_mux,
3961 u32 mac_id,
3962 u32 utility,
3963 u8 method,
3964 u8 is_cck_rate
3965
3966 )
3967 {
3968 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3969 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
3970 struct phydm_phyinfo_struct *p_phy_info = (struct phydm_phyinfo_struct *)p_phy_info_void;
3971
3972 if (method == RSSI_METHOD) {
3973
3974 if (is_cck_rate) {
3975 if (antsel_tr_mux == ANT1_2G) {
3976 if (p_dm_fat_table->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
3977 return;
3978
3979 p_dm_fat_table->main_ant_sum_cck[mac_id] += (u16)utility;
3980 p_dm_fat_table->main_ant_cnt_cck[mac_id]++;
3981 } else {
3982 if (p_dm_fat_table->aux_ant_sum_cck[mac_id] > 65435)
3983 return;
3984
3985 p_dm_fat_table->aux_ant_sum_cck[mac_id] += (u16)utility;
3986 p_dm_fat_table->aux_ant_cnt_cck[mac_id]++;
3987 }
3988
3989 } else { /*ofdm rate*/
3990
3991 if (antsel_tr_mux == ANT1_2G) {
3992 if (p_dm_fat_table->main_ant_sum[mac_id] > 65435)
3993 return;
3994
3995 p_dm_fat_table->main_ant_sum[mac_id] += (u16)utility;
3996 p_dm_fat_table->main_ant_cnt[mac_id]++;
3997 } else {
3998 if (p_dm_fat_table->aux_ant_sum[mac_id] > 65435)
3999 return;
4000
4001 p_dm_fat_table->aux_ant_sum[mac_id] += (u16)utility;
4002 p_dm_fat_table->aux_ant_cnt[mac_id]++;
4003 }
4004 }
4005 }
4006 #ifdef ODM_EVM_ENHANCE_ANTDIV
4007 else if (method == EVM_METHOD) {
4008 if (p_dm->rate_ss == 1) {
4009
4010 if (antsel_tr_mux == ANT1_2G) {
4011 p_dm_fat_table->main_ant_evm_sum[mac_id] += ((p_phy_info->rx_mimo_evm_dbm[0])<<5);
4012 p_dm_fat_table->main_ant_evm_cnt[mac_id]++;
4013 } else {
4014 p_dm_fat_table->aux_ant_evm_sum[mac_id] += ((p_phy_info->rx_mimo_evm_dbm[0])<<5);
4015 p_dm_fat_table->aux_ant_evm_cnt[mac_id]++;
4016 }
4017
4018 } else {/*>= 2SS*/
4019
4020 if (antsel_tr_mux == ANT1_2G) {
4021
4022 p_dm_fat_table->main_ant_evm_2ss_sum[mac_id][0] += (p_phy_info->rx_mimo_evm_dbm[0]<<5);
4023 p_dm_fat_table->main_ant_evm_2ss_sum[mac_id][1] += (p_phy_info->rx_mimo_evm_dbm[1]<<5);
4024 p_dm_fat_table->main_ant_evm_2ss_cnt[mac_id]++;
4025
4026 } else {
4027
4028 p_dm_fat_table->aux_ant_evm_2ss_sum[mac_id][0] += (p_phy_info->rx_mimo_evm_dbm[0]<<5);
4029 p_dm_fat_table->aux_ant_evm_2ss_sum[mac_id][1] += (p_phy_info->rx_mimo_evm_dbm[1]<<5);
4030 p_dm_fat_table->aux_ant_evm_2ss_cnt[mac_id]++;
4031 }
4032 }
4033
4034 } else if (method == CRC32_METHOD) {
4035
4036 if (antsel_tr_mux == ANT1_2G) {
4037 p_dm_fat_table->main_crc32_ok_cnt += utility;
4038 p_dm_fat_table->main_crc32_fail_cnt++;
4039 } else {
4040 p_dm_fat_table->aux_crc32_ok_cnt += utility;
4041 p_dm_fat_table->aux_crc32_fail_cnt++;
4042 }
4043
4044 } else if (method == TP_METHOD) {
4045 if (((utility <= ODM_RATEMCS15) && (utility >= ODM_RATEMCS0)) &&
4046 (p_dm_fat_table->fat_state_cnt <= p_dm->antdiv_tp_period)
4047 ) {
4048
4049 if (antsel_tr_mux == ANT1_2G) {
4050 p_dm_fat_table->antdiv_tp_main += (phy_rate_table[utility])<<5;
4051 p_dm_fat_table->antdiv_tp_main_cnt++;
4052 } else {
4053 p_dm_fat_table->antdiv_tp_aux += (phy_rate_table[utility])<<5;
4054 p_dm_fat_table->antdiv_tp_aux_cnt++;
4055 }
4056 }
4057 }
4058 #endif
4059 }
4060
4061 void
odm_process_rssi_for_ant_div(void * p_dm_void,void * p_phy_info_void,void * p_pkt_info_void)4062 odm_process_rssi_for_ant_div(
4063 void *p_dm_void,
4064 void *p_phy_info_void,
4065 void *p_pkt_info_void
4066 )
4067 {
4068 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4069 struct phydm_phyinfo_struct *p_phy_info = (struct phydm_phyinfo_struct *)p_phy_info_void;
4070 struct phydm_perpkt_info_struct *p_pktinfo = (struct phydm_perpkt_info_struct *)p_pkt_info_void;
4071 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
4072 #if (defined(CONFIG_HL_SMART_ANTENNA))
4073 struct smt_ant_honbo *pdm_sat_table = &(p_dm->dm_sat_table);
4074 u32 beam_tmp;
4075 u8 next_ant;
4076 u8 train_pkt_number;
4077 #endif
4078 u8 is_cck_rate = FALSE;
4079 u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0];
4080 u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1];
4081 u8 rx_evm_ant0 = p_phy_info->rx_mimo_signal_quality[0];
4082 u8 rx_evm_ant1 = p_phy_info->rx_mimo_signal_quality[1];
4083 u8 rssi_avg;
4084
4085 is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
4086
4087 if ((p_dm->support_ic_type & ODM_IC_2SS) && (!is_cck_rate)) {
4088
4089 if (rx_power_ant1 < 100)
4090 rssi_avg = (u8)odm_convert_to_db((odm_convert_to_linear(rx_power_ant0) + odm_convert_to_linear(rx_power_ant1))>>1); /*averaged PWDB*/
4091
4092 } else {
4093 rx_power_ant0 = (u8)p_phy_info->rx_pwdb_all;
4094 rssi_avg = rx_power_ant0;
4095 }
4096
4097 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
4098 if ((p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE))
4099 phydm_process_rssi_for_hb_smtant_type2(p_dm, p_phy_info, p_pktinfo, rssi_avg); /*for 8822B*/
4100 else
4101 #endif
4102
4103 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
4104 #ifdef CONFIG_FAT_PATCH
4105 if ((p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) {
4106
4107 /*[Beacon]*/
4108 if (p_pktinfo->is_packet_beacon) {
4109
4110 pdm_sat_table->beacon_counter++;
4111 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter));
4112
4113 if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) {
4114
4115 if (pdm_sat_table->ant_num > 1) {
4116 next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
4117 odm_update_rx_idle_ant(p_dm, next_ant);
4118 }
4119
4120 pdm_sat_table->update_beam_idx++;
4121
4122 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
4123 pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx));
4124
4125 pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter;
4126 pdm_sat_table->pkt_counter = 0;
4127 }
4128 }
4129 /*[data]*/
4130 else if (p_pktinfo->is_packet_to_self) {
4131
4132 if (pdm_sat_table->pkt_skip_statistic_en == 0) {
4133 /*
4134 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
4135 p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0));
4136 */
4137 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
4138 p_pktinfo->station_id, pdm_sat_table->pkt_counter, p_dm_fat_table->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, rx_power_ant0));
4139
4140 pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0;
4141 pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++;
4142 pdm_sat_table->pkt_counter++;
4143
4144 #if 1
4145 train_pkt_number = pdm_sat_table->beam_train_cnt[p_dm_fat_table->rx_idle_ant - 1][pdm_sat_table->fast_training_beam_num];
4146 #else
4147 train_pkt_number = pdm_sat_table->per_beam_training_pkt_num;
4148 #endif
4149
4150 /*Swich Antenna erery N pkts*/
4151 if (pdm_sat_table->pkt_counter == train_pkt_number) {
4152
4153 if (pdm_sat_table->ant_num > 1) {
4154
4155 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number));
4156 next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
4157 odm_update_rx_idle_ant(p_dm, next_ant);
4158 }
4159
4160 pdm_sat_table->update_beam_idx++;
4161 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
4162 pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx));
4163
4164 pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter;
4165 pdm_sat_table->pkt_counter = 0;
4166 }
4167 }
4168 }
4169
4170 /*Swich Beam after switch "pdm_sat_table->ant_num" antennas*/
4171 if (pdm_sat_table->update_beam_idx == pdm_sat_table->ant_num) {
4172
4173 pdm_sat_table->update_beam_idx = 0;
4174 pdm_sat_table->pkt_counter = 0;
4175 beam_tmp = pdm_sat_table->fast_training_beam_num;
4176
4177 if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) {
4178
4179 p_dm_fat_table->fat_state = FAT_DECISION_STATE;
4180
4181 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
4182 odm_fast_ant_training_hl_smart_antenna_type1(p_dm);
4183 #else
4184 odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem);
4185 #endif
4186
4187
4188 } else {
4189 pdm_sat_table->fast_training_beam_num++;
4190 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num));
4191 phydm_set_all_ant_same_beam_num(p_dm);
4192
4193 p_dm_fat_table->fat_state = FAT_TRAINING_STATE;
4194 }
4195 }
4196
4197 }
4198 #else
4199
4200 if (p_dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
4201 if ((p_dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
4202 (p_pktinfo->is_packet_to_self) &&
4203 (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)
4204 ) {
4205
4206 if (pdm_sat_table->pkt_skip_statistic_en == 0) {
4207 /*
4208 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
4209 p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0));
4210 */
4211 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
4212 p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->is_packet_to_self, pdm_sat_table->fast_training_beam_num, rx_power_ant0));
4213
4214
4215 pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0;
4216 pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++;
4217 pdm_sat_table->pkt_counter++;
4218
4219 /*swich beam every N pkt*/
4220 if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) {
4221
4222 pdm_sat_table->pkt_counter = 0;
4223 beam_tmp = pdm_sat_table->fast_training_beam_num;
4224
4225 if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) {
4226
4227 p_dm_fat_table->fat_state = FAT_DECISION_STATE;
4228
4229 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
4230 odm_fast_ant_training_hl_smart_antenna_type1(p_dm);
4231 #else
4232 odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem);
4233 #endif
4234
4235
4236 } else {
4237 pdm_sat_table->fast_training_beam_num++;
4238 phydm_set_all_ant_same_beam_num(p_dm);
4239
4240 p_dm_fat_table->fat_state = FAT_TRAINING_STATE;
4241 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num));
4242 }
4243 }
4244 }
4245 }
4246 }
4247 #endif
4248 else
4249 #endif
4250 if (p_dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
4251 if ((p_dm->support_ic_type & ODM_SMART_ANT_SUPPORT) && (p_pktinfo->is_packet_to_self) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { /* (p_pktinfo->is_packet_match_bssid && (!p_pktinfo->is_packet_beacon)) */
4252 u8 antsel_tr_mux;
4253 antsel_tr_mux = (p_dm_fat_table->antsel_rx_keep_2 << 2) | (p_dm_fat_table->antsel_rx_keep_1 << 1) | p_dm_fat_table->antsel_rx_keep_0;
4254 p_dm_fat_table->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
4255 p_dm_fat_table->ant_rssi_cnt[antsel_tr_mux]++;
4256 }
4257 } else { /* ant_div_type != CG_TRX_SMART_ANTDIV */
4258 if ((p_dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_pktinfo->is_packet_to_self || p_dm_fat_table->use_ctrl_frame_antdiv)) {
4259
4260 if (p_dm->ant_div_type == S0S1_SW_ANTDIV) {
4261
4262 if (is_cck_rate || (p_dm->support_ic_type == ODM_RTL8188F))
4263 p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
4264
4265 odm_antsel_statistics(p_dm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate);
4266
4267 } else {
4268
4269 odm_antsel_statistics(p_dm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate);
4270
4271 #ifdef ODM_EVM_ENHANCE_ANTDIV
4272 if (p_dm->support_ic_type == ODM_RTL8192E) {
4273 if (!is_cck_rate) {
4274 odm_antsel_statistics(p_dm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, EVM_METHOD, is_cck_rate);
4275 odm_antsel_statistics(p_dm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, TP_METHOD, is_cck_rate);
4276 }
4277
4278 }
4279 #endif
4280 }
4281 }
4282 }
4283 /* PHYDM_DBG(p_dm,DBG_ANT_DIV,("is_cck_rate=%d, PWDB_ALL=%d\n",is_cck_rate, p_phy_info->rx_pwdb_all)); */
4284 /* PHYDM_DBG(p_dm,DBG_ANT_DIV,("antsel_tr_mux=3'b%d%d%d\n",p_dm_fat_table->antsel_rx_keep_2, p_dm_fat_table->antsel_rx_keep_1, p_dm_fat_table->antsel_rx_keep_0)); */
4285 }
4286
4287 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
4288 void
odm_set_tx_ant_by_tx_info(void * p_dm_void,u8 * p_desc,u8 mac_id)4289 odm_set_tx_ant_by_tx_info(
4290 void *p_dm_void,
4291 u8 *p_desc,
4292 u8 mac_id
4293
4294 )
4295 {
4296 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4297 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
4298
4299 if (!(p_dm->support_ability & ODM_BB_ANT_DIV))
4300 return;
4301
4302 if (p_dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4303 return;
4304
4305
4306 if (p_dm->support_ic_type == ODM_RTL8723B) {
4307 #if (RTL8723B_SUPPORT == 1)
4308 SET_TX_DESC_ANTSEL_A_8723B(p_desc, p_dm_fat_table->antsel_a[mac_id]);
4309 /*PHYDM_DBG(p_dm,DBG_ANT_DIV, ("[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4310 mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/
4311 #endif
4312 } else if (p_dm->support_ic_type == ODM_RTL8821) {
4313 #if (RTL8821A_SUPPORT == 1)
4314 SET_TX_DESC_ANTSEL_A_8812(p_desc, p_dm_fat_table->antsel_a[mac_id]);
4315 /*PHYDM_DBG(p_dm,DBG_ANT_DIV, ("[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4316 mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/
4317 #endif
4318 } else if (p_dm->support_ic_type == ODM_RTL8188E) {
4319 #if (RTL8188E_SUPPORT == 1)
4320 SET_TX_DESC_ANTSEL_A_88E(p_desc, p_dm_fat_table->antsel_a[mac_id]);
4321 SET_TX_DESC_ANTSEL_B_88E(p_desc, p_dm_fat_table->antsel_b[mac_id]);
4322 SET_TX_DESC_ANTSEL_C_88E(p_desc, p_dm_fat_table->antsel_c[mac_id]);
4323 /*PHYDM_DBG(p_dm,DBG_ANT_DIV, ("[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4324 mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/
4325 #endif
4326 } else if (p_dm->support_ic_type == ODM_RTL8821C) {
4327 #if (RTL8821C_SUPPORT == 1)
4328 SET_TX_DESC_ANTSEL_A_8821C(p_desc, p_dm_fat_table->antsel_a[mac_id]);
4329 /*PHYDM_DBG(p_dm,DBG_ANT_DIV, ("[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4330 mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/
4331 #endif
4332 }
4333 }
4334 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
4335
4336 void
odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv * priv,struct tx_desc * pdesc,unsigned short aid)4337 odm_set_tx_ant_by_tx_info(
4338 struct rtl8192cd_priv *priv,
4339 struct tx_desc *pdesc,
4340 unsigned short aid
4341 )
4342 {
4343 struct PHY_DM_STRUCT *p_dm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/
4344 struct phydm_fat_struct *p_dm_fat_table = &(p_dm->dm_fat_table);
4345
4346 if (!(p_dm->support_ability & ODM_BB_ANT_DIV))
4347 return;
4348
4349 if (p_dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4350 return;
4351
4352 if (p_dm->support_ic_type == ODM_RTL8881A) {
4353 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */
4354 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
4355 pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16);
4356 } else if (p_dm->support_ic_type == ODM_RTL8192E) {
4357 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */
4358 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
4359 pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16);
4360 } else if (p_dm->support_ic_type == ODM_RTL8188E) {
4361 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
4362 pdesc->Dword2 &= set_desc(~BIT(24));
4363 pdesc->Dword2 &= set_desc(~BIT(25));
4364 pdesc->Dword7 &= set_desc(~BIT(29));
4365
4366 pdesc->Dword2 |= set_desc(p_dm_fat_table->antsel_a[aid] << 24);
4367 pdesc->Dword2 |= set_desc(p_dm_fat_table->antsel_b[aid] << 25);
4368 pdesc->Dword7 |= set_desc(p_dm_fat_table->antsel_c[aid] << 29);
4369
4370
4371 } else if (p_dm->support_ic_type == ODM_RTL8812) {
4372 /*[path-A]*/
4373 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
4374
4375 pdesc->Dword6 &= set_desc(~BIT(16));
4376 pdesc->Dword6 &= set_desc(~BIT(17));
4377 pdesc->Dword6 &= set_desc(~BIT(18));
4378
4379 pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16);
4380 pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_b[aid] << 17);
4381 pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_c[aid] << 18);
4382
4383 }
4384 }
4385
4386
4387 #if 1 /*def CONFIG_WLAN_HAL*/
4388 void
odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv * priv,void * pdesc_data,u16 aid)4389 odm_set_tx_ant_by_tx_info_hal(
4390 struct rtl8192cd_priv *priv,
4391 void *pdesc_data,
4392 u16 aid
4393 )
4394 {
4395 struct PHY_DM_STRUCT *p_dm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/
4396 struct phydm_fat_struct *p_dm_fat_table = &(p_dm->dm_fat_table);
4397 PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
4398
4399 if (!(p_dm->support_ability & ODM_BB_ANT_DIV))
4400 return;
4401
4402 if (p_dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4403 return;
4404
4405 if (p_dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A)) {
4406 /*panic_printk("[%s] [%d] ******odm_set_tx_ant_by_tx_info_hal******\n",__FUNCTION__,__LINE__);*/
4407 pdescdata->ant_sel = 1;
4408 pdescdata->ant_sel_a = p_dm_fat_table->antsel_a[aid];
4409 }
4410 }
4411 #endif /*#ifdef CONFIG_WLAN_HAL*/
4412
4413 #endif
4414
4415
4416 void
odm_ant_div_config(void * p_dm_void)4417 odm_ant_div_config(
4418 void *p_dm_void
4419 )
4420 {
4421 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4422 struct phydm_fat_struct *p_dm_fat_table = &p_dm->dm_fat_table;
4423 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
4424 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("WIN Config Antenna Diversity\n"));
4425 /*
4426 if(p_dm->support_ic_type==ODM_RTL8723B)
4427 {
4428 if((!p_dm->dm_swat_table.ANTA_ON || !p_dm->dm_swat_table.ANTB_ON))
4429 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
4430 }
4431 */
4432 if (p_dm->support_ic_type == ODM_RTL8723D) {
4433
4434 p_dm->ant_div_type = S0S1_TRX_HW_ANTDIV;
4435 /**/
4436 }
4437 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
4438
4439 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("CE Config Antenna Diversity\n"));
4440
4441 if (p_dm->support_ic_type == ODM_RTL8723B)
4442 p_dm->ant_div_type = S0S1_SW_ANTDIV;
4443
4444
4445
4446 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4447
4448 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("AP Config Antenna Diversity\n"));
4449
4450 /* 2 [ NOT_SUPPORT_ANTDIV ] */
4451 #if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
4452 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
4453 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n"));
4454
4455 /* 2 [ 2G&5G_SUPPORT_ANTDIV ] */
4456 #elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
4457 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n"));
4458 p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
4459
4460 if (p_dm->support_ic_type & ODM_ANTDIV_SUPPORT)
4461 p_dm->support_ability |= ODM_BB_ANT_DIV;
4462 if (*p_dm->p_band_type == ODM_BAND_5G) {
4463 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
4464 p_dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4465 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"));
4466 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
4467 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
4468 p_dm->ant_div_type = CG_TRX_HW_ANTDIV;
4469 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"));
4470 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
4471 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
4472 p_dm->ant_div_type = CG_TRX_SMART_ANTDIV;
4473 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"));
4474 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
4475 p_dm->ant_div_type = S0S1_SW_ANTDIV;
4476 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"));
4477 #endif
4478 } else if (*p_dm->p_band_type == ODM_BAND_2_4G) {
4479 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
4480 p_dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4481 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"));
4482 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
4483 p_dm->ant_div_type = CG_TRX_HW_ANTDIV;
4484 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"));
4485 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4486 p_dm->ant_div_type = CG_TRX_SMART_ANTDIV;
4487 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"));
4488 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
4489 p_dm->ant_div_type = S0S1_SW_ANTDIV;
4490 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"));
4491 #endif
4492 }
4493
4494 /* 2 [ 5G_SUPPORT_ANTDIV ] */
4495 #elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
4496 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"));
4497 panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
4498 p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_5G);
4499 if (*p_dm->p_band_type == ODM_BAND_5G) {
4500 if (p_dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
4501 p_dm->support_ability |= ODM_BB_ANT_DIV;
4502 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
4503 p_dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4504 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"));
4505 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
4506 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
4507 p_dm->ant_div_type = CG_TRX_HW_ANTDIV;
4508 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
4509 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"));
4510 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
4511 p_dm->ant_div_type = CG_TRX_SMART_ANTDIV;
4512 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"));
4513 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
4514 p_dm->ant_div_type = S0S1_SW_ANTDIV;
4515 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"));
4516 #endif
4517 } else if (*p_dm->p_band_type == ODM_BAND_2_4G) {
4518 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Not Support 2G ant_div_type\n"));
4519 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
4520 }
4521
4522 /* 2 [ 2G_SUPPORT_ANTDIV ] */
4523 #elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
4524 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n"));
4525 p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G);
4526 if (*p_dm->p_band_type == ODM_BAND_2_4G) {
4527 if (p_dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
4528 p_dm->support_ability |= ODM_BB_ANT_DIV;
4529 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
4530 p_dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4531 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"));
4532 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
4533 p_dm->ant_div_type = CG_TRX_HW_ANTDIV;
4534 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"));
4535 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4536 p_dm->ant_div_type = CG_TRX_SMART_ANTDIV;
4537 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"));
4538 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
4539 p_dm->ant_div_type = S0S1_SW_ANTDIV;
4540 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"));
4541 #endif
4542 } else if (*p_dm->p_band_type == ODM_BAND_5G) {
4543 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Not Support 5G ant_div_type\n"));
4544 p_dm->support_ability &= ~(ODM_BB_ANT_DIV);
4545 }
4546 #endif
4547 #endif
4548
4549 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((p_dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0)));
4550 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", p_dm->dm_fat_table.b_fix_tx_ant));
4551
4552 }
4553
4554
4555 void
odm_ant_div_timers(void * p_dm_void,u8 state)4556 odm_ant_div_timers(
4557 void *p_dm_void,
4558 u8 state
4559 )
4560 {
4561 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4562 if (state == INIT_ANTDIV_TIMMER) {
4563 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4564 odm_initialize_timer(p_dm, &(p_dm->dm_swat_table.phydm_sw_antenna_switch_timer),
4565 (void *)odm_sw_antdiv_callback, NULL, "phydm_sw_antenna_switch_timer");
4566 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4567 odm_initialize_timer(p_dm, &p_dm->fast_ant_training_timer,
4568 (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer");
4569 #endif
4570
4571 #ifdef ODM_EVM_ENHANCE_ANTDIV
4572 odm_initialize_timer(p_dm, &p_dm->evm_fast_ant_training_timer,
4573 (void *)odm_evm_fast_ant_training_callback, NULL, "evm_fast_ant_training_timer");
4574 #endif
4575 } else if (state == CANCEL_ANTDIV_TIMMER) {
4576 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4577 odm_cancel_timer(p_dm, &(p_dm->dm_swat_table.phydm_sw_antenna_switch_timer));
4578 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4579 odm_cancel_timer(p_dm, &p_dm->fast_ant_training_timer);
4580 #endif
4581
4582 #ifdef ODM_EVM_ENHANCE_ANTDIV
4583 odm_cancel_timer(p_dm, &p_dm->evm_fast_ant_training_timer);
4584 #endif
4585 } else if (state == RELEASE_ANTDIV_TIMMER) {
4586 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4587 odm_release_timer(p_dm, &(p_dm->dm_swat_table.phydm_sw_antenna_switch_timer));
4588 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4589 odm_release_timer(p_dm, &p_dm->fast_ant_training_timer);
4590 #endif
4591
4592 #ifdef ODM_EVM_ENHANCE_ANTDIV
4593 odm_release_timer(p_dm, &p_dm->evm_fast_ant_training_timer);
4594 #endif
4595 }
4596
4597 }
4598
4599 void
phydm_antdiv_debug(void * p_dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)4600 phydm_antdiv_debug(
4601 void *p_dm_void,
4602 u32 *const dm_value,
4603 u32 *_used,
4604 char *output,
4605 u32 *_out_len
4606 )
4607 {
4608 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4609 /*struct phydm_fat_struct* p_dm_fat_table = &p_dm->dm_fat_table;*/
4610 u32 used = *_used;
4611 u32 out_len = *_out_len;
4612
4613 if (dm_value[0] == 1) { /*fixed or auto antenna*/
4614
4615 if (dm_value[1] == 0) {
4616 p_dm->ant_type = ODM_AUTO_ANT;
4617 PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Auto\n"));
4618 } else if (dm_value[1] == 1) {
4619 p_dm->ant_type = ODM_FIX_MAIN_ANT;
4620 PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix Main\n"));
4621 } else if (dm_value[1] == 2) {
4622 p_dm->ant_type = ODM_FIX_AUX_ANT;
4623 PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix Aux\n"));
4624 }
4625
4626 if (p_dm->ant_type != ODM_AUTO_ANT) {
4627
4628 odm_stop_antenna_switch_dm(p_dm);
4629 if (p_dm->ant_type == ODM_FIX_MAIN_ANT)
4630 odm_update_rx_idle_ant(p_dm, MAIN_ANT);
4631 else if (p_dm->ant_type == ODM_FIX_AUX_ANT)
4632 odm_update_rx_idle_ant(p_dm, AUX_ANT);
4633 } else {
4634 phydm_enable_antenna_diversity(p_dm);
4635 }
4636 p_dm->pre_ant_type = p_dm->ant_type;
4637 } else if (dm_value[0] == 2) { /*dynamic period for AntDiv*/
4638
4639 p_dm->antdiv_period = (u8)dm_value[1];
4640 PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv_period = ((%d))\n", p_dm->antdiv_period));
4641 }
4642 *_used = used;
4643 *_out_len = out_len;
4644 }
4645
4646 #endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/
4647
4648 void
odm_ant_div_reset(void * p_dm_void)4649 odm_ant_div_reset(
4650 void *p_dm_void
4651 )
4652 {
4653 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4654
4655 if (p_dm->ant_div_type == S0S1_SW_ANTDIV) {
4656 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4657 odm_s0s1_sw_ant_div_reset(p_dm);
4658 #endif
4659 }
4660
4661 }
4662
4663 void
odm_antenna_diversity_init(void * p_dm_void)4664 odm_antenna_diversity_init(
4665 void *p_dm_void
4666 )
4667 {
4668 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
4669 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4670
4671 #if 0
4672 if (*(p_dm->p_mp_mode) == true)
4673 return;
4674 #endif
4675
4676 odm_ant_div_config(p_dm);
4677 odm_ant_div_init(p_dm);
4678 #endif
4679 }
4680
4681 void
odm_antenna_diversity(void * p_dm_void)4682 odm_antenna_diversity(
4683 void *p_dm_void
4684 )
4685 {
4686 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
4687
4688 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
4689
4690 if (*(p_dm->p_mp_mode) == true)
4691 return;
4692
4693 if (!(p_dm->support_ability & ODM_BB_ANT_DIV)) {
4694 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("[Return!!!] Not Support Antenna Diversity Function\n"));
4695 return;
4696 }
4697
4698 if (p_dm->pause_ability & ODM_BB_ANT_DIV) {
4699
4700 PHYDM_DBG(p_dm, DBG_ANT_DIV, ("Return: Pause AntDIv in LV=%d\n", p_dm->pause_lv_table.lv_antdiv));
4701 return;
4702 }
4703
4704 odm_ant_div(p_dm);
4705 #endif
4706 }
4707