1 // SPDX-License-Identifier: GPL-2.0
2 /********************************************************************************
3 *
4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.All rights reserved.
6 * Module : install driver main
7 * Description : driver main
8 * Author :
9 * Date :
10 * Version : Version 2.0
11 *
12 ********************************************************************************
13 * History :
14 *
15 *
16 ********************************************************************************/
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/fcntl.h>
23 #include <linux/mm.h>
24 #include <linux/proc_fs.h>
25
26 #ifndef CONFIG_HISI_SNAPSHOT_BOOT
27 #include <linux/miscdevice.h>
28 #endif
29
30 #include <linux/fs.h>
31 #include <linux/slab.h>
32 #include <linux/init.h>
33 #include <linux/uaccess.h>
34 #include <asm/io.h>
35 //#include <asm/system.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/string.h>
39 #include <linux/list.h>
40 #include <asm/delay.h>
41 #include <linux/timer.h>
42 #include <linux/delay.h>
43 #include <linux/proc_fs.h>
44 #include <linux/poll.h>
45 #include <asm/bitops.h>
46 #include <linux/uaccess.h>
47 #include <asm/irq.h>
48 #include <linux/moduleparam.h>
49 #include <linux/ioport.h>
50 #include <linux/interrupt.h>
51 #include <linux/semaphore.h>
52 #include <linux/kthread.h>
53
54 #include <linux/i2c.h>
55 #include <linux/i2c-dev.h>
56
57 //#include "gpio_i2c.h"
58 #include "nvp6158_video.h"
59 #include "nvp6158_coax_protocol.h"
60 #include "nvp6158_motion.h"
61 #include "nvp6158_common.h"
62 #include "nvp6158_audio.h"
63 #include "nvp6158_video_auto_detect.h"
64 //#include "acp_firmup.h"
65 #include "nvp6158_video_eq.h"
66 #include "nvp6158_drv.h"
67
68 //#define STREAM_ON_DEFLAULT
69 /*BT601 is not used by Nextchip */
70 //#define BT601
71 #define BT1120
72
73 #define AF_CNT 1
74
75 #ifdef CONFIG_HISI_SNAPSHOT_BOOT
76 #include "himedia.h"
77 #define DEV_NAME "nvp6158"
78 #endif
79
80 static struct i2c_board_info nvp6158_hi_info =
81 {
82 I2C_BOARD_INFO("nvp6158", 0x60),
83 };
84 static bool nvp6158_init_state;
85 unsigned int nvp6158_gCoaxFirmUpdateFlag[16] = {0,};
86 unsigned char nvp6158_det_mode[16] = {NVP6158_DET_MODE_AUTO,};
87 struct semaphore nvp6158_lock;
88 extern unsigned char nvp6158_ch_mode_status[16];
89 extern unsigned char nvp6158_ch_vfmt_status[16];
90 extern unsigned char nvp6158_acp_isp_wr_en[16];
91
92 #define NVP6158_DRIVER_VER "1.1.01"
93 #define NVP6158_HW_REG(reg) *((volatile unsigned int *)(reg))
94
95 int nvp6158_g_soc_chiptype = 0x3521;
96 int nvp6158_chip_id[4];
97 int nvp6158_rev_id[4];
98
99 unsigned int nvp6158_cnt = 0;
100 unsigned int nvp6158_iic_addr[4] = {0x60, 0x62, 0x64, 0x66};
101 struct i2c_client* nvp6158_client;
102
103 /*******************************************************************************
104 * Description : Get rev ID
105 * Argurments : dec(slave address)
106 * Return value : rev ID
107 * Modify :
108 * warning :
109 *******************************************************************************/
nvp6158_check_rev(unsigned int dec)110 static int nvp6158_check_rev(unsigned int dec)
111 {
112 int ret;
113 gpio_i2c_write(dec, 0xFF, 0x00);
114 ret = gpio_i2c_read(dec, 0xf5);
115 return ret;
116 }
117
118 /*******************************************************************************
119 * Description : Get Device ID
120 * Argurments : dec(slave address)
121 * Return value : Device ID
122 * Modify :
123 * warning :
124 *******************************************************************************/
nvp6158_check_id(unsigned int dec)125 static int nvp6158_check_id(unsigned int dec)
126 {
127 int ret;
128 gpio_i2c_write(dec, 0xFF, 0x00);
129 ret = gpio_i2c_read(dec, 0xf4);
130 return ret;
131 }
132
133 /*******************************************************************************
134 * Description : Check decoder count
135 * Argurments : void
136 * Return value : (total chip count - 1) or -1(not found any chip)
137 * Modify :
138 * warning :
139 *******************************************************************************/
nvp6158_check_decoder_count(void)140 static int nvp6158_check_decoder_count(void)
141 {
142 int chip;
143 int ret = -1;
144
145 /* check Device ID of maxium 4chip on the slave address,
146 * manage slave address. chip count. */
147 for(chip = 0; chip < 4; chip ++) {
148 nvp6158_chip_id[chip] = nvp6158_check_id(nvp6158_iic_addr[chip]);
149 nvp6158_rev_id[chip] = nvp6158_check_rev(nvp6158_iic_addr[chip]);
150 if( (nvp6158_chip_id[chip] != NVP6158_R0_ID ) && (nvp6158_chip_id[chip] != NVP6158C_R0_ID) &&
151 (nvp6158_chip_id[chip] != NVP6168_R0_ID ) && (nvp6158_chip_id[chip] != NVP6168C_R0_ID)) {
152 printk("[NVP6158_DRV]Device ID Error... 0x%x\n", nvp6158_chip_id[chip]);
153 } else {
154 printk("[NVP6158_DRV]Device (0x%x) ID OK... 0x%x\n", nvp6158_iic_addr[chip], nvp6158_chip_id[chip]);
155 printk("[NVP6158_DRV]Device (0x%x) REV ... 0x%x\n", nvp6158_iic_addr[chip], nvp6158_rev_id[chip]);
156 nvp6158_iic_addr[nvp6158_cnt] = nvp6158_iic_addr[chip];
157 if(nvp6158_cnt<chip)
158 nvp6158_iic_addr[chip] = 0xFF;
159 nvp6158_chip_id[nvp6158_cnt] = nvp6158_chip_id[chip];
160 nvp6158_rev_id[nvp6158_cnt] = nvp6158_rev_id[chip];
161 nvp6158_cnt++;
162 }
163 }
164
165 printk("[NVP6158_DRV]Chip Count = %d\n", nvp6158_cnt);
166 printk("[NVP6158_DRV]Address [0x%x][0x%x][0x%x][0x%x]\n", nvp6158_iic_addr[0],
167 nvp6158_iic_addr[1], nvp6158_iic_addr[2], nvp6158_iic_addr[3]);
168 printk("[NVP6158_DRV]Chip Id [0x%x][0x%x][0x%x][0x%x]\n", nvp6158_chip_id[0],
169 nvp6158_chip_id[1], nvp6158_chip_id[2], nvp6158_chip_id[3]);
170 printk("[NVP6158_DRV]Rev Id [0x%x][0x%x][0x%x][0x%x]\n", nvp6158_rev_id[0],
171 nvp6158_rev_id[1], nvp6158_rev_id[2], nvp6158_rev_id[3]);
172
173 ret = nvp6158_cnt;
174
175 return ret;
176 }
177
178 /*******************************************************************************
179 * Description : Video decoder initial
180 * Argurments : void
181 * Return value : void
182 * Modify :
183 * warning :
184 *******************************************************************************/
nvp6158_video_decoder_init(void)185 static void nvp6158_video_decoder_init(void)
186 {
187 int chip = 0;
188 unsigned char ch = 0;
189 video_input_auto_detect vin_auto_det;
190 #ifdef _NVP6168_USE_MANUAL_MODE_
191 video_input_manual_mode vin_manual_det;
192 #endif
193
194 printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
195 /* initialize common value of AHD */
196 for(chip = 0; chip < nvp6158_cnt; chip++) {
197 nvp6158_common_init(chip);
198 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID || nvp6158_chip_id[chip] == NVP6158_R0_ID) {
199 nvp6158_additional_for3MoverDef(chip);
200 } else {
201 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x01 );
202 gpio_i2c_write(nvp6158_iic_addr[chip], 0x97, 0x00); // CH_RST ON
203 gpio_i2c_write(nvp6158_iic_addr[chip], 0x97, 0x0f); // CH_RST OFF
204 gpio_i2c_write(nvp6158_iic_addr[chip], 0x7a, 0x0f); // Clock Auto ON
205 gpio_i2c_write(nvp6158_iic_addr[chip], 0xca, 0xff); // VCLK_EN, VDO_EN
206
207 for(ch = 0; ch < 4; ch++) {
208 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x05 + ch);
209 gpio_i2c_write(nvp6158_iic_addr[chip], 0x00, 0xd0);
210
211 gpio_i2c_write(nvp6158_iic_addr[chip], 0x05, 0x04);
212 gpio_i2c_write(nvp6158_iic_addr[chip], 0x08, 0x55);
213 gpio_i2c_write(nvp6158_iic_addr[chip], 0x47, 0xEE);
214 gpio_i2c_write(nvp6158_iic_addr[chip], 0x59, 0x00);
215 gpio_i2c_write(nvp6158_iic_addr[chip], 0x76, 0x00);
216 gpio_i2c_write(nvp6158_iic_addr[chip], 0x77, 0x80);
217 gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0x00);
218 gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0x11);
219 gpio_i2c_write(nvp6158_iic_addr[chip], 0xB8, 0xB8); // H_PLL_BYPASS
220 gpio_i2c_write(nvp6158_iic_addr[chip], 0x7B, 0x11); // v_rst_on
221 gpio_i2c_write(nvp6158_iic_addr[chip], 0xb9, 0x72);
222 gpio_i2c_write(nvp6158_iic_addr[chip], 0xB8, 0xB8); // No Video Set
223
224 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x00);
225 gpio_i2c_write(nvp6158_iic_addr[chip], 0x00+ch, 0x10);
226 gpio_i2c_write(nvp6158_iic_addr[chip], 0x22+(ch*0x04), 0x0b);
227 }
228
229 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x13);
230 gpio_i2c_write(nvp6158_iic_addr[chip], 0x12, 0x04);
231 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2E, 0x10);
232 gpio_i2c_write(nvp6158_iic_addr[chip], 0x30, 0x00);
233 gpio_i2c_write(nvp6158_iic_addr[chip], 0x77, 0xff);
234 gpio_i2c_write(nvp6158_iic_addr[chip], 0x3a, 0xff);
235 gpio_i2c_write(nvp6158_iic_addr[chip], 0x3b, 0xff);
236 gpio_i2c_write(nvp6158_iic_addr[chip], 0x3c, 0xff);
237 gpio_i2c_write(nvp6158_iic_addr[chip], 0x3d, 0xff);
238 gpio_i2c_write(nvp6158_iic_addr[chip], 0x3e, 0xff);
239 gpio_i2c_write(nvp6158_iic_addr[chip], 0x3f, 0x0f);
240 gpio_i2c_write(nvp6158_iic_addr[chip], 0x70, 0x00);
241 gpio_i2c_write(nvp6158_iic_addr[chip], 0x72, 0x05);
242 gpio_i2c_write(nvp6158_iic_addr[chip], 0x7A, 0xf0);
243 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x61, 0x03);
244 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x62, 0x00);
245 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x63, 0x03);
246 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x64, 0x00);
247 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x65, 0x03);
248 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x66, 0x00);
249 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x67, 0x03);
250 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x68, 0x00);
251 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x60, 0x0f);
252 // gpio_i2c_write(nvp6158_iic_addr[chip], 0x60, 0x00);
253 gpio_i2c_write(nvp6158_iic_addr[chip], 0x07, 0x47);
254 gpio_i2c_write(nvp6158_iic_addr[chip], 0x59, 0x24);
255
256 /* SAM Range */
257 gpio_i2c_write(nvp6158_iic_addr[chip], 0x74, 0x00);
258 gpio_i2c_write(nvp6158_iic_addr[chip], 0x76, 0x00);
259 gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0x00);
260 gpio_i2c_write(nvp6158_iic_addr[chip], 0x75, 0xff);
261 gpio_i2c_write(nvp6158_iic_addr[chip], 0x77, 0xff);
262 gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0xff);
263
264 gpio_i2c_write(nvp6158_iic_addr[chip], 0x01, 0x0c);
265 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2f, 0xc8);
266
267 // EQ Stage Get
268 gpio_i2c_write(nvp6158_iic_addr[chip], 0x73, 0x23);
269
270 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x09);
271 gpio_i2c_write(nvp6158_iic_addr[chip], 0x96, 0x03);
272 gpio_i2c_write(nvp6158_iic_addr[chip], 0xB6, 0x03);
273 gpio_i2c_write(nvp6158_iic_addr[chip], 0xD6, 0x03);
274 gpio_i2c_write(nvp6158_iic_addr[chip], 0xF6, 0x03);
275
276 /********************************************************
277 * Audio Default Setting
278 ********************************************************/
279 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x01);
280 gpio_i2c_write(nvp6158_iic_addr[chip], 0x05, 0x09);
281 gpio_i2c_write(nvp6158_iic_addr[chip], 0x58, 0x02);
282 gpio_i2c_write(nvp6158_iic_addr[chip], 0x59, 0x00);
283
284 }
285 }
286
287 for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
288 nvp6158_det_mode[ch] = NVP6158_DET_MODE_AUTO;
289 vin_auto_det.ch = ch % 4;
290 vin_auto_det.devnum = ch / 4;
291 #ifdef _NVP6168_USE_MANUAL_MODE_
292 vin_manual_det.ch = ch % 4;
293 vin_manual_det.dev_num = ch / 4;
294 #endif
295 if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID) {
296 nvp6158_video_input_auto_detect_set(&vin_auto_det);
297 nvp6158_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
298 } else {
299 nvp6168_video_input_auto_detect_set(&vin_auto_det);
300 #ifdef _NVP6168_USE_MANUAL_MODE_
301 nvp6168_video_input_manual_mode_set(&vin_manual_det);
302 #endif
303 nvp6168_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
304 }
305 }
306
307 for(chip = 0; chip < nvp6158_cnt; chip++) {
308 if(nvp6158_chip_id[chip] == NVP6158_R0_ID || nvp6158_chip_id[chip] == NVP6168_R0_ID) {
309 //set nvp6158 output mode of 4port, 0~3 port is available
310 nvp6158_set_portmode(chip, 0, NVP6158_OUTMODE_1MUX_FHD, 0);
311 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 1);
312 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 2);
313 nvp6158_set_portmode(chip, 3, NVP6158_OUTMODE_1MUX_FHD, 3);
314 } else {//if(nvp6158_chip_id[chip] == NVP6158C_R0_ID)
315 //set nvp6158C output mode of 2port, 1/2 port is available
316 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_FHD, 0);
317 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_FHD, 1);
318 }
319 }
320
321 }
322
323
nvp6158_open(struct inode * inode,struct file * file)324 int nvp6158_open(struct inode * inode, struct file * file)
325 {
326 printk("[DRV] Nvp6158 Driver Open\n");
327 printk("[DRV] Nvp6158 Driver Ver::%s\n", NVP6158_DRIVER_VER);
328 return 0;
329 }
330
nvp6158_close(struct inode * inode,struct file * file)331 int nvp6158_close(struct inode * inode, struct file * file)
332 {
333 printk("[DRV] Nvp6158 Driver Close\n");
334 return 0;
335 }
336
337 unsigned int nvp6158_g_vloss=0xFFFF;
338
nvp6158_native_ioctl(struct file * file,unsigned int cmd,unsigned long arg)339 long nvp6158_native_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
340 {
341 unsigned int __user *argp = (unsigned int __user *)arg;
342 int cpy2usr_ret;
343 unsigned char i;
344 //unsigned char oCableDistance = 0;
345 video_equalizer_info_s s_eq_dist;
346 nvp6158_opt_mode optmode;
347 //nvp6158_video_mode vmode;
348 nvp6158_chn_mode schnmode;
349 nvp6158_video_adjust v_adj;
350 NVP6158_INFORMATION_S vfmt;
351 nvp6158_coax_str coax_val;
352 nvp6158_input_videofmt_ch vfmt_ch;
353 nvp6124_i2c_mode i2c;
354 FIRMWARE_UP_FILE_INFO coax_fw_val;
355 motion_mode motion_set;
356 //int ret=0;
357
358
359 /* you must skip other command to improve speed of f/w update
360 * when you are updating cam's f/w up. we need to review and test */
361 //if( acp_dvr_checkFWUpdateStatus( cmd ) == -1 )
362 //{
363 //printk(">>>>> DRV[%s:%d] Now cam f/w update mode. so Skip other command.\n", __func__, __LINE__ );
364 //return 0;
365 //}
366 down(&nvp6158_lock);
367 switch (cmd) {
368 case IOC_VDEC_SET_I2C : // nextchip demoboard test
369 if (copy_from_user(&i2c, argp, sizeof(nvp6124_i2c_mode))) {
370 up(&nvp6158_lock);
371 return -1;
372 }
373
374 if(i2c.flag == 0) {// read
375 gpio_i2c_write(i2c.slaveaddr, 0xFF, i2c.bank);
376 i2c.data = gpio_i2c_read(i2c.slaveaddr, i2c.address);
377 } else {//write
378 gpio_i2c_write(i2c.slaveaddr, 0xFF, i2c.bank);
379 gpio_i2c_write(i2c.slaveaddr, i2c.address, i2c.data);
380 }
381 if(copy_to_user(argp, &i2c, sizeof(nvp6124_i2c_mode)))
382 printk("IOC_VDEC_I2C error\n");
383 break;
384 case IOC_VDEC_GET_VIDEO_LOSS: // Not use
385 //nvp6158_g_vloss = nvp6158_getvideoloss();
386 if(copy_to_user(argp, &nvp6158_g_vloss, sizeof(unsigned int)))
387 printk("IOC_VDEC_GET_VIDEO_LOSS error\n");
388 break;
389 case IOC_VDEC_GET_EQ_DIST:
390 if (copy_from_user(&s_eq_dist, argp, sizeof(video_equalizer_info_s))) {
391 up(&nvp6158_lock);
392 return -1;
393 }
394
395 s_eq_dist.distance = nvp6158_get_eq_dist(&s_eq_dist);
396 if(copy_to_user(argp, &s_eq_dist, sizeof(video_equalizer_info_s)))
397 printk("IOC_VDEC_GET_EQ_DIST error\n");
398 break;
399 case IOC_VDEC_SET_EQUALIZER:
400 if (copy_from_user(&s_eq_dist, argp, sizeof(video_equalizer_info_s))) {
401 up(&nvp6158_lock);
402 return -1;
403 }
404 if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
405 nvp6158_set_equalizer(&s_eq_dist);
406 else
407 nvp6168_set_equalizer(&s_eq_dist);
408 break;
409 case IOC_VDEC_GET_DRIVERVER:
410 if(copy_to_user(argp, &NVP6158_DRIVER_VER, sizeof(NVP6158_DRIVER_VER)))
411 printk("IOC_VDEC_GET_DRIVERVER error\n");
412 break;
413 case IOC_VDEC_ACP_WRITE:
414 /*if (copy_from_user(&ispdata, argp, sizeof(nvp6158_acp_rw_data)))
415 return -1;
416 if(ispdata.opt == 0)
417 acp_isp_write(ispdata.ch, ispdata.addr, ispdata.data);
418 else
419 {
420 ispdata.data = acp_isp_read(ispdata.ch, ispdata.addr);
421 if(copy_to_user(argp, &ispdata, sizeof(nvp6158_acp_rw_data)))
422 printk("IOC_VDEC_ACP_WRITE error\n");
423 }*/
424 break;
425 case IOC_VDEC_ACP_WRITE_EXTENTION:
426
427 break;
428 case IOC_VDEC_PTZ_ACP_READ:
429 //if (copy_from_user(&vfmt, argp, sizeof(nvp6158_input_videofmt)))
430 // return -1;
431 //for(i=0;i<(4*nvp6158_cnt);i++)
432 //{
433 // if(1)
434 // {
435 /* read A-CP */
436 //if(((nvp6158_g_vloss>>i)&0x01) == 0x00)
437 // acp_read(&vfmt, i);
438 // }
439 //}
440 //if(copy_to_user(argp, &vfmt, sizeof(nvp6158_input_videofmt)))
441 // printk("IOC_VDEC_PTZ_ACP_READ error\n");
442 break;
443 case IOC_VDEC_PTZ_ACP_READ_EACH_CH:
444 if (copy_from_user(&vfmt_ch, argp, sizeof(nvp6158_input_videofmt_ch))) {
445 up(&nvp6158_lock);
446 return -1;
447 }
448 /* read A-CP */
449 if(((nvp6158_g_vloss>>vfmt_ch.ch) & 0x01) == 0x00) {
450 //acp_read(&vfmt_ch.vfmt, vfmt_ch.ch);
451 }
452
453 if(copy_to_user(argp, &vfmt_ch, sizeof(nvp6158_input_videofmt_ch)))
454 printk("IOC_VDEC_PTZ_ACP_READ_EACH_CH error\n");
455 break;
456 case IOC_VDEC_GET_INPUT_VIDEO_FMT:
457 if (copy_from_user(&vfmt, argp, sizeof(NVP6158_INFORMATION_S))) {
458 up(&nvp6158_lock);
459 return -1;
460 }
461 if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
462 nvp6158_video_fmt_det(vfmt.ch, &vfmt);
463 else
464 nvp6168_video_fmt_det(vfmt.ch, &vfmt);
465 if(copy_to_user(argp, &vfmt, sizeof(NVP6158_INFORMATION_S)))
466 printk("IOC_VDEC_GET_INPUT_VIDEO_FMT error\n");
467 break;
468 case IOC_VDEC_SET_CHDETMODE:
469 if (copy_from_user(&nvp6158_det_mode, argp, sizeof(unsigned char) * 16)) {
470 up(&nvp6158_lock);
471 return -1;
472 }
473 for(i = 0; i<(nvp6158_cnt * 4); i++) {
474 printk("IOC_VDEC_SET_CHNMODE nvp6158_det_mode[%d]==%d\n",
475 i, nvp6158_det_mode[i]);
476 if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
477 nvp6158_set_chnmode(i, NC_VIVO_CH_FORMATDEF_UNKNOWN);
478 else
479 nvp6168_set_chnmode(i, NC_VIVO_CH_FORMATDEF_UNKNOWN);
480 }
481 break;
482 case IOC_VDEC_SET_CHNMODE:
483 if (copy_from_user(&schnmode, argp, sizeof(nvp6158_chn_mode))) {
484 up(&nvp6158_lock);
485 return -1;
486 }
487 if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID) {
488 if(0 == nvp6158_set_chnmode(schnmode.ch, schnmode.chmode))
489 printk("IOC_VDEC_SET_CHNMODE OK\n");
490 } else {
491 if(0 == nvp6168_set_chnmode(schnmode.ch, schnmode.chmode))
492 printk("IOC_VDEC_SET_CHNMODE OK\n");
493 }
494 break;
495 case IOC_VDEC_SET_OUTPORTMODE:
496 if(copy_from_user(&optmode, argp, sizeof(nvp6158_opt_mode))) {
497 up(&nvp6158_lock);
498 return -1;
499 }
500 nvp6158_set_portmode(optmode.chipsel, optmode.portsel, optmode.portmode, optmode.chid);
501 break;
502 case IOC_VDEC_SET_BRIGHTNESS:
503 if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
504 up(&nvp6158_lock);
505 return -1;
506 }
507 //nvp6158_video_set_brightness(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
508 break;
509 case IOC_VDEC_SET_CONTRAST:
510 if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
511 up(&nvp6158_lock);
512 return -1;
513 }
514 //nvp6158_video_set_contrast(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
515 break;
516 case IOC_VDEC_SET_HUE:
517 if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
518 up(&nvp6158_lock);
519 return -1;
520 }
521 //nvp6158_video_set_hue(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
522 break;
523 case IOC_VDEC_SET_SATURATION:
524 if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
525 up(&nvp6158_lock);
526 return -1;
527 }
528 //nvp6158_video_set_saturation(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
529 break;
530 case IOC_VDEC_SET_SHARPNESS:
531 if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
532 up(&nvp6158_lock);
533 return -1;
534 }
535 nvp6158_video_set_sharpness(v_adj.ch, v_adj.value);
536 break;
537 /*----------------------- Coaxial Protocol ----------------------*/
538 case IOC_VDEC_COAX_TX_INIT: //SK_CHANGE 170703
539 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
540 printk("IOC_VDEC_COAX_TX_INIT error\n");
541 nvp6158_coax_tx_init(&coax_val);
542 break;
543 case IOC_VDEC_COAX_TX_16BIT_INIT: //SK_CHANGE 170703
544 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
545 printk("IOC_VDEC_COAX_TX_INIT error\n");
546 nvp6158_coax_tx_16bit_init(&coax_val);
547 break;
548 case IOC_VDEC_COAX_TX_CMD_SEND: //SK_CHANGE 170703
549 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
550 printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
551 nvp6158_coax_tx_cmd_send(&coax_val);
552 break;
553 case IOC_VDEC_COAX_TX_16BIT_CMD_SEND: //SK_CHANGE 170703
554 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
555 printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
556 nvp6158_coax_tx_16bit_cmd_send(&coax_val);
557 break;
558 case IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND: //SK_CHANGE 170703
559 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
560 printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
561 nvp6158_coax_tx_cvi_new_cmd_send(&coax_val);
562 break;
563 case IOC_VDEC_COAX_RX_INIT:
564 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
565 printk(" IOC_VDEC_COAX_RX_INIT error\n");
566 nvp6158_coax_rx_init(&coax_val);
567 break;
568 case IOC_VDEC_COAX_RX_DATA_READ:
569 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
570 printk(" IOC_VDEC_COAX_RX_DATA_READ error\n");
571 nvp6158_coax_rx_data_get(&coax_val);
572 cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(nvp6158_coax_str));
573 break;
574 case IOC_VDEC_COAX_RX_BUF_CLEAR:
575 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
576 printk(" IOC_VDEC_COAX_RX_BUF_CLEAR error\n");
577 nvp6158_coax_rx_buffer_clear(&coax_val);
578 break;
579 case IOC_VDEC_COAX_RX_DEINIT:
580 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
581 printk("IOC_VDEC_COAX_RX_DEINIT error\n");
582 nvp6158_coax_rx_deinit(&coax_val);
583 break;
584 /*=============== Coaxial Protocol A-CP Option ===============*/
585 case IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET:
586 if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
587 printk(" IOC_VDEC_COAX_SHOT_SET error\n");
588 nvp6158_coax_option_rt_nrt_mode_change_set(&coax_val);
589 cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(nvp6158_coax_str));
590 break;
591 /*=========== Coaxial Protocol Firmware Update ==============*/
592 case IOC_VDEC_COAX_FW_ACP_HEADER_GET:
593 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
594 printk("IOC_VDEC_COAX_FW_READY_CMD_SET error\n");
595 nvp6158_coax_fw_ready_header_check_from_isp_recv(&coax_fw_val);
596 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
597 break;
598 case IOC_VDEC_COAX_FW_READY_CMD_SET:
599 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
600 printk("IOC_VDEC_COAX_FW_READY_CMD_SET error\n");
601 nvp6158_coax_fw_ready_cmd_to_isp_send(&coax_fw_val);
602 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
603 break;
604 case IOC_VDEC_COAX_FW_READY_ACK_GET:
605 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
606 printk("IOC_VDEC_COAX_FW_READY_ISP_STATUS_GET error\n");
607 nvp6158_coax_fw_ready_cmd_ack_from_isp_recv(&coax_fw_val);
608 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
609 break;
610 case IOC_VDEC_COAX_FW_START_CMD_SET:
611 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
612 printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
613 nvp6158_coax_fw_start_cmd_to_isp_send(&coax_fw_val);
614 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
615 break;
616 case IOC_VDEC_COAX_FW_START_ACK_GET:
617 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
618 printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
619 nvp6158_coax_fw_start_cmd_ack_from_isp_recv(&coax_fw_val);
620 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
621 break;
622 case IOC_VDEC_COAX_FW_SEND_DATA_SET:
623 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
624 printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
625 nvp6158_coax_fw_one_packet_data_to_isp_send(&coax_fw_val);
626 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
627 break;
628 case IOC_VDEC_COAX_FW_SEND_ACK_GET:
629 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
630 printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
631 nvp6158_coax_fw_one_packet_data_ack_from_isp_recv(&coax_fw_val);
632 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
633 break;
634 case IOC_VDEC_COAX_FW_END_CMD_SET:
635 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
636 printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
637 nvp6158_coax_fw_end_cmd_to_isp_send(&coax_fw_val);
638 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
639 break;
640 case IOC_VDEC_COAX_FW_END_ACK_GET:
641 if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
642 printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
643 nvp6158_coax_fw_end_cmd_ack_from_isp_recv(&coax_fw_val);
644 cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
645 break;
646 /*=========== Coaxial Protocol Firmware Update END ==============*/
647 /*----------------------- MOTION ----------------------*/
648 case IOC_VDEC_MOTION_DETECTION_GET :
649 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
650 printk("IOC_VDEC_MOTION_SET error\n");
651 nvp6158_motion_detection_get(&motion_set);
652 cpy2usr_ret = copy_to_user(argp, &motion_set, sizeof(motion_mode));
653 break;
654 case IOC_VDEC_MOTION_SET :
655 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
656 printk("IOC_VDEC_MOTION_SET error\n");
657 nvp6158_motion_onoff_set(&motion_set);
658 break;
659 case IOC_VDEC_MOTION_PIXEL_SET :
660 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
661 printk("IOC_VDEC_MOTION_Pixel_SET error\n");
662 nvp6158_motion_pixel_onoff_set(&motion_set);
663 break;
664 case IOC_VDEC_MOTION_PIXEL_GET :
665 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
666 printk("IOC_VDEC_MOTION_Pixel_SET error\n");
667 nvp6158_motion_pixel_onoff_get(&motion_set);
668 cpy2usr_ret = copy_to_user(argp, &motion_set, sizeof(motion_mode));
669 break;
670 case IOC_VDEC_MOTION_ALL_PIXEL_SET :
671 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
672 printk("IOC_VDEC_MOTION_Pixel_SET error\n");
673 nvp6158_motion_pixel_all_onoff_set(&motion_set);
674 break;
675 case IOC_VDEC_MOTION_TSEN_SET :
676 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
677 printk("IOC_VDEC_MOTION_TSEN_SET error\n");
678 nvp6158_motion_tsen_set(&motion_set);
679 break;
680 case IOC_VDEC_MOTION_PSEN_SET :
681 if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
682 printk("IOC_VDEC_MOTION_PSEN_SET error\n");
683 nvp6158_motion_psen_set(&motion_set);
684 break;
685 default:
686 //printk("drv:invalid nc decoder ioctl cmd[%x]\n", cmd);
687 break;
688 }
689 up(&nvp6158_lock);
690 return 0;
691 }
692
693 #ifdef TEST
nvp6158_set_bt656_601_mode(void)694 void nvp6158_set_bt656_601_mode(void)
695 {
696 unsigned char ch = 0;
697 int chip = 0;
698
699 printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
700 for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
701 nvp6158_set_chnmode(ch, AHD20_1080P_30P);
702 }
703
704 for(chip = 0; chip < nvp6158_cnt; chip++) {
705 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
706 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
707 }
708 //VDO1 diabled
709 gpio_i2c_write(0x60, 0xFF, 0x01);
710 gpio_i2c_write(0x60, 0xCA, 0x64);
711 #ifdef BT601
712 //BT601 test
713 gpio_i2c_write(0x60, 0xFF, 0x01);
714 gpio_i2c_write(0x60, 0xA8, 0x80); //BT601 out
715 gpio_i2c_write(0x60, 0xAB, 0x80); //BT601 out
716 gpio_i2c_write(0x60, 0xBD, 0x00); //BT601 VSYNC HSYNC
717 gpio_i2c_write(0x60, 0xBE, 0x00); //BT601 VSYNC HSYNC
718 gpio_i2c_write(0x60, 0xA9, 0x10); //CH1 Signal out for BT601 (MPP1 = V_BLK1, MPP2=H_BLK1)
719 gpio_i2c_write(0x60, 0xAA, 0x20); //CH2 Signal out for BT601 (MPP3 = V_BLK1, MPP4=H_BLK1)
720 #endif
721 }
722
nvp6158_set_bt1120_720P_mode(void)723 void nvp6158_set_bt1120_720P_mode(void)
724 {
725 unsigned char ch = 0;
726 int chip = 0;
727
728 printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
729 for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
730 nvp6158_set_chnmode(ch, AHD20_720P_30P);
731 }
732
733 for(chip = 0; chip < nvp6158_cnt; chip ++) {
734 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
735 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
736 }
737 }
738
nvp6158_set_bt1120_1080P_mode(void)739 void nvp6158_set_bt1120_1080P_mode(void)
740 {
741 unsigned char ch = 0;
742 int chip = 0;
743
744 printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
745 for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
746 nvp6158_set_chnmode(ch, AHD20_1080P_30P);
747 }
748
749 for(chip = 0; chip < nvp6158_cnt; chip++) {
750 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
751 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
752 }
753 }
754 #endif
755
nvp6158_start(video_init_all * video_init,bool dual_edge)756 void nvp6158_start(video_init_all *video_init, bool dual_edge)
757 {
758 unsigned char ch = 0;
759 int chip = 0;
760 NC_VIVO_CH_FORMATDEF fmt_idx;
761 NVP6158_DVP_MODE mode;
762
763 fmt_idx = video_init->ch_param[0].format;
764 mode = video_init->mode;
765 down(&nvp6158_lock);
766 nvp6158_video_decoder_init();
767 /* initialize Audio
768 * recmaster, pbmaster, ch_num, samplerate, bits */
769 if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
770 nvp6158_audio_init(1,0,16,0,0);
771 else
772 nvp6168_audio_init(1,0,16,0,0);
773
774 switch (fmt_idx) {
775 /* normal output */
776 case AHD20_720P_25P:
777 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
778 nvp6158_set_chnmode(ch, AHD20_720P_25P);
779 break;
780 case AHD20_720P_30P:
781 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
782 nvp6158_set_chnmode(ch, AHD20_720P_30P);
783 break;
784 case AHD20_1080P_25P:
785 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
786 nvp6158_set_chnmode(ch, AHD20_1080P_25P);
787 break;
788 case AHD20_1080P_30P:
789 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
790 nvp6158_set_chnmode(ch, AHD20_1080P_30P);
791 break;
792 case AHD30_3M_18P:
793 for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
794 if (dual_edge)
795 nvp6158_set_chnmode(ch, AHD30_3M_30P);
796 else
797 nvp6158_set_chnmode(ch, AHD30_3M_18P);
798
799 }
800 break;
801 case AHD30_4M_15P:
802 for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
803 if (dual_edge)
804 nvp6158_set_chnmode(ch, AHD30_4M_30P);
805 else
806 nvp6158_set_chnmode(ch, AHD30_4M_15P);
807 }
808 break;
809 case AHD30_5M_12_5P:
810 for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
811 if (dual_edge)
812 nvp6158_set_chnmode(ch, AHD30_5M_20P);
813 else
814 nvp6158_set_chnmode(ch, AHD30_5M_12_5P);
815 }
816 break;
817 case AHD30_8M_7_5P:
818 for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
819 if (dual_edge)
820 nvp6158_set_chnmode(ch, AHD30_8M_15P);
821 else
822 nvp6158_set_chnmode(ch, AHD30_8M_7_5P);
823 }
824 break;
825
826 /* test output */
827 case AHD20_SD_SH720_NT:
828 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
829 nvp6158_set_chnmode(ch, AHD20_SD_SH720_NT); /* 720*480i*/
830 break;
831 case AHD20_SD_SH720_PAL:
832 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
833 nvp6158_set_chnmode(ch, AHD20_SD_SH720_PAL); /* 720*576i*/
834 break;
835 case AHD20_SD_H960_PAL:
836 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
837 nvp6158_set_chnmode(ch, AHD20_SD_H960_PAL); /* 960*576i*/
838 break;
839 case AHD20_SD_H960_EX_PAL:
840 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
841 nvp6158_set_chnmode(ch, AHD20_SD_H960_EX_PAL); /*1920*576i*/
842 break;
843 default:
844 for (ch = 0; ch < nvp6158_cnt * 4; ch++)
845 nvp6158_set_chnmode(ch, AHD20_1080P_30P);
846 break;
847 }
848
849 nvp6158_set_colorpattern();
850 //nvp6158_set_colorpattern2();
851 //nvp6158_set_colorpattern3();
852
853 switch (mode) {
854 /* normal output */
855 case BT656_1MUX:
856 if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
857 for (chip = 0; chip < nvp6158_cnt; chip++) {
858 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
859 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
860 }
861 } else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
862 for (chip = 0; chip < nvp6158_cnt; chip++) {
863 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_HD, 0);
864 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_HD, 1);
865 }
866 } else if ((fmt_idx == AHD30_3M_18P) || (fmt_idx == AHD30_4M_15P) ||
867 (fmt_idx == AHD30_5M_12_5P) || (fmt_idx == AHD30_8M_7_5P)) {
868 for (chip = 0; chip < nvp6158_cnt; chip++) {
869 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
870 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
871 }
872 } else if ((fmt_idx == AHD20_1080P_50P) || (fmt_idx == AHD20_1080P_60P) ||
873 (fmt_idx == AHD30_3M_30P) || (fmt_idx == AHD30_4M_30P) ||
874 (fmt_idx == AHD30_3M_25P) || (fmt_idx == AHD30_4M_25P) ||
875 (fmt_idx == AHD30_5M_20P) || (fmt_idx == AHD30_8M_15P)) {
876 for (chip = 0; chip < nvp6158_cnt; chip++) {
877 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
878 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
879 }
880 }
881 //standard sync head
882 gpio_i2c_write(0x60, 0xFF, 0x00);
883 gpio_i2c_write(0x60, 0x54, 0x00);
884 //VDO2/VDO1 enabled VCLK_1/2_EN
885 gpio_i2c_write(0x60, 0xFF, 0x01);
886 gpio_i2c_write(0x60, 0xCA, 0x66);
887 break;
888 case BT656_2MUX:
889 if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
890 for (chip = 0; chip < nvp6158_cnt; chip++) {
891 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_FHD, 0);
892 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_FHD, 0);
893 }
894 } else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
895 for (chip = 0; chip < nvp6158_cnt; chip++) {
896 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_HD, 0);
897 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_HD, 0);
898 }
899 }
900 //standard sync head
901 gpio_i2c_write(0x60, 0xFF, 0x00);
902 gpio_i2c_write(0x60, 0x54, 0x00);
903 //VDO2 enabled VDO1 disabled VCLK_1_EN
904 gpio_i2c_write(0x60, 0xFF, 0x01);
905 gpio_i2c_write(0x60, 0xCA, 0x66);
906 break;
907 case BT1120_1MUX:
908 if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
909 for (chip = 0; chip < nvp6158_cnt; chip++) {
910 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
911 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
912 }
913 } else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
914 for (chip = 0; chip < nvp6158_cnt; chip++) {
915 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
916 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
917 }
918 }
919 //VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
920 gpio_i2c_write(0x60, 0xFF, 0x01);
921 gpio_i2c_write(0x60, 0xCA, 0x66);
922 break;
923 case BT1120_2MUX:
924 if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
925 for (chip = 0; chip < nvp6158_cnt; chip++) {
926 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_BT1120S_1080P, 0);
927 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_BT1120S_1080P, 1);
928 }
929 } else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
930 for (chip = 0; chip < nvp6158_cnt; chip++) {
931 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_BT1120S_720P, 0);
932 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_BT1120S_720P, 1);
933 }
934 }
935 //VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
936 gpio_i2c_write(0x60, 0xFF, 0x01);
937 gpio_i2c_write(0x60, 0xCA, 0x66);
938 break;
939 case BT1120_4MUX:
940 if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
941 for (chip = 0; chip < nvp6158_cnt; chip++) {
942 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_4MUX_BT1120S_1080P, 0);
943 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_4MUX_BT1120S_1080P, 1);
944 }
945 } else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
946 for (chip = 0; chip < nvp6158_cnt; chip++) {
947 if (dual_edge) {
948 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_4MUX_BT1120S_DDR, 0);
949 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_4MUX_BT1120S_DDR, 1);
950 } else {
951 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_4MUX_BT1120S, 0);
952 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_4MUX_BT1120S, 1);
953 }
954 }
955 }
956 //VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
957 gpio_i2c_write(0x60, 0xFF, 0x01);
958 gpio_i2c_write(0x60, 0xCA, 0x66);
959 break;
960 /* test output */
961 case BT656I_TEST_MODES:
962 if (fmt_idx == AHD20_SD_H960_EX_PAL) {
963 for (chip = 0; chip < nvp6158_cnt; chip++) {
964 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_HD, 0);
965 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_HD, 1);
966 }
967 } else {
968 for (chip = 0; chip < nvp6158_cnt; chip++) {
969 nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_SD, 0);
970 nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_SD, 1);
971 }
972 }
973 //VDO2 enabled VDO1 disabled VCLK_1_EN
974 gpio_i2c_write(0x60, 0xFF, 0x01);
975 //gpio_i2c_write(0x60, 0xCA, 0x64);
976 //VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
977 gpio_i2c_write(0x60, 0xCA, 0x66);
978 break;
979 default:
980 printk("mode %d not supported yet\n", mode);
981 break;
982 }
983 up(&nvp6158_lock);
984 }
985
nvp6158_stop(void)986 void nvp6158_stop(void)
987 {
988 unsigned char ch = 0;
989
990 down(&nvp6158_lock);
991 //VDO_1/2 disabled, VCLK_x disabled
992 gpio_i2c_write(0x60, 0xFF, 0x01);
993 gpio_i2c_write(0x60, 0xCA, 0x00);
994
995 for(ch = 0; ch < 4;ch++) {
996 nvp6158_channel_reset(ch);
997 }
998 up(&nvp6158_lock);
999 }
1000
1001 /*******************************************************************************
1002 * Description : i2c client initial
1003 * Argurments : int
1004 * Return value : 0
1005 * Modify :
1006 * warning :
1007 *******************************************************************************/
nvp6158_i2c_client_init(int i2c_bus)1008 static int nvp6158_i2c_client_init(int i2c_bus)
1009 {
1010 struct i2c_adapter* i2c_adap;
1011
1012 printk("[DRV] I2C Client Init \n");
1013 i2c_adap = i2c_get_adapter(i2c_bus);
1014
1015 nvp6158_client = i2c_new_client_device(i2c_adap, &nvp6158_hi_info);
1016 i2c_put_adapter(i2c_adap);
1017
1018 return 0;
1019 }
1020
1021 /*******************************************************************************
1022 * Description : i2c client release
1023 * Argurments : void
1024 * Return value : void
1025 * Modify :
1026 * warning :
1027 *******************************************************************************/
nvp6158_i2c_client_exit(void)1028 void nvp6158_i2c_client_exit(void)
1029 {
1030 i2c_unregister_device(nvp6158_client);
1031 }
1032
nvp6158_init(int i2c_bus)1033 int nvp6158_init(int i2c_bus)
1034 {
1035 int ret = 0;
1036 #ifdef FMT_SETTING_SAMPLE
1037 int dev_num = 0;
1038 #endif
1039
1040 if (nvp6158_init_state)
1041 return 0;
1042
1043 ret = nvp6158_i2c_client_init(i2c_bus);
1044 if (ret) {
1045 printk(KERN_ERR "ERROR: could not find nvp6158\n");
1046 return ret;
1047 }
1048
1049 /* decoder count function */
1050 ret = nvp6158_check_decoder_count();
1051 if (ret <= 0) {
1052 printk(KERN_ERR "ERROR: could not find nvp6158 devices:%#x\n", ret);
1053 nvp6158_i2c_client_exit();
1054 return -ENODEV;
1055 }
1056
1057 /* initialize semaphore */
1058 sema_init(&nvp6158_lock, 1);
1059 nvp6158_init_state = true;
1060
1061 return 0;
1062 }
1063
nvp6158_exit(void)1064 void nvp6158_exit(void)
1065 {
1066 nvp6158_i2c_client_exit();
1067 nvp6158_init_state = false;
1068 }
1069
1070 /*******************************************************************************
1071 * End of file
1072 *******************************************************************************/
1073
1074