1 // SPDX-License-Identifier: GPL-2.0
2 /********************************************************************************
3 *
4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
5 * Module : The decoder's video format module
6 * Description : Video format
7 * Author :
8 * Date :
9 * Version : Version 2.0
10 *
11 ********************************************************************************
12 * History :
13 *
14 *
15 ********************************************************************************/
16 #include <linux/string.h>
17 #include <linux/delay.h>
18
19 //#include "eq_common.h"
20 #include "nvp6158_video.h"
21 #include "nvp6158_video_auto_detect.h"
22 #include "nvp6158_coax_protocol.h"
23 //#include "acp.h"
24 #include "nvp6158_video_eq.h"
25 #define _ENABLE_DET_DEBOUNCE_
26 #define AHD_720P30_Detect_Count 1 //1:1time 0:2time check //2020-12-16
27 /*******************************************************************************
28 * extern variable
29 *******************************************************************************/
30 extern unsigned int nvp6158_cnt;
31 extern int nvp6158_chip_id[4];
32 extern unsigned int nvp6158_g_vloss;
33 extern unsigned int nvp6158_iic_addr[4];
34 unsigned char nvp6158_g_ch_video_fmt[16] = {[0 ... 15] = 0xFF}; // save user's video format
35 extern unsigned char nvp6158_det_mode[16];
36 extern unsigned int nvp6158_gCoaxFirmUpdateFlag[16];
37
38 unsigned char nvp6158_motion_sens_tbl[8] = {0xe0, 0xc8, 0xa0, 0x98, 0x78, 0x68, 0x50, 0x48};
39 unsigned char nvp6158_ch_mode_status[16] = {[0 ... 15] = 0xff};
40 unsigned char nvp6158_ch_vfmt_status[16] = {[0 ... 15] = 0xff};
41 #ifdef _ENABLE_DET_DEBOUNCE_
42 NVP6158_INFORMATION_S nvp6158_s_raptor3_vfmts;
43 #endif
44
nvp6158_dump_reg(unsigned char ch,unsigned char bank)45 void nvp6158_dump_reg( unsigned char ch, unsigned char bank )
46 {
47 int tmp = 0;
48 int i = 0, j= 0;
49
50 printk("***************IIC ADDR 0x%02x - CH[%02d] *****************\r\n",
51 nvp6158_iic_addr[ch/4], ch );
52 printk("***************Chip[0x%02x] Bank[0x%x]*****************\r\n",
53 nvp6158_iic_addr[ch/4], bank );
54 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, bank );
55 for (i = 0; i <= 0xF; i++) {
56 if(i == 0) {
57 printk("0x%02x ",i);
58 } else if (i==0xF) {
59 printk("0x%02x\r\n",i);
60 } else {
61 printk("0x%02x ",i);
62 }
63 }
64 for (i = 0; i <= 0xF; i++) {
65 for(j = 0; j <= 0xF; j++) {
66 tmp = gpio_i2c_read(nvp6158_iic_addr[ch / 4], (i << 4) | j);
67 if (j == 0) {
68 printk("0x%02x-0x%02x ",(i << 4) | j, tmp);
69 } else if (j == 0xF) {
70 printk("0x%02x\r\n",tmp);
71 } else {
72 printk("0x%02x ",tmp);
73 }
74 }
75 }
76 }
77
nvp6158_video_get_adcclk(unsigned char ch)78 unsigned char nvp6158_video_get_adcclk(unsigned char ch)
79 {
80 unsigned char adc_value;
81
82 gpio_i2c_write(nvp6158_iic_addr[ch / 4], 0xFF, 0x01);
83 adc_value = gpio_i2c_read(nvp6158_iic_addr[ch / 4], 0x84 + ch % 4);
84 printk(">>>>> DRV[%s:%d] CH:%d, Bank:0x%02x, ADC clock delay:0x%x\n",
85 __func__, __LINE__, ch, nvp6158_iic_addr[ch/4], adc_value );
86 return adc_value;
87 }
88
nvp6158_video_set_adcclk(unsigned char ch,unsigned char value)89 void nvp6158_video_set_adcclk(unsigned char ch, unsigned char value)
90 {
91 gpio_i2c_write(nvp6158_iic_addr[ch / 4], 0xFF, 0x01);
92 gpio_i2c_write(nvp6158_iic_addr[ch / 4], 0x84 + ch % 4, value);
93 printk(">>>>> DRV[%s:%d] CH:%d, Bank:0x%02x, ADC clock delay:0x%x\n",
94 __func__, __LINE__, ch, nvp6158_iic_addr[ch/4], value );
95 }
96
NVP6158_set_afe(unsigned char ch,unsigned char onoff)97 static __maybe_unused void NVP6158_set_afe(unsigned char ch, unsigned char onoff)
98 {
99 unsigned char afe_value;
100 {
101 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
102 afe_value = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x00+ch%4);
103 if(onoff==1)
104 _CLE_BIT(afe_value, 0);
105 else
106 _SET_BIT(afe_value, 0);
107 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x00+ch%4, afe_value);
108 msleep(10);
109 printk("NVP6158_set_afe ch[%d] [%s] done\n", ch, onoff?"ON":"OFF");
110 }
111 }
112
nvp6158_datareverse(unsigned char chip,unsigned char port)113 static __maybe_unused void nvp6158_datareverse(unsigned char chip, unsigned char port)
114 {
115
116 unsigned char tmp;
117 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x01);
118 tmp = gpio_i2c_read(nvp6158_iic_addr[chip], 0xCB);
119 _SET_BIT(tmp, port);
120 gpio_i2c_write(nvp6158_iic_addr[chip], 0xCB, tmp);
121 printk("nvp6158[%d] port[%d] data reversed\n", chip, port);
122 }
123
nvp6158_pll_bypass(unsigned char chip,int flag)124 static __maybe_unused void nvp6158_pll_bypass(unsigned char chip, int flag)
125 {
126 unsigned char val_1x81;
127 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x01);
128 val_1x81 = gpio_i2c_read(nvp6158_iic_addr[chip], 0x81);
129 if(flag == 1) {
130 val_1x81 |= 0x02;
131 } else {
132 val_1x81 &= 0xFD;
133 }
134 gpio_i2c_write(nvp6158_iic_addr[chip], 0x81, val_1x81);
135 }
136
137
nvp6158_system_init(unsigned char chip)138 static void nvp6158_system_init(unsigned char chip)
139 {
140 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x00);
141 gpio_i2c_write(nvp6158_iic_addr[chip], 0x80, 0x0F);
142
143 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x01);
144 gpio_i2c_write(nvp6158_iic_addr[chip], 0x80, 0x40);
145 msleep(30);
146 gpio_i2c_write(nvp6158_iic_addr[chip], 0x80, 0x61);
147 msleep(30);
148 gpio_i2c_write(nvp6158_iic_addr[chip], 0x80, 0x60);
149
150 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x01);
151 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID || nvp6158_chip_id[chip] == NVP6168C_R0_ID)
152 gpio_i2c_write(nvp6158_iic_addr[chip], 0xCA, 0x66); //NVP6158C/6158B ONLY HAS 2 PORTS
153 else
154 gpio_i2c_write(nvp6158_iic_addr[chip], 0xCA, 0xFF); //NVP6158 HAS 4 PORTS
155
156 printk("nvp6158[C]_system_init\n");
157 }
158
159 /*******************************************************************************
160 * Description : Initialize common value of AHD
161 * Argurments : dec(slave address)
162 * Return value : rev ID
163 * Modify :
164 * warning :
165 *******************************************************************************/
nvp6158_common_init(unsigned char chip)166 void nvp6158_common_init(unsigned char chip)
167 {
168 int ch;
169 /* initialize chip */
170 nvp6158_system_init(chip);
171 //VDO_1/2 disabled, VCLK_x disabled
172 gpio_i2c_write(0x60, 0xFF, 0x01);
173 gpio_i2c_write(0x60, 0xCA, 0x00);
174 for(ch = 0; ch < 4; ch++) {
175 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x00);
176 //gpio_i2c_write(nvp6158_iic_addr[chip], 0x00+ch, 0x10);
177 gpio_i2c_write(nvp6158_iic_addr[chip], 0x22+ 4 * ch, 0x0B);
178 gpio_i2c_write(nvp6158_iic_addr[chip], 0x23+ 4 * ch, 0x41);
179
180 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x05 + ch % 4);
181 gpio_i2c_write(nvp6158_iic_addr[chip], 0x00, 0xD0); // Clamp speed
182 gpio_i2c_write(nvp6158_iic_addr[chip], 0xA9, 0x80);
183 gpio_i2c_write(nvp6158_iic_addr[chip], 0x76, 0x00);
184 gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0x00);
185 gpio_i2c_write(nvp6158_iic_addr[chip], 0xD5, 0x80);
186 }
187 }
188
189 #define MAX_DEBOUNCE_CNT 5
nvp6158_AutoDebouceCheck(unsigned char ch,NVP6158_INFORMATION_S * pInformation)190 static int nvp6158_AutoDebouceCheck( unsigned char ch, NVP6158_INFORMATION_S *pInformation )
191 {
192 int i;
193 int ret = 0;
194 //unsigned char oDevNum = 0;
195 unsigned char oDebncIdx = 0;
196 unsigned char oVfc = 0;
197 NC_VIVO_CH_FORMATDEF oFmtB5Def;
198 video_input_vfc sVFC;
199 //decoder_dev_ch_info_s sDevChInfo;
200
201
202 sVFC.ch = ch % 4;
203 sVFC.devnum = ch / 4;
204 nvp6158_video_input_onvideo_check_data(&sVFC);
205
206 oDebncIdx = pInformation->debounceidx[ch];
207 pInformation->debounce[ch][oDebncIdx%MAX_DEBOUNCE_CNT] = sVFC.vfc;
208
209 /* For Debug Ch1 Only */
210 /*
211 if( ch == 0)
212 printk("debunce:0x%02X, debncIdx:%d\n", pInformation->debounce[ch][pInformation->debounceidx[ch]], pInformation->debounceidx[ch]);
213 */
214 pInformation->debounceidx[ch]++;
215 pInformation->debounceidx[ch] = ( (pInformation->debounceidx[ch] % MAX_DEBOUNCE_CNT) == 0 ) ?
216 0 : pInformation->debounceidx[ch];
217
218 oVfc = pInformation->debounce[ch][pInformation->debounceidx[ch]];
219 for( i = 0; i < MAX_DEBOUNCE_CNT; i++ ) {
220 if( oVfc != pInformation->debounce[ch][i]) {
221 break;
222 }
223 }
224 if( i == MAX_DEBOUNCE_CNT ) {
225 oFmtB5Def = NVP6158_NC_VD_AUTO_VFCtoFMTDEF(ch, oVfc);
226 //if( ( oFmtB5Def != AHD30_5M_20P ) && ( oFmtB5Def != pInformation->prevideofmt[ch] ) )
227 if( ( ( oFmtB5Def != AHD30_5M_20P ) && ( oFmtB5Def != CVI_8M_15P ) &&
228 ( oFmtB5Def != CVI_8M_12_5P ) && ( oFmtB5Def != CVI_HD_30P_EX ) &&
229 ( oFmtB5Def != AHD20_1080P_25P ) && ( oFmtB5Def != AHD20_1080P_30P ) &&
230 ( oFmtB5Def != CVI_FHD_25P ) ) && ( oFmtB5Def != pInformation->prevideofmt[ch] ) ) {
231 printk("\n\n\n>>>>>>WATCH OUT<<<<<<ch[%d] oVfc[%2x]oFmtB5Def[%2x] != pInformation->prevideofmt[%2x]\n\n\n",
232 ch, oVfc, oFmtB5Def , pInformation->prevideofmt[ch]);
233 ret = -1;
234 }
235 }
236
237
238 return ret;
239 }
240
nvp6158_channel_reset(unsigned char ch)241 void nvp6158_channel_reset(unsigned char ch)
242 {
243 unsigned char reg_1x97, bank_save;
244 bank_save = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0xFF);
245 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x01);
246 reg_1x97 = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x97);
247 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x97, reg_1x97&(~(1<<(ch%4))));
248 msleep(30);
249 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x97, reg_1x97|0x0F);
250 msleep(30);
251 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, bank_save);
252 printk("CH[%d] channel been resetted\n", ch);
253 }
254
nvp6158_set_colorpattern(void)255 void nvp6158_set_colorpattern(void)
256 {
257 int chip;
258 for(chip = 0; chip < nvp6158_cnt; chip++) {
259 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x00);
260 gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0xaa);
261 gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0xaa);
262 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x05);
263 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
264 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x90);
265 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x06);
266 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
267 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x90);
268 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x07);
269 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
270 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x90);
271 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x08);
272 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
273 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x90);
274 }
275 }
276
nvp6158_set_colorpattern2(void)277 void nvp6158_set_colorpattern2(void)
278 {
279 int chip;
280
281 printk("[NVP6158_VIDEO] %s(%d) \n", __func__, __LINE__);
282 for(chip = 0; chip < nvp6158_cnt; chip++) {
283 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x05);
284 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
285 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
286 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x06);
287 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
288 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
289 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x07);
290 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
291 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
292 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x08);
293 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
294 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
295
296 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x00);
297 /* gpio_i2c_write(nvp6158_iic_addr[0], 0x78, 0x42);//ch1:Blue *//* ch2:Yellow ch3:Green ch4:Red */
298 /* gpio_i2c_write(nvp6158_iic_addr[0], 0x79, 0x76); */
299 gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0xce); /* ch1:Blue ch2:Yellow ch3:Green ch4:Red */
300 gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0xba);
301 }
302 }
303
nvp6158_set_colorpattern3(void)304 void nvp6158_set_colorpattern3(void)
305 {
306 int chip;
307
308 printk("[NVP6158_VIDEO] %s(%d) \n", __func__, __LINE__);
309 for(chip = 0; chip < nvp6158_cnt; chip++) {
310 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x05);
311 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
312 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
313 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x06);
314 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
315 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
316 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x07);
317 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
318 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
319 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x08);
320 gpio_i2c_write(nvp6158_iic_addr[chip], 0x2c, 0x08);
321 gpio_i2c_write(nvp6158_iic_addr[chip], 0x6a, 0x80);
322
323 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x00);
324 /* gpio_i2c_write(nvp6158_iic_addr[0], 0x78, 0x42); //ch1:Green ch2:Green ch3:Green ch4:Green */
325 /* gpio_i2c_write(nvp6158_iic_addr[0], 0x79, 0x76); */
326 gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0x44); /* ch1:Green ch2:Green ch3:Green ch4:Green */
327 gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0x44);
328 }
329 }
330
nvp6158_adc_reset(unsigned char ch)331 static __maybe_unused void nvp6158_adc_reset(unsigned char ch)
332 {
333 unsigned char bank_save;
334 bank_save = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0xFF);
335 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x05+ch%4);
336 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x0B, 0xF0);
337 msleep(30);
338 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x0B, 0x0F);
339 msleep(30);
340 printk("CH[%d] adc been resetted\n", ch);
341 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, bank_save);
342 }
343
nvp6158_GetFormatEachCh(unsigned char ch,NVP6158_INFORMATION_S * pInformation)344 static int nvp6158_GetFormatEachCh( unsigned char ch, NVP6158_INFORMATION_S *pInformation )
345 {
346 video_input_vfc sVFC;
347 video_input_vfc svin_vfc_bak;
348 video_input_novid sNoVideo;
349 NC_VIVO_CH_FORMATDEF oCurVidFmt;
350 //NC_VIDEO_ONOFF oCurVideoloss;
351
352 /* initialize current video format - pInformation structure is for app */
353 pInformation->curvideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
354 pInformation->curvideoloss[ch] = VIDEO_LOSS_OFF;
355 pInformation->vfc[ch] = 0xff;
356
357 /* initialize vfc(B5xF0) and videoloss information(B0xA8) */
358 sVFC.ch = ch%4;
359 sVFC.devnum = ch/4;
360 sNoVideo.ch = ch%4;
361 sNoVideo.devnum = ch/4;
362
363 /* get vfc and videoloss */
364 if(nvp6158_chip_id[ch/4]==NVP6158C_R0_ID || nvp6158_chip_id[ch/4] == NVP6158_R0_ID)
365 nvp6158_video_input_vfc_read(&sVFC);
366 else
367 nvp6168_video_input_vfc_read(&sVFC);
368 nvp6158_video_input_novid_read(&sNoVideo);
369 svin_vfc_bak.ch = ch%4;
370 svin_vfc_bak.devnum = ch/4;
371 if(nvp6158_chip_id[ch/4]==NVP6158C_R0_ID || nvp6158_chip_id[ch/4] == NVP6158_R0_ID)
372 nvp6158_video_input_onvideo_check_data(&svin_vfc_bak);
373
374 /* check vfc&videoloss and run debounce */
375 if(((((sVFC.vfc >> 4 ) & 0xF) != 0xF) && ((sVFC.vfc & 0x0F) != 0xF)) && !sNoVideo.novid) {// OnVideo
376 /* convert vfc to formatDefine for APP and save videoloss information */
377 oCurVidFmt = NVP6158_NC_VD_AUTO_VFCtoFMTDEF(ch, sVFC.vfc);
378
379 /* debouce */
380 pInformation->curvideofmt[ch] = oCurVidFmt;
381 pInformation->vfc[ch] = sVFC.vfc;
382 } else if (((((sVFC.vfc >> 4 ) & 0xF) == 0xF) && ((sVFC.vfc & 0x0F) == 0xF)) && !sNoVideo.novid) {
383 if(nvp6158_chip_id[ch/4]==NVP6158C_R0_ID || nvp6158_chip_id[ch/4]==NVP6158_R0_ID) {
384 if(svin_vfc_bak.vfc == 0xFF) {
385 //nvp6158_channel_reset(ch);
386 //nvp6158_adc_reset(ch);
387 }
388 }
389 }
390
391 /* check novideo option */
392 if( !sNoVideo.novid ) {
393 pInformation->curvideoloss[ch] = VIDEO_LOSS_ON;
394 }
395
396 return 0;
397 }
398
399 /*******************************************************************************
400 * Description : get videoloss information and get video format.
401 * Argurments : pvideofmt(video format buffer point)
402 * Return value : vloss(video loss information)
403 * Modify :
404 * warning :
405 *******************************************************************************/
406 #if(AHD_720P30_Detect_Count == 0)
407 static int CVI_720P30[16]={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,};
408 #else
409 static int CVI_720P30[16]={1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; //2020-12-16 for ahd 720p30 detect slow
410 #endif
nvp6158_video_fmt_det(const unsigned char ch,NVP6158_INFORMATION_S * ps_nvp6158_vfmts)411 unsigned int nvp6158_video_fmt_det(const unsigned char ch, NVP6158_INFORMATION_S *ps_nvp6158_vfmts)
412 {
413 int ret;
414 unsigned char oCurVideofmt = 0x00;
415 unsigned char oPreVideofmt = 0x00;
416 NC_VIVO_CH_FORMATDEF oFmtDef;
417 decoder_dev_ch_info_s sDevChInfo;
418 video_input_vfc sVFC_B13;
419 video_input_vfc sVFC_B5;
420
421 //for(ch=0; ch<nvp6158_cnt*4; ch++)
422 {
423 /* get video format */
424 nvp6158_GetFormatEachCh( ch, ps_nvp6158_vfmts );
425 /* process video format on/off */
426 oCurVideofmt = ps_nvp6158_vfmts->curvideofmt[ch];
427 oPreVideofmt = ps_nvp6158_vfmts->prevideofmt[ch];
428
429 if( ps_nvp6158_vfmts->curvideoloss[ch] == VIDEO_LOSS_ON) {
430 /* on video */
431 if( (oCurVideofmt != NC_VIVO_CH_FORMATDEF_UNKNOWN) && (oPreVideofmt == NC_VIVO_CH_FORMATDEF_UNKNOWN) ) {
432 oFmtDef = NVP6158_NC_VD_AUTO_VFCtoFMTDEF( ch, ps_nvp6158_vfmts->vfc[ch] );
433 sDevChInfo.ch = ch%4;
434 sDevChInfo.devnum = ch/4;
435 sDevChInfo.fmt_def = oFmtDef;
436 if(oFmtDef == AHD30_5M_20P ) {
437 printk("[CH:%d] >> finding format: %x....\n", ch, oFmtDef);
438
439 nvp6158_video_input_ahd_tvi_distinguish(&sDevChInfo);
440 oFmtDef = sDevChInfo.fmt_def;
441
442 ps_nvp6158_vfmts->curvideofmt[ch] = oFmtDef;
443 } else if( oFmtDef == CVI_8M_15P || oFmtDef == CVI_8M_12_5P ) {
444 if( oFmtDef == CVI_8M_15P )
445 printk("[CH:%d] >> finding format:CVI 8M 15P....\n", ch);
446 else
447 printk("[CH:%d] >> finding format:CVI 8M 12.5P....\n", ch);
448
449 if(-1 == nvp6158_video_input_cvi_tvi_distinguish(&sDevChInfo)) {
450 printk("error nvp6158_video_input_cvi_tvi_distinguish\n");
451 return 1;
452 }
453 oFmtDef = sDevChInfo.fmt_def;
454
455 if( oFmtDef == TVI_8M_15P ) {
456 printk("[CH:%d] >> changing format:TVI 8M 15P....\n", ch);
457 ps_nvp6158_vfmts->curvideofmt[ch] = TVI_8M_15P;
458 } else if( oFmtDef == TVI_8M_12_5P ) {
459 printk("[CH:%d] >> changing format:TVI 8M 12_5P....\n", ch);
460 ps_nvp6158_vfmts->curvideofmt[ch] = TVI_8M_12_5P;
461 }
462 } else if( oFmtDef == AHD20_720P_30P_EX_Btype/* || oFmtDef == CVI_HD_30P_EX*/) {
463 if(CVI_720P30[ch] == 0) {
464 oFmtDef = CVI_HD_30P_EX;
465 ps_nvp6158_vfmts->curvideofmt[ch] = CVI_HD_30P_EX;
466 CVI_720P30[ch] = 1;
467 printk("[CH:%d] >> AHD20_720P_30P_EX_Btype changing format:CVI CVI_HD_30P_EX ....\n", ch); //2020-12-16
468 } else
469 printk("[CH:%d] >> AHD20_720P_30P_EX_Btype non changing format:CVI CVI_HD_30P_EX ....\n", ch); //2020-12-16
470 } else if(oFmtDef == CVI_FHD_25P ) {
471 printk("[CH:%d] >> finding format: %x....\n", ch, oFmtDef);
472
473 nvp6158_video_input_cvi_ahd_1080p_distinguish(&sDevChInfo);
474 oFmtDef = sDevChInfo.fmt_def;
475
476 if( oFmtDef == AHD20_1080P_25P ) {
477 printk("[CH:%d] >> changing format:AHD 2M 25P....\n", ch);
478
479 ps_nvp6158_vfmts->curvideofmt[ch] = AHD20_1080P_25P;
480 }
481 }
482
483 if(ps_nvp6158_vfmts->vfc[ch] == 0x2B) {
484 sDevChInfo.ch = ch%4;
485 sDevChInfo.devnum = ch/4;
486 sDevChInfo.fmt_def = ps_nvp6158_vfmts->vfc[ch];
487 nvp6158_video_input_ahd_tvi_distinguish(&sDevChInfo);
488 oFmtDef = sDevChInfo.fmt_def;
489
490 if( oFmtDef == TVI_4M_15P ) {
491 if((nvp6158_det_mode[ch] == NVP6158_DET_MODE_AUTO)||(nvp6158_det_mode[ch] == NVP6158_DET_MODE_TVI)) {
492 printk("[CH:%d] >> changing format:TVI 4M 15P....\n", ch);
493
494 ps_nvp6158_vfmts->curvideofmt[ch] = TVI_4M_15P;
495 } else
496 ps_nvp6158_vfmts->curvideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
497 }
498 }
499
500 ps_nvp6158_vfmts->prevideofmt[ch] = ps_nvp6158_vfmts->curvideofmt[ch];
501 #ifdef _ENABLE_DET_DEBOUNCE_
502 nvp6158_s_raptor3_vfmts.debounce[ch][0] = 0; //clear debounce param status
503 nvp6158_s_raptor3_vfmts.debounce[ch][1] = 0;
504 nvp6158_s_raptor3_vfmts.debounce[ch][2] = 0;
505 nvp6158_s_raptor3_vfmts.debounce[ch][3] = 0;
506 nvp6158_s_raptor3_vfmts.debounce[ch][4] = 0;
507 nvp6158_s_raptor3_vfmts.debounceidx[ch] = 0;
508 nvp6158_s_raptor3_vfmts.prevideofmt[ch] = ps_nvp6158_vfmts->curvideofmt[ch]; //information for debounce.
509 #endif
510 //nvp6158_set_chnmode(ch, ps_nvp6158_vfmts->prevideofmt[ch]);
511 printk(">>>>> CH[%d], Set video format : 0x%02X\n", ch, oCurVideofmt);
512 } else if( (oCurVideofmt == NC_VIVO_CH_FORMATDEF_UNKNOWN ) && (oPreVideofmt == NC_VIVO_CH_FORMATDEF_UNKNOWN) ) {
513 int ii = 0;
514 int retry_cnt = 0;
515
516 /* AHD 1080P, 720P NRT Detection Part */
517 /*
518 1. Check Bank13 0xF0
519 2. Check NoVideo Register ( Bank0 0xA8 )
520 3. Set Value 0x7f to Bank5 0x82
521 4. Read Bank13 0xf0
522 5. Read Bank5 0xf0
523 6. Check H Count
524 7. AHD 1080P or 720P Set
525 8. Set value 0x00 to bank5 0x82
526 */
527
528 sVFC_B13.ch = ch%4;
529 sVFC_B13.devnum = ch / 4;
530 sVFC_B5.ch = ch%4;
531 sVFC_B5.devnum = ch / 4;
532
533 sDevChInfo.ch = ch%4;
534 sDevChInfo.devnum = ch / 4;
535
536 //nvp6158_video_input_manual_agc_stable_endi(&sDevChInfo, 1);
537
538 for(ii = 0; ii < 20; ii++ ) {
539 nvp6158_video_input_vfc_read( &sVFC_B13 );
540 nvp6158_video_input_onvideo_check_data( &sVFC_B5 );
541
542 if( ((sVFC_B5.vfc >> 4) & 0xf ) < 0x2) {
543 break;
544 }
545
546 if( sVFC_B13.vfc == 0x2b && sVFC_B5.vfc == 0x3f) {
547 printk("[DRV] CH[%d] Bank13 0xF0 [%02x], Bank5 0xF0[%02x]\n", ch, sVFC_B13.vfc, sVFC_B5.vfc );
548 printk("[DRV] CH[%d] AFHD 15P or 12.5P [%d]\n" , ch, retry_cnt );
549 break;
550 } else if(sVFC_B5.vfc != 0x2f) {
551 printk("[DRV] CH[%d] Bank13 0xF0 [%02x], Bank5 0xF0[%02x]\n", ch, sVFC_B13.vfc, sVFC_B5.vfc );
552 printk("[DRV] CH[%d] Unknown Status [%d] \n", ch, retry_cnt );
553 }
554
555 if(retry_cnt >= 20 ) {
556 printk("CH[%d] Unknown Status Disitinguish Finished ...\n", ch );
557 break;
558 }
559
560 retry_cnt++;
561 msleep( 33 );
562 }
563
564 if( ((sVFC_B5.vfc >> 4) & 0xf ) < 0x2)
565 return 0;
566
567 nvp6158_video_input_ahd_nrt_distinguish( &sDevChInfo );
568
569 if( sDevChInfo.fmt_def == NC_VIVO_CH_FORMATDEF_UNKNOWN ) {
570 printk("[DRV] CH[%d] unknown format \n", ch);
571 return 0;
572 }
573
574 oFmtDef = sDevChInfo.fmt_def;
575 /* set video format(DEC) */
576 ps_nvp6158_vfmts->curvideofmt[ ch ] = oFmtDef;
577 ps_nvp6158_vfmts->prevideofmt[ch] = ps_nvp6158_vfmts->curvideofmt[ch];
578 #ifdef _ENABLE_DET_DEBOUNCE_
579 nvp6158_s_raptor3_vfmts.debounce[ch][0] = 0; //clear debounce param status
580 nvp6158_s_raptor3_vfmts.debounce[ch][1] = 0;
581 nvp6158_s_raptor3_vfmts.debounce[ch][2] = 0;
582 nvp6158_s_raptor3_vfmts.debounce[ch][3] = 0;
583 nvp6158_s_raptor3_vfmts.debounce[ch][4] = 0;
584 nvp6158_s_raptor3_vfmts.debounceidx[ch] = 0;
585 nvp6158_s_raptor3_vfmts.prevideofmt[ch] = ps_nvp6158_vfmts->curvideofmt[ch]; //information for debounce.
586 #endif
587
588 /* save onvideo to prevideofmt */
589 //nvp6158_s_raptor3_vfmts.prevideofmt[ch] = nvp6158_s_raptor3_vfmts.curvideofmt[ch];
590
591 //nvp6158_video_input_manual_agc_stable_endi(&sDevChInfo, 0);
592 printk(">>>>> CH[%d], Auto, Set video format : 0x%02X\n", ch, oCurVideofmt );
593
594 }
595 #ifdef _ENABLE_DET_DEBOUNCE_
596 else {
597 ret = nvp6158_AutoDebouceCheck( ch, &nvp6158_s_raptor3_vfmts ); //note!!!!
598 if( ( ret == -1 ) && ( nvp6158_gCoaxFirmUpdateFlag[ch] == 0 ) ) {
599 sDevChInfo.ch = ch % 4;
600 sDevChInfo.devnum = ch/4;
601 /* hide decoder */
602 nvp6158_hide_ch(ch);
603
604 /* decoder afe power down */
605 nvp6158_video_input_vafe_control(&sDevChInfo, 0);
606 /* set no video- first(i:channel, raptor3_vfmts:information */
607 //nvp6158_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
608
609 nvp6158_video_input_vafe_control(&sDevChInfo, 1);
610
611 /* for forced agc stable */
612 //nvp6158_video_input_manual_agc_stable_endi(&sDevChInfo, 0);
613 //msleep(50);
614
615 /* save onvideo to prevideofmt */
616 ps_nvp6158_vfmts->prevideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
617 nvp6158_s_raptor3_vfmts.prevideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
618 printk( ">>>>> CH[%d], Reset, Set No video : 0x%02X\n", ch, oCurVideofmt );
619 }
620 }
621 #endif
622 }
623 else {
624 /* no video */
625 if( oPreVideofmt != NC_VIVO_CH_FORMATDEF_UNKNOWN ) {
626 //nvp6158_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
627 ps_nvp6158_vfmts->prevideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
628
629 #if(AHD_720P30_Detect_Count == 0) //wait 2s to redetect
630 CVI_720P30[ch] = 0;
631 #else
632 CVI_720P30[ch] = 1; //2020-12-16
633 #endif
634
635 #ifdef _ENABLE_DET_DEBOUNCE_
636 nvp6158_s_raptor3_vfmts.prevideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
637 #endif
638 printk( ">>>>> CH[%d], Set No video : 0x%02X\n", ch, oCurVideofmt );
639 }
640
641 }
642 }
643
644 return ps_nvp6158_vfmts->prevideofmt[ch];
645 }
646
nvp6168_video_fmt_det(const unsigned char ch,NVP6158_INFORMATION_S * ps_nvp6158_vfmts)647 unsigned int nvp6168_video_fmt_det(const unsigned char ch, NVP6158_INFORMATION_S *ps_nvp6158_vfmts)
648 {
649 //int ret;
650 unsigned char oCurVideofmt = 0x00;
651 unsigned char oPreVideofmt = 0x00;
652 NC_VIVO_CH_FORMATDEF oFmtDef;
653 decoder_dev_ch_info_s sDevChInfo;
654 //video_input_vfc sVFC_B13;
655 //video_input_vfc sVFC_B5;
656
657 //for(ch=0; ch<nvp6158_cnt*4; ch++)
658 {
659 /* get video format */
660 nvp6158_GetFormatEachCh( ch, ps_nvp6158_vfmts );
661 /* process video format on/off */
662 oCurVideofmt = ps_nvp6158_vfmts->curvideofmt[ch];
663 oPreVideofmt = ps_nvp6158_vfmts->prevideofmt[ch];
664
665 if( ps_nvp6158_vfmts->curvideoloss[ch] == VIDEO_LOSS_ON) {
666 /* on video */
667 if( (oCurVideofmt != NC_VIVO_CH_FORMATDEF_UNKNOWN) &&
668 (oPreVideofmt == NC_VIVO_CH_FORMATDEF_UNKNOWN) ) {
669 oFmtDef = NVP6158_NC_VD_AUTO_VFCtoFMTDEF( ch, ps_nvp6158_vfmts->vfc[ch] );
670 sDevChInfo.ch = ch%4;
671 sDevChInfo.devnum = ch/4;
672 sDevChInfo.fmt_def = oFmtDef;
673
674 if(oFmtDef == TVI_5M_20P) {//needs 2nd identify
675 nvp6168_video_input_cvi_tvi_5M20p_distinguish(&sDevChInfo);
676 oFmtDef = sDevChInfo.fmt_def;
677
678 ps_nvp6158_vfmts->curvideofmt[ch] = oFmtDef;
679 }
680
681 ps_nvp6158_vfmts->prevideofmt[ch] = ps_nvp6158_vfmts->curvideofmt[ch];
682
683 //nvp6158_set_chnmode(ch, ps_nvp6158_vfmts->prevideofmt[ch]);
684 printk(">>>>> CH[%d], Set video format : 0x%02X\n", ch, oCurVideofmt);
685 }
686
687 } else {
688 /* no video */
689 if( oPreVideofmt != NC_VIVO_CH_FORMATDEF_UNKNOWN ) {
690 //nvp6158_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
691 ps_nvp6158_vfmts->prevideofmt[ch] = NC_VIVO_CH_FORMATDEF_UNKNOWN;
692
693 printk( ">>>>> CH[%d], Set No video : 0x%02X\n", ch, oCurVideofmt );
694 }
695
696 }
697 }
698
699 return ps_nvp6158_vfmts->prevideofmt[ch];
700 }
701
702
nvp6158_getvideoloss(void)703 unsigned int nvp6158_getvideoloss(void)
704 {
705 unsigned int vloss=0, i;
706 unsigned char vlossperchip[4];
707
708 for(i = 0; i < nvp6158_cnt; i++) {
709 gpio_i2c_write(nvp6158_iic_addr[i], 0xFF, 0x00);
710 vlossperchip[i] = (gpio_i2c_read(nvp6158_iic_addr[i], 0xA8)&0x0F);
711 vloss |= (vlossperchip[i]<<(4*i));
712 }
713
714 return vloss;
715 }
716 static unsigned char nvp6158_vloss_pre = 0xFF;
717 static unsigned char nvp6158_ch_first_plug_status[8]={1, 1, 1, 1, 1, 1, 1, 1};
nvp6158_is_first_plugin(unsigned char ch)718 static __maybe_unused unsigned char nvp6158_is_first_plugin(unsigned char ch)
719 {
720 unsigned int vloss=0;
721
722 vloss = nvp6158_getvideoloss();
723 //for(ch=0;ch<(nvp6158_cnt*4);ch++)
724 {
725 if( ( ((vloss>>ch)&0x01)==0 ) && ( ((nvp6158_vloss_pre>>ch)&0x01)==1 )) //video first input
726 {
727 nvp6158_ch_first_plug_status[ch] = 0;
728 nvp6158_vloss_pre &= ~(1<<ch); //corresponding bit, corresponding channel not in;
729 }
730 }
731
732 return nvp6158_ch_first_plug_status[ch];
733 }
734
nvp6158_vd_chnreset(unsigned char ch)735 void nvp6158_vd_chnreset(unsigned char ch)
736 {
737 unsigned char reg_1x97;
738 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x01);
739 reg_1x97 = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x97);
740 _CLE_BIT(reg_1x97,(ch%4));
741 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x97, reg_1x97);
742 msleep(10);
743 _SET_BIT(reg_1x97,(ch%4));
744 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x97, reg_1x97);
745 }
746
747 /*0:agc unlocked; 1:agc locked*/
nvp6158_GetAgcLockStatus(unsigned char ch)748 int nvp6158_GetAgcLockStatus(unsigned char ch)
749 {
750 int agc_lock, ret;
751 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
752 agc_lock = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0xE0);
753 ret = ((agc_lock>>(ch%4))&0x01);
754
755 return ret;
756 }
757
758 /*0:fsc unlocked; 1:fsc locked*/
nvp6158_GetFSCLockStatus(unsigned char ch)759 int nvp6158_GetFSCLockStatus(unsigned char ch)
760 {
761 int fsc_lock, ret;
762 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
763 fsc_lock = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0xE8+(ch%4));
764 ret = ((fsc_lock>>1)&0x01);
765
766 return ret;
767 }
768
nvp6158_ResetFSCLock(unsigned char ch)769 void nvp6158_ResetFSCLock(unsigned char ch)
770 {
771 unsigned char acc_ref=0;
772 unsigned char check_cnt = 4;
773 do {
774 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x05+(ch%4));
775 acc_ref = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x27);
776 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x23, 0x80);
777 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x27, 0x10);
778 msleep(35);
779 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x23, 0x00);
780 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x27, acc_ref);
781 msleep(300);
782 }
783 while((nvp6158_GetFSCLockStatus(ch)==0) && ((check_cnt--)>0));
784
785 printk("%s, %d\n", __FUNCTION__, __LINE__);
786 }
787
nvp6158_chn_killcolor(unsigned char ch,unsigned char onoff)788 void nvp6158_chn_killcolor(unsigned char ch, unsigned char onoff)
789 {
790 unsigned char colorkill;
791 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
792 colorkill = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x22+(ch%4)*4);
793 if(onoff==1)
794 _SET_BIT(colorkill, 4);
795 else
796 _CLE_BIT(colorkill, 4);
797 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x22+(ch%4)*4, colorkill);
798 printk("%s, %d %x %x\n", __FUNCTION__, __LINE__, onoff, colorkill);
799 }
800
nvp6158_hide_ch(unsigned char ch)801 void nvp6158_hide_ch(unsigned char ch)
802 {
803 unsigned char reg_0x7a;
804 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
805 reg_0x7a = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x7A+((ch%4)/2));
806 reg_0x7a &= (ch%2==0?0xF0:0x0F);
807 reg_0x7a |= (ch%2==0?0x0F:0xF0);
808 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x7A+((ch%4)/2),reg_0x7a);
809 //printk("%s, %d\n", __FUNCTION__, __LINE__);
810 }
811
nvp6158_show_ch(unsigned char ch)812 void nvp6158_show_ch(unsigned char ch)
813 {
814 unsigned char reg_0x7a;
815 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
816 reg_0x7a = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x7A+((ch%4)/2));
817 reg_0x7a &= (ch%2==0?0xF0:0x0F);
818 reg_0x7a |= (ch%2==0?0x01:0x10);
819 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x7A+((ch%4)/2),reg_0x7a);
820 //printk("%s, %d\n", __FUNCTION__, __LINE__);
821 }
822
823
824 /*
825 support AHD 3M/4M real-time camera switch between NTSC and PAL
826 */
nvp6158_acp_SetVFmt(unsigned char ch,const unsigned char vfmt)827 int nvp6158_acp_SetVFmt(unsigned char ch, const unsigned char vfmt)
828 {
829 /*nvp6158_acp_rw_data_extention acpdata;
830
831 if((vfmt!=NTSC) && (vfmt!=PAL))
832 {
833 printk("%s vfmt[%d] out of range!!!\n", __FUNCTION__, vfmt);
834 return -1;
835 }
836 if(nvp6158_ch_vfmt_status[ch] == vfmt)
837 {
838 printk("%s vfmt is %d now!!!\n", __FUNCTION__, vfmt);
839 return -2;
840 }
841
842 acpdata.ch = ch;
843 acpdata.data[0] = 0x60; // register write
844 acpdata.data[1] = 0x82; // Output mode command
845 acpdata.data[2] = 0x19; // Output Format Change mode
846 acpdata.data[3] = 0x00; // Output Mode value
847 acpdata.data[4] = 0x00;
848 acpdata.data[5] = 0x00;
849 acpdata.data[6] = 0x00;
850 acpdata.data[7] = 0x00;
851 if( (nvp6158_ch_mode_status[ch] == NVP6158_VI_3M ||
852 nvp6158_ch_mode_status[ch] == NVP6158_VI_3M_NRT ||
853 nvp6158_ch_mode_status[ch] == NVP6158_VI_4M_NRT ||
854 nvp6158_ch_mode_status[ch] == NVP6158_VI_4M ) &&
855 nvp6158_GetAgcLockStatus(ch)==1)
856 {
857 acpdata.data[3] = vfmt^1; //CAUTION!!! IN CAMERA SIDE 0:PAL, 1:NTSC.
858 acp_isp_write_extention(ch, &acpdata);
859 msleep(100);
860 printk("%s change ch[%d] to %s!!!\n", __FUNCTION__, ch, vfmt==NTSC?"NTSC":"PAL");
861 }
862 */
863 return 0;
864 }
865
nvp6158_video_set_contrast(unsigned char ch,unsigned int value,unsigned int v_format)866 void nvp6158_video_set_contrast(unsigned char ch, unsigned int value, unsigned int v_format)
867 {
868 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
869 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x10+(ch%4)), value);
870 }
871
nvp6158_video_set_brightness(unsigned char ch,unsigned int value,unsigned int v_format)872 void nvp6158_video_set_brightness(unsigned char ch, unsigned int value, unsigned int v_format)
873 {
874 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
875 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x0C+(ch%4)), value);
876 }
877
nvp6158_video_set_saturation(unsigned char ch,unsigned int value,unsigned int v_format)878 void nvp6158_video_set_saturation(unsigned char ch, unsigned int value, unsigned int v_format)
879 {
880 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
881 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x3C+(ch%4)),value);
882 }
883
nvp6158_video_set_hue(unsigned char ch,unsigned int value,unsigned int v_format)884 void nvp6158_video_set_hue(unsigned char ch, unsigned int value, unsigned int v_format)
885 {
886 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
887 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x40+(ch%4)), value);
888 }
889
nvp6158_video_set_sharpness(unsigned char ch,unsigned int value)890 void nvp6158_video_set_sharpness(unsigned char ch, unsigned int value)
891 {
892 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
893 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x14+(ch%4)), (0x90+value-100));
894 }
895
896 //u-gain value B0 0x44~0x47
nvp6158_video_set_ugain(unsigned char ch,unsigned int value)897 void nvp6158_video_set_ugain(unsigned char ch, unsigned int value)
898 {
899 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
900 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x44+(ch%4)), value);
901 }
902
903 //v-gain value B0 0x48~0x4b
nvp6158_video_set_vgain(unsigned char ch,unsigned int value)904 void nvp6158_video_set_vgain(unsigned char ch, unsigned int value)
905 {
906 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
907 gpio_i2c_write(nvp6158_iic_addr[ch/4], (0x48+(ch%4)), value);
908 }
909
nvp6158_video_input_new_format_set(const unsigned char ch,const unsigned char chnmode)910 void nvp6158_video_input_new_format_set(const unsigned char ch, const unsigned char chnmode)
911 {
912 unsigned char val_9x44;
913
914 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x11);
915 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x00 + ( (ch%4) * 0x20 ), 0x00);
916
917 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF,0x09);
918 val_9x44 = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x44);
919 val_9x44 &= ~(1 << (ch%4));
920
921 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x44, val_9x44);
922
923 /* CVI HD 30P PN Value Set */
924 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x50 + ( (ch%4) * 4 ) , 0x30);
925 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x51 + ( (ch%4) * 4 ) , 0x6F);
926 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x52 + ( (ch%4) * 4 ) , 0x67);
927 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x53 + ( (ch%4) * 4 ) , 0x48);
928
929 }
930
nvp6158_set_chn_ycmerge(const unsigned char ch,unsigned char onoff)931 static void nvp6158_set_chn_ycmerge(const unsigned char ch, unsigned char onoff)
932 {
933 unsigned char YCmerge, val5x69;
934 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x01);
935 YCmerge = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0xed);
936 _CLE_BIT(YCmerge, (ch%4));
937 if(onoff == 1)
938 _SET_BIT(YCmerge, (ch%4));
939
940 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xed, YCmerge);
941
942 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x05+ch%4);
943 val5x69 = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x69);
944 _CLE_BIT(val5x69, 4);
945 if(onoff == 1)
946 _SET_BIT(val5x69, 4);
947
948 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x69, val5x69);
949 }
950
951 /*******************************************************************************
952 * Description : set this value
953 * Argurments : ch(channel)
954 * Return value : void
955 * Modify :
956 * warning : You don't have to change these values.
957 *******************************************************************************/
nvp6158_set_chn_commonvalue(const unsigned char ch,const unsigned char chnmode)958 void nvp6158_set_chn_commonvalue(const unsigned char ch, const unsigned char chnmode)
959 {
960 decoder_dev_ch_info_s decoder_info;
961 unsigned char val_0x54;
962 unsigned char vfmt = chnmode%2;
963
964 if((chnmode <= AHD20_SD_H960_2EX_Btype_PAL) && (chnmode>=AHD20_SD_H960_NT)) {
965 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
966 val_0x54 = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x54);
967 _CLE_BIT(val_0x54, (ch%4+4));
968 if(vfmt != PAL)
969 _SET_BIT(val_0x54, (ch%4+4));
970 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x54, val_0x54);
971
972 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x05+ch%4);
973 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x69,0x01);
974 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xB8,0xB8);
975 } else {
976 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x00);
977 val_0x54 = gpio_i2c_read(nvp6158_iic_addr[ch/4], 0x54);
978 _CLE_BIT(val_0x54, (ch%4+4));
979 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x54, val_0x54);
980
981 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xFF, 0x05+ch%4);
982 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x69, 0x00);
983 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xB8,0x39);
984 }
985
986 decoder_info.ch = ch%4;
987 decoder_info.devnum = ch/4;
988 decoder_info.fmt_def = chnmode;
989 if(__nvp6158_IsOver3MRTVideoFormat( &decoder_info ))
990 nvp6158_set_chn_ycmerge(ch, 1);
991 else
992 nvp6158_set_chn_ycmerge(ch, 0);
993 if(nvp6158_chip_id[decoder_info.devnum]==NVP6158C_R0_ID || nvp6158_chip_id[decoder_info.devnum]==NVP6158_R0_ID)
994 nvp6158_video_input_onvideo_set( &decoder_info );
995 else
996 nvp6168_video_input_onvideo_set( &decoder_info );
997 }
998
nvp6158_set_chnmode(const unsigned char ch,const unsigned char chnmode)999 int nvp6158_set_chnmode(const unsigned char ch, const unsigned char chnmode)
1000 {
1001 //unsigned char tmp;
1002 video_equalizer_info_s vin_eq_set;
1003 video_input_novid auto_novid;
1004 nvp6158_coax_str s_coax_str;
1005
1006 if(ch >= (nvp6158_cnt*4)) {
1007 printk("func[nvp6158_set_chnmode] Channel %d is out of range!!!\n", ch);
1008 return -1;
1009 }
1010
1011 /* set video format each format */
1012 if(chnmode < NC_VIVO_CH_FORMATDEF_MAX) {
1013 if(NC_VIVO_CH_FORMATDEF_UNKNOWN != chnmode) {
1014 nvp6158_set_chn_commonvalue( ch, chnmode );
1015
1016 nvp6158_video_input_new_format_set(ch, chnmode);
1017
1018 s_coax_str.ch = ch;
1019 s_coax_str.fmt_def = chnmode;
1020 nvp6158_coax_tx_init(&s_coax_str);
1021 nvp6158_coax_tx_16bit_init(&s_coax_str); //for ahd 720P and CVI 4M
1022 nvp6158_coax_rx_init(&s_coax_str);
1023
1024 vin_eq_set.Ch = ch%4;
1025 vin_eq_set.devnum = ch/4;
1026 vin_eq_set.distance = 0;
1027 vin_eq_set.FmtDef = chnmode;
1028 nvp6158_set_equalizer(&vin_eq_set);
1029
1030 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xff,0x09);
1031 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x40+ch%4,0x61);
1032 msleep(35);
1033 if(AHD20_SD_H960_2EX_Btype_PAL >= chnmode)
1034 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x40+ch%4,0x60); //for comet setting
1035 else
1036 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x40+ch%4,0x00);
1037
1038 nvp6158_show_ch(ch);
1039 } else {
1040 nvp6158_hide_ch(ch);
1041 auto_novid.ch = ch%4;
1042 auto_novid.devnum = ch/4;
1043 nvp6158_video_input_no_video_set(&auto_novid);
1044 nvp6158_set_chn_ycmerge(ch, 0);
1045 }
1046 nvp6158_ch_mode_status[ch] = chnmode;
1047 //nvp6158_ch_vfmt_status[ch] = chnmode%2;
1048
1049 printk(">>>>%s CH[%d] been setted to %2x mode\n", __func__, ch, chnmode);
1050 }
1051
1052 return 0;
1053 }
1054
nvp6168_set_chnmode(const unsigned char ch,const unsigned char chnmode)1055 int nvp6168_set_chnmode(const unsigned char ch, const unsigned char chnmode)
1056 {
1057 //unsigned char tmp;
1058 video_equalizer_info_s vin_eq_set;
1059 video_input_novid auto_novid;
1060 nvp6158_coax_str s_coax_str;
1061
1062 if(ch >= (nvp6158_cnt*4)) {
1063 printk("func[nvp6168_set_chnmode] Channel %d is out of range!!!\n", ch);
1064 return -1;
1065 }
1066
1067 /* set video format each format */
1068 if(chnmode < NC_VIVO_CH_FORMATDEF_MAX) {
1069 if(NC_VIVO_CH_FORMATDEF_UNKNOWN != chnmode) {
1070 nvp6158_set_chn_commonvalue( ch, chnmode );
1071
1072 //nvp6158_video_input_new_format_set(ch, chnmode);
1073
1074 s_coax_str.ch = ch;
1075 s_coax_str.fmt_def = chnmode;
1076 nvp6158_coax_tx_init(&s_coax_str);
1077 nvp6158_coax_tx_16bit_init(&s_coax_str); //for ahd 720P and CVI 4M
1078 nvp6158_coax_rx_init(&s_coax_str);
1079
1080 vin_eq_set.Ch = ch%4;
1081 vin_eq_set.devnum = ch/4;
1082 vin_eq_set.distance = 0;
1083 vin_eq_set.FmtDef = chnmode;
1084 nvp6168_set_equalizer(&vin_eq_set);
1085
1086 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0xff,0x09);
1087 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x40+ch%4,0x61);
1088 msleep(35);
1089 if(AHD20_SD_H960_2EX_Btype_PAL >= chnmode)
1090 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x40+ch%4,0x60); //for comet setting
1091 else
1092 gpio_i2c_write(nvp6158_iic_addr[ch/4], 0x40+ch%4,0x00);
1093
1094 nvp6158_show_ch(ch);
1095 } else {
1096 nvp6158_hide_ch(ch);
1097 auto_novid.ch = ch%4;
1098 auto_novid.devnum = ch/4;
1099 nvp6168_video_input_no_video_set(&auto_novid);
1100 nvp6158_set_chn_ycmerge(ch, 0);
1101 }
1102 nvp6158_ch_mode_status[ch] = chnmode;
1103 //nvp6158_ch_vfmt_status[ch] = chnmode%2;
1104
1105 printk(">>>>%s CH[%d] been setted to %2x mode\n", __func__, ch, chnmode);
1106 }
1107
1108 return 0;
1109 }
1110
1111
1112 /*
1113 chip:chip select[0,1,2,3];
1114 portsel: port select->6158c[1,2],6158[0,1,2,3];
1115 portmode: port mode select[1mux,2mux,4mux]
1116 chid: channel id, 1mux[0,1,2,3], 2mux[0,1], 4mux[0]
1117 */
1118 /*******************************************************************************
1119 * Description : select port
1120 * Argurments : chip(chip select[0,1,2,3]),
1121 * portsel(port select->6158c[1,2],6158[0,1,2,3];)
1122 * portmode(port mode select[1mux,2mux,4mux]),
1123 * chid(channel id, 1mux[0,1,2,3], 2mux[0,1], 4mux[0])
1124 * Return value : 0
1125 * Modify :
1126 * warning :
1127 *******************************************************************************/
nvp6158_set_portmode(const unsigned char chip,const unsigned char portsel,const unsigned char portmode,const unsigned char chid)1128 int nvp6158_set_portmode(const unsigned char chip, const unsigned char portsel,
1129 const unsigned char portmode, const unsigned char chid)
1130 {
1131 unsigned char chipaddr = nvp6158_iic_addr[chip];
1132 unsigned char tmp=0, tmp1=0, reg1=0, reg2=0;
1133
1134 if((portsel!=1) && (portsel!=2) && (nvp6158_chip_id[chip]==NVP6158C_R0_ID ||
1135 nvp6158_chip_id[chip] == NVP6168C_R0_ID)) {
1136 printk("nvp6158C_set_portmode portsel[%d] error!!!\n", portsel);
1137 //return -1;
1138 }
1139
1140 switch(portmode) {
1141 case NVP6158_OUTMODE_1MUX_SD:
1142 /*Output 720H/960H Single Channel data, Data Rate 37.125MHz,Pclk 37.125MHz, Single Edge.*/
1143 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1144 gpio_i2c_write(chipaddr, 0x56, 0x10);
1145 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1146 gpio_i2c_write(chipaddr, 0xC0+portsel*2, (chid<<4)|chid);
1147 gpio_i2c_write(chipaddr, 0xC1+portsel*2, (chid<<4)|chid);
1148 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1149 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1150 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x86);
1151 break;
1152 case NVP6158_OUTMODE_1MUX_HD:
1153 /*Output 720P/1280H/1440H Single Channel data,Data Rate 74.25MHz,Pclk 74.25MHz, Single Edge.*/
1154 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1155 gpio_i2c_write(chipaddr, 0x56, 0x10);
1156 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1157 gpio_i2c_write(chipaddr, 0xC0+portsel*2, (chid<<4)|chid);
1158 gpio_i2c_write(chipaddr, 0xC1+portsel*2, (chid<<4)|chid);
1159 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1160 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1161 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x16);
1162 break;
1163 case NVP6158_OUTMODE_1MUX_FHD:
1164 /*Output 720P@5060 /1080P Single Channel data,Data Rate 148.5MHz,Pclk 148.5MHz, Single Edge.*/
1165 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1166 gpio_i2c_write(chipaddr, 0x56, 0x10);
1167 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1168 gpio_i2c_write(chipaddr, 0xC0+portsel*2, (chid<<4)|chid);
1169 gpio_i2c_write(chipaddr, 0xC1+portsel*2, (chid<<4)|chid);
1170 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1171 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1172 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x56); //0x40~0x5f adjust delay
1173 break;
1174 case NVP6158_OUTMODE_1MUX_FHD_DDR:
1175 /*Output 720P@5060 /1080P Single Channel data,Data Rate 148.5MHz,Pclk 148.5MHz, Single Edge.*/
1176 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1177 gpio_i2c_write(chipaddr, 0x56, 0x10);
1178 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1179 gpio_i2c_write(chipaddr, 0xC0+portsel*2, (chid<<4)|chid);
1180 gpio_i2c_write(chipaddr, 0xC1+portsel*2, (chid<<4)|chid);
1181 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1182 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1183 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x06); //0x00~0x3f adjust delay
1184 break;
1185 case NVP6158_OUTMODE_2MUX_SD:
1186 /*Output 720H/960H 2 Channel data,Data Rate 74.25MHz,Pclk 74.25MHz, Single Edge.*/
1187 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1188 gpio_i2c_write(chipaddr, 0x56, 0x10);
1189 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1190 gpio_i2c_write(chipaddr, 0xC0+portsel*2, chid==0?0x10:0x32);
1191 gpio_i2c_write(chipaddr, 0xC1+portsel*2, chid==0?0x10:0x32);
1192 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1193 tmp |= (portsel%2?0x20:0x02);
1194 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1195 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x16);
1196 break;
1197 case NVP6158_OUTMODE_2MUX_HD:
1198 /*Output HD 2 Channel data,Data Rate 148.5MHz,Pclk 148.5MHz, Single Edge.*/
1199 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1200 gpio_i2c_write(chipaddr, 0x56, 0x10);
1201 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1202 gpio_i2c_write(chipaddr, 0xC0+portsel*2, chid==0?0x10:0x32);
1203 gpio_i2c_write(chipaddr, 0xC1+portsel*2, chid==0?0x10:0x32);
1204 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1205 tmp |= (portsel%2?0x20:0x02);
1206 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1207 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x58);
1208 break;
1209 case NVP6158_OUTMODE_4MUX_SD:
1210 /*Output 720H/960H 4 Channel data,Data Rate 148.5MHz,Pclk 148.5MHz, Single Edge.*/
1211 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1212 gpio_i2c_write(chipaddr, 0x56, 0x32);
1213 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1214 gpio_i2c_write(chipaddr, 0xC0+portsel*2, 0x10);
1215 gpio_i2c_write(chipaddr, 0xC1+portsel*2, 0x32);
1216 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1217 tmp |= (portsel%2?0x80:0x08);
1218 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1219 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x58);
1220 break;
1221 case NVP6158_OUTMODE_4MUX_HD:
1222 /*Output 720P 4 Channel data,Data Rate 297MHz,Pclk 297MHz, Single Edge.*/
1223 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1224 gpio_i2c_write(chipaddr, 0x56, 0x32);
1225 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1226 gpio_i2c_write(chipaddr, 0xC0+portsel*2, 0x98);
1227 gpio_i2c_write(chipaddr, 0xC1+portsel*2, 0xba);
1228 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1229 tmp |= (portsel%2?0x80:0x08);
1230 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1231 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x58);
1232 //gpio_i2c_write(chipaddr, 0xCC+portsel, 0x66); //single up
1233 break;
1234 case NVP6158_OUTMODE_2MUX_FHD:
1235 /*5M_20P,5M_12P,4M_RT,4M_15P,3M_RT/NRT,FHD,3840H,HDEX 2mux mix, ,Data Rate 297MHz,Pclk 297MHz, Dual Edge.
1236 SOC VI Port abandon some data, Realize 3840H->960H, HDEX->720P.*/
1237 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1238 gpio_i2c_write(chipaddr, 0x56, 0x10);
1239 #if 1
1240 //CHANNEL 1 JUDGE
1241 tmp = gpio_i2c_read(chipaddr, 0x81)&0x0F;
1242 tmp1 = gpio_i2c_read(chipaddr, 0x85)&0x0F;
1243 if(((tmp == 0x02) || (tmp == 0x03)) && (tmp1 == 0x04))
1244 reg1 |= 0x08; //3M_RT, THEN OUTPUT 3M_CIF DATA
1245 else if(((tmp == 0x0E) || (tmp == 0x0F)) && (tmp1 == 0x00))
1246 reg1 |= 0x08; //4M, THEN OUTPUT 4M_CIF DATA
1247 else if((tmp == 0x01) && (tmp1 == 0x05)) //ahd 5m20p
1248 reg1 |= 0x08;
1249 else if(((tmp == 0x0E) || (tmp == 0x0F)) && ((tmp1 == 0x02) || (tmp1 == 0x03))) //tvi/cvi 4m rt
1250 reg1 |= 0x08;
1251 else if(((tmp == 0x01) || (tmp == 0x02)) && ((tmp1 == 0x08) || (tmp1 == 0x09) || (tmp1 == 0x0a))) //8M
1252 reg1 |= 0x08;
1253 else
1254 reg1 &= 0xF0;
1255 //CHANNEL 2 JUDGE
1256 tmp = gpio_i2c_read(chipaddr, 0x82)&0x0F;
1257 tmp1 = gpio_i2c_read(chipaddr, 0x86)&0x0F;
1258 if(((tmp == 0x02) || (tmp == 0x03)) && (tmp1 == 0x04))
1259 reg1 |= 0x80;
1260 else if(((tmp == 0x0E) || (tmp == 0x0F)) && (tmp1 == 0x00))
1261 reg1 |= 0x80;
1262 else if((tmp == 0x01) && (tmp1 == 0x05))
1263 reg1 |= 0x80;
1264 else if(((tmp == 0x0E) || (tmp == 0x0F)) && ((tmp1 == 0x02) || (tmp1 == 0x03))) //tvi/cvi 4m rt
1265 reg1 |= 0x80;
1266 else if(((tmp == 0x01) || (tmp == 0x02)) && ((tmp1 == 0x08) || (tmp1 == 0x09) ||(tmp1 == 0x0a))) //8M
1267 reg1 |= 0x80;
1268 else
1269 reg1 &= 0x0F;
1270 //CHANNEL 3 JUDGE
1271 tmp = gpio_i2c_read(chipaddr, 0x83)&0x0F;
1272 tmp1 = gpio_i2c_read(chipaddr, 0x87)&0x0F;
1273 if(((tmp == 0x02) || (tmp == 0x03)) && (tmp1 == 0x04))
1274 reg2 |= 0x08;
1275 else if(((tmp == 0x0E) || (tmp == 0x0F)) && (tmp1 == 0x00))
1276 reg2 |= 0x08;
1277 else if((tmp == 0x01) && (tmp1 == 0x05))
1278 reg2 |= 0x08;
1279 else if(((tmp == 0x0E) || (tmp == 0x0F)) && ((tmp1 == 0x02) || (tmp1 == 0x03))) //tvi/cvi 4m rt
1280 reg2 |= 0x08;
1281 else if(((tmp == 0x01) || (tmp == 0x02)) && ((tmp1 == 0x08) || (tmp1 == 0x09) ||(tmp1 == 0x0a))) //8M
1282 reg2 |= 0x08;
1283 else
1284 reg2 &= 0xF0;
1285 //CHANNEL 4 JUDGE
1286 tmp = gpio_i2c_read(chipaddr, 0x84)&0x0F;
1287 tmp1 = gpio_i2c_read(chipaddr, 0x88)&0x0F;
1288 if(((tmp == 0x02) || (tmp == 0x03)) && (tmp1 == 0x04))
1289 reg2 |= 0x80;
1290 else if(((tmp == 0x0E) || (tmp == 0x0F)) && (tmp1 == 0x00))
1291 reg2 |= 0x80;
1292 else if((tmp == 0x01) && (tmp1 == 0x05))
1293 reg2 |= 0x80;
1294 else if(((tmp == 0x0E) || (tmp == 0x0F)) && ((tmp1 == 0x02) || (tmp1 == 0x03))) //tvi/cvi 4m rt
1295 reg2 |= 0x80;
1296 else if(((tmp == 0x01) || (tmp == 0x02)) && ((tmp1 == 0x08) || (tmp1 == 0x09) ||(tmp1 == 0x0a))) //ahd 8M
1297 reg2 |= 0x80;
1298 else
1299 reg2 &= 0x0F;
1300 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1301 gpio_i2c_write(chipaddr, 0xC0+portsel*2, chid==0?(0x10|reg1):(0x32|reg2));
1302 gpio_i2c_write(chipaddr, 0xC1+portsel*2, chid==0?(0x10|reg1):(0x32|reg2));
1303 #else
1304 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1305 gpio_i2c_write(chipaddr, 0xC0+portsel*2, chid==0?0x10:0x32);
1306 gpio_i2c_write(chipaddr, 0xC1+portsel*2, chid==0?0x10:0x32);
1307 #endif
1308 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1309 tmp |= (portsel%2?0x20:0x02);
1310 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1311 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x56);
1312 //gpio_i2c_write(chipaddr, 0xCC+portsel, 0x66); //single up
1313 break;
1314 case NVP6158_OUTMODE_4MUX_MIX:
1315 /*HD,1920H,FHD-X 4mux mix,Data Rate 297MHz,Pclk 297MHz, Dual Edge.
1316 SOC VI Port Abandon some data��realize 1920H->960H */
1317 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1318 gpio_i2c_write(chipaddr, 0x56, 0x32);
1319 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1320 gpio_i2c_write(chipaddr, 0xC0+portsel*2, 0x98);
1321 gpio_i2c_write(chipaddr, 0xC1+portsel*2, 0xba);
1322 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1323 tmp |= (portsel%2?0x80:0x08);
1324 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1325 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x58);
1326 //gpio_i2c_write(chipaddr, 0xCC+portsel, 0x66); //single up
1327 break;
1328 case NVP6158_OUTMODE_2MUX_MIX:
1329 /*HD,1920H,FHD-X 2mux mix,Data Rate 148.5MHz,Pclk 148.5MHz, Single Edge.
1330 SOC VI Port Abandon some data, realize 1920H->960H */
1331 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1332 gpio_i2c_write(chipaddr, 0x56, 0x10);
1333 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1334 gpio_i2c_write(chipaddr, 0xC0+portsel*2, chid==0?0x98:0xba);
1335 gpio_i2c_write(chipaddr, 0xC1+portsel*2, chid==0?0x98:0xba);
1336 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1337 tmp |= (portsel%2?0x20:0x02);
1338 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1339 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x58);
1340 break;
1341 case NVP6158_OUTMODE_1MUX_BT1120S_720P:
1342 /*Output 720P Single Channel data,Data Rate 37.125MHz,Pclk 37.125MHz, Single Edge.*/
1343 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1344 gpio_i2c_write(chipaddr, 0x56, 0x10);
1345 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1346 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1347 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1348 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1349 gpio_i2c_write(chipaddr, 0xC2, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1350 gpio_i2c_write(chipaddr, 0xC3, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1351 gpio_i2c_write(chipaddr, 0xC4, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1352 gpio_i2c_write(chipaddr, 0xC5, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1353 gpio_i2c_write(chipaddr, 0xC8, 0x00);
1354 gpio_i2c_write(chipaddr, 0xC9, 0x00);
1355 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x86); //37.125MHz clock
1356 } else {
1357 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1358 gpio_i2c_write(chipaddr, 0xC0+portsel*4, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1359 gpio_i2c_write(chipaddr, 0xC1+portsel*4, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1360 gpio_i2c_write(chipaddr, 0xC2+portsel*4, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1361 gpio_i2c_write(chipaddr, 0xC3+portsel*4, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1362 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x00);
1363 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x86); //37.125MHz clock
1364 }
1365 break;
1366 case NVP6158_OUTMODE_1MUX_BT1120S_1080P:
1367 /*Output 1080 Single Channel data,Data Rate 74.25MHz,Pclk 74.25MHz, Single Edge.*/
1368 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1369 gpio_i2c_write(chipaddr, 0x56, 0x10);
1370 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1371 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1372 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1373 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1374 gpio_i2c_write(chipaddr, 0xC2, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1375 gpio_i2c_write(chipaddr, 0xC3, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1376 gpio_i2c_write(chipaddr, 0xC4, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1377 gpio_i2c_write(chipaddr, 0xC5, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1378 gpio_i2c_write(chipaddr, 0xC8, 0x00);
1379 gpio_i2c_write(chipaddr, 0xC9, 0x00);
1380 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x06); //74.25MHz clock
1381 } else {
1382 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1383 gpio_i2c_write(chipaddr, 0xC0+portsel*4, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1384 gpio_i2c_write(chipaddr, 0xC1+portsel*4, (((chid%4)+0x0C)<<4)|((chid%4)+0x0C));
1385 gpio_i2c_write(chipaddr, 0xC2+portsel*4, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1386 gpio_i2c_write(chipaddr, 0xC3+portsel*4, (((chid%4)+0x04)<<4)|((chid%4)+0x04));
1387 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x00);
1388 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x86); //37.125MHz clock
1389 }
1390 break;
1391 case NVP6158_OUTMODE_2MUX_BT1120S:
1392 case NVP6158_OUTMODE_2MUX_BT1120S_720P:
1393 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1394 gpio_i2c_write(chipaddr, 0x56, 0x10);
1395 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1396 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1397 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1398 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1399 gpio_i2c_write(chipaddr, 0xC2, 0xdc);
1400 gpio_i2c_write(chipaddr, 0xC3, 0xdc);
1401 gpio_i2c_write(chipaddr, 0xC4, 0x54);
1402 gpio_i2c_write(chipaddr, 0xC5, 0x54);
1403 gpio_i2c_write(chipaddr, 0xC8, 0x22);
1404 gpio_i2c_write(chipaddr, 0xC9, 0x22);
1405 gpio_i2c_write(chipaddr, 0xCD, 0x1f); //74.25MHz clock
1406 gpio_i2c_write(chipaddr, 0xCE, 0x1f); //74.25MHz clock
1407 } else {
1408 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1409 gpio_i2c_write(chipaddr, 0xC0+portsel*4, 0xdc);
1410 gpio_i2c_write(chipaddr, 0xC1+portsel*4, 0xdc);
1411 gpio_i2c_write(chipaddr, 0xC2+portsel*4, 0x54);
1412 gpio_i2c_write(chipaddr, 0xC3+portsel*4, 0x54);
1413 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x00);
1414 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x06); //74.25MHz clock
1415 }
1416 break;
1417 case NVP6158_OUTMODE_2MUX_BT1120S_1080P:
1418 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1419 gpio_i2c_write(chipaddr, 0x56, 0x10);
1420 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1421 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1422 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1423 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1424 gpio_i2c_write(chipaddr, 0xC2, 0x54);
1425 gpio_i2c_write(chipaddr, 0xC3, 0x54);
1426 gpio_i2c_write(chipaddr, 0xC4, 0xdc);
1427 gpio_i2c_write(chipaddr, 0xC5, 0xdc);
1428 gpio_i2c_write(chipaddr, 0xC8, 0x22);
1429 gpio_i2c_write(chipaddr, 0xC9, 0x22);
1430 gpio_i2c_write(chipaddr, 0xCD, 0x56); //148.5MHz clock
1431 gpio_i2c_write(chipaddr, 0xCE, 0x56); //148.5MHz clock
1432 } else {
1433 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1434 gpio_i2c_write(chipaddr, 0xC0+portsel*4, 0xdc);
1435 gpio_i2c_write(chipaddr, 0xC1+portsel*4, 0xdc);
1436 gpio_i2c_write(chipaddr, 0xC2+portsel*4, 0x54);
1437 gpio_i2c_write(chipaddr, 0xC3+portsel*4, 0x54);
1438 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x00);
1439 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x06); //74.25MHz clock
1440 }
1441 break;
1442 case NVP6158_OUTMODE_4MUX_BT1120S:
1443 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1444 gpio_i2c_write(chipaddr, 0x56, 0x32);
1445 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1446 if (nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1447 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1448 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1449 gpio_i2c_write(chipaddr, 0xC2, 0x54);
1450 gpio_i2c_write(chipaddr, 0xC3, 0x76);
1451 gpio_i2c_write(chipaddr, 0xC4, 0xdc);
1452 gpio_i2c_write(chipaddr, 0xC5, 0xfe);
1453 gpio_i2c_write(chipaddr, 0xC8, 0x88);
1454 gpio_i2c_write(chipaddr, 0xC9, 0x88);
1455
1456 //single edge
1457 gpio_i2c_write(chipaddr, 0xCD, 0x46); //148.5MHz clock
1458 gpio_i2c_write(chipaddr, 0xCE, 0x46); //148.5MHz clock
1459 // //dual_edge
1460 // gpio_i2c_write(chipaddr, 0xCD, 0x06); //74.25MHz clock
1461 // gpio_i2c_write(chipaddr, 0xCE, 0x06); //74.25MHz clock
1462 } else {
1463 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1464 gpio_i2c_write(chipaddr, 0xC0+portsel*4, 0xdc);
1465 gpio_i2c_write(chipaddr, 0xC1+portsel*4, 0xfe);
1466 gpio_i2c_write(chipaddr, 0xC2+portsel*4, 0x54);
1467 gpio_i2c_write(chipaddr, 0xC3+portsel*4, 0x76);
1468 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x88);
1469 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x58); //148.5MHz clock
1470 }
1471 break;
1472 case NVP6158_OUTMODE_4MUX_BT1120S_DDR:
1473 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1474 gpio_i2c_write(chipaddr, 0x56, 0x32);
1475 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1476 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1477 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1478 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1479 gpio_i2c_write(chipaddr, 0xC2, 0x54);
1480 gpio_i2c_write(chipaddr, 0xC3, 0x76);
1481 gpio_i2c_write(chipaddr, 0xC4, 0xdc);
1482 gpio_i2c_write(chipaddr, 0xC5, 0xfe);
1483 gpio_i2c_write(chipaddr, 0xC8, 0x88);
1484 gpio_i2c_write(chipaddr, 0xC9, 0x88);
1485 //dual_edge
1486 gpio_i2c_write(chipaddr, 0xCD, 0x06); //74.25MHz clock
1487 gpio_i2c_write(chipaddr, 0xCE, 0x06); //74.25MHz clock
1488 } else {
1489 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1490 gpio_i2c_write(chipaddr, 0xC0+portsel*4, 0xdc);
1491 gpio_i2c_write(chipaddr, 0xC1+portsel*4, 0xfe);
1492 gpio_i2c_write(chipaddr, 0xC2+portsel*4, 0x54);
1493 gpio_i2c_write(chipaddr, 0xC3+portsel*4, 0x76);
1494 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x88);
1495 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x58); //148.5MHz clock
1496 }
1497 break;
1498
1499 case NVP6158_OUTMODE_4MUX_BT1120S_1080P:
1500 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1501 gpio_i2c_write(chipaddr, 0x56, 0x32);
1502 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1503 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1504 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1505 //6158C makes 2 bt656 ports to 1 bt1120 port. portsel=[1,2] to choose clock.
1506 gpio_i2c_write(chipaddr, 0xC2, 0x54);
1507 gpio_i2c_write(chipaddr, 0xC3, 0x76);
1508 gpio_i2c_write(chipaddr, 0xC4, 0xdc);
1509 gpio_i2c_write(chipaddr, 0xC5, 0xfe);
1510 gpio_i2c_write(chipaddr, 0xC8, 0x88);
1511 gpio_i2c_write(chipaddr, 0xC9, 0x88);
1512 gpio_i2c_write(chipaddr, 0xCD, 0x40); //148.5MHz clock
1513 gpio_i2c_write(chipaddr, 0xCE, 0x40); //148.5MHz clock
1514 } else {
1515 //6158 makes 4 bt656 ports to 2 bt1120 port. portsel=[0,1] to choose clock.
1516 gpio_i2c_write(chipaddr, 0xC0+portsel*4, 0xdc);
1517 gpio_i2c_write(chipaddr, 0xC1+portsel*4, 0xfe);
1518 gpio_i2c_write(chipaddr, 0xC2+portsel*4, 0x54);
1519 gpio_i2c_write(chipaddr, 0xC3+portsel*4, 0x76);
1520 gpio_i2c_write(chipaddr, 0xC8+(portsel), 0x88);
1521 gpio_i2c_write(chipaddr, 0xCC+portsel*2, 0x58); //148.5MHz clock
1522 }
1523 break;
1524 case NVP6158_OUTMODE_1MUX_297MHz:
1525 /*1MUX data output, Pclk 297MHZ*/
1526 gpio_i2c_write(chipaddr, 0xFF, 0x00);
1527 gpio_i2c_write(chipaddr, 0x56, 0x10);
1528 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1529 gpio_i2c_write(chipaddr, 0xC0+portsel*2, (chid<<4)|chid); /* Port selection */
1530 gpio_i2c_write(chipaddr, 0xC1+portsel*2, (chid<<4)|chid); /* Port selection */
1531 tmp = gpio_i2c_read(chipaddr, 0xC8+(portsel/2)) & (portsel%2?0x0F:0xF0);
1532 gpio_i2c_write(chipaddr, 0xC8+(portsel/2), tmp);
1533 gpio_i2c_write(chipaddr, 0xCC+portsel, 0x66);
1534 break;
1535 default:
1536 printk("portmode %d not supported yet\n", portmode);
1537 break;
1538 }
1539
1540 printk("nvp6158(b)_set_portmode portsel %d portmode %d setting\n", portsel, portmode);
1541
1542 if(portmode==NVP6158_OUTMODE_2MUX_SD ||\
1543 portmode==NVP6158_OUTMODE_4MUX_SD ||\
1544 portmode==NVP6158_OUTMODE_2MUX_HD ||\
1545 portmode==NVP6158_OUTMODE_2MUX_MIX ||\
1546 portmode==NVP6158_OUTMODE_2MUX_BT1120S ||\
1547 portmode==NVP6158_OUTMODE_2MUX_BT1120S_720P ||\
1548 portmode==NVP6158_OUTMODE_2MUX_BT1120S_1080P ||\
1549 portmode==NVP6158_OUTMODE_4MUX_BT1120S) {
1550 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1551 gpio_i2c_write(chipaddr, 0xA0+portsel, 0x20); //TM clock mode sel manual
1552 printk("TM clock mode sel manual mode \n");
1553
1554 } else {
1555 gpio_i2c_write(chipaddr, 0xFF, 0x01);
1556 gpio_i2c_write(chipaddr, 0xA0+portsel, 0x00); //TM clock mode sel auto
1557 printk("TM clock mode sel auto mode \n");
1558 }
1559
1560 return 0;
1561 }
1562
1563
1564 /*
1565 chip:0~3
1566 portsel: 6158b/c->1/2, 6158->0~3
1567 enclk: enable clock pin, 1:enable,0:disable;
1568 endata: enable data port, 1:enable,0:disable;
1569 */
nvp6158_set_portcontrol(const unsigned char chip,const unsigned char portsel,const unsigned char enclk,const unsigned char endata)1570 void nvp6158_set_portcontrol(const unsigned char chip, const unsigned char portsel,
1571 const unsigned char enclk, const unsigned char endata)
1572 {
1573 unsigned char reg_portctl;
1574 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x01);
1575 reg_portctl = gpio_i2c_read(nvp6158_iic_addr[chip], 0xCA);
1576 if(nvp6158_chip_id[chip] == NVP6158C_R0_ID ||
1577 nvp6158_chip_id[chip] == NVP6168C_R0_ID) {
1578 if(enclk == 1)
1579 _SET_BIT(reg_portctl, (portsel+5));
1580 else
1581 _CLE_BIT(reg_portctl, (portsel+5));
1582
1583 if(endata == 1)
1584 _SET_BIT(reg_portctl, portsel);
1585 else
1586 _CLE_BIT(reg_portctl, portsel);
1587 } else if(nvp6158_chip_id[chip] == NVP6158_R0_ID) {
1588 if(enclk == 1)
1589 _SET_BIT(reg_portctl, (portsel+4));
1590 else
1591 _CLE_BIT(reg_portctl, (portsel+4));
1592
1593 if(endata == 1)
1594 _SET_BIT(reg_portctl, portsel);
1595 else
1596 _CLE_BIT(reg_portctl, portsel);
1597 }
1598 }
1599
NVP6158_GetFmtStd_from_Fmtdef(NC_VIVO_CH_FORMATDEF vivofmt)1600 NC_FORMAT_STANDARD NVP6158_GetFmtStd_from_Fmtdef(NC_VIVO_CH_FORMATDEF vivofmt)
1601 {
1602 NC_FORMAT_STANDARD vformat_std= FMT_STD_UNKNOWN;
1603 if((vivofmt>=AHD20_SD_H960_NT) && (vivofmt<=AHD20_SD_H960_2EX_Btype_PAL))
1604 vformat_std = FMT_SD;
1605 else if((vivofmt>=CVI_FHD_30P) && (vivofmt<=CVI_8M_12_5P))
1606 vformat_std = FMT_CVI;
1607 else if((vivofmt>=TVI_FHD_30P) && (vivofmt<=TVI_8M_12_5P))
1608 vformat_std = FMT_TVI;
1609 else if((vivofmt>=AHD20_1080P_60P) && (vivofmt<=AHD20_720P_25P_EX_Btype))
1610 vformat_std = FMT_AHD20;
1611 else if((vivofmt>=AHD30_4M_30P) && (vivofmt<=AHD30_8M_15P))
1612 vformat_std = FMT_AHD30;
1613 else
1614 vformat_std = FMT_STD_UNKNOWN;
1615 return vformat_std;
1616 }
1617
nvp6158_additional_for3MoverDef(unsigned char chip)1618 void nvp6158_additional_for3MoverDef(unsigned char chip)
1619 {
1620 unsigned char ch = 0;
1621
1622 for(ch = 0; ch < 4; ch++) {
1623 gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x0a + (ch / 2));
1624
1625 gpio_i2c_write(nvp6158_iic_addr[chip], 0x00 + ( 0x80 * (ch % 2)), 0x80 );
1626 gpio_i2c_write(nvp6158_iic_addr[chip], 0x01 + ( 0x80 * (ch % 2)), 0x02 );
1627 gpio_i2c_write(nvp6158_iic_addr[chip], 0x02 + ( 0x80 * (ch % 2)), 0x04 );
1628 gpio_i2c_write(nvp6158_iic_addr[chip], 0x03 + ( 0x80 * (ch % 2)), 0x80 );
1629 gpio_i2c_write(nvp6158_iic_addr[chip], 0x04 + ( 0x80 * (ch % 2)), 0x06 );
1630 gpio_i2c_write(nvp6158_iic_addr[chip], 0x05 + ( 0x80 * (ch % 2)), 0x07 );
1631 gpio_i2c_write(nvp6158_iic_addr[chip], 0x06 + ( 0x80 * (ch % 2)), 0x80 );
1632 gpio_i2c_write(nvp6158_iic_addr[chip], 0x07 + ( 0x80 * (ch % 2)), 0x07 );
1633 gpio_i2c_write(nvp6158_iic_addr[chip], 0x08 + ( 0x80 * (ch % 2)), 0x03 );
1634 gpio_i2c_write(nvp6158_iic_addr[chip], 0x09 + ( 0x80 * (ch % 2)), 0x08 );
1635 gpio_i2c_write(nvp6158_iic_addr[chip], 0x0a + ( 0x80 * (ch % 2)), 0x04 );
1636 gpio_i2c_write(nvp6158_iic_addr[chip], 0x0b + ( 0x80 * (ch % 2)), 0x10 );
1637 gpio_i2c_write(nvp6158_iic_addr[chip], 0x0c + ( 0x80 * (ch % 2)), 0x08 );
1638 gpio_i2c_write(nvp6158_iic_addr[chip], 0x0d + ( 0x80 * (ch % 2)), 0x1f );
1639 gpio_i2c_write(nvp6158_iic_addr[chip], 0x0e + ( 0x80 * (ch % 2)), 0x2e );
1640 gpio_i2c_write(nvp6158_iic_addr[chip], 0x0f + ( 0x80 * (ch % 2)), 0x08 );
1641 gpio_i2c_write(nvp6158_iic_addr[chip], 0x10 + ( 0x80 * (ch % 2)), 0x38 );
1642 gpio_i2c_write(nvp6158_iic_addr[chip], 0x11 + ( 0x80 * (ch % 2)), 0x35 );
1643 gpio_i2c_write(nvp6158_iic_addr[chip], 0x12 + ( 0x80 * (ch % 2)), 0x00 );
1644 gpio_i2c_write(nvp6158_iic_addr[chip], 0x13 + ( 0x80 * (ch % 2)), 0x20 );
1645 gpio_i2c_write(nvp6158_iic_addr[chip], 0x14 + ( 0x80 * (ch % 2)), 0x0d );
1646 gpio_i2c_write(nvp6158_iic_addr[chip], 0x15 + ( 0x80 * (ch % 2)), 0x80 );
1647 gpio_i2c_write(nvp6158_iic_addr[chip], 0x16 + ( 0x80 * (ch % 2)), 0x54 );
1648 gpio_i2c_write(nvp6158_iic_addr[chip], 0x17 + ( 0x80 * (ch % 2)), 0xb1 );
1649 gpio_i2c_write(nvp6158_iic_addr[chip], 0x18 + ( 0x80 * (ch % 2)), 0x91 );
1650 gpio_i2c_write(nvp6158_iic_addr[chip], 0x19 + ( 0x80 * (ch % 2)), 0x1c );
1651 gpio_i2c_write(nvp6158_iic_addr[chip], 0x1a + ( 0x80 * (ch % 2)), 0x87 );
1652 gpio_i2c_write(nvp6158_iic_addr[chip], 0x1b + ( 0x80 * (ch % 2)), 0x92 );
1653 gpio_i2c_write(nvp6158_iic_addr[chip], 0x1c + ( 0x80 * (ch % 2)), 0xe2 );
1654 gpio_i2c_write(nvp6158_iic_addr[chip], 0x1d + ( 0x80 * (ch % 2)), 0x20 );
1655 gpio_i2c_write(nvp6158_iic_addr[chip], 0x1e + ( 0x80 * (ch % 2)), 0xd0 );
1656 gpio_i2c_write(nvp6158_iic_addr[chip], 0x1f + ( 0x80 * (ch % 2)), 0xcc );
1657 }
1658 }
1659
nvp6158_video_powerdown(unsigned char ch)1660 void nvp6158_video_powerdown(unsigned char ch)
1661 {
1662 unsigned char val_0x00; //video afe;
1663 unsigned char val_1x97; //clock;
1664 unsigned char val_1x98; //channel;
1665 unsigned char chip = ch / 4;
1666
1667 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x00);
1668 val_0x00 = gpio_i2c_read(nvp6158_iic_addr[chip], 0x00+(ch%4));
1669 gpio_i2c_write(nvp6158_iic_addr[chip], 0x00+(ch%4), (val_0x00|0x01));
1670
1671 gpio_i2c_write(nvp6158_iic_addr[chip], 0xFF, 0x01);
1672 val_1x97 = gpio_i2c_read(nvp6158_iic_addr[chip], 0x97);
1673 gpio_i2c_write(nvp6158_iic_addr[chip], 0x97, (val_1x97&(~(0x01<<(ch%4)))));
1674
1675 val_1x98 = gpio_i2c_read(nvp6158_iic_addr[chip], 0x98);
1676 gpio_i2c_write(nvp6158_iic_addr[chip], 0x98, (val_1x98|(0x01<<(ch%4))));
1677 printk(">>>>%s CH[%d] been setted to powerdown mode\n", __func__, ch);
1678 }
1679
1680 /********************************************************************************
1681 * End of file
1682 ********************************************************************************/
1683