1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd 4 * 5 * author: 6 * Herman Chen <herman.chen@rock-chips.com> 7 * 8 */ 9 #ifndef __ROCKCHIP_MPP_RKVDEC2_H__ 10 #define __ROCKCHIP_MPP_RKVDEC2_H__ 11 12 #include <linux/dma-iommu.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_platform.h> 15 #include <linux/of_address.h> 16 #include <linux/slab.h> 17 #include <linux/uaccess.h> 18 #include <linux/regmap.h> 19 #include <linux/kernel.h> 20 #include <linux/thermal.h> 21 #include <linux/notifier.h> 22 #include <linux/proc_fs.h> 23 #include <linux/nospec.h> 24 #include <linux/rockchip/rockchip_sip.h> 25 #include <linux/regulator/consumer.h> 26 27 #include <soc/rockchip/pm_domains.h> 28 #include <soc/rockchip/rockchip_sip.h> 29 30 #include "mpp_debug.h" 31 #include "mpp_common.h" 32 #include "mpp_iommu.h" 33 34 #define RKVDEC_DRIVER_NAME "mpp_rkvdec2" 35 36 #define RKVDEC_REG_IMPORTANT_BASE 0x2c 37 #define RKVDEC_REG_IMPORTANT_INDEX 11 38 #define RKVDEC_SOFTREST_EN BIT(20) 39 40 #define RKVDEC_SESSION_MAX_BUFFERS 40 41 /* The maximum registers number of all the version */ 42 #define RKVDEC_REG_NUM 279 43 #define RKVDEC_REG_HW_ID_INDEX 0 44 #define RKVDEC_REG_START_INDEX 0 45 #define RKVDEC_REG_END_INDEX 278 46 47 #define REVDEC_GET_PROD_NUM(x) (((x) >> 16) & 0xffff) 48 #define RKVDEC_REG_FORMAT_INDEX 9 49 #define RKVDEC_GET_FORMAT(x) ((x) & 0x3ff) 50 51 #define RKVDEC_REG_START_EN_BASE 0x28 52 53 #define RKVDEC_REG_START_EN_INDEX 10 54 55 #define RKVDEC_START_EN BIT(0) 56 57 #define RKVDEC_REG_YSTRIDE_INDEX 20 58 #define RKVDEC_REG_CORE_CTRL_INDEX 28 59 #define RKVDEC_REG_FILM_IDX_MASK (0x3ff0000) 60 61 #define RKVDEC_REG_RLC_BASE 0x200 62 #define RKVDEC_REG_RLC_BASE_INDEX (128) 63 64 #define RKVDEC_REG_INT_EN 0x380 65 #define RKVDEC_REG_INT_EN_INDEX (224) 66 #define RKVDEC_SOFT_RESET_READY BIT(9) 67 #define RKVDEC_CABAC_END_STA BIT(8) 68 #define RKVDEC_COLMV_REF_ERR_STA BIT(7) 69 #define RKVDEC_BUF_EMPTY_STA BIT(6) 70 #define RKVDEC_TIMEOUT_STA BIT(5) 71 #define RKVDEC_ERROR_STA BIT(4) 72 #define RKVDEC_BUS_STA BIT(3) 73 #define RKVDEC_READY_STA BIT(2) 74 #define RKVDEC_IRQ_RAW BIT(1) 75 #define RKVDEC_IRQ BIT(0) 76 #define RKVDEC_INT_ERROR_MASK (RKVDEC_COLMV_REF_ERR_STA |\ 77 RKVDEC_BUF_EMPTY_STA |\ 78 RKVDEC_TIMEOUT_STA |\ 79 RKVDEC_ERROR_STA) 80 #define RKVDEC_PERF_WORKING_CNT 0x41c 81 82 /* perf sel reference register */ 83 #define RKVDEC_PERF_SEL_OFFSET 0x20000 84 #define RKVDEC_PERF_SEL_NUM 64 85 #define RKVDEC_PERF_SEL_BASE 0x424 86 #define RKVDEC_SEL_VAL0_BASE 0x428 87 #define RKVDEC_SEL_VAL1_BASE 0x42c 88 #define RKVDEC_SEL_VAL2_BASE 0x430 89 #define RKVDEC_SET_PERF_SEL(a, b, c) ((a) | ((b) << 8) | ((c) << 16)) 90 91 /* cache reference register */ 92 #define RKVDEC_REG_CACHE0_SIZE_BASE 0x51c 93 #define RKVDEC_REG_CACHE1_SIZE_BASE 0x55c 94 #define RKVDEC_REG_CACHE2_SIZE_BASE 0x59c 95 #define RKVDEC_REG_CLR_CACHE0_BASE 0x510 96 #define RKVDEC_REG_CLR_CACHE1_BASE 0x550 97 #define RKVDEC_REG_CLR_CACHE2_BASE 0x590 98 99 #define RKVDEC_CACHE_PERMIT_CACHEABLE_ACCESS BIT(0) 100 #define RKVDEC_CACHE_PERMIT_READ_ALLOCATE BIT(1) 101 #define RKVDEC_CACHE_LINE_SIZE_64_BYTES BIT(4) 102 103 #define to_rkvdec2_task(task) \ 104 container_of(task, struct rkvdec2_task, mpp_task) 105 #define to_rkvdec2_dev(dev) \ 106 container_of(dev, struct rkvdec2_dev, mpp) 107 108 enum RKVDEC_FMT { 109 RKVDEC_FMT_H265D = 0, 110 RKVDEC_FMT_H264D = 1, 111 RKVDEC_FMT_VP9D = 2, 112 RKVDEC_FMT_AVS2 = 3, 113 }; 114 115 #define RKVDEC_MAX_RCB_NUM (16) 116 117 struct rcb_info_elem { 118 u32 index; 119 u32 size; 120 }; 121 122 struct rkvdec2_rcb_info { 123 u32 cnt; 124 struct rcb_info_elem elem[RKVDEC_MAX_RCB_NUM]; 125 }; 126 127 struct rkvdec2_task { 128 struct mpp_task mpp_task; 129 130 enum MPP_CLOCK_MODE clk_mode; 131 u32 reg[RKVDEC_REG_NUM]; 132 struct reg_offset_info off_inf; 133 134 /* perf sel data back */ 135 u32 reg_sel[RKVDEC_PERF_SEL_NUM]; 136 137 u32 strm_addr; 138 u32 irq_status; 139 /* req for current task */ 140 u32 w_req_cnt; 141 struct mpp_request w_reqs[MPP_MAX_MSG_NUM]; 142 u32 r_req_cnt; 143 struct mpp_request r_reqs[MPP_MAX_MSG_NUM]; 144 /* image info */ 145 u32 width; 146 u32 height; 147 u32 pixels; 148 149 /* task index for link table rnunning list */ 150 int slot_idx; 151 u32 need_hack; 152 153 /* link table DMA buffer */ 154 struct mpp_dma_buffer *table; 155 }; 156 157 struct rkvdec2_session_priv { 158 /* codec info from user */ 159 struct { 160 /* show mode */ 161 u32 flag; 162 /* item data */ 163 u64 val; 164 } codec_info[DEC_INFO_BUTT]; 165 /* rcb_info for sram */ 166 struct rkvdec2_rcb_info rcb_inf; 167 }; 168 169 struct rkvdec2_dev { 170 struct mpp_dev mpp; 171 /* sip smc reset lock */ 172 struct mutex sip_reset_lock; 173 174 struct mpp_clk_info aclk_info; 175 struct mpp_clk_info hclk_info; 176 struct mpp_clk_info core_clk_info; 177 struct mpp_clk_info cabac_clk_info; 178 struct mpp_clk_info hevc_cabac_clk_info; 179 struct mpp_clk_info *cycle_clk; 180 181 u32 default_max_load; 182 #ifdef CONFIG_ROCKCHIP_MPP_PROC_FS 183 struct proc_dir_entry *procfs; 184 #endif 185 struct reset_control *rst_a; 186 struct reset_control *rst_h; 187 struct reset_control *rst_niu_a; 188 struct reset_control *rst_niu_h; 189 struct reset_control *rst_core; 190 struct reset_control *rst_cabac; 191 struct reset_control *rst_hevc_cabac; 192 193 #ifdef CONFIG_PM_DEVFREQ 194 struct regulator *vdd; 195 struct devfreq *devfreq; 196 unsigned long volt; 197 unsigned long core_rate_hz; 198 unsigned long core_last_rate_hz; 199 struct ipa_power_model_data *model_data; 200 struct thermal_cooling_device *devfreq_cooling; 201 struct monitor_dev_info *mdev_info; 202 #endif 203 204 /* internal rcb-memory */ 205 u32 sram_size; 206 u32 rcb_size; 207 dma_addr_t rcb_iova; 208 struct page *rcb_page; 209 u32 rcb_min_width; 210 u32 rcb_info_count; 211 u32 rcb_infos[RKVDEC_MAX_RCB_NUM * 2]; 212 213 /* for link mode */ 214 struct rkvdec_link_dev *link_dec; 215 struct mpp_dma_buffer *fix; 216 217 /* for ccu link mode */ 218 struct rkvdec2_ccu *ccu; 219 u32 core_mask; 220 u32 task_index; 221 /* mmu info */ 222 void __iomem *mmu_base; 223 u32 fault_iova; 224 u32 mmu_fault; 225 u32 mmu0_st; 226 u32 mmu1_st; 227 u32 mmu0_pta; 228 u32 mmu1_pta; 229 }; 230 231 int mpp_set_rcbbuf(struct mpp_dev *mpp, struct mpp_session *session, 232 struct mpp_task *task); 233 int rkvdec2_task_init(struct mpp_dev *mpp, struct mpp_session *session, 234 struct rkvdec2_task *task, struct mpp_task_msgs *msgs); 235 void *rkvdec2_alloc_task(struct mpp_session *session, 236 struct mpp_task_msgs *msgs); 237 int rkvdec2_free_task(struct mpp_session *session, struct mpp_task *mpp_task); 238 239 int rkvdec2_free_session(struct mpp_session *session); 240 241 int rkvdec2_result(struct mpp_dev *mpp, struct mpp_task *mpp_task, 242 struct mpp_task_msgs *msgs); 243 int rkvdec2_reset(struct mpp_dev *mpp); 244 245 void mpp_devfreq_set_core_rate(struct mpp_dev *mpp, enum MPP_CLOCK_MODE mode); 246 247 #endif 248