1 /*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/arch/device.h>
9 #include <asm/arch/msg_port.h>
10 #include <asm/arch/quark.h>
11
msg_port_setup(int op,int port,int reg)12 void msg_port_setup(int op, int port, int reg)
13 {
14 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
15 (((op) << 24) | ((port) << 16) |
16 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
17 }
18
msg_port_read(u8 port,u32 reg)19 u32 msg_port_read(u8 port, u32 reg)
20 {
21 u32 value;
22
23 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
24 reg & 0xffffff00);
25 msg_port_setup(MSG_OP_READ, port, reg);
26 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
27
28 return value;
29 }
30
msg_port_write(u8 port,u32 reg,u32 value)31 void msg_port_write(u8 port, u32 reg, u32 value)
32 {
33 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
34 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
35 reg & 0xffffff00);
36 msg_port_setup(MSG_OP_WRITE, port, reg);
37 }
38
msg_port_alt_read(u8 port,u32 reg)39 u32 msg_port_alt_read(u8 port, u32 reg)
40 {
41 u32 value;
42
43 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
44 reg & 0xffffff00);
45 msg_port_setup(MSG_OP_ALT_READ, port, reg);
46 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
47
48 return value;
49 }
50
msg_port_alt_write(u8 port,u32 reg,u32 value)51 void msg_port_alt_write(u8 port, u32 reg, u32 value)
52 {
53 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
54 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
55 reg & 0xffffff00);
56 msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
57 }
58
msg_port_io_read(u8 port,u32 reg)59 u32 msg_port_io_read(u8 port, u32 reg)
60 {
61 u32 value;
62
63 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
64 reg & 0xffffff00);
65 msg_port_setup(MSG_OP_IO_READ, port, reg);
66 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
67
68 return value;
69 }
70
msg_port_io_write(u8 port,u32 reg,u32 value)71 void msg_port_io_write(u8 port, u32 reg, u32 value)
72 {
73 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
74 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
75 reg & 0xffffff00);
76 msg_port_setup(MSG_OP_IO_WRITE, port, reg);
77 }
78