1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44 #include <linux/android_kabi.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /*
54 * The PCI interface treats multi-function devices as independent
55 * devices. The slot/function address of each device is encoded
56 * in a single byte as follows:
57 *
58 * 7:3 = slot
59 * 2:0 = function
60 *
61 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
62 * In the interest of not exposing interfaces to user-space unnecessarily,
63 * the following kernel-only defines are being added here.
64 */
65 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
66 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
67 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68
69 /* pci_slot represents a physical slot */
70 struct pci_slot {
71 struct pci_bus *bus; /* Bus this slot is on */
72 struct list_head list; /* Node in list of slots */
73 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
74 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
75 struct kobject kobj;
76 };
77
pci_slot_name(const struct pci_slot * slot)78 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 {
80 return kobject_name(&slot->kobj);
81 }
82
83 /* File state for mmap()s on /proc/bus/pci/X/Y */
84 enum pci_mmap_state {
85 pci_mmap_io,
86 pci_mmap_mem
87 };
88
89 /* For PCI devices, the region numbers are assigned this way: */
90 enum {
91 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCES,
93 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94
95 /* #6: expansion ROM resource */
96 PCI_ROM_RESOURCE,
97
98 /* Device-specific resources */
99 #ifdef CONFIG_PCI_IOV
100 PCI_IOV_RESOURCES,
101 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
102 #endif
103
104 /* PCI-to-PCI (P2P) bridge windows */
105 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
106 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
107 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
108
109 /* CardBus bridge windows */
110 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
113 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
114
115 /* Total number of bridge resources for P2P and CardBus */
116 #define PCI_BRIDGE_RESOURCE_NUM 4
117
118 /* Resources assigned to buses behind the bridge */
119 PCI_BRIDGE_RESOURCES,
120 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
121 PCI_BRIDGE_RESOURCE_NUM - 1,
122
123 /* Total resources associated with a PCI device */
124 PCI_NUM_RESOURCES,
125
126 /* Preserve this for compatibility */
127 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
128 };
129
130 /**
131 * enum pci_interrupt_pin - PCI INTx interrupt values
132 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
133 * @PCI_INTERRUPT_INTA: PCI INTA pin
134 * @PCI_INTERRUPT_INTB: PCI INTB pin
135 * @PCI_INTERRUPT_INTC: PCI INTC pin
136 * @PCI_INTERRUPT_INTD: PCI INTD pin
137 *
138 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
139 * PCI_INTERRUPT_PIN register.
140 */
141 enum pci_interrupt_pin {
142 PCI_INTERRUPT_UNKNOWN,
143 PCI_INTERRUPT_INTA,
144 PCI_INTERRUPT_INTB,
145 PCI_INTERRUPT_INTC,
146 PCI_INTERRUPT_INTD,
147 };
148
149 /* The number of legacy PCI INTx interrupts */
150 #define PCI_NUM_INTX 4
151
152 /*
153 * pci_power_t values must match the bits in the Capabilities PME_Support
154 * and Control/Status PowerState fields in the Power Management capability.
155 */
156 typedef int __bitwise pci_power_t;
157
158 #define PCI_D0 ((pci_power_t __force) 0)
159 #define PCI_D1 ((pci_power_t __force) 1)
160 #define PCI_D2 ((pci_power_t __force) 2)
161 #define PCI_D3hot ((pci_power_t __force) 3)
162 #define PCI_D3cold ((pci_power_t __force) 4)
163 #define PCI_UNKNOWN ((pci_power_t __force) 5)
164 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
165
166 /* Remember to update this when the list above changes! */
167 extern const char *pci_power_names[];
168
pci_power_name(pci_power_t state)169 static inline const char *pci_power_name(pci_power_t state)
170 {
171 return pci_power_names[1 + (__force int) state];
172 }
173
174 /**
175 * typedef pci_channel_state_t
176 *
177 * The pci_channel state describes connectivity between the CPU and
178 * the PCI device. If some PCI bus between here and the PCI device
179 * has crashed or locked up, this info is reflected here.
180 */
181 typedef unsigned int __bitwise pci_channel_state_t;
182
183 enum {
184 /* I/O channel is in normal state */
185 pci_channel_io_normal = (__force pci_channel_state_t) 1,
186
187 /* I/O to channel is blocked */
188 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
189
190 /* PCI card is dead */
191 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
192 };
193
194 typedef unsigned int __bitwise pcie_reset_state_t;
195
196 enum pcie_reset_state {
197 /* Reset is NOT asserted (Use to deassert reset) */
198 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
199
200 /* Use #PERST to reset PCIe device */
201 pcie_warm_reset = (__force pcie_reset_state_t) 2,
202
203 /* Use PCIe Hot Reset to reset device */
204 pcie_hot_reset = (__force pcie_reset_state_t) 3
205 };
206
207 typedef unsigned short __bitwise pci_dev_flags_t;
208 enum pci_dev_flags {
209 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
210 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
211 /* Device configuration is irrevocably lost if disabled into D3 */
212 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
213 /* Provide indication device is assigned by a Virtual Machine Manager */
214 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
215 /* Flag for quirk use to store if quirk-specific ACS is enabled */
216 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
217 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
218 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
219 /* Do not use bus resets for device */
220 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
221 /* Do not use PM reset even if device advertises NoSoftRst- */
222 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
223 /* Get VPD from function 0 VPD */
224 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
225 /* A non-root bridge where translation occurs, stop alias search here */
226 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
227 /* Do not use FLR even if device advertises PCI_AF_CAP */
228 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
229 /* Don't use Relaxed Ordering for TLPs directed at this device */
230 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
231 /* Device does honor MSI masking despite saying otherwise */
232 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
233 };
234
235 enum pci_irq_reroute_variant {
236 INTEL_IRQ_REROUTE_VARIANT = 1,
237 MAX_IRQ_REROUTE_VARIANTS = 3
238 };
239
240 typedef unsigned short __bitwise pci_bus_flags_t;
241 enum pci_bus_flags {
242 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
243 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
244 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
245 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
246 };
247
248 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
249 enum pcie_link_width {
250 PCIE_LNK_WIDTH_RESRV = 0x00,
251 PCIE_LNK_X1 = 0x01,
252 PCIE_LNK_X2 = 0x02,
253 PCIE_LNK_X4 = 0x04,
254 PCIE_LNK_X8 = 0x08,
255 PCIE_LNK_X12 = 0x0c,
256 PCIE_LNK_X16 = 0x10,
257 PCIE_LNK_X32 = 0x20,
258 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
259 };
260
261 /* See matching string table in pci_speed_string() */
262 enum pci_bus_speed {
263 PCI_SPEED_33MHz = 0x00,
264 PCI_SPEED_66MHz = 0x01,
265 PCI_SPEED_66MHz_PCIX = 0x02,
266 PCI_SPEED_100MHz_PCIX = 0x03,
267 PCI_SPEED_133MHz_PCIX = 0x04,
268 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
269 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
270 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
271 PCI_SPEED_66MHz_PCIX_266 = 0x09,
272 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
273 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
274 AGP_UNKNOWN = 0x0c,
275 AGP_1X = 0x0d,
276 AGP_2X = 0x0e,
277 AGP_4X = 0x0f,
278 AGP_8X = 0x10,
279 PCI_SPEED_66MHz_PCIX_533 = 0x11,
280 PCI_SPEED_100MHz_PCIX_533 = 0x12,
281 PCI_SPEED_133MHz_PCIX_533 = 0x13,
282 PCIE_SPEED_2_5GT = 0x14,
283 PCIE_SPEED_5_0GT = 0x15,
284 PCIE_SPEED_8_0GT = 0x16,
285 PCIE_SPEED_16_0GT = 0x17,
286 PCIE_SPEED_32_0GT = 0x18,
287 PCI_SPEED_UNKNOWN = 0xff,
288 };
289
290 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
291 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
292
293 struct pci_cap_saved_data {
294 u16 cap_nr;
295 bool cap_extended;
296 unsigned int size;
297 u32 data[];
298 };
299
300 struct pci_cap_saved_state {
301 struct hlist_node next;
302 struct pci_cap_saved_data cap;
303 };
304
305 struct irq_affinity;
306 struct pcie_link_state;
307 struct pci_vpd;
308 struct pci_sriov;
309 struct pci_p2pdma;
310
311 /* The pci_dev structure describes PCI devices */
312 struct pci_dev {
313 struct list_head bus_list; /* Node in per-bus list */
314 struct pci_bus *bus; /* Bus this device is on */
315 struct pci_bus *subordinate; /* Bus this device bridges to */
316
317 void *sysdata; /* Hook for sys-specific extension */
318 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
319 struct pci_slot *slot; /* Physical slot this device is in */
320
321 unsigned int devfn; /* Encoded device & function index */
322 unsigned short vendor;
323 unsigned short device;
324 unsigned short subsystem_vendor;
325 unsigned short subsystem_device;
326 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
327 u8 revision; /* PCI revision, low byte of class word */
328 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
329 #ifdef CONFIG_PCIEAER
330 u16 aer_cap; /* AER capability offset */
331 struct aer_stats *aer_stats; /* AER stats for this device */
332 #endif
333 u8 pcie_cap; /* PCIe capability offset */
334 u8 msi_cap; /* MSI capability offset */
335 u8 msix_cap; /* MSI-X capability offset */
336 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
337 u8 rom_base_reg; /* Config register controlling ROM */
338 u8 pin; /* Interrupt pin this device uses */
339 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
340 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
341
342 struct pci_driver *driver; /* Driver bound to this device */
343 u64 dma_mask; /* Mask of the bits of bus address this
344 device implements. Normally this is
345 0xffffffff. You only need to change
346 this if your device has broken DMA
347 or supports 64-bit transfers. */
348
349 struct device_dma_parameters dma_parms;
350
351 pci_power_t current_state; /* Current operating state. In ACPI,
352 this is D0-D3, D0 being fully
353 functional, and D3 being off. */
354 unsigned int imm_ready:1; /* Supports Immediate Readiness */
355 u8 pm_cap; /* PM capability offset */
356 unsigned int pme_support:5; /* Bitmask of states from which PME#
357 can be generated */
358 unsigned int pme_poll:1; /* Poll device's PME status bit */
359 unsigned int d1_support:1; /* Low power state D1 is supported */
360 unsigned int d2_support:1; /* Low power state D2 is supported */
361 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
362 unsigned int no_d3cold:1; /* D3cold is forbidden */
363 unsigned int bridge_d3:1; /* Allow D3 for bridge */
364 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
365 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
366 decoding during BAR sizing */
367 unsigned int wakeup_prepared:1;
368 unsigned int runtime_d3cold:1; /* Whether go through runtime
369 D3cold, not set for devices
370 powered on/off by the
371 corresponding bridge */
372 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
373 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
374 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
375 controlled exclusively by
376 user sysfs */
377 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
378 bit manually */
379 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
380 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
381
382 #ifdef CONFIG_PCIEASPM
383 struct pcie_link_state *link_state; /* ASPM link state */
384 unsigned int ltr_path:1; /* Latency Tolerance Reporting
385 supported from root to here */
386 int l1ss; /* L1SS Capability pointer */
387 #endif
388 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
389
390 pci_channel_state_t error_state; /* Current connectivity state */
391 struct device dev; /* Generic device interface */
392
393 int cfg_size; /* Size of config space */
394
395 /*
396 * Instead of touching interrupt line and base address registers
397 * directly, use the values stored here. They might be different!
398 */
399 unsigned int irq;
400 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
401
402 bool match_driver; /* Skip attaching driver */
403
404 unsigned int transparent:1; /* Subtractive decode bridge */
405 unsigned int io_window:1; /* Bridge has I/O window */
406 unsigned int pref_window:1; /* Bridge has pref mem window */
407 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
408 unsigned int multifunction:1; /* Multi-function device */
409
410 unsigned int is_busmaster:1; /* Is busmaster */
411 unsigned int no_msi:1; /* May not use MSI */
412 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
413 unsigned int block_cfg_access:1; /* Config space access blocked */
414 unsigned int broken_parity_status:1; /* Generates false positive parity */
415 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
416 unsigned int msi_enabled:1;
417 unsigned int msix_enabled:1;
418 unsigned int ari_enabled:1; /* ARI forwarding */
419 unsigned int ats_enabled:1; /* Address Translation Svc */
420 unsigned int pasid_enabled:1; /* Process Address Space ID */
421 unsigned int pri_enabled:1; /* Page Request Interface */
422 unsigned int is_managed:1;
423 unsigned int needs_freset:1; /* Requires fundamental reset */
424 unsigned int state_saved:1;
425 unsigned int is_physfn:1;
426 unsigned int is_virtfn:1;
427 unsigned int reset_fn:1;
428 unsigned int is_hotplug_bridge:1;
429 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
430 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
431 /*
432 * Devices marked being untrusted are the ones that can potentially
433 * execute DMA attacks and similar. They are typically connected
434 * through external ports such as Thunderbolt but not limited to
435 * that. When an IOMMU is enabled they should be getting full
436 * mappings to make sure they cannot access arbitrary memory.
437 */
438 unsigned int untrusted:1;
439 /*
440 * Info from the platform, e.g., ACPI or device tree, may mark a
441 * device as "external-facing". An external-facing device is
442 * itself internal but devices downstream from it are external.
443 */
444 unsigned int external_facing:1;
445 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
446 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
447 unsigned int irq_managed:1;
448 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
449 unsigned int is_probed:1; /* Device probing in progress */
450 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
451 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
452 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
453 pci_dev_flags_t dev_flags;
454 atomic_t enable_cnt; /* pci_enable_device has been called */
455
456 #ifdef CONFIG_NO_GKI
457 atomic_t sysfs_init_cnt; /* pci_create_sysfs_dev_files has been called */
458 #endif
459 u32 saved_config_space[16]; /* Config space saved at suspend time */
460 struct hlist_head saved_cap_space;
461 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
462 int rom_attr_enabled; /* Display of ROM attribute enabled? */
463 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
464 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
465
466 #ifdef CONFIG_HOTPLUG_PCI_PCIE
467 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
468 #endif
469 #ifdef CONFIG_PCIE_PTM
470 unsigned int ptm_root:1;
471 unsigned int ptm_enabled:1;
472 u8 ptm_granularity;
473 #endif
474 #ifdef CONFIG_PCI_MSI
475 const struct attribute_group **msi_irq_groups;
476 #endif
477 struct pci_vpd *vpd;
478 #ifdef CONFIG_PCIE_DPC
479 u16 dpc_cap;
480 unsigned int dpc_rp_extensions:1;
481 u8 dpc_rp_log_size;
482 #endif
483 #ifdef CONFIG_PCI_ATS
484 union {
485 struct pci_sriov *sriov; /* PF: SR-IOV info */
486 struct pci_dev *physfn; /* VF: related PF */
487 };
488 u16 ats_cap; /* ATS Capability offset */
489 u8 ats_stu; /* ATS Smallest Translation Unit */
490 #endif
491 #ifdef CONFIG_PCI_PRI
492 u16 pri_cap; /* PRI Capability offset */
493 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
494 unsigned int pasid_required:1; /* PRG Response PASID Required */
495 #endif
496 #ifdef CONFIG_PCI_PASID
497 u16 pasid_cap; /* PASID Capability offset */
498 u16 pasid_features;
499 #endif
500 #ifdef CONFIG_PCI_P2PDMA
501 struct pci_p2pdma *p2pdma;
502 #endif
503 u16 acs_cap; /* ACS Capability offset */
504 phys_addr_t rom; /* Physical address if not from BAR */
505 size_t romlen; /* Length if not from BAR */
506 char *driver_override; /* Driver name to force a match */
507
508 unsigned long priv_flags; /* Private flags for the PCI driver */
509
510 ANDROID_KABI_RESERVE(1);
511 ANDROID_KABI_RESERVE(2);
512 ANDROID_KABI_RESERVE(3);
513 ANDROID_KABI_RESERVE(4);
514 };
515
pci_physfn(struct pci_dev * dev)516 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
517 {
518 #ifdef CONFIG_PCI_IOV
519 if (dev->is_virtfn)
520 dev = dev->physfn;
521 #endif
522 return dev;
523 }
524
525 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
526
527 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
528 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
529
pci_channel_offline(struct pci_dev * pdev)530 static inline int pci_channel_offline(struct pci_dev *pdev)
531 {
532 return (pdev->error_state != pci_channel_io_normal);
533 }
534
535 struct pci_host_bridge {
536 struct device dev;
537 struct pci_bus *bus; /* Root bus */
538 struct pci_ops *ops;
539 struct pci_ops *child_ops;
540 void *sysdata;
541 int busnr;
542 struct list_head windows; /* resource_entry */
543 struct list_head dma_ranges; /* dma ranges resource list */
544 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
545 int (*map_irq)(const struct pci_dev *, u8, u8);
546 void (*release_fn)(struct pci_host_bridge *);
547 void *release_data;
548 struct msi_controller *msi;
549 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
550 unsigned int no_ext_tags:1; /* No Extended Tags */
551 unsigned int native_aer:1; /* OS may use PCIe AER */
552 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
553 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
554 unsigned int native_pme:1; /* OS may use PCIe PME */
555 unsigned int native_ltr:1; /* OS may use PCIe LTR */
556 unsigned int native_dpc:1; /* OS may use PCIe DPC */
557 unsigned int preserve_config:1; /* Preserve FW resource setup */
558 unsigned int size_windows:1; /* Enable root bus sizing */
559
560 /* Resource alignment requirements */
561 resource_size_t (*align_resource)(struct pci_dev *dev,
562 const struct resource *res,
563 resource_size_t start,
564 resource_size_t size,
565 resource_size_t align);
566
567 ANDROID_KABI_RESERVE(1);
568 ANDROID_KABI_RESERVE(2);
569
570 unsigned long private[] ____cacheline_aligned;
571 };
572
573 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
574
pci_host_bridge_priv(struct pci_host_bridge * bridge)575 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
576 {
577 return (void *)bridge->private;
578 }
579
pci_host_bridge_from_priv(void * priv)580 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
581 {
582 return container_of(priv, struct pci_host_bridge, private);
583 }
584
585 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
586 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
587 size_t priv);
588 void pci_free_host_bridge(struct pci_host_bridge *bridge);
589 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
590
591 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
592 void (*release_fn)(struct pci_host_bridge *),
593 void *release_data);
594
595 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
596
597 /*
598 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
599 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
600 * buses below host bridges or subtractive decode bridges) go in the list.
601 * Use pci_bus_for_each_resource() to iterate through all the resources.
602 */
603
604 /*
605 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
606 * and there's no way to program the bridge with the details of the window.
607 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
608 * decode bit set, because they are explicit and can be programmed with _SRS.
609 */
610 #define PCI_SUBTRACTIVE_DECODE 0x1
611
612 struct pci_bus_resource {
613 struct list_head list;
614 struct resource *res;
615 unsigned int flags;
616 };
617
618 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
619
620 struct pci_bus {
621 struct list_head node; /* Node in list of buses */
622 struct pci_bus *parent; /* Parent bus this bridge is on */
623 struct list_head children; /* List of child buses */
624 struct list_head devices; /* List of devices on this bus */
625 struct pci_dev *self; /* Bridge device as seen by parent */
626 struct list_head slots; /* List of slots on this bus;
627 protected by pci_slot_mutex */
628 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
629 struct list_head resources; /* Address space routed to this bus */
630 struct resource busn_res; /* Bus numbers routed to this bus */
631
632 struct pci_ops *ops; /* Configuration access functions */
633 struct msi_controller *msi; /* MSI controller */
634 void *sysdata; /* Hook for sys-specific extension */
635 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
636
637 unsigned char number; /* Bus number */
638 unsigned char primary; /* Number of primary bridge */
639 unsigned char max_bus_speed; /* enum pci_bus_speed */
640 unsigned char cur_bus_speed; /* enum pci_bus_speed */
641 #ifdef CONFIG_PCI_DOMAINS_GENERIC
642 int domain_nr;
643 #endif
644
645 char name[48];
646
647 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
648 pci_bus_flags_t bus_flags; /* Inherited by child buses */
649 struct device *bridge;
650 struct device dev;
651 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
652 struct bin_attribute *legacy_mem; /* Legacy mem */
653 unsigned int is_added:1;
654
655 ANDROID_KABI_RESERVE(1);
656 ANDROID_KABI_RESERVE(2);
657 ANDROID_KABI_RESERVE(3);
658 ANDROID_KABI_RESERVE(4);
659 };
660
661 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
662
pci_dev_id(struct pci_dev * dev)663 static inline u16 pci_dev_id(struct pci_dev *dev)
664 {
665 return PCI_DEVID(dev->bus->number, dev->devfn);
666 }
667
668 /*
669 * Returns true if the PCI bus is root (behind host-PCI bridge),
670 * false otherwise
671 *
672 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
673 * This is incorrect because "virtual" buses added for SR-IOV (via
674 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
675 */
pci_is_root_bus(struct pci_bus * pbus)676 static inline bool pci_is_root_bus(struct pci_bus *pbus)
677 {
678 return !(pbus->parent);
679 }
680
681 /**
682 * pci_is_bridge - check if the PCI device is a bridge
683 * @dev: PCI device
684 *
685 * Return true if the PCI device is bridge whether it has subordinate
686 * or not.
687 */
pci_is_bridge(struct pci_dev * dev)688 static inline bool pci_is_bridge(struct pci_dev *dev)
689 {
690 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
691 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
692 }
693
694 #define for_each_pci_bridge(dev, bus) \
695 list_for_each_entry(dev, &bus->devices, bus_list) \
696 if (!pci_is_bridge(dev)) {} else
697
pci_upstream_bridge(struct pci_dev * dev)698 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
699 {
700 dev = pci_physfn(dev);
701 if (pci_is_root_bus(dev->bus))
702 return NULL;
703
704 return dev->bus->self;
705 }
706
707 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)708 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
709 {
710 return pci_dev->msi_enabled || pci_dev->msix_enabled;
711 }
712 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)713 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
714 #endif
715
716 /* Error values that may be returned by PCI functions */
717 #define PCIBIOS_SUCCESSFUL 0x00
718 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
719 #define PCIBIOS_BAD_VENDOR_ID 0x83
720 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
721 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
722 #define PCIBIOS_SET_FAILED 0x88
723 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
724
725 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)726 static inline int pcibios_err_to_errno(int err)
727 {
728 if (err <= PCIBIOS_SUCCESSFUL)
729 return err; /* Assume already errno */
730
731 switch (err) {
732 case PCIBIOS_FUNC_NOT_SUPPORTED:
733 return -ENOENT;
734 case PCIBIOS_BAD_VENDOR_ID:
735 return -ENOTTY;
736 case PCIBIOS_DEVICE_NOT_FOUND:
737 return -ENODEV;
738 case PCIBIOS_BAD_REGISTER_NUMBER:
739 return -EFAULT;
740 case PCIBIOS_SET_FAILED:
741 return -EIO;
742 case PCIBIOS_BUFFER_TOO_SMALL:
743 return -ENOSPC;
744 }
745
746 return -ERANGE;
747 }
748
749 /* Low-level architecture-dependent routines */
750
751 struct pci_ops {
752 int (*add_bus)(struct pci_bus *bus);
753 void (*remove_bus)(struct pci_bus *bus);
754 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
755 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
756 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
757
758 ANDROID_KABI_RESERVE(1);
759 };
760
761 /*
762 * ACPI needs to be able to access PCI config space before we've done a
763 * PCI bus scan and created pci_bus structures.
764 */
765 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
766 int reg, int len, u32 *val);
767 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
768 int reg, int len, u32 val);
769
770 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
771 typedef u64 pci_bus_addr_t;
772 #else
773 typedef u32 pci_bus_addr_t;
774 #endif
775
776 struct pci_bus_region {
777 pci_bus_addr_t start;
778 pci_bus_addr_t end;
779 };
780
781 struct pci_dynids {
782 spinlock_t lock; /* Protects list, index */
783 struct list_head list; /* For IDs added at runtime */
784 };
785
786
787 /*
788 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
789 * a set of callbacks in struct pci_error_handlers, that device driver
790 * will be notified of PCI bus errors, and will be driven to recovery
791 * when an error occurs.
792 */
793
794 typedef unsigned int __bitwise pci_ers_result_t;
795
796 enum pci_ers_result {
797 /* No result/none/not supported in device driver */
798 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
799
800 /* Device driver can recover without slot reset */
801 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
802
803 /* Device driver wants slot to be reset */
804 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
805
806 /* Device has completely failed, is unrecoverable */
807 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
808
809 /* Device driver is fully recovered and operational */
810 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
811
812 /* No AER capabilities registered for the driver */
813 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
814 };
815
816 /* PCI bus error event callbacks */
817 struct pci_error_handlers {
818 /* PCI bus error detected on this device */
819 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
820 pci_channel_state_t error);
821
822 /* MMIO has been re-enabled, but not DMA */
823 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
824
825 /* PCI slot has been reset */
826 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
827
828 /* PCI function reset prepare or completed */
829 void (*reset_prepare)(struct pci_dev *dev);
830 void (*reset_done)(struct pci_dev *dev);
831
832 /* Device driver may resume normal operations */
833 void (*resume)(struct pci_dev *dev);
834
835 ANDROID_KABI_RESERVE(1);
836 };
837
838
839 struct module;
840
841 /**
842 * struct pci_driver - PCI driver structure
843 * @node: List of driver structures.
844 * @name: Driver name.
845 * @id_table: Pointer to table of device IDs the driver is
846 * interested in. Most drivers should export this
847 * table using MODULE_DEVICE_TABLE(pci,...).
848 * @probe: This probing function gets called (during execution
849 * of pci_register_driver() for already existing
850 * devices or later if a new device gets inserted) for
851 * all PCI devices which match the ID table and are not
852 * "owned" by the other drivers yet. This function gets
853 * passed a "struct pci_dev \*" for each device whose
854 * entry in the ID table matches the device. The probe
855 * function returns zero when the driver chooses to
856 * take "ownership" of the device or an error code
857 * (negative number) otherwise.
858 * The probe function always gets called from process
859 * context, so it can sleep.
860 * @remove: The remove() function gets called whenever a device
861 * being handled by this driver is removed (either during
862 * deregistration of the driver or when it's manually
863 * pulled out of a hot-pluggable slot).
864 * The remove function always gets called from process
865 * context, so it can sleep.
866 * @suspend: Put device into low power state.
867 * @resume: Wake device from low power state.
868 * (Please see Documentation/power/pci.rst for descriptions
869 * of PCI Power Management and the related functions.)
870 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
871 * Intended to stop any idling DMA operations.
872 * Useful for enabling wake-on-lan (NIC) or changing
873 * the power state of a device before reboot.
874 * e.g. drivers/net/e100.c.
875 * @sriov_configure: Optional driver callback to allow configuration of
876 * number of VFs to enable via sysfs "sriov_numvfs" file.
877 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
878 * @groups: Sysfs attribute groups.
879 * @driver: Driver model structure.
880 * @dynids: List of dynamically added device IDs.
881 */
882 struct pci_driver {
883 struct list_head node;
884 const char *name;
885 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
886 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
887 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
888 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
889 int (*resume)(struct pci_dev *dev); /* Device woken up */
890 void (*shutdown)(struct pci_dev *dev);
891 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
892 const struct pci_error_handlers *err_handler;
893 const struct attribute_group **groups;
894 struct device_driver driver;
895 struct pci_dynids dynids;
896
897 ANDROID_KABI_RESERVE(1);
898 ANDROID_KABI_RESERVE(2);
899 ANDROID_KABI_RESERVE(3);
900 ANDROID_KABI_RESERVE(4);
901 };
902
903 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
904
905 /**
906 * PCI_DEVICE - macro used to describe a specific PCI device
907 * @vend: the 16 bit PCI Vendor ID
908 * @dev: the 16 bit PCI Device ID
909 *
910 * This macro is used to create a struct pci_device_id that matches a
911 * specific device. The subvendor and subdevice fields will be set to
912 * PCI_ANY_ID.
913 */
914 #define PCI_DEVICE(vend,dev) \
915 .vendor = (vend), .device = (dev), \
916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
917
918 /**
919 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
920 * @vend: the 16 bit PCI Vendor ID
921 * @dev: the 16 bit PCI Device ID
922 * @subvend: the 16 bit PCI Subvendor ID
923 * @subdev: the 16 bit PCI Subdevice ID
924 *
925 * This macro is used to create a struct pci_device_id that matches a
926 * specific device with subsystem information.
927 */
928 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
929 .vendor = (vend), .device = (dev), \
930 .subvendor = (subvend), .subdevice = (subdev)
931
932 /**
933 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
934 * @dev_class: the class, subclass, prog-if triple for this device
935 * @dev_class_mask: the class mask for this device
936 *
937 * This macro is used to create a struct pci_device_id that matches a
938 * specific PCI class. The vendor, device, subvendor, and subdevice
939 * fields will be set to PCI_ANY_ID.
940 */
941 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
942 .class = (dev_class), .class_mask = (dev_class_mask), \
943 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
945
946 /**
947 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
948 * @vend: the vendor name
949 * @dev: the 16 bit PCI Device ID
950 *
951 * This macro is used to create a struct pci_device_id that matches a
952 * specific PCI device. The subvendor, and subdevice fields will be set
953 * to PCI_ANY_ID. The macro allows the next field to follow as the device
954 * private data.
955 */
956 #define PCI_VDEVICE(vend, dev) \
957 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
958 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
959
960 /**
961 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
962 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
963 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
964 * @data: the driver data to be filled
965 *
966 * This macro is used to create a struct pci_device_id that matches a
967 * specific PCI device. The subvendor, and subdevice fields will be set
968 * to PCI_ANY_ID.
969 */
970 #define PCI_DEVICE_DATA(vend, dev, data) \
971 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
972 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
973 .driver_data = (kernel_ulong_t)(data)
974
975 enum {
976 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
977 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
978 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
979 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
980 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
981 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
982 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
983 };
984
985 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
986 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
987 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
988 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
989
990 /* These external functions are only available when PCI support is enabled */
991 #ifdef CONFIG_PCI
992
993 extern unsigned int pci_flags;
994
pci_set_flags(int flags)995 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)996 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)997 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)998 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
999
1000 void pcie_bus_configure_settings(struct pci_bus *bus);
1001
1002 enum pcie_bus_config_types {
1003 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1004 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1005 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1006 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1007 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1008 };
1009
1010 extern enum pcie_bus_config_types pcie_bus_config;
1011
1012 extern struct bus_type pci_bus_type;
1013
1014 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1015 * code, or PCI core code. */
1016 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1017 /* Some device drivers need know if PCI is initiated */
1018 int no_pci_devices(void);
1019
1020 void pcibios_resource_survey_bus(struct pci_bus *bus);
1021 void pcibios_bus_add_device(struct pci_dev *pdev);
1022 void pcibios_add_bus(struct pci_bus *bus);
1023 void pcibios_remove_bus(struct pci_bus *bus);
1024 void pcibios_fixup_bus(struct pci_bus *);
1025 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1026 /* Architecture-specific versions may override this (weak) */
1027 char *pcibios_setup(char *str);
1028
1029 /* Used only when drivers/pci/setup.c is used */
1030 resource_size_t pcibios_align_resource(void *, const struct resource *,
1031 resource_size_t,
1032 resource_size_t);
1033
1034 /* Weak but can be overridden by arch */
1035 void pci_fixup_cardbus(struct pci_bus *);
1036
1037 /* Generic PCI functions used internally */
1038
1039 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1040 struct resource *res);
1041 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1042 struct pci_bus_region *region);
1043 void pcibios_scan_specific_bus(int busn);
1044 struct pci_bus *pci_find_bus(int domain, int busnr);
1045 void pci_bus_add_devices(const struct pci_bus *bus);
1046 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1047 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1048 struct pci_ops *ops, void *sysdata,
1049 struct list_head *resources);
1050 int pci_host_probe(struct pci_host_bridge *bridge);
1051 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1052 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1053 void pci_bus_release_busn_res(struct pci_bus *b);
1054 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1055 struct pci_ops *ops, void *sysdata,
1056 struct list_head *resources);
1057 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1058 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1059 int busnr);
1060 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1061 const char *name,
1062 struct hotplug_slot *hotplug);
1063 void pci_destroy_slot(struct pci_slot *slot);
1064 #ifdef CONFIG_SYSFS
1065 void pci_dev_assign_slot(struct pci_dev *dev);
1066 #else
pci_dev_assign_slot(struct pci_dev * dev)1067 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1068 #endif
1069 int pci_scan_slot(struct pci_bus *bus, int devfn);
1070 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1071 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1072 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1073 void pci_bus_add_device(struct pci_dev *dev);
1074 void pci_read_bridge_bases(struct pci_bus *child);
1075 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1076 struct resource *res);
1077 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1078 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1079 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1080 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1081 void pci_dev_put(struct pci_dev *dev);
1082 void pci_remove_bus(struct pci_bus *b);
1083 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1084 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1085 void pci_stop_root_bus(struct pci_bus *bus);
1086 void pci_remove_root_bus(struct pci_bus *bus);
1087 void pci_setup_cardbus(struct pci_bus *bus);
1088 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1089 void pci_sort_breadthfirst(void);
1090 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1091 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1092
1093 /* Generic PCI functions exported to card drivers */
1094
1095 int pci_find_capability(struct pci_dev *dev, int cap);
1096 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1097 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1098 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1099 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1100 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1101 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1102
1103 u64 pci_get_dsn(struct pci_dev *dev);
1104
1105 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1106 struct pci_dev *from);
1107 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1108 unsigned int ss_vendor, unsigned int ss_device,
1109 struct pci_dev *from);
1110 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1111 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1112 unsigned int devfn);
1113 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1114 int pci_dev_present(const struct pci_device_id *ids);
1115
1116 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1117 int where, u8 *val);
1118 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1119 int where, u16 *val);
1120 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1121 int where, u32 *val);
1122 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1123 int where, u8 val);
1124 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1125 int where, u16 val);
1126 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1127 int where, u32 val);
1128
1129 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1130 int where, int size, u32 *val);
1131 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1132 int where, int size, u32 val);
1133 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1134 int where, int size, u32 *val);
1135 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1136 int where, int size, u32 val);
1137
1138 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1139
1140 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1141 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1142 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1143 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1144 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1145 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1146
1147 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1148 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1149 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1150 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1151 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1152 u16 clear, u16 set);
1153 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1154 u32 clear, u32 set);
1155
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1156 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1157 u16 set)
1158 {
1159 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1160 }
1161
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1162 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1163 u32 set)
1164 {
1165 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1166 }
1167
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1168 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1169 u16 clear)
1170 {
1171 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1172 }
1173
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1174 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1175 u32 clear)
1176 {
1177 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1178 }
1179
1180 /* User-space driven config access */
1181 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1182 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1183 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1184 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1185 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1186 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1187
1188 int __must_check pci_enable_device(struct pci_dev *dev);
1189 int __must_check pci_enable_device_io(struct pci_dev *dev);
1190 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1191 int __must_check pci_reenable_device(struct pci_dev *);
1192 int __must_check pcim_enable_device(struct pci_dev *pdev);
1193 void pcim_pin_device(struct pci_dev *pdev);
1194
pci_intx_mask_supported(struct pci_dev * pdev)1195 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1196 {
1197 /*
1198 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1199 * writable and no quirk has marked the feature broken.
1200 */
1201 return !pdev->broken_intx_masking;
1202 }
1203
pci_is_enabled(struct pci_dev * pdev)1204 static inline int pci_is_enabled(struct pci_dev *pdev)
1205 {
1206 return (atomic_read(&pdev->enable_cnt) > 0);
1207 }
1208
pci_is_managed(struct pci_dev * pdev)1209 static inline int pci_is_managed(struct pci_dev *pdev)
1210 {
1211 return pdev->is_managed;
1212 }
1213
1214 void pci_disable_device(struct pci_dev *dev);
1215
1216 extern unsigned int pcibios_max_latency;
1217 void pci_set_master(struct pci_dev *dev);
1218 void pci_clear_master(struct pci_dev *dev);
1219
1220 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1221 int pci_set_cacheline_size(struct pci_dev *dev);
1222 #define HAVE_PCI_SET_MWI
1223 int __must_check pci_set_mwi(struct pci_dev *dev);
1224 int __must_check pcim_set_mwi(struct pci_dev *dev);
1225 int pci_try_set_mwi(struct pci_dev *dev);
1226 void pci_clear_mwi(struct pci_dev *dev);
1227 void pci_intx(struct pci_dev *dev, int enable);
1228 bool pci_check_and_mask_intx(struct pci_dev *dev);
1229 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1230 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1231 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1232 int pcix_get_max_mmrbc(struct pci_dev *dev);
1233 int pcix_get_mmrbc(struct pci_dev *dev);
1234 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1235 int pcie_get_readrq(struct pci_dev *dev);
1236 int pcie_set_readrq(struct pci_dev *dev, int rq);
1237 int pcie_get_mps(struct pci_dev *dev);
1238 int pcie_set_mps(struct pci_dev *dev, int mps);
1239 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1240 enum pci_bus_speed *speed,
1241 enum pcie_link_width *width);
1242 void pcie_print_link_status(struct pci_dev *dev);
1243 bool pcie_has_flr(struct pci_dev *dev);
1244 int pcie_flr(struct pci_dev *dev);
1245 int __pci_reset_function_locked(struct pci_dev *dev);
1246 int pci_reset_function(struct pci_dev *dev);
1247 int pci_reset_function_locked(struct pci_dev *dev);
1248 int pci_try_reset_function(struct pci_dev *dev);
1249 int pci_probe_reset_slot(struct pci_slot *slot);
1250 int pci_probe_reset_bus(struct pci_bus *bus);
1251 int pci_reset_bus(struct pci_dev *dev);
1252 void pci_reset_secondary_bus(struct pci_dev *dev);
1253 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1254 void pci_update_resource(struct pci_dev *dev, int resno);
1255 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1256 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1257 void pci_release_resource(struct pci_dev *dev, int resno);
1258 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1259 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1260 bool pci_device_is_present(struct pci_dev *pdev);
1261 void pci_ignore_hotplug(struct pci_dev *dev);
1262 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1263 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1264
1265 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1266 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1267 const char *fmt, ...);
1268 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1269
1270 /* ROM control related routines */
1271 int pci_enable_rom(struct pci_dev *pdev);
1272 void pci_disable_rom(struct pci_dev *pdev);
1273 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1274 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1275
1276 /* Power management related routines */
1277 int pci_save_state(struct pci_dev *dev);
1278 void pci_restore_state(struct pci_dev *dev);
1279 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1280 int pci_load_saved_state(struct pci_dev *dev,
1281 struct pci_saved_state *state);
1282 int pci_load_and_free_saved_state(struct pci_dev *dev,
1283 struct pci_saved_state **state);
1284 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1285 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1286 u16 cap);
1287 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1288 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1289 u16 cap, unsigned int size);
1290 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1291 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1292 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1293 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1294 void pci_pme_active(struct pci_dev *dev, bool enable);
1295 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1296 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1297 int pci_prepare_to_sleep(struct pci_dev *dev);
1298 int pci_back_from_sleep(struct pci_dev *dev);
1299 bool pci_dev_run_wake(struct pci_dev *dev);
1300 void pci_d3cold_enable(struct pci_dev *dev);
1301 void pci_d3cold_disable(struct pci_dev *dev);
1302 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1303 void pci_wakeup_bus(struct pci_bus *bus);
1304 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1305
1306 /* For use by arch with custom probe code */
1307 void set_pcie_port_type(struct pci_dev *pdev);
1308 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1309
1310 /* Functions for PCI Hotplug drivers to use */
1311 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1312 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1313 unsigned int pci_rescan_bus(struct pci_bus *bus);
1314 void pci_lock_rescan_remove(void);
1315 void pci_unlock_rescan_remove(void);
1316
1317 /* Vital Product Data routines */
1318 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1319 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1320 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1321
1322 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1323 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1324 void pci_bus_assign_resources(const struct pci_bus *bus);
1325 void pci_bus_claim_resources(struct pci_bus *bus);
1326 void pci_bus_size_bridges(struct pci_bus *bus);
1327 int pci_claim_resource(struct pci_dev *, int);
1328 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1329 void pci_assign_unassigned_resources(void);
1330 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1331 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1332 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1333 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1334 void pdev_enable_device(struct pci_dev *);
1335 int pci_enable_resources(struct pci_dev *, int mask);
1336 void pci_assign_irq(struct pci_dev *dev);
1337 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1338 #define HAVE_PCI_REQ_REGIONS 2
1339 int __must_check pci_request_regions(struct pci_dev *, const char *);
1340 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1341 void pci_release_regions(struct pci_dev *);
1342 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1343 void pci_release_region(struct pci_dev *, int);
1344 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1345 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1346 void pci_release_selected_regions(struct pci_dev *, int);
1347
1348 /* drivers/pci/bus.c */
1349 void pci_add_resource(struct list_head *resources, struct resource *res);
1350 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1351 resource_size_t offset);
1352 void pci_free_resource_list(struct list_head *resources);
1353 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1354 unsigned int flags);
1355 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1356 void pci_bus_remove_resources(struct pci_bus *bus);
1357 int devm_request_pci_bus_resources(struct device *dev,
1358 struct list_head *resources);
1359
1360 /* Temporary until new and working PCI SBR API in place */
1361 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1362
1363 #define pci_bus_for_each_resource(bus, res, i) \
1364 for (i = 0; \
1365 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1366 i++)
1367
1368 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1369 struct resource *res, resource_size_t size,
1370 resource_size_t align, resource_size_t min,
1371 unsigned long type_mask,
1372 resource_size_t (*alignf)(void *,
1373 const struct resource *,
1374 resource_size_t,
1375 resource_size_t),
1376 void *alignf_data);
1377
1378
1379 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1380 resource_size_t size);
1381 unsigned long pci_address_to_pio(phys_addr_t addr);
1382 phys_addr_t pci_pio_to_address(unsigned long pio);
1383 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1384 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1385 phys_addr_t phys_addr);
1386 void pci_unmap_iospace(struct resource *res);
1387 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1388 resource_size_t offset,
1389 resource_size_t size);
1390 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1391 struct resource *res);
1392
pci_bus_address(struct pci_dev * pdev,int bar)1393 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1394 {
1395 struct pci_bus_region region;
1396
1397 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1398 return region.start;
1399 }
1400
1401 /* Proper probing supporting hot-pluggable devices */
1402 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1403 const char *mod_name);
1404
1405 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1406 #define pci_register_driver(driver) \
1407 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1408
1409 void pci_unregister_driver(struct pci_driver *dev);
1410
1411 /**
1412 * module_pci_driver() - Helper macro for registering a PCI driver
1413 * @__pci_driver: pci_driver struct
1414 *
1415 * Helper macro for PCI drivers which do not do anything special in module
1416 * init/exit. This eliminates a lot of boilerplate. Each module may only
1417 * use this macro once, and calling it replaces module_init() and module_exit()
1418 */
1419 #define module_pci_driver(__pci_driver) \
1420 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1421
1422 /**
1423 * builtin_pci_driver() - Helper macro for registering a PCI driver
1424 * @__pci_driver: pci_driver struct
1425 *
1426 * Helper macro for PCI drivers which do not do anything special in their
1427 * init code. This eliminates a lot of boilerplate. Each driver may only
1428 * use this macro once, and calling it replaces device_initcall(...)
1429 */
1430 #define builtin_pci_driver(__pci_driver) \
1431 builtin_driver(__pci_driver, pci_register_driver)
1432
1433 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1434 int pci_add_dynid(struct pci_driver *drv,
1435 unsigned int vendor, unsigned int device,
1436 unsigned int subvendor, unsigned int subdevice,
1437 unsigned int class, unsigned int class_mask,
1438 unsigned long driver_data);
1439 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1440 struct pci_dev *dev);
1441 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1442 int pass);
1443
1444 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1445 void *userdata);
1446 int pci_cfg_space_size(struct pci_dev *dev);
1447 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1448 void pci_setup_bridge(struct pci_bus *bus);
1449 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1450 unsigned long type);
1451
1452 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1453 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1454
1455 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1456 unsigned int command_bits, u32 flags);
1457
1458 /*
1459 * Virtual interrupts allow for more interrupts to be allocated
1460 * than the device has interrupts for. These are not programmed
1461 * into the device's MSI-X table and must be handled by some
1462 * other driver means.
1463 */
1464 #define PCI_IRQ_VIRTUAL (1 << 4)
1465
1466 #define PCI_IRQ_ALL_TYPES \
1467 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1468
1469 /* kmem_cache style wrapper around pci_alloc_consistent() */
1470
1471 #include <linux/dmapool.h>
1472
1473 #define pci_pool dma_pool
1474 #define pci_pool_create(name, pdev, size, align, allocation) \
1475 dma_pool_create(name, &pdev->dev, size, align, allocation)
1476 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1477 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1478 #define pci_pool_zalloc(pool, flags, handle) \
1479 dma_pool_zalloc(pool, flags, handle)
1480 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1481
1482 struct msix_entry {
1483 u32 vector; /* Kernel uses to write allocated vector */
1484 u16 entry; /* Driver uses to specify entry, OS writes */
1485 };
1486
1487 #ifdef CONFIG_PCI_MSI
1488 int pci_msi_vec_count(struct pci_dev *dev);
1489 void pci_disable_msi(struct pci_dev *dev);
1490 int pci_msix_vec_count(struct pci_dev *dev);
1491 void pci_disable_msix(struct pci_dev *dev);
1492 void pci_restore_msi_state(struct pci_dev *dev);
1493 int pci_msi_enabled(void);
1494 int pci_enable_msi(struct pci_dev *dev);
1495 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1496 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1497 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1498 struct msix_entry *entries, int nvec)
1499 {
1500 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1501 if (rc < 0)
1502 return rc;
1503 return 0;
1504 }
1505 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1506 unsigned int max_vecs, unsigned int flags,
1507 struct irq_affinity *affd);
1508
1509 void pci_free_irq_vectors(struct pci_dev *dev);
1510 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1511 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1512
1513 #else
pci_msi_vec_count(struct pci_dev * dev)1514 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1515 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1516 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1517 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1518 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1519 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1520 static inline int pci_enable_msi(struct pci_dev *dev)
1521 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1522 static inline int pci_enable_msix_range(struct pci_dev *dev,
1523 struct msix_entry *entries, int minvec, int maxvec)
1524 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1525 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1526 struct msix_entry *entries, int nvec)
1527 { return -ENOSYS; }
1528
1529 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1530 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1531 unsigned int max_vecs, unsigned int flags,
1532 struct irq_affinity *aff_desc)
1533 {
1534 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1535 return 1;
1536 return -ENOSPC;
1537 }
1538
pci_free_irq_vectors(struct pci_dev * dev)1539 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1540 {
1541 }
1542
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1543 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1544 {
1545 if (WARN_ON_ONCE(nr > 0))
1546 return -EINVAL;
1547 return dev->irq;
1548 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1549 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1550 int vec)
1551 {
1552 return cpu_possible_mask;
1553 }
1554 #endif
1555
1556 /**
1557 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1558 * @d: the INTx IRQ domain
1559 * @node: the DT node for the device whose interrupt we're translating
1560 * @intspec: the interrupt specifier data from the DT
1561 * @intsize: the number of entries in @intspec
1562 * @out_hwirq: pointer at which to write the hwirq number
1563 * @out_type: pointer at which to write the interrupt type
1564 *
1565 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1566 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1567 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1568 * INTx value to obtain the hwirq number.
1569 *
1570 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1571 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1572 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1573 struct device_node *node,
1574 const u32 *intspec,
1575 unsigned int intsize,
1576 unsigned long *out_hwirq,
1577 unsigned int *out_type)
1578 {
1579 const u32 intx = intspec[0];
1580
1581 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1582 return -EINVAL;
1583
1584 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1585 return 0;
1586 }
1587
1588 #ifdef CONFIG_PCIEPORTBUS
1589 extern bool pcie_ports_disabled;
1590 extern bool pcie_ports_native;
1591 #else
1592 #define pcie_ports_disabled true
1593 #define pcie_ports_native false
1594 #endif
1595
1596 #define PCIE_LINK_STATE_L0S BIT(0)
1597 #define PCIE_LINK_STATE_L1 BIT(1)
1598 #define PCIE_LINK_STATE_CLKPM BIT(2)
1599 #define PCIE_LINK_STATE_L1_1 BIT(3)
1600 #define PCIE_LINK_STATE_L1_2 BIT(4)
1601 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1602 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1603
1604 #ifdef CONFIG_PCIEASPM
1605 int pci_disable_link_state(struct pci_dev *pdev, int state);
1606 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1607 void pcie_no_aspm(void);
1608 bool pcie_aspm_support_enabled(void);
1609 bool pcie_aspm_enabled(struct pci_dev *pdev);
1610 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1611 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1612 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1613 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1614 { return 0; }
pcie_no_aspm(void)1615 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1616 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1617 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1618 #endif
1619
1620 #ifdef CONFIG_PCIEAER
1621 bool pci_aer_available(void);
1622 #else
pci_aer_available(void)1623 static inline bool pci_aer_available(void) { return false; }
1624 #endif
1625
1626 bool pci_ats_disabled(void);
1627
1628 #ifdef CONFIG_PCIE_PTM
1629 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1630 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1631 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1632 { return -EINVAL; }
1633 #endif
1634
1635 void pci_cfg_access_lock(struct pci_dev *dev);
1636 bool pci_cfg_access_trylock(struct pci_dev *dev);
1637 void pci_cfg_access_unlock(struct pci_dev *dev);
1638
1639 /*
1640 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1641 * a PCI domain is defined to be a set of PCI buses which share
1642 * configuration space.
1643 */
1644 #ifdef CONFIG_PCI_DOMAINS
1645 extern int pci_domains_supported;
1646 #else
1647 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1648 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1649 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1650 #endif /* CONFIG_PCI_DOMAINS */
1651
1652 /*
1653 * Generic implementation for PCI domain support. If your
1654 * architecture does not need custom management of PCI
1655 * domains then this implementation will be used
1656 */
1657 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1658 static inline int pci_domain_nr(struct pci_bus *bus)
1659 {
1660 return bus->domain_nr;
1661 }
1662 #ifdef CONFIG_ACPI
1663 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1664 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1665 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1666 { return 0; }
1667 #endif
1668 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1669 #endif
1670
1671 /* Some architectures require additional setup to direct VGA traffic */
1672 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1673 unsigned int command_bits, u32 flags);
1674 void pci_register_set_vga_state(arch_set_vga_state_t func);
1675
1676 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1677 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1678 {
1679 return pci_request_selected_regions(pdev,
1680 pci_select_bars(pdev, IORESOURCE_IO), name);
1681 }
1682
1683 static inline void
pci_release_io_regions(struct pci_dev * pdev)1684 pci_release_io_regions(struct pci_dev *pdev)
1685 {
1686 return pci_release_selected_regions(pdev,
1687 pci_select_bars(pdev, IORESOURCE_IO));
1688 }
1689
1690 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1691 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1692 {
1693 return pci_request_selected_regions(pdev,
1694 pci_select_bars(pdev, IORESOURCE_MEM), name);
1695 }
1696
1697 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1698 pci_release_mem_regions(struct pci_dev *pdev)
1699 {
1700 return pci_release_selected_regions(pdev,
1701 pci_select_bars(pdev, IORESOURCE_MEM));
1702 }
1703
1704 #else /* CONFIG_PCI is not enabled */
1705
pci_set_flags(int flags)1706 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1707 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1708 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1709 static inline int pci_has_flag(int flag) { return 0; }
1710
1711 /*
1712 * If the system does not have PCI, clearly these return errors. Define
1713 * these as simple inline functions to avoid hair in drivers.
1714 */
1715 #define _PCI_NOP(o, s, t) \
1716 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1717 int where, t val) \
1718 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1719
1720 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1721 _PCI_NOP(o, word, u16 x) \
1722 _PCI_NOP(o, dword, u32 x)
1723 _PCI_NOP_ALL(read, *)
1724 _PCI_NOP_ALL(write,)
1725
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1726 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1727 unsigned int device,
1728 struct pci_dev *from)
1729 { return NULL; }
1730
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1731 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1732 unsigned int device,
1733 unsigned int ss_vendor,
1734 unsigned int ss_device,
1735 struct pci_dev *from)
1736 { return NULL; }
1737
pci_get_class(unsigned int class,struct pci_dev * from)1738 static inline struct pci_dev *pci_get_class(unsigned int class,
1739 struct pci_dev *from)
1740 { return NULL; }
1741
1742 #define pci_dev_present(ids) (0)
1743 #define no_pci_devices() (1)
1744 #define pci_dev_put(dev) do { } while (0)
1745
pci_set_master(struct pci_dev * dev)1746 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1747 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1748 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1749 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1750 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1751 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1752 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1753 struct module *owner,
1754 const char *mod_name)
1755 { return 0; }
pci_register_driver(struct pci_driver * drv)1756 static inline int pci_register_driver(struct pci_driver *drv)
1757 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1758 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1759 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1760 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1761 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1762 int cap)
1763 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1764 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1765 { return 0; }
1766
pci_get_dsn(struct pci_dev * dev)1767 static inline u64 pci_get_dsn(struct pci_dev *dev)
1768 { return 0; }
1769
1770 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1771 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1772 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1773 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1774 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1775 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1776 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1777 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1778 pm_message_t state)
1779 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1780 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1781 int enable)
1782 { return 0; }
1783
pci_find_resource(struct pci_dev * dev,struct resource * res)1784 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1785 struct resource *res)
1786 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1787 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1788 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1789 static inline void pci_release_regions(struct pci_dev *dev) { }
1790
pci_address_to_pio(phys_addr_t addr)1791 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1792
pci_find_next_bus(const struct pci_bus * from)1793 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1794 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1795 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1796 unsigned int devfn)
1797 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1798 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1799 unsigned int bus, unsigned int devfn)
1800 { return NULL; }
1801
pci_domain_nr(struct pci_bus * bus)1802 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1803 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1804
1805 #define dev_is_pci(d) (false)
1806 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1807 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1808 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1809 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1810 struct device_node *node,
1811 const u32 *intspec,
1812 unsigned int intsize,
1813 unsigned long *out_hwirq,
1814 unsigned int *out_type)
1815 { return -EINVAL; }
1816
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1817 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1818 struct pci_dev *dev)
1819 { return NULL; }
pci_ats_disabled(void)1820 static inline bool pci_ats_disabled(void) { return true; }
1821
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1822 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1823 {
1824 return -EINVAL;
1825 }
1826
1827 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1828 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1829 unsigned int max_vecs, unsigned int flags,
1830 struct irq_affinity *aff_desc)
1831 {
1832 return -ENOSPC;
1833 }
1834 #endif /* CONFIG_PCI */
1835
1836 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1837 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1838 unsigned int max_vecs, unsigned int flags)
1839 {
1840 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1841 NULL);
1842 }
1843
1844 /* Include architecture-dependent settings and functions */
1845
1846 #include <asm/pci.h>
1847
1848 /* These two functions provide almost identical functionality. Depending
1849 * on the architecture, one will be implemented as a wrapper around the
1850 * other (in drivers/pci/mmap.c).
1851 *
1852 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1853 * is expected to be an offset within that region.
1854 *
1855 * pci_mmap_page_range() is the legacy architecture-specific interface,
1856 * which accepts a "user visible" resource address converted by
1857 * pci_resource_to_user(), as used in the legacy mmap() interface in
1858 * /proc/bus/pci/.
1859 */
1860 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1861 struct vm_area_struct *vma,
1862 enum pci_mmap_state mmap_state, int write_combine);
1863 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1864 struct vm_area_struct *vma,
1865 enum pci_mmap_state mmap_state, int write_combine);
1866
1867 #ifndef arch_can_pci_mmap_wc
1868 #define arch_can_pci_mmap_wc() 0
1869 #endif
1870
1871 #ifndef arch_can_pci_mmap_io
1872 #define arch_can_pci_mmap_io() 0
1873 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1874 #else
1875 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1876 #endif
1877
1878 #ifndef pci_root_bus_fwnode
1879 #define pci_root_bus_fwnode(bus) NULL
1880 #endif
1881
1882 /*
1883 * These helpers provide future and backwards compatibility
1884 * for accessing popular PCI BAR info
1885 */
1886 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1887 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1888 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1889 #define pci_resource_len(dev,bar) \
1890 ((pci_resource_start((dev), (bar)) == 0 && \
1891 pci_resource_end((dev), (bar)) == \
1892 pci_resource_start((dev), (bar))) ? 0 : \
1893 \
1894 (pci_resource_end((dev), (bar)) - \
1895 pci_resource_start((dev), (bar)) + 1))
1896
1897 /*
1898 * Similar to the helpers above, these manipulate per-pci_dev
1899 * driver-specific data. They are really just a wrapper around
1900 * the generic device structure functions of these calls.
1901 */
pci_get_drvdata(struct pci_dev * pdev)1902 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1903 {
1904 return dev_get_drvdata(&pdev->dev);
1905 }
1906
pci_set_drvdata(struct pci_dev * pdev,void * data)1907 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1908 {
1909 dev_set_drvdata(&pdev->dev, data);
1910 }
1911
pci_name(const struct pci_dev * pdev)1912 static inline const char *pci_name(const struct pci_dev *pdev)
1913 {
1914 return dev_name(&pdev->dev);
1915 }
1916
1917 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1918 const struct resource *rsrc,
1919 resource_size_t *start, resource_size_t *end);
1920
1921 /*
1922 * The world is not perfect and supplies us with broken PCI devices.
1923 * For at least a part of these bugs we need a work-around, so both
1924 * generic (drivers/pci/quirks.c) and per-architecture code can define
1925 * fixup hooks to be called for particular buggy devices.
1926 */
1927
1928 struct pci_fixup {
1929 u16 vendor; /* Or PCI_ANY_ID */
1930 u16 device; /* Or PCI_ANY_ID */
1931 u32 class; /* Or PCI_ANY_ID */
1932 unsigned int class_shift; /* should be 0, 8, 16 */
1933 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1934 int hook_offset;
1935 #else
1936 void (*hook)(struct pci_dev *dev);
1937 #endif
1938 };
1939
1940 enum pci_fixup_pass {
1941 pci_fixup_early, /* Before probing BARs */
1942 pci_fixup_header, /* After reading configuration header */
1943 pci_fixup_final, /* Final phase of device fixups */
1944 pci_fixup_enable, /* pci_enable_device() time */
1945 pci_fixup_resume, /* pci_device_resume() */
1946 pci_fixup_suspend, /* pci_device_suspend() */
1947 pci_fixup_resume_early, /* pci_device_resume_early() */
1948 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1949 };
1950
1951 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1952 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1953 class_shift, hook, stub) \
1954 void __cficanonical stub(struct pci_dev *dev); \
1955 void __cficanonical stub(struct pci_dev *dev) \
1956 { \
1957 hook(dev); \
1958 } \
1959 asm(".section " #sec ", \"a\" \n" \
1960 ".balign 16 \n" \
1961 ".short " #vendor ", " #device " \n" \
1962 ".long " #class ", " #class_shift " \n" \
1963 ".long " #stub " - . \n" \
1964 ".previous \n");
1965
1966 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1967 class_shift, hook, stub) \
1968 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1969 class_shift, hook, stub)
1970 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1971 class_shift, hook) \
1972 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1973 class_shift, hook, __UNIQUE_ID(hook))
1974 #else
1975 /* Anonymous variables would be nice... */
1976 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1977 class_shift, hook) \
1978 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1979 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1980 = { vendor, device, class, class_shift, hook };
1981 #endif
1982
1983 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1984 class_shift, hook) \
1985 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1986 hook, vendor, device, class, class_shift, hook)
1987 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1988 class_shift, hook) \
1989 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1990 hook, vendor, device, class, class_shift, hook)
1991 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1992 class_shift, hook) \
1993 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1994 hook, vendor, device, class, class_shift, hook)
1995 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1996 class_shift, hook) \
1997 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1998 hook, vendor, device, class, class_shift, hook)
1999 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2000 class_shift, hook) \
2001 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2002 resume##hook, vendor, device, class, class_shift, hook)
2003 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2004 class_shift, hook) \
2005 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2006 resume_early##hook, vendor, device, class, class_shift, hook)
2007 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2008 class_shift, hook) \
2009 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2010 suspend##hook, vendor, device, class, class_shift, hook)
2011 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2012 class_shift, hook) \
2013 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2014 suspend_late##hook, vendor, device, class, class_shift, hook)
2015
2016 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2017 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2018 hook, vendor, device, PCI_ANY_ID, 0, hook)
2019 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2020 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2021 hook, vendor, device, PCI_ANY_ID, 0, hook)
2022 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2023 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2024 hook, vendor, device, PCI_ANY_ID, 0, hook)
2025 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2026 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2027 hook, vendor, device, PCI_ANY_ID, 0, hook)
2028 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2029 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2030 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2031 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2032 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2033 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2034 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2035 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2036 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2037 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2038 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2039 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2040
2041 #ifdef CONFIG_PCI_QUIRKS
2042 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2043 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2044 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2045 struct pci_dev *dev) { }
2046 #endif
2047
2048 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2049 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2050 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2051 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2052 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2053 const char *name);
2054 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2055
2056 extern int pci_pci_problems;
2057 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2058 #define PCIPCI_TRITON 2
2059 #define PCIPCI_NATOMA 4
2060 #define PCIPCI_VIAETBF 8
2061 #define PCIPCI_VSFX 16
2062 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2063 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2064
2065 extern unsigned long pci_cardbus_io_size;
2066 extern unsigned long pci_cardbus_mem_size;
2067 extern u8 pci_dfl_cache_line_size;
2068 extern u8 pci_cache_line_size;
2069
2070 /* Architecture-specific versions may override these (weak) */
2071 void pcibios_disable_device(struct pci_dev *dev);
2072 void pcibios_set_master(struct pci_dev *dev);
2073 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2074 enum pcie_reset_state state);
2075 int pcibios_add_device(struct pci_dev *dev);
2076 void pcibios_release_device(struct pci_dev *dev);
2077 #ifdef CONFIG_PCI
2078 void pcibios_penalize_isa_irq(int irq, int active);
2079 #else
pcibios_penalize_isa_irq(int irq,int active)2080 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2081 #endif
2082 int pcibios_alloc_irq(struct pci_dev *dev);
2083 void pcibios_free_irq(struct pci_dev *dev);
2084 resource_size_t pcibios_default_alignment(void);
2085
2086 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2087 void __init pci_mmcfg_early_init(void);
2088 void __init pci_mmcfg_late_init(void);
2089 #else
pci_mmcfg_early_init(void)2090 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2091 static inline void pci_mmcfg_late_init(void) { }
2092 #endif
2093
2094 int pci_ext_cfg_avail(void);
2095
2096 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2097 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2098
2099 #ifdef CONFIG_PCI_IOV
2100 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2101 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2102
2103 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2104 void pci_disable_sriov(struct pci_dev *dev);
2105
2106 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2107 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2108 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2109 int pci_num_vf(struct pci_dev *dev);
2110 int pci_vfs_assigned(struct pci_dev *dev);
2111 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2112 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2113 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2114 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2115 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2116
2117 /* Arch may override these (weak) */
2118 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2119 int pcibios_sriov_disable(struct pci_dev *pdev);
2120 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2121 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2122 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2123 {
2124 return -ENOSYS;
2125 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2126 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2127 {
2128 return -ENOSYS;
2129 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2130 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2131 { return -ENODEV; }
2132
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2133 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2134 struct pci_dev *virtfn, int id)
2135 {
2136 return -ENODEV;
2137 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2138 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2139 {
2140 return -ENOSYS;
2141 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2142 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2143 int id) { }
pci_disable_sriov(struct pci_dev * dev)2144 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2145 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2146 static inline int pci_vfs_assigned(struct pci_dev *dev)
2147 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2148 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2149 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2150 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2151 { return 0; }
2152 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2153 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2154 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2155 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2156 #endif
2157
2158 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2159 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2160 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2161 #endif
2162
2163 /**
2164 * pci_pcie_cap - get the saved PCIe capability offset
2165 * @dev: PCI device
2166 *
2167 * PCIe capability offset is calculated at PCI device initialization
2168 * time and saved in the data structure. This function returns saved
2169 * PCIe capability offset. Using this instead of pci_find_capability()
2170 * reduces unnecessary search in the PCI configuration space. If you
2171 * need to calculate PCIe capability offset from raw device for some
2172 * reasons, please use pci_find_capability() instead.
2173 */
pci_pcie_cap(struct pci_dev * dev)2174 static inline int pci_pcie_cap(struct pci_dev *dev)
2175 {
2176 return dev->pcie_cap;
2177 }
2178
2179 /**
2180 * pci_is_pcie - check if the PCI device is PCI Express capable
2181 * @dev: PCI device
2182 *
2183 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2184 */
pci_is_pcie(struct pci_dev * dev)2185 static inline bool pci_is_pcie(struct pci_dev *dev)
2186 {
2187 return pci_pcie_cap(dev);
2188 }
2189
2190 /**
2191 * pcie_caps_reg - get the PCIe Capabilities Register
2192 * @dev: PCI device
2193 */
pcie_caps_reg(const struct pci_dev * dev)2194 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2195 {
2196 return dev->pcie_flags_reg;
2197 }
2198
2199 /**
2200 * pci_pcie_type - get the PCIe device/port type
2201 * @dev: PCI device
2202 */
pci_pcie_type(const struct pci_dev * dev)2203 static inline int pci_pcie_type(const struct pci_dev *dev)
2204 {
2205 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2206 }
2207
2208 /**
2209 * pcie_find_root_port - Get the PCIe root port device
2210 * @dev: PCI device
2211 *
2212 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2213 * for a given PCI/PCIe Device.
2214 */
pcie_find_root_port(struct pci_dev * dev)2215 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2216 {
2217 while (dev) {
2218 if (pci_is_pcie(dev) &&
2219 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2220 return dev;
2221 dev = pci_upstream_bridge(dev);
2222 }
2223
2224 return NULL;
2225 }
2226
2227 void pci_request_acs(void);
2228 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2229 bool pci_acs_path_enabled(struct pci_dev *start,
2230 struct pci_dev *end, u16 acs_flags);
2231 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2232
2233 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2234 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2235
2236 /* Large Resource Data Type Tag Item Names */
2237 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2238 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2239 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2240
2241 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2242 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2243 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2244
2245 /* Small Resource Data Type Tag Item Names */
2246 #define PCI_VPD_STIN_END 0x0f /* End */
2247
2248 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2249
2250 #define PCI_VPD_SRDT_TIN_MASK 0x78
2251 #define PCI_VPD_SRDT_LEN_MASK 0x07
2252 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2253
2254 #define PCI_VPD_LRDT_TAG_SIZE 3
2255 #define PCI_VPD_SRDT_TAG_SIZE 1
2256
2257 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2258
2259 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2260 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2261 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2262 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2263 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2264
2265 /**
2266 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2267 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2268 *
2269 * Returns the extracted Large Resource Data Type length.
2270 */
pci_vpd_lrdt_size(const u8 * lrdt)2271 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2272 {
2273 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2274 }
2275
2276 /**
2277 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2278 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2279 *
2280 * Returns the extracted Large Resource Data Type Tag item.
2281 */
pci_vpd_lrdt_tag(const u8 * lrdt)2282 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2283 {
2284 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2285 }
2286
2287 /**
2288 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2289 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2290 *
2291 * Returns the extracted Small Resource Data Type length.
2292 */
pci_vpd_srdt_size(const u8 * srdt)2293 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2294 {
2295 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2296 }
2297
2298 /**
2299 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2300 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2301 *
2302 * Returns the extracted Small Resource Data Type Tag Item.
2303 */
pci_vpd_srdt_tag(const u8 * srdt)2304 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2305 {
2306 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2307 }
2308
2309 /**
2310 * pci_vpd_info_field_size - Extracts the information field length
2311 * @info_field: Pointer to the beginning of an information field header
2312 *
2313 * Returns the extracted information field length.
2314 */
pci_vpd_info_field_size(const u8 * info_field)2315 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2316 {
2317 return info_field[2];
2318 }
2319
2320 /**
2321 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2322 * @buf: Pointer to buffered vpd data
2323 * @off: The offset into the buffer at which to begin the search
2324 * @len: The length of the vpd buffer
2325 * @rdt: The Resource Data Type to search for
2326 *
2327 * Returns the index where the Resource Data Type was found or
2328 * -ENOENT otherwise.
2329 */
2330 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2331
2332 /**
2333 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2334 * @buf: Pointer to buffered vpd data
2335 * @off: The offset into the buffer at which to begin the search
2336 * @len: The length of the buffer area, relative to off, in which to search
2337 * @kw: The keyword to search for
2338 *
2339 * Returns the index where the information field keyword was found or
2340 * -ENOENT otherwise.
2341 */
2342 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2343 unsigned int len, const char *kw);
2344
2345 /* PCI <-> OF binding helpers */
2346 #ifdef CONFIG_OF
2347 struct device_node;
2348 struct irq_domain;
2349 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2350
2351 /* Arch may override this (weak) */
2352 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2353
2354 #else /* CONFIG_OF */
2355 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2356 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2357 #endif /* CONFIG_OF */
2358
2359 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2360 pci_device_to_OF_node(const struct pci_dev *pdev)
2361 {
2362 return pdev ? pdev->dev.of_node : NULL;
2363 }
2364
pci_bus_to_OF_node(struct pci_bus * bus)2365 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2366 {
2367 return bus ? bus->dev.of_node : NULL;
2368 }
2369
2370 #ifdef CONFIG_ACPI
2371 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2372
2373 void
2374 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2375 bool pci_pr3_present(struct pci_dev *pdev);
2376 #else
2377 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2378 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2379 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2380 #endif
2381
2382 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2383 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2384 {
2385 return pdev->dev.archdata.edev;
2386 }
2387 #endif
2388
2389 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2390 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2391 int pci_for_each_dma_alias(struct pci_dev *pdev,
2392 int (*fn)(struct pci_dev *pdev,
2393 u16 alias, void *data), void *data);
2394
2395 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2396 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2397 {
2398 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2399 }
pci_clear_dev_assigned(struct pci_dev * pdev)2400 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2401 {
2402 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2403 }
pci_is_dev_assigned(struct pci_dev * pdev)2404 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2405 {
2406 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2407 }
2408
2409 /**
2410 * pci_ari_enabled - query ARI forwarding status
2411 * @bus: the PCI bus
2412 *
2413 * Returns true if ARI forwarding is enabled.
2414 */
pci_ari_enabled(struct pci_bus * bus)2415 static inline bool pci_ari_enabled(struct pci_bus *bus)
2416 {
2417 return bus->self && bus->self->ari_enabled;
2418 }
2419
2420 /**
2421 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2422 * @pdev: PCI device to check
2423 *
2424 * Walk upwards from @pdev and check for each encountered bridge if it's part
2425 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2426 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2427 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2428 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2429 {
2430 struct pci_dev *parent = pdev;
2431
2432 if (pdev->is_thunderbolt)
2433 return true;
2434
2435 while ((parent = pci_upstream_bridge(parent)))
2436 if (parent->is_thunderbolt)
2437 return true;
2438
2439 return false;
2440 }
2441
2442 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2443 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2444 #endif
2445
2446 /* Provide the legacy pci_dma_* API */
2447 #include <linux/pci-dma-compat.h>
2448
2449 #define pci_printk(level, pdev, fmt, arg...) \
2450 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2451
2452 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2453 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2454 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2455 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2456 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2457 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2458 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2459 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2460
2461 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2462 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2463
2464 #define pci_info_ratelimited(pdev, fmt, arg...) \
2465 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2466
2467 #define pci_WARN(pdev, condition, fmt, arg...) \
2468 WARN(condition, "%s %s: " fmt, \
2469 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2470
2471 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2472 WARN_ONCE(condition, "%s %s: " fmt, \
2473 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2474
2475 #endif /* LINUX_PCI_H */
2476