1 /*
2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <rdma/ib_verbs.h>
34 #include <linux/mlx5/fs.h>
35 #include "en.h"
36 #include "ipoib.h"
37
38 #define IB_DEFAULT_Q_KEY 0xb1b
39 #define MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE 9
40
41 static int mlx5i_open(struct net_device *netdev);
42 static int mlx5i_close(struct net_device *netdev);
43 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu);
44
45 static const struct net_device_ops mlx5i_netdev_ops = {
46 .ndo_open = mlx5i_open,
47 .ndo_stop = mlx5i_close,
48 .ndo_get_stats64 = mlx5i_get_stats,
49 .ndo_init = mlx5i_dev_init,
50 .ndo_uninit = mlx5i_dev_cleanup,
51 .ndo_change_mtu = mlx5i_change_mtu,
52 .ndo_do_ioctl = mlx5i_ioctl,
53 };
54
55 /* IPoIB mlx5 netdev profile */
mlx5i_build_nic_params(struct mlx5_core_dev * mdev,struct mlx5e_params * params)56 static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev,
57 struct mlx5e_params *params)
58 {
59 /* Override RQ params as IPoIB supports only LINKED LIST RQ for now */
60 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, false);
61 mlx5e_set_rq_type(mdev, params);
62 mlx5e_init_rq_type_params(mdev, params);
63
64 /* RQ size in ipoib by default is 512 */
65 params->log_rq_mtu_frames = is_kdump_kernel() ?
66 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
67 MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE;
68
69 params->lro_en = false;
70 params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN;
71 params->tunneled_offload_en = false;
72 }
73
74 /* Called directly after IPoIB netdevice was created to initialize SW structs */
mlx5i_init(struct mlx5_core_dev * mdev,struct net_device * netdev,const struct mlx5e_profile * profile,void * ppriv)75 int mlx5i_init(struct mlx5_core_dev *mdev,
76 struct net_device *netdev,
77 const struct mlx5e_profile *profile,
78 void *ppriv)
79 {
80 struct mlx5e_priv *priv = mlx5i_epriv(netdev);
81 int err;
82
83 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
84 if (err)
85 return err;
86
87 mlx5e_set_netdev_mtu_boundaries(priv);
88 netdev->mtu = netdev->max_mtu;
89
90 mlx5e_build_nic_params(priv, NULL, &priv->rss_params, &priv->channels.params,
91 netdev->mtu);
92 mlx5i_build_nic_params(mdev, &priv->channels.params);
93
94 mlx5e_timestamp_init(priv);
95
96 /* netdev init */
97 netdev->hw_features |= NETIF_F_SG;
98 netdev->hw_features |= NETIF_F_IP_CSUM;
99 netdev->hw_features |= NETIF_F_IPV6_CSUM;
100 netdev->hw_features |= NETIF_F_GRO;
101 netdev->hw_features |= NETIF_F_TSO;
102 netdev->hw_features |= NETIF_F_TSO6;
103 netdev->hw_features |= NETIF_F_RXCSUM;
104 netdev->hw_features |= NETIF_F_RXHASH;
105
106 netdev->netdev_ops = &mlx5i_netdev_ops;
107 netdev->ethtool_ops = &mlx5i_ethtool_ops;
108
109 return 0;
110 }
111
112 /* Called directly before IPoIB netdevice is destroyed to cleanup SW structs */
mlx5i_cleanup(struct mlx5e_priv * priv)113 void mlx5i_cleanup(struct mlx5e_priv *priv)
114 {
115 mlx5e_netdev_cleanup(priv->netdev, priv);
116 }
117
mlx5i_grp_sw_update_stats(struct mlx5e_priv * priv)118 static void mlx5i_grp_sw_update_stats(struct mlx5e_priv *priv)
119 {
120 struct mlx5e_sw_stats s = { 0 };
121 int i, j;
122
123 for (i = 0; i < priv->max_nch; i++) {
124 struct mlx5e_channel_stats *channel_stats;
125 struct mlx5e_rq_stats *rq_stats;
126
127 channel_stats = &priv->channel_stats[i];
128 rq_stats = &channel_stats->rq;
129
130 s.rx_packets += rq_stats->packets;
131 s.rx_bytes += rq_stats->bytes;
132
133 for (j = 0; j < priv->max_opened_tc; j++) {
134 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
135
136 s.tx_packets += sq_stats->packets;
137 s.tx_bytes += sq_stats->bytes;
138 s.tx_queue_dropped += sq_stats->dropped;
139 }
140 }
141
142 memcpy(&priv->stats.sw, &s, sizeof(s));
143 }
144
mlx5i_get_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)145 void mlx5i_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
146 {
147 struct mlx5e_priv *priv = mlx5i_epriv(dev);
148 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
149
150 mlx5i_grp_sw_update_stats(priv);
151
152 stats->rx_packets = sstats->rx_packets;
153 stats->rx_bytes = sstats->rx_bytes;
154 stats->tx_packets = sstats->tx_packets;
155 stats->tx_bytes = sstats->tx_bytes;
156 stats->tx_dropped = sstats->tx_queue_dropped;
157 }
158
mlx5i_init_underlay_qp(struct mlx5e_priv * priv)159 int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
160 {
161 struct mlx5_core_dev *mdev = priv->mdev;
162 struct mlx5i_priv *ipriv = priv->ppriv;
163 int ret;
164
165 {
166 u32 in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {};
167 u32 *qpc;
168
169 qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc);
170
171 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
172 MLX5_SET(qpc, qpc, primary_address_path.pkey_index,
173 ipriv->pkey_index);
174 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
175 MLX5_SET(qpc, qpc, q_key, IB_DEFAULT_Q_KEY);
176
177 MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP);
178 MLX5_SET(rst2init_qp_in, in, qpn, ipriv->qpn);
179 ret = mlx5_cmd_exec_in(mdev, rst2init_qp, in);
180 if (ret)
181 goto err_qp_modify_to_err;
182 }
183 {
184 u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {};
185
186 MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP);
187 MLX5_SET(init2rtr_qp_in, in, qpn, ipriv->qpn);
188 ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, in);
189 if (ret)
190 goto err_qp_modify_to_err;
191 }
192 {
193 u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {};
194
195 MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP);
196 MLX5_SET(rtr2rts_qp_in, in, qpn, ipriv->qpn);
197 ret = mlx5_cmd_exec_in(mdev, rtr2rts_qp, in);
198 if (ret)
199 goto err_qp_modify_to_err;
200 }
201 return 0;
202
203 err_qp_modify_to_err:
204 {
205 u32 in[MLX5_ST_SZ_DW(qp_2err_in)] = {};
206
207 MLX5_SET(qp_2err_in, in, opcode, MLX5_CMD_OP_2ERR_QP);
208 MLX5_SET(qp_2err_in, in, qpn, ipriv->qpn);
209 mlx5_cmd_exec_in(mdev, qp_2err, in);
210 }
211 return ret;
212 }
213
mlx5i_uninit_underlay_qp(struct mlx5e_priv * priv)214 void mlx5i_uninit_underlay_qp(struct mlx5e_priv *priv)
215 {
216 struct mlx5i_priv *ipriv = priv->ppriv;
217 struct mlx5_core_dev *mdev = priv->mdev;
218 u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {};
219
220 MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP);
221 MLX5_SET(qp_2rst_in, in, qpn, ipriv->qpn);
222 mlx5_cmd_exec_in(mdev, qp_2rst, in);
223 }
224
225 #define MLX5_QP_ENHANCED_ULP_STATELESS_MODE 2
226
mlx5i_create_underlay_qp(struct mlx5e_priv * priv)227 int mlx5i_create_underlay_qp(struct mlx5e_priv *priv)
228 {
229 unsigned char *dev_addr = priv->netdev->dev_addr;
230 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
231 u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {};
232 struct mlx5i_priv *ipriv = priv->ppriv;
233 void *addr_path;
234 int qpn = 0;
235 int ret = 0;
236 void *qpc;
237
238 if (MLX5_CAP_GEN(priv->mdev, mkey_by_name)) {
239 qpn = (dev_addr[1] << 16) + (dev_addr[2] << 8) + dev_addr[3];
240 MLX5_SET(create_qp_in, in, input_qpn, qpn);
241 }
242
243 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
244 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD);
245 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
246 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode,
247 MLX5_QP_ENHANCED_ULP_STATELESS_MODE);
248
249 addr_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
250 MLX5_SET(ads, addr_path, vhca_port_num, 1);
251 MLX5_SET(ads, addr_path, grh, 1);
252
253 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
254 ret = mlx5_cmd_exec_inout(priv->mdev, create_qp, in, out);
255 if (ret)
256 return ret;
257
258 ipriv->qpn = MLX5_GET(create_qp_out, out, qpn);
259
260 return 0;
261 }
262
mlx5i_destroy_underlay_qp(struct mlx5_core_dev * mdev,u32 qpn)263 void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, u32 qpn)
264 {
265 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
266
267 MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
268 MLX5_SET(destroy_qp_in, in, qpn, qpn);
269 mlx5_cmd_exec_in(mdev, destroy_qp, in);
270 }
271
mlx5i_update_nic_rx(struct mlx5e_priv * priv)272 int mlx5i_update_nic_rx(struct mlx5e_priv *priv)
273 {
274 return mlx5e_refresh_tirs(priv, true, true);
275 }
276
mlx5i_create_tis(struct mlx5_core_dev * mdev,u32 underlay_qpn,u32 * tisn)277 int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn)
278 {
279 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
280 void *tisc;
281
282 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
283
284 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
285
286 return mlx5e_create_tis(mdev, in, tisn);
287 }
288
mlx5i_init_tx(struct mlx5e_priv * priv)289 static int mlx5i_init_tx(struct mlx5e_priv *priv)
290 {
291 struct mlx5i_priv *ipriv = priv->ppriv;
292 int err;
293
294 err = mlx5i_create_underlay_qp(priv);
295 if (err) {
296 mlx5_core_warn(priv->mdev, "create underlay QP failed, %d\n", err);
297 return err;
298 }
299
300 err = mlx5i_create_tis(priv->mdev, ipriv->qpn, &priv->tisn[0][0]);
301 if (err) {
302 mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err);
303 goto err_destroy_underlay_qp;
304 }
305
306 return 0;
307
308 err_destroy_underlay_qp:
309 mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
310 return err;
311 }
312
mlx5i_cleanup_tx(struct mlx5e_priv * priv)313 static void mlx5i_cleanup_tx(struct mlx5e_priv *priv)
314 {
315 struct mlx5i_priv *ipriv = priv->ppriv;
316
317 mlx5e_destroy_tis(priv->mdev, priv->tisn[0][0]);
318 mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
319 }
320
mlx5i_create_flow_steering(struct mlx5e_priv * priv)321 static int mlx5i_create_flow_steering(struct mlx5e_priv *priv)
322 {
323 struct ttc_params ttc_params = {};
324 int tt, err;
325
326 priv->fs.ns = mlx5_get_flow_namespace(priv->mdev,
327 MLX5_FLOW_NAMESPACE_KERNEL);
328
329 if (!priv->fs.ns)
330 return -EINVAL;
331
332 err = mlx5e_arfs_create_tables(priv);
333 if (err) {
334 netdev_err(priv->netdev, "Failed to create arfs tables, err=%d\n",
335 err);
336 priv->netdev->hw_features &= ~NETIF_F_NTUPLE;
337 }
338
339 mlx5e_set_ttc_basic_params(priv, &ttc_params);
340 mlx5e_set_ttc_ft_params(&ttc_params);
341 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
342 ttc_params.indir_tirn[tt] = priv->indir_tir[tt].tirn;
343
344 err = mlx5e_create_ttc_table(priv, &ttc_params, &priv->fs.ttc);
345 if (err) {
346 netdev_err(priv->netdev, "Failed to create ttc table, err=%d\n",
347 err);
348 goto err_destroy_arfs_tables;
349 }
350
351 return 0;
352
353 err_destroy_arfs_tables:
354 mlx5e_arfs_destroy_tables(priv);
355
356 return err;
357 }
358
mlx5i_destroy_flow_steering(struct mlx5e_priv * priv)359 static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv)
360 {
361 mlx5e_destroy_ttc_table(priv, &priv->fs.ttc);
362 mlx5e_arfs_destroy_tables(priv);
363 }
364
mlx5i_init_rx(struct mlx5e_priv * priv)365 static int mlx5i_init_rx(struct mlx5e_priv *priv)
366 {
367 struct mlx5_core_dev *mdev = priv->mdev;
368 int err;
369
370 mlx5e_create_q_counters(priv);
371
372 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
373 if (err) {
374 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
375 goto err_destroy_q_counters;
376 }
377
378 err = mlx5e_create_indirect_rqt(priv);
379 if (err)
380 goto err_close_drop_rq;
381
382 err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
383 if (err)
384 goto err_destroy_indirect_rqts;
385
386 err = mlx5e_create_indirect_tirs(priv, false);
387 if (err)
388 goto err_destroy_direct_rqts;
389
390 err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
391 if (err)
392 goto err_destroy_indirect_tirs;
393
394 err = mlx5i_create_flow_steering(priv);
395 if (err)
396 goto err_destroy_direct_tirs;
397
398 return 0;
399
400 err_destroy_direct_tirs:
401 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
402 err_destroy_indirect_tirs:
403 mlx5e_destroy_indirect_tirs(priv);
404 err_destroy_direct_rqts:
405 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
406 err_destroy_indirect_rqts:
407 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
408 err_close_drop_rq:
409 mlx5e_close_drop_rq(&priv->drop_rq);
410 err_destroy_q_counters:
411 mlx5e_destroy_q_counters(priv);
412 return err;
413 }
414
mlx5i_cleanup_rx(struct mlx5e_priv * priv)415 static void mlx5i_cleanup_rx(struct mlx5e_priv *priv)
416 {
417 mlx5i_destroy_flow_steering(priv);
418 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
419 mlx5e_destroy_indirect_tirs(priv);
420 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
421 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
422 mlx5e_close_drop_rq(&priv->drop_rq);
423 mlx5e_destroy_q_counters(priv);
424 }
425
426 /* The stats groups order is opposite to the update_stats() order calls */
427 static mlx5e_stats_grp_t mlx5i_stats_grps[] = {
428 &MLX5E_STATS_GRP(sw),
429 &MLX5E_STATS_GRP(qcnt),
430 &MLX5E_STATS_GRP(vnic_env),
431 &MLX5E_STATS_GRP(vport),
432 &MLX5E_STATS_GRP(802_3),
433 &MLX5E_STATS_GRP(2863),
434 &MLX5E_STATS_GRP(2819),
435 &MLX5E_STATS_GRP(phy),
436 &MLX5E_STATS_GRP(pcie),
437 &MLX5E_STATS_GRP(per_prio),
438 &MLX5E_STATS_GRP(pme),
439 &MLX5E_STATS_GRP(channels),
440 &MLX5E_STATS_GRP(per_port_buff_congest),
441 };
442
mlx5i_stats_grps_num(struct mlx5e_priv * priv)443 static unsigned int mlx5i_stats_grps_num(struct mlx5e_priv *priv)
444 {
445 return ARRAY_SIZE(mlx5i_stats_grps);
446 }
447
448 static const struct mlx5e_profile mlx5i_nic_profile = {
449 .init = mlx5i_init,
450 .cleanup = mlx5i_cleanup,
451 .init_tx = mlx5i_init_tx,
452 .cleanup_tx = mlx5i_cleanup_tx,
453 .init_rx = mlx5i_init_rx,
454 .cleanup_rx = mlx5i_cleanup_rx,
455 .enable = NULL, /* mlx5i_enable */
456 .disable = NULL, /* mlx5i_disable */
457 .update_rx = mlx5i_update_nic_rx,
458 .update_stats = NULL, /* mlx5i_update_stats */
459 .update_carrier = NULL, /* no HW update in IB link */
460 .rx_handlers = &mlx5i_rx_handlers,
461 .max_tc = MLX5I_MAX_NUM_TC,
462 .rq_groups = MLX5E_NUM_RQ_GROUPS(REGULAR),
463 .stats_grps = mlx5i_stats_grps,
464 .stats_grps_num = mlx5i_stats_grps_num,
465 };
466
467 /* mlx5i netdev NDos */
468
mlx5i_change_mtu(struct net_device * netdev,int new_mtu)469 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu)
470 {
471 struct mlx5e_priv *priv = mlx5i_epriv(netdev);
472 struct mlx5e_channels new_channels = {};
473 struct mlx5e_params *params;
474 int err = 0;
475
476 mutex_lock(&priv->state_lock);
477
478 params = &priv->channels.params;
479
480 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
481 params->sw_mtu = new_mtu;
482 netdev->mtu = params->sw_mtu;
483 goto out;
484 }
485
486 new_channels.params = *params;
487 new_channels.params.sw_mtu = new_mtu;
488
489 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
490 if (err)
491 goto out;
492
493 netdev->mtu = new_channels.params.sw_mtu;
494
495 out:
496 mutex_unlock(&priv->state_lock);
497 return err;
498 }
499
mlx5i_dev_init(struct net_device * dev)500 int mlx5i_dev_init(struct net_device *dev)
501 {
502 struct mlx5e_priv *priv = mlx5i_epriv(dev);
503 struct mlx5i_priv *ipriv = priv->ppriv;
504
505 /* Set dev address using underlay QP */
506 dev->dev_addr[1] = (ipriv->qpn >> 16) & 0xff;
507 dev->dev_addr[2] = (ipriv->qpn >> 8) & 0xff;
508 dev->dev_addr[3] = (ipriv->qpn) & 0xff;
509
510 /* Add QPN to net-device mapping to HT */
511 mlx5i_pkey_add_qpn(dev, ipriv->qpn);
512
513 return 0;
514 }
515
mlx5i_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)516 int mlx5i_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
517 {
518 struct mlx5e_priv *priv = mlx5i_epriv(dev);
519
520 switch (cmd) {
521 case SIOCSHWTSTAMP:
522 return mlx5e_hwstamp_set(priv, ifr);
523 case SIOCGHWTSTAMP:
524 return mlx5e_hwstamp_get(priv, ifr);
525 default:
526 return -EOPNOTSUPP;
527 }
528 }
529
mlx5i_dev_cleanup(struct net_device * dev)530 void mlx5i_dev_cleanup(struct net_device *dev)
531 {
532 struct mlx5e_priv *priv = mlx5i_epriv(dev);
533 struct mlx5i_priv *ipriv = priv->ppriv;
534
535 mlx5i_uninit_underlay_qp(priv);
536
537 /* Delete QPN to net-device mapping from HT */
538 mlx5i_pkey_del_qpn(dev, ipriv->qpn);
539 }
540
mlx5i_open(struct net_device * netdev)541 static int mlx5i_open(struct net_device *netdev)
542 {
543 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
544 struct mlx5i_priv *ipriv = epriv->ppriv;
545 struct mlx5_core_dev *mdev = epriv->mdev;
546 int err;
547
548 mutex_lock(&epriv->state_lock);
549
550 set_bit(MLX5E_STATE_OPENED, &epriv->state);
551
552 err = mlx5i_init_underlay_qp(epriv);
553 if (err) {
554 mlx5_core_warn(mdev, "prepare underlay qp state failed, %d\n", err);
555 goto err_clear_state_opened_flag;
556 }
557
558 err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qpn);
559 if (err) {
560 mlx5_core_warn(mdev, "attach underlay qp to ft failed, %d\n", err);
561 goto err_reset_qp;
562 }
563
564 err = mlx5e_open_channels(epriv, &epriv->channels);
565 if (err)
566 goto err_remove_fs_underlay_qp;
567
568 epriv->profile->update_rx(epriv);
569 mlx5e_activate_priv_channels(epriv);
570
571 mutex_unlock(&epriv->state_lock);
572 return 0;
573
574 err_remove_fs_underlay_qp:
575 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
576 err_reset_qp:
577 mlx5i_uninit_underlay_qp(epriv);
578 err_clear_state_opened_flag:
579 clear_bit(MLX5E_STATE_OPENED, &epriv->state);
580 mutex_unlock(&epriv->state_lock);
581 return err;
582 }
583
mlx5i_close(struct net_device * netdev)584 static int mlx5i_close(struct net_device *netdev)
585 {
586 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
587 struct mlx5i_priv *ipriv = epriv->ppriv;
588 struct mlx5_core_dev *mdev = epriv->mdev;
589
590 /* May already be CLOSED in case a previous configuration operation
591 * (e.g RX/TX queue size change) that involves close&open failed.
592 */
593 mutex_lock(&epriv->state_lock);
594
595 if (!test_bit(MLX5E_STATE_OPENED, &epriv->state))
596 goto unlock;
597
598 clear_bit(MLX5E_STATE_OPENED, &epriv->state);
599
600 netif_carrier_off(epriv->netdev);
601 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
602 mlx5e_deactivate_priv_channels(epriv);
603 mlx5e_close_channels(&epriv->channels);
604 mlx5i_uninit_underlay_qp(epriv);
605 unlock:
606 mutex_unlock(&epriv->state_lock);
607 return 0;
608 }
609
610 /* IPoIB RDMA netdev callbacks */
mlx5i_attach_mcast(struct net_device * netdev,struct ib_device * hca,union ib_gid * gid,u16 lid,int set_qkey,u32 qkey)611 static int mlx5i_attach_mcast(struct net_device *netdev, struct ib_device *hca,
612 union ib_gid *gid, u16 lid, int set_qkey,
613 u32 qkey)
614 {
615 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
616 struct mlx5_core_dev *mdev = epriv->mdev;
617 struct mlx5i_priv *ipriv = epriv->ppriv;
618 int err;
619
620 mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qpn,
621 gid->raw);
622 err = mlx5_core_attach_mcg(mdev, gid, ipriv->qpn);
623 if (err)
624 mlx5_core_warn(mdev, "failed attaching QPN 0x%x, MGID %pI6\n",
625 ipriv->qpn, gid->raw);
626
627 if (set_qkey) {
628 mlx5_core_dbg(mdev, "%s setting qkey 0x%x\n",
629 netdev->name, qkey);
630 ipriv->qkey = qkey;
631 }
632
633 return err;
634 }
635
mlx5i_detach_mcast(struct net_device * netdev,struct ib_device * hca,union ib_gid * gid,u16 lid)636 static int mlx5i_detach_mcast(struct net_device *netdev, struct ib_device *hca,
637 union ib_gid *gid, u16 lid)
638 {
639 struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
640 struct mlx5_core_dev *mdev = epriv->mdev;
641 struct mlx5i_priv *ipriv = epriv->ppriv;
642 int err;
643
644 mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qpn,
645 gid->raw);
646
647 err = mlx5_core_detach_mcg(mdev, gid, ipriv->qpn);
648 if (err)
649 mlx5_core_dbg(mdev, "failed detaching QPN 0x%x, MGID %pI6\n",
650 ipriv->qpn, gid->raw);
651
652 return err;
653 }
654
mlx5i_xmit(struct net_device * dev,struct sk_buff * skb,struct ib_ah * address,u32 dqpn)655 static int mlx5i_xmit(struct net_device *dev, struct sk_buff *skb,
656 struct ib_ah *address, u32 dqpn)
657 {
658 struct mlx5e_priv *epriv = mlx5i_epriv(dev);
659 struct mlx5e_txqsq *sq = epriv->txq2sq[skb_get_queue_mapping(skb)];
660 struct mlx5_ib_ah *mah = to_mah(address);
661 struct mlx5i_priv *ipriv = epriv->ppriv;
662
663 mlx5i_sq_xmit(sq, skb, &mah->av, dqpn, ipriv->qkey, netdev_xmit_more());
664
665 return NETDEV_TX_OK;
666 }
667
mlx5i_set_pkey_index(struct net_device * netdev,int id)668 static void mlx5i_set_pkey_index(struct net_device *netdev, int id)
669 {
670 struct mlx5i_priv *ipriv = netdev_priv(netdev);
671
672 ipriv->pkey_index = (u16)id;
673 }
674
mlx5i_check_required_hca_cap(struct mlx5_core_dev * mdev)675 static int mlx5i_check_required_hca_cap(struct mlx5_core_dev *mdev)
676 {
677 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
678 return -EOPNOTSUPP;
679
680 if (!MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) {
681 mlx5_core_warn(mdev, "IPoIB enhanced offloads are not supported\n");
682 return -EOPNOTSUPP;
683 }
684
685 return 0;
686 }
687
mlx5_rdma_netdev_free(struct net_device * netdev)688 static void mlx5_rdma_netdev_free(struct net_device *netdev)
689 {
690 struct mlx5e_priv *priv = mlx5i_epriv(netdev);
691 struct mlx5i_priv *ipriv = priv->ppriv;
692 const struct mlx5e_profile *profile = priv->profile;
693
694 mlx5e_detach_netdev(priv);
695 profile->cleanup(priv);
696
697 if (!ipriv->sub_interface) {
698 mlx5i_pkey_qpn_ht_cleanup(netdev);
699 mlx5e_destroy_mdev_resources(priv->mdev);
700 }
701 }
702
mlx5_is_sub_interface(struct mlx5_core_dev * mdev)703 static bool mlx5_is_sub_interface(struct mlx5_core_dev *mdev)
704 {
705 return mdev->mlx5e_res.pdn != 0;
706 }
707
mlx5_get_profile(struct mlx5_core_dev * mdev)708 static const struct mlx5e_profile *mlx5_get_profile(struct mlx5_core_dev *mdev)
709 {
710 if (mlx5_is_sub_interface(mdev))
711 return mlx5i_pkey_get_profile();
712 return &mlx5i_nic_profile;
713 }
714
mlx5_rdma_setup_rn(struct ib_device * ibdev,u8 port_num,struct net_device * netdev,void * param)715 static int mlx5_rdma_setup_rn(struct ib_device *ibdev, u8 port_num,
716 struct net_device *netdev, void *param)
717 {
718 struct mlx5_core_dev *mdev = (struct mlx5_core_dev *)param;
719 const struct mlx5e_profile *prof = mlx5_get_profile(mdev);
720 struct mlx5i_priv *ipriv;
721 struct mlx5e_priv *epriv;
722 struct rdma_netdev *rn;
723 int err;
724
725 ipriv = netdev_priv(netdev);
726 epriv = mlx5i_epriv(netdev);
727
728 ipriv->sub_interface = mlx5_is_sub_interface(mdev);
729 if (!ipriv->sub_interface) {
730 err = mlx5i_pkey_qpn_ht_init(netdev);
731 if (err) {
732 mlx5_core_warn(mdev, "allocate qpn_to_netdev ht failed\n");
733 return err;
734 }
735
736 /* This should only be called once per mdev */
737 err = mlx5e_create_mdev_resources(mdev);
738 if (err)
739 goto destroy_ht;
740 }
741
742 prof->init(mdev, netdev, prof, ipriv);
743
744 err = mlx5e_attach_netdev(epriv);
745 if (err)
746 goto detach;
747 netif_carrier_off(netdev);
748
749 /* set rdma_netdev func pointers */
750 rn = &ipriv->rn;
751 rn->hca = ibdev;
752 rn->send = mlx5i_xmit;
753 rn->attach_mcast = mlx5i_attach_mcast;
754 rn->detach_mcast = mlx5i_detach_mcast;
755 rn->set_id = mlx5i_set_pkey_index;
756
757 netdev->priv_destructor = mlx5_rdma_netdev_free;
758 netdev->needs_free_netdev = 1;
759
760 return 0;
761
762 detach:
763 prof->cleanup(epriv);
764 if (ipriv->sub_interface)
765 return err;
766 mlx5e_destroy_mdev_resources(mdev);
767 destroy_ht:
768 mlx5i_pkey_qpn_ht_cleanup(netdev);
769 return err;
770 }
771
mlx5_rdma_rn_get_params(struct mlx5_core_dev * mdev,struct ib_device * device,struct rdma_netdev_alloc_params * params)772 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
773 struct ib_device *device,
774 struct rdma_netdev_alloc_params *params)
775 {
776 int nch;
777 int rc;
778
779 rc = mlx5i_check_required_hca_cap(mdev);
780 if (rc)
781 return rc;
782
783 nch = mlx5e_get_max_num_channels(mdev);
784
785 *params = (struct rdma_netdev_alloc_params){
786 .sizeof_priv = sizeof(struct mlx5i_priv) +
787 sizeof(struct mlx5e_priv),
788 .txqs = nch * MLX5E_MAX_NUM_TC,
789 .rxqs = nch,
790 .param = mdev,
791 .initialize_rdma_netdev = mlx5_rdma_setup_rn,
792 };
793
794 return 0;
795 }
796 EXPORT_SYMBOL(mlx5_rdma_rn_get_params);
797