1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <drm/drm_damage_helper.h>
9 #include <drm/drm_fourcc.h>
10 #include <drm/drm_print.h>
11
12 #include "mdp5_kms.h"
13
14 struct mdp5_plane {
15 struct drm_plane base;
16
17 uint32_t nformats;
18 uint32_t formats[32];
19 };
20 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
21
22 static int mdp5_plane_mode_set(struct drm_plane *plane,
23 struct drm_crtc *crtc, struct drm_framebuffer *fb,
24 struct drm_rect *src, struct drm_rect *dest);
25
get_kms(struct drm_plane * plane)26 static struct mdp5_kms *get_kms(struct drm_plane *plane)
27 {
28 struct msm_drm_private *priv = plane->dev->dev_private;
29 return to_mdp5_kms(to_mdp_kms(priv->kms));
30 }
31
plane_enabled(struct drm_plane_state * state)32 static bool plane_enabled(struct drm_plane_state *state)
33 {
34 return state->visible;
35 }
36
mdp5_plane_destroy(struct drm_plane * plane)37 static void mdp5_plane_destroy(struct drm_plane *plane)
38 {
39 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
40
41 drm_plane_cleanup(plane);
42
43 kfree(mdp5_plane);
44 }
45
mdp5_plane_install_rotation_property(struct drm_device * dev,struct drm_plane * plane)46 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
47 struct drm_plane *plane)
48 {
49 drm_plane_create_rotation_property(plane,
50 DRM_MODE_ROTATE_0,
51 DRM_MODE_ROTATE_0 |
52 DRM_MODE_ROTATE_180 |
53 DRM_MODE_REFLECT_X |
54 DRM_MODE_REFLECT_Y);
55 }
56
57 /* helper to install properties which are common to planes and crtcs */
mdp5_plane_install_properties(struct drm_plane * plane,struct drm_mode_object * obj)58 static void mdp5_plane_install_properties(struct drm_plane *plane,
59 struct drm_mode_object *obj)
60 {
61 struct drm_device *dev = plane->dev;
62 struct msm_drm_private *dev_priv = dev->dev_private;
63 struct drm_property *prop;
64
65 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
66 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
67 if (!prop) { \
68 prop = drm_property_##fnc(dev, 0, #name, \
69 ##__VA_ARGS__); \
70 if (!prop) { \
71 dev_warn(dev->dev, \
72 "Create property %s failed\n", \
73 #name); \
74 return; \
75 } \
76 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
77 } \
78 drm_object_attach_property(&plane->base, prop, init_val); \
79 } while (0)
80
81 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
82 INSTALL_PROPERTY(name, NAME, init_val, \
83 create_range, min, max)
84
85 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
86 INSTALL_PROPERTY(name, NAME, init_val, \
87 create_enum, name##_prop_enum_list, \
88 ARRAY_SIZE(name##_prop_enum_list))
89
90 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
91
92 mdp5_plane_install_rotation_property(dev, plane);
93
94 #undef INSTALL_RANGE_PROPERTY
95 #undef INSTALL_ENUM_PROPERTY
96 #undef INSTALL_PROPERTY
97 }
98
mdp5_plane_atomic_set_property(struct drm_plane * plane,struct drm_plane_state * state,struct drm_property * property,uint64_t val)99 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
100 struct drm_plane_state *state, struct drm_property *property,
101 uint64_t val)
102 {
103 struct drm_device *dev = plane->dev;
104 struct mdp5_plane_state *pstate;
105 struct msm_drm_private *dev_priv = dev->dev_private;
106 int ret = 0;
107
108 pstate = to_mdp5_plane_state(state);
109
110 #define SET_PROPERTY(name, NAME, type) do { \
111 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
112 pstate->name = (type)val; \
113 DBG("Set property %s %d", #name, (type)val); \
114 goto done; \
115 } \
116 } while (0)
117
118 SET_PROPERTY(zpos, ZPOS, uint8_t);
119
120 DRM_DEV_ERROR(dev->dev, "Invalid property\n");
121 ret = -EINVAL;
122 done:
123 return ret;
124 #undef SET_PROPERTY
125 }
126
mdp5_plane_atomic_get_property(struct drm_plane * plane,const struct drm_plane_state * state,struct drm_property * property,uint64_t * val)127 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
128 const struct drm_plane_state *state,
129 struct drm_property *property, uint64_t *val)
130 {
131 struct drm_device *dev = plane->dev;
132 struct mdp5_plane_state *pstate;
133 struct msm_drm_private *dev_priv = dev->dev_private;
134 int ret = 0;
135
136 pstate = to_mdp5_plane_state(state);
137
138 #define GET_PROPERTY(name, NAME, type) do { \
139 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
140 *val = pstate->name; \
141 DBG("Get property %s %lld", #name, *val); \
142 goto done; \
143 } \
144 } while (0)
145
146 GET_PROPERTY(zpos, ZPOS, uint8_t);
147
148 DRM_DEV_ERROR(dev->dev, "Invalid property\n");
149 ret = -EINVAL;
150 done:
151 return ret;
152 #undef SET_PROPERTY
153 }
154
155 static void
mdp5_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)156 mdp5_plane_atomic_print_state(struct drm_printer *p,
157 const struct drm_plane_state *state)
158 {
159 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
160 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
161
162 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
163 pstate->hwpipe->name : "(null)");
164 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
165 drm_printf(p, "\tright-hwpipe=%s\n",
166 pstate->r_hwpipe ? pstate->r_hwpipe->name :
167 "(null)");
168 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
169 drm_printf(p, "\tzpos=%u\n", pstate->zpos);
170 drm_printf(p, "\talpha=%u\n", pstate->alpha);
171 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
172 }
173
mdp5_plane_reset(struct drm_plane * plane)174 static void mdp5_plane_reset(struct drm_plane *plane)
175 {
176 struct mdp5_plane_state *mdp5_state;
177
178 if (plane->state && plane->state->fb)
179 drm_framebuffer_put(plane->state->fb);
180
181 kfree(to_mdp5_plane_state(plane->state));
182 plane->state = NULL;
183 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
184 if (!mdp5_state)
185 return;
186
187 /* assign default blend parameters */
188 mdp5_state->alpha = 255;
189 mdp5_state->premultiplied = 0;
190
191 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
192 mdp5_state->zpos = STAGE_BASE;
193 else
194 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
195
196 mdp5_state->base.plane = plane;
197
198 plane->state = &mdp5_state->base;
199 }
200
201 static struct drm_plane_state *
mdp5_plane_duplicate_state(struct drm_plane * plane)202 mdp5_plane_duplicate_state(struct drm_plane *plane)
203 {
204 struct mdp5_plane_state *mdp5_state;
205
206 if (WARN_ON(!plane->state))
207 return NULL;
208
209 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
210 sizeof(*mdp5_state), GFP_KERNEL);
211 if (!mdp5_state)
212 return NULL;
213
214 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
215
216 return &mdp5_state->base;
217 }
218
mdp5_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)219 static void mdp5_plane_destroy_state(struct drm_plane *plane,
220 struct drm_plane_state *state)
221 {
222 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
223
224 if (state->fb)
225 drm_framebuffer_put(state->fb);
226
227 kfree(pstate);
228 }
229
230 static const struct drm_plane_funcs mdp5_plane_funcs = {
231 .update_plane = drm_atomic_helper_update_plane,
232 .disable_plane = drm_atomic_helper_disable_plane,
233 .destroy = mdp5_plane_destroy,
234 .atomic_set_property = mdp5_plane_atomic_set_property,
235 .atomic_get_property = mdp5_plane_atomic_get_property,
236 .reset = mdp5_plane_reset,
237 .atomic_duplicate_state = mdp5_plane_duplicate_state,
238 .atomic_destroy_state = mdp5_plane_destroy_state,
239 .atomic_print_state = mdp5_plane_atomic_print_state,
240 };
241
mdp5_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)242 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
243 struct drm_plane_state *old_state)
244 {
245 struct mdp5_kms *mdp5_kms = get_kms(plane);
246 struct msm_kms *kms = &mdp5_kms->base.base;
247 struct drm_framebuffer *fb = old_state->fb;
248
249 if (!fb)
250 return;
251
252 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
253 msm_framebuffer_cleanup(fb, kms->aspace);
254 }
255
mdp5_plane_atomic_check_with_state(struct drm_crtc_state * crtc_state,struct drm_plane_state * state)256 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
257 struct drm_plane_state *state)
258 {
259 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
260 struct drm_plane *plane = state->plane;
261 struct drm_plane_state *old_state = plane->state;
262 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
263 bool new_hwpipe = false;
264 bool need_right_hwpipe = false;
265 uint32_t max_width, max_height;
266 bool out_of_bounds = false;
267 uint32_t caps = 0;
268 int min_scale, max_scale;
269 int ret;
270
271 DBG("%s: check (%d -> %d)", plane->name,
272 plane_enabled(old_state), plane_enabled(state));
273
274 max_width = config->hw->lm.max_width << 16;
275 max_height = config->hw->lm.max_height << 16;
276
277 /* Make sure source dimensions are within bounds. */
278 if (state->src_h > max_height)
279 out_of_bounds = true;
280
281 if (state->src_w > max_width) {
282 /* If source split is supported, we can go up to 2x
283 * the max LM width, but we'd need to stage another
284 * hwpipe to the right LM. So, the drm_plane would
285 * consist of 2 hwpipes.
286 */
287 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
288 (state->src_w <= 2 * max_width))
289 need_right_hwpipe = true;
290 else
291 out_of_bounds = true;
292 }
293
294 if (out_of_bounds) {
295 struct drm_rect src = drm_plane_state_src(state);
296 DBG("Invalid source size "DRM_RECT_FP_FMT,
297 DRM_RECT_FP_ARG(&src));
298 return -ERANGE;
299 }
300
301 min_scale = FRAC_16_16(1, 8);
302 max_scale = FRAC_16_16(8, 1);
303
304 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
305 min_scale, max_scale,
306 true, true);
307 if (ret)
308 return ret;
309
310 if (plane_enabled(state)) {
311 unsigned int rotation;
312 const struct mdp_format *format;
313 struct mdp5_kms *mdp5_kms = get_kms(plane);
314 uint32_t blkcfg = 0;
315
316 format = to_mdp_format(msm_framebuffer_format(state->fb));
317 if (MDP_FORMAT_IS_YUV(format))
318 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
319
320 if (((state->src_w >> 16) != state->crtc_w) ||
321 ((state->src_h >> 16) != state->crtc_h))
322 caps |= MDP_PIPE_CAP_SCALE;
323
324 rotation = drm_rotation_simplify(state->rotation,
325 DRM_MODE_ROTATE_0 |
326 DRM_MODE_REFLECT_X |
327 DRM_MODE_REFLECT_Y);
328
329 if (rotation & DRM_MODE_REFLECT_X)
330 caps |= MDP_PIPE_CAP_HFLIP;
331
332 if (rotation & DRM_MODE_REFLECT_Y)
333 caps |= MDP_PIPE_CAP_VFLIP;
334
335 if (plane->type == DRM_PLANE_TYPE_CURSOR)
336 caps |= MDP_PIPE_CAP_CURSOR;
337
338 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
339 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
340 new_hwpipe = true;
341
342 /*
343 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
344 * or we're switching from 2 hw pipes to 1 hw pipe because the
345 * new src_w can be supported by 1 hw pipe itself.
346 */
347 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
348 (!need_right_hwpipe && mdp5_state->r_hwpipe))
349 new_hwpipe = true;
350
351 if (mdp5_kms->smp) {
352 const struct mdp_format *format =
353 to_mdp_format(msm_framebuffer_format(state->fb));
354
355 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
356 state->src_w >> 16, false);
357
358 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
359 new_hwpipe = true;
360 }
361
362 /* (re)assign hwpipe if needed, otherwise keep old one: */
363 if (new_hwpipe) {
364 /* TODO maybe we want to re-assign hwpipe sometimes
365 * in cases when we no-longer need some caps to make
366 * it available for other planes?
367 */
368 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
369 struct mdp5_hw_pipe *old_right_hwpipe =
370 mdp5_state->r_hwpipe;
371 struct mdp5_hw_pipe *new_hwpipe = NULL;
372 struct mdp5_hw_pipe *new_right_hwpipe = NULL;
373
374 ret = mdp5_pipe_assign(state->state, plane, caps,
375 blkcfg, &new_hwpipe,
376 need_right_hwpipe ?
377 &new_right_hwpipe : NULL);
378 if (ret) {
379 DBG("%s: failed to assign hwpipe(s)!",
380 plane->name);
381 return ret;
382 }
383
384 mdp5_state->hwpipe = new_hwpipe;
385 if (need_right_hwpipe)
386 mdp5_state->r_hwpipe = new_right_hwpipe;
387 else
388 /*
389 * set it to NULL so that the driver knows we
390 * don't have a right hwpipe when committing a
391 * new state
392 */
393 mdp5_state->r_hwpipe = NULL;
394
395
396 ret = mdp5_pipe_release(state->state, old_hwpipe);
397 if (ret)
398 return ret;
399
400 ret = mdp5_pipe_release(state->state, old_right_hwpipe);
401 if (ret)
402 return ret;
403
404 }
405 } else {
406 ret = mdp5_pipe_release(state->state, mdp5_state->hwpipe);
407 if (ret)
408 return ret;
409
410 ret = mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
411 if (ret)
412 return ret;
413
414 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
415 }
416
417 return 0;
418 }
419
mdp5_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)420 static int mdp5_plane_atomic_check(struct drm_plane *plane,
421 struct drm_plane_state *state)
422 {
423 struct drm_crtc *crtc;
424 struct drm_crtc_state *crtc_state;
425
426 crtc = state->crtc ? state->crtc : plane->state->crtc;
427 if (!crtc)
428 return 0;
429
430 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
431 if (WARN_ON(!crtc_state))
432 return -EINVAL;
433
434 return mdp5_plane_atomic_check_with_state(crtc_state, state);
435 }
436
mdp5_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)437 static void mdp5_plane_atomic_update(struct drm_plane *plane,
438 struct drm_plane_state *old_state)
439 {
440 struct drm_plane_state *state = plane->state;
441
442 DBG("%s: update", plane->name);
443
444 if (plane_enabled(state)) {
445 int ret;
446
447 ret = mdp5_plane_mode_set(plane,
448 state->crtc, state->fb,
449 &state->src, &state->dst);
450 /* atomic_check should have ensured that this doesn't fail */
451 WARN_ON(ret < 0);
452 }
453 }
454
mdp5_plane_atomic_async_check(struct drm_plane * plane,struct drm_plane_state * state)455 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
456 struct drm_plane_state *state)
457 {
458 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
459 struct drm_crtc_state *crtc_state;
460 int min_scale, max_scale;
461 int ret;
462
463 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
464 state->crtc);
465 if (WARN_ON(!crtc_state))
466 return -EINVAL;
467
468 if (!crtc_state->active)
469 return -EINVAL;
470
471 mdp5_state = to_mdp5_plane_state(state);
472
473 /* don't use fast path if we don't have a hwpipe allocated yet */
474 if (!mdp5_state->hwpipe)
475 return -EINVAL;
476
477 /* only allow changing of position(crtc x/y or src x/y) in fast path */
478 if (plane->state->crtc != state->crtc ||
479 plane->state->src_w != state->src_w ||
480 plane->state->src_h != state->src_h ||
481 plane->state->crtc_w != state->crtc_w ||
482 plane->state->crtc_h != state->crtc_h ||
483 !plane->state->fb ||
484 plane->state->fb != state->fb)
485 return -EINVAL;
486
487 min_scale = FRAC_16_16(1, 8);
488 max_scale = FRAC_16_16(8, 1);
489
490 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
491 min_scale, max_scale,
492 true, true);
493 if (ret)
494 return ret;
495
496 /*
497 * if the visibility of the plane changes (i.e, if the cursor is
498 * clipped out completely, we can't take the async path because
499 * we need to stage/unstage the plane from the Layer Mixer(s). We
500 * also assign/unassign the hwpipe(s) tied to the plane. We avoid
501 * taking the fast path for both these reasons.
502 */
503 if (state->visible != plane->state->visible)
504 return -EINVAL;
505
506 return 0;
507 }
508
mdp5_plane_atomic_async_update(struct drm_plane * plane,struct drm_plane_state * new_state)509 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
510 struct drm_plane_state *new_state)
511 {
512 struct drm_framebuffer *old_fb = plane->state->fb;
513
514 plane->state->src_x = new_state->src_x;
515 plane->state->src_y = new_state->src_y;
516 plane->state->crtc_x = new_state->crtc_x;
517 plane->state->crtc_y = new_state->crtc_y;
518
519 if (plane_enabled(new_state)) {
520 struct mdp5_ctl *ctl;
521 struct mdp5_pipeline *pipeline =
522 mdp5_crtc_get_pipeline(new_state->crtc);
523 int ret;
524
525 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
526 &new_state->src, &new_state->dst);
527 WARN_ON(ret < 0);
528
529 ctl = mdp5_crtc_get_ctl(new_state->crtc);
530
531 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
532 }
533
534 *to_mdp5_plane_state(plane->state) =
535 *to_mdp5_plane_state(new_state);
536
537 new_state->fb = old_fb;
538 }
539
540 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
541 .prepare_fb = msm_atomic_prepare_fb,
542 .cleanup_fb = mdp5_plane_cleanup_fb,
543 .atomic_check = mdp5_plane_atomic_check,
544 .atomic_update = mdp5_plane_atomic_update,
545 .atomic_async_check = mdp5_plane_atomic_async_check,
546 .atomic_async_update = mdp5_plane_atomic_async_update,
547 };
548
set_scanout_locked(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct drm_framebuffer * fb)549 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
550 enum mdp5_pipe pipe,
551 struct drm_framebuffer *fb)
552 {
553 struct msm_kms *kms = &mdp5_kms->base.base;
554
555 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
556 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
557 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
558
559 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
560 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
561 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
562
563 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
564 msm_framebuffer_iova(fb, kms->aspace, 0));
565 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
566 msm_framebuffer_iova(fb, kms->aspace, 1));
567 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
568 msm_framebuffer_iova(fb, kms->aspace, 2));
569 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
570 msm_framebuffer_iova(fb, kms->aspace, 3));
571 }
572
573 /* Note: mdp5_plane->pipe_lock must be locked */
csc_disable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe)574 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
575 {
576 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
577 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
578
579 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
580 }
581
582 /* Note: mdp5_plane->pipe_lock must be locked */
csc_enable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct csc_cfg * csc)583 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
584 struct csc_cfg *csc)
585 {
586 uint32_t i, mode = 0; /* RGB, no CSC */
587 uint32_t *matrix;
588
589 if (unlikely(!csc))
590 return;
591
592 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
593 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
594 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
595 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
596 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
597 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
598
599 matrix = csc->matrix;
600 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
601 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
602 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
603 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
604 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
605 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
606 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
607 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
608 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
609 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
610 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
611 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
612 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
613 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
614
615 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
616 uint32_t *pre_clamp = csc->pre_clamp;
617 uint32_t *post_clamp = csc->post_clamp;
618
619 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
620 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
621 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
622
623 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
624 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
625 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
626
627 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
628 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
629
630 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
631 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
632 }
633 }
634
635 #define PHASE_STEP_SHIFT 21
636 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
637
calc_phase_step(uint32_t src,uint32_t dst,uint32_t * out_phase)638 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
639 {
640 uint32_t unit;
641
642 if (src == 0 || dst == 0)
643 return -EINVAL;
644
645 /*
646 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
647 * where 2^21 represents the unity "1" in fixed-point hardware design.
648 * This leaves 5 bits for the integer part (downscale case):
649 * -> maximum downscale ratio = 0b1_1111 = 31
650 */
651 if (src > (dst * DOWN_SCALE_RATIO_MAX))
652 return -EOVERFLOW;
653
654 unit = 1 << PHASE_STEP_SHIFT;
655 *out_phase = mult_frac(unit, src, dst);
656
657 return 0;
658 }
659
calc_scalex_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasex_steps[COMP_MAX])660 static int calc_scalex_steps(struct drm_plane *plane,
661 uint32_t pixel_format, uint32_t src, uint32_t dest,
662 uint32_t phasex_steps[COMP_MAX])
663 {
664 const struct drm_format_info *info = drm_format_info(pixel_format);
665 struct mdp5_kms *mdp5_kms = get_kms(plane);
666 struct device *dev = mdp5_kms->dev->dev;
667 uint32_t phasex_step;
668 int ret;
669
670 ret = calc_phase_step(src, dest, &phasex_step);
671 if (ret) {
672 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
673 return ret;
674 }
675
676 phasex_steps[COMP_0] = phasex_step;
677 phasex_steps[COMP_3] = phasex_step;
678 phasex_steps[COMP_1_2] = phasex_step / info->hsub;
679
680 return 0;
681 }
682
calc_scaley_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasey_steps[COMP_MAX])683 static int calc_scaley_steps(struct drm_plane *plane,
684 uint32_t pixel_format, uint32_t src, uint32_t dest,
685 uint32_t phasey_steps[COMP_MAX])
686 {
687 const struct drm_format_info *info = drm_format_info(pixel_format);
688 struct mdp5_kms *mdp5_kms = get_kms(plane);
689 struct device *dev = mdp5_kms->dev->dev;
690 uint32_t phasey_step;
691 int ret;
692
693 ret = calc_phase_step(src, dest, &phasey_step);
694 if (ret) {
695 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
696 return ret;
697 }
698
699 phasey_steps[COMP_0] = phasey_step;
700 phasey_steps[COMP_3] = phasey_step;
701 phasey_steps[COMP_1_2] = phasey_step / info->vsub;
702
703 return 0;
704 }
705
get_scale_config(const struct mdp_format * format,uint32_t src,uint32_t dst,bool horz)706 static uint32_t get_scale_config(const struct mdp_format *format,
707 uint32_t src, uint32_t dst, bool horz)
708 {
709 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
710 bool scaling = format->is_yuv ? true : (src != dst);
711 uint32_t sub;
712 uint32_t ya_filter, uv_filter;
713 bool yuv = format->is_yuv;
714
715 if (!scaling)
716 return 0;
717
718 if (yuv) {
719 sub = horz ? info->hsub : info->vsub;
720 uv_filter = ((src / sub) <= dst) ?
721 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
722 }
723 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
724
725 if (horz)
726 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
727 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
728 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
729 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
730 else
731 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
732 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
733 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
734 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
735 }
736
calc_pixel_ext(const struct mdp_format * format,uint32_t src,uint32_t dst,uint32_t phase_step[2],int pix_ext_edge1[COMP_MAX],int pix_ext_edge2[COMP_MAX],bool horz)737 static void calc_pixel_ext(const struct mdp_format *format,
738 uint32_t src, uint32_t dst, uint32_t phase_step[2],
739 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
740 bool horz)
741 {
742 bool scaling = format->is_yuv ? true : (src != dst);
743 int i;
744
745 /*
746 * Note:
747 * We assume here that:
748 * 1. PCMN filter is used for downscale
749 * 2. bilinear filter is used for upscale
750 * 3. we are in a single pipe configuration
751 */
752
753 for (i = 0; i < COMP_MAX; i++) {
754 pix_ext_edge1[i] = 0;
755 pix_ext_edge2[i] = scaling ? 1 : 0;
756 }
757 }
758
mdp5_write_pixel_ext(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,const struct mdp_format * format,uint32_t src_w,int pe_left[COMP_MAX],int pe_right[COMP_MAX],uint32_t src_h,int pe_top[COMP_MAX],int pe_bottom[COMP_MAX])759 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
760 const struct mdp_format *format,
761 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
762 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
763 {
764 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
765 uint32_t lr, tb, req;
766 int i;
767
768 for (i = 0; i < COMP_MAX; i++) {
769 uint32_t roi_w = src_w;
770 uint32_t roi_h = src_h;
771
772 if (format->is_yuv && i == COMP_1_2) {
773 roi_w /= info->hsub;
774 roi_h /= info->vsub;
775 }
776
777 lr = (pe_left[i] >= 0) ?
778 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
779 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
780
781 lr |= (pe_right[i] >= 0) ?
782 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
783 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
784
785 tb = (pe_top[i] >= 0) ?
786 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
787 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
788
789 tb |= (pe_bottom[i] >= 0) ?
790 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
791 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
792
793 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
794 pe_left[i] + pe_right[i]);
795
796 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
797 pe_top[i] + pe_bottom[i]);
798
799 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
800 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
801 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
802
803 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
804 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
805 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
806 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
807 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
808 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
809
810 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
811 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
812 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
813 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
814 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
815 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
816 }
817 }
818
819 struct pixel_ext {
820 int left[COMP_MAX];
821 int right[COMP_MAX];
822 int top[COMP_MAX];
823 int bottom[COMP_MAX];
824 };
825
826 struct phase_step {
827 u32 x[COMP_MAX];
828 u32 y[COMP_MAX];
829 };
830
mdp5_hwpipe_mode_set(struct mdp5_kms * mdp5_kms,struct mdp5_hw_pipe * hwpipe,struct drm_framebuffer * fb,struct phase_step * step,struct pixel_ext * pe,u32 scale_config,u32 hdecm,u32 vdecm,bool hflip,bool vflip,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,u32 src_img_w,u32 src_img_h,u32 src_x,u32 src_y,u32 src_w,u32 src_h)831 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
832 struct mdp5_hw_pipe *hwpipe,
833 struct drm_framebuffer *fb,
834 struct phase_step *step,
835 struct pixel_ext *pe,
836 u32 scale_config, u32 hdecm, u32 vdecm,
837 bool hflip, bool vflip,
838 int crtc_x, int crtc_y,
839 unsigned int crtc_w, unsigned int crtc_h,
840 u32 src_img_w, u32 src_img_h,
841 u32 src_x, u32 src_y,
842 u32 src_w, u32 src_h)
843 {
844 enum mdp5_pipe pipe = hwpipe->pipe;
845 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
846 const struct mdp_format *format =
847 to_mdp_format(msm_framebuffer_format(fb));
848
849 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
850 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
851 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
852
853 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
854 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
855 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
856
857 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
858 MDP5_PIPE_SRC_XY_X(src_x) |
859 MDP5_PIPE_SRC_XY_Y(src_y));
860
861 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
862 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
863 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
864
865 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
866 MDP5_PIPE_OUT_XY_X(crtc_x) |
867 MDP5_PIPE_OUT_XY_Y(crtc_y));
868
869 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
870 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
871 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
872 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
873 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
874 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
875 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
876 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
877 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
878 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
879 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
880
881 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
882 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
883 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
884 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
885 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
886
887 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
888 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
889 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
890 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
891 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
892
893 /* not using secure mode: */
894 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
895
896 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
897 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
898 src_w, pe->left, pe->right,
899 src_h, pe->top, pe->bottom);
900
901 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
902 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
903 step->x[COMP_0]);
904 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
905 step->y[COMP_0]);
906 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
907 step->x[COMP_1_2]);
908 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
909 step->y[COMP_1_2]);
910 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
911 MDP5_PIPE_DECIMATION_VERT(vdecm) |
912 MDP5_PIPE_DECIMATION_HORZ(hdecm));
913 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
914 scale_config);
915 }
916
917 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
918 if (MDP_FORMAT_IS_YUV(format))
919 csc_enable(mdp5_kms, pipe,
920 mdp_get_default_csc_cfg(CSC_YUV2RGB));
921 else
922 csc_disable(mdp5_kms, pipe);
923 }
924
925 set_scanout_locked(mdp5_kms, pipe, fb);
926 }
927
mdp5_plane_mode_set(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_rect * src,struct drm_rect * dest)928 static int mdp5_plane_mode_set(struct drm_plane *plane,
929 struct drm_crtc *crtc, struct drm_framebuffer *fb,
930 struct drm_rect *src, struct drm_rect *dest)
931 {
932 struct drm_plane_state *pstate = plane->state;
933 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
934 struct mdp5_kms *mdp5_kms = get_kms(plane);
935 enum mdp5_pipe pipe = hwpipe->pipe;
936 struct mdp5_hw_pipe *right_hwpipe;
937 const struct mdp_format *format;
938 uint32_t nplanes, config = 0;
939 struct phase_step step = { { 0 } };
940 struct pixel_ext pe = { { 0 } };
941 uint32_t hdecm = 0, vdecm = 0;
942 uint32_t pix_format;
943 unsigned int rotation;
944 bool vflip, hflip;
945 int crtc_x, crtc_y;
946 unsigned int crtc_w, crtc_h;
947 uint32_t src_x, src_y;
948 uint32_t src_w, src_h;
949 uint32_t src_img_w, src_img_h;
950 int ret;
951
952 nplanes = fb->format->num_planes;
953
954 /* bad formats should already be rejected: */
955 if (WARN_ON(nplanes > pipe2nclients(pipe)))
956 return -EINVAL;
957
958 format = to_mdp_format(msm_framebuffer_format(fb));
959 pix_format = format->base.pixel_format;
960
961 src_x = src->x1;
962 src_y = src->y1;
963 src_w = drm_rect_width(src);
964 src_h = drm_rect_height(src);
965
966 crtc_x = dest->x1;
967 crtc_y = dest->y1;
968 crtc_w = drm_rect_width(dest);
969 crtc_h = drm_rect_height(dest);
970
971 /* src values are in Q16 fixed point, convert to integer: */
972 src_x = src_x >> 16;
973 src_y = src_y >> 16;
974 src_w = src_w >> 16;
975 src_h = src_h >> 16;
976
977 src_img_w = min(fb->width, src_w);
978 src_img_h = min(fb->height, src_h);
979
980 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
981 fb->base.id, src_x, src_y, src_w, src_h,
982 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
983
984 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
985 if (right_hwpipe) {
986 /*
987 * if the plane comprises of 2 hw pipes, assume that the width
988 * is split equally across them. The only parameters that varies
989 * between the 2 pipes are src_x and crtc_x
990 */
991 crtc_w /= 2;
992 src_w /= 2;
993 src_img_w /= 2;
994 }
995
996 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
997 if (ret)
998 return ret;
999
1000 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
1001 if (ret)
1002 return ret;
1003
1004 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1005 calc_pixel_ext(format, src_w, crtc_w, step.x,
1006 pe.left, pe.right, true);
1007 calc_pixel_ext(format, src_h, crtc_h, step.y,
1008 pe.top, pe.bottom, false);
1009 }
1010
1011 /* TODO calc hdecm, vdecm */
1012
1013 /* SCALE is used to both scale and up-sample chroma components */
1014 config |= get_scale_config(format, src_w, crtc_w, true);
1015 config |= get_scale_config(format, src_h, crtc_h, false);
1016 DBG("scale config = %x", config);
1017
1018 rotation = drm_rotation_simplify(pstate->rotation,
1019 DRM_MODE_ROTATE_0 |
1020 DRM_MODE_REFLECT_X |
1021 DRM_MODE_REFLECT_Y);
1022 hflip = !!(rotation & DRM_MODE_REFLECT_X);
1023 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1024
1025 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1026 config, hdecm, vdecm, hflip, vflip,
1027 crtc_x, crtc_y, crtc_w, crtc_h,
1028 src_img_w, src_img_h,
1029 src_x, src_y, src_w, src_h);
1030 if (right_hwpipe)
1031 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1032 config, hdecm, vdecm, hflip, vflip,
1033 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1034 src_img_w, src_img_h,
1035 src_x + src_w, src_y, src_w, src_h);
1036
1037 return ret;
1038 }
1039
1040 /*
1041 * Use this func and the one below only after the atomic state has been
1042 * successfully swapped
1043 */
mdp5_plane_pipe(struct drm_plane * plane)1044 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1045 {
1046 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1047
1048 if (WARN_ON(!pstate->hwpipe))
1049 return SSPP_NONE;
1050
1051 return pstate->hwpipe->pipe;
1052 }
1053
mdp5_plane_right_pipe(struct drm_plane * plane)1054 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1055 {
1056 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1057
1058 if (!pstate->r_hwpipe)
1059 return SSPP_NONE;
1060
1061 return pstate->r_hwpipe->pipe;
1062 }
1063
mdp5_plane_get_flush(struct drm_plane * plane)1064 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1065 {
1066 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1067 u32 mask;
1068
1069 if (WARN_ON(!pstate->hwpipe))
1070 return 0;
1071
1072 mask = pstate->hwpipe->flush_mask;
1073
1074 if (pstate->r_hwpipe)
1075 mask |= pstate->r_hwpipe->flush_mask;
1076
1077 return mask;
1078 }
1079
1080 /* initialize plane */
mdp5_plane_init(struct drm_device * dev,enum drm_plane_type type)1081 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1082 enum drm_plane_type type)
1083 {
1084 struct drm_plane *plane = NULL;
1085 struct mdp5_plane *mdp5_plane;
1086 int ret;
1087
1088 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1089 if (!mdp5_plane) {
1090 ret = -ENOMEM;
1091 goto fail;
1092 }
1093
1094 plane = &mdp5_plane->base;
1095
1096 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1097 ARRAY_SIZE(mdp5_plane->formats), false);
1098
1099 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1100 mdp5_plane->formats, mdp5_plane->nformats,
1101 NULL, type, NULL);
1102 if (ret)
1103 goto fail;
1104
1105 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1106
1107 mdp5_plane_install_properties(plane, &plane->base);
1108
1109 drm_plane_enable_fb_damage_clips(plane);
1110
1111 return plane;
1112
1113 fail:
1114 if (plane)
1115 mdp5_plane_destroy(plane);
1116
1117 return ERR_PTR(ret);
1118 }
1119