1 /* 2 * Copyright 2022 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __VDPU382_COM_H__ 18 #define __VDPU382_COM_H__ 19 20 #include "mpp_device.h" 21 #include "mpp_buf_slot.h" 22 #include "vdpu382.h" 23 24 #define OFFSET_COMMON_REGS (8 * sizeof(RK_U32)) 25 #define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(RK_U32)) 26 #define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) 27 #define OFFSET_CODEC_ADDR_REGS (160 * sizeof(RK_U32)) 28 #define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(RK_U32)) 29 #define OFFSET_INTERRUPT_REGS (224 * sizeof(RK_U32)) 30 #define OFFSET_STATISTIC_REGS (256 * sizeof(RK_U32)) 31 32 #define RCB_ALLINE_SIZE (64) 33 34 #define MPP_RCB_BYTES(bits) MPP_ALIGN((bits + 7) / 8, RCB_ALLINE_SIZE) 35 36 typedef enum Vdpu382_RCB_TYPE_E { 37 RCB_DBLK_ROW, 38 RCB_INTRA_ROW, 39 RCB_TRANSD_ROW, 40 RCB_STRMD_ROW, 41 RCB_INTER_ROW, 42 RCB_SAO_ROW, 43 RCB_FBC_ROW, 44 RCB_TRANSD_COL, 45 RCB_INTER_COL, 46 RCB_FILT_COL, 47 48 RCB_BUF_COUNT, 49 } Vdpu382RcbType_e; 50 51 typedef enum Vdpu382_RCB_SET_MODE_E { 52 RCB_SET_BY_SIZE_SORT_MODE, 53 RCB_SET_BY_PRIORITY_MODE, 54 } Vdpu382RcbSetMode_e; 55 56 /* base: OFFSET_COMMON_REGS */ 57 typedef struct Vdpu382RegCommon_t { 58 struct SWREG8_IN_OUT { 59 RK_U32 in_endian : 1; 60 RK_U32 in_swap32_e : 1; 61 RK_U32 in_swap64_e : 1; 62 RK_U32 str_endian : 1; 63 RK_U32 str_swap32_e : 1; 64 RK_U32 str_swap64_e : 1; 65 RK_U32 out_endian : 1; 66 RK_U32 out_swap32_e : 1; 67 RK_U32 out_cbcr_swap : 1; 68 RK_U32 out_swap64_e : 1; 69 RK_U32 reserve : 22; 70 } reg008; 71 72 struct SWREG9_DEC_MODE { 73 RK_U32 dec_mode : 10; 74 RK_U32 reserve : 22; 75 } reg009; 76 77 struct SWREG10_DEC_E { 78 RK_U32 dec_e : 1; 79 RK_U32 reserve : 31; 80 } reg010; 81 82 struct SWREG11_IMPORTANT_EN { 83 RK_U32 reserver : 1; 84 RK_U32 dec_clkgate_e : 1; 85 RK_U32 reserve1 : 2; 86 87 RK_U32 dec_irq_dis : 1; 88 RK_U32 dec_line_irq_dis : 1; //change to reg205[9] 89 RK_U32 buf_empty_en : 1; 90 RK_U32 reserve2 : 1; 91 92 RK_U32 dec_line_irq_en : 1; 93 RK_U32 reserve3 : 1; 94 RK_U32 dec_e_rewrite_valid : 1; 95 RK_U32 reserve4 : 9; 96 97 RK_U32 softrst_en_p : 1; 98 RK_U32 reserve5 : 1; //change to reg205[0] 99 RK_U32 err_head_fill_e : 1; 100 RK_U32 err_colmv_fill_e : 1; 101 RK_U32 pix_range_detection_e : 1; 102 RK_U32 reserve6 : 3; 103 RK_U32 wlast_match_fail : 1; 104 RK_U32 mmu_wlast_match_fail : 1; 105 RK_U32 reserve7 : 2; 106 } reg011; 107 108 struct SWREG12_SENCODARY_EN { 109 RK_U32 reserve0 : 1; 110 RK_U32 colmv_compress_en : 1; 111 RK_U32 fbc_e : 1; 112 RK_U32 tile_e : 1; 113 114 RK_U32 reserve1 : 1; 115 RK_U32 error_info_en : 1; 116 RK_U32 info_collect_en : 1; 117 RK_U32 reserve2 : 1; //change to reg205[4] 118 119 RK_U32 scanlist_addr_valid_en : 1; 120 RK_U32 scale_down_en : 1; 121 RK_U32 reserve3 : 22; 122 } reg012; 123 124 struct SWREG13_EN_MODE_SET { 125 RK_U32 reserve0 : 1; 126 RK_U32 req_timeout_rst_sel : 1; 127 RK_U32 reserve1 : 1; 128 RK_U32 dec_commonirq_mode : 1; 129 RK_U32 reserve2 : 2; 130 RK_U32 stmerror_waitdecfifo_empty : 1; 131 RK_U32 reserve3 : 1; 132 RK_U32 strmd_zero_rm_en : 1; 133 RK_U32 reserve4 : 3; 134 RK_U32 allow_not_wr_unref_bframe : 1; 135 RK_U32 fbc_output_wr_disable : 1; 136 137 RK_U32 reserve5 : 4; 138 RK_U32 h26x_error_mode : 1; 139 RK_U32 reserve6 : 5; 140 RK_U32 cur_pic_is_idr : 1; 141 RK_U32 reserve8 : 6; //change to reg205[5] 142 RK_U32 filter_outbuf_mode : 1; 143 144 } reg013; 145 146 struct SWREG14_FBC_PARAM_SET { 147 RK_U32 fbc_force_uncompress : 1; 148 149 RK_U32 reserve0 : 2; 150 RK_U32 allow_16x8_cp_flag : 1; 151 RK_U32 reserve1 : 2; 152 153 RK_U32 fbc_h264_exten_4or8_flag: 1; 154 RK_U32 reserve2 : 25; 155 } reg014; 156 157 struct SWREG15_STREAM_PARAM_SET { 158 RK_U32 rlc_mode_direct_write : 1; 159 RK_U32 rlc_mode : 1; 160 RK_U32 strmd_ofifo_perf_opt_en : 1; 161 RK_U32 reserve0 : 2; 162 163 RK_U32 strm_start_bit : 7; 164 RK_U32 reserve1 : 20; 165 } reg015; 166 167 RK_U32 reg016_str_len; 168 169 struct SWREG17_SLICE_NUMBER { 170 RK_U32 slice_num : 25; 171 RK_U32 reserve : 7; 172 } reg017; 173 174 struct SWREG18_Y_HOR_STRIDE { 175 RK_U32 y_hor_virstride : 16; 176 RK_U32 reserve : 16; 177 } reg018; 178 179 struct SWREG19_UV_HOR_STRIDE { 180 RK_U32 uv_hor_virstride : 16; 181 RK_U32 reserve : 16; 182 } reg019; 183 184 union { 185 struct SWREG20_Y_STRIDE { 186 RK_U32 y_virstride : 28; 187 RK_U32 reserve : 4; 188 } reg020_y_virstride; 189 190 struct SWREG20_FBC_PAYLOAD_OFFSET { 191 RK_U32 reserve : 4; 192 RK_U32 payload_st_offset : 28; 193 } reg020_fbc_payload_off; 194 }; 195 196 197 struct SWREG21_ERROR_CTRL_SET { 198 RK_U32 inter_error_prc_mode : 1; 199 RK_U32 error_intra_mode : 1; 200 RK_U32 error_deb_en : 1; 201 RK_U32 picidx_replace : 5; 202 RK_U32 error_spread_e : 1; 203 RK_U32 : 3; 204 RK_U32 error_inter_pred_cross_slice : 1; 205 RK_U32 reserve0 : 11; 206 207 RK_U32 roi_error_ctu_cal_en : 1; 208 RK_U32 reserve1 : 7; 209 } reg021; 210 211 struct SWREG22_ERR_ROI_CTU_OFFSET_START { 212 RK_U32 roi_x_ctu_offset_st : 12; 213 RK_U32 reserve0 : 4; 214 RK_U32 roi_y_ctu_offset_st : 12; 215 RK_U32 reserve1 : 4; 216 } reg022; 217 218 struct SWREG23_ERR_ROI_CTU_OFFSET_END { 219 RK_U32 roi_x_ctu_offset_end : 12; 220 RK_U32 reserve0 : 4; 221 RK_U32 roi_y_ctu_offset_end : 12; 222 RK_U32 reserve1 : 4; 223 } reg023; 224 225 struct SWREG24_CABAC_ERROR_EN_LOWBITS { 226 RK_U32 cabac_err_en_lowbits : 32; 227 } reg024; 228 229 struct SWREG25_CABAC_ERROR_EN_HIGHBITS { 230 RK_U32 cabac_err_en_highbits : 30; 231 RK_U32 reserve : 2; 232 } reg025; 233 234 struct SWREG26_BLOCK_GATING_EN { 235 RK_U32 inter_auto_gating_e : 1; 236 RK_U32 filterd_auto_gating_e : 1; 237 RK_U32 strmd_auto_gating_e : 1; 238 RK_U32 mcp_auto_gating_e : 1; 239 RK_U32 busifd_auto_gating_e : 1; 240 RK_U32 reserved : 3; 241 RK_U32 dec_ctrl_auto_gating_e : 1; 242 RK_U32 intra_auto_gating_e : 1; 243 RK_U32 mc_auto_gating_e : 1; 244 RK_U32 transd_auto_gating_e : 1; 245 RK_U32 reserved1 : 4; 246 RK_U32 sram_auto_gating_e : 1; 247 RK_U32 cru_auto_gating_e : 1; 248 RK_U32 reserved2 : 13; 249 RK_U32 reg_cfg_gating_en : 1; 250 } reg026; 251 252 /* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */ 253 struct SW027_CORE_SAFE_PIXELS { 254 // colmv and recon report coord x safe pixels 255 RK_U32 core_safe_x_pixels : 16; 256 // colmv and recon report coord y safe pixels 257 RK_U32 core_safe_y_pixels : 16; 258 } reg027; 259 260 struct SWREG28_MULTIPLY_CORE_CTRL { 261 RK_U32 swreg_vp9_wr_prob_idx : 3; 262 RK_U32 reserve0 : 1; 263 RK_U32 swreg_vp9_rd_prob_idx : 3; 264 RK_U32 reserve1 : 1; 265 266 RK_U32 swreg_ref_req_advance_flag : 1; 267 RK_U32 sw_colmv_req_advance_flag : 1; 268 RK_U32 sw_poc_only_highbit_flag : 1; 269 RK_U32 sw_poc_arb_flag : 1; 270 271 RK_U32 reserve2 : 4; 272 RK_U32 sw_film_idx : 10; 273 RK_U32 reserve3 : 2; 274 RK_U32 sw_pu_req_mismatch_dis : 1; 275 RK_U32 sw_colmv_req_mismatch_dis : 1; 276 RK_U32 reserve4 : 2; 277 } reg028; 278 279 struct SWREG29_SCALE_DOWN_CTRL { 280 RK_U32 scale_down_y_wratio : 5; 281 RK_U32 reserve0 : 3; 282 RK_U32 scale_down_y_hratio : 5; 283 RK_U32 reserve1 : 3; 284 RK_U32 scale_down_c_wratio : 5; 285 RK_U32 reserve2 : 3; 286 RK_U32 scale_down_c_hratio : 5; 287 RK_U32 reserve3 : 1; 288 RK_U32 scale_down_roi_mode : 1; 289 RK_U32 scale_down_tile_mode : 1; 290 } reg029; 291 292 struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE { 293 RK_U32 y_scale_down_hor_stride : 20; 294 RK_U32 : 12; 295 } reg030; 296 297 struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE { 298 RK_U32 uv_scale_down_hor_stride : 20; 299 RK_U32 : 12; 300 } reg031; 301 302 /* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */ 303 /* NOTE: timeout must be config in vdpu38x */ 304 RK_U32 reg032_timeout_threshold; 305 306 struct SW033_LINE_IRQ_CTRL { 307 RK_U32 dec_line_irq_step : 12; 308 RK_U32 dec_line_offset_y_st : 12; 309 RK_U32 buf_empty_timeout_threshold : 8; 310 } reg033; 311 312 /* 0x00000088 reg34 */ 313 struct SW034_SCALE_DOWN_ROI_OFFSET { 314 RK_U32 scale_down_roi_st_offsetx : 16; 315 RK_U32 scale_down_roi_st_offsety : 16; 316 } reg034; 317 318 /* 0x0000008c reg35 */ 319 struct SW035_SCALE_DOWN_ROI_OUT_SIZE { 320 RK_U32 scale_down_roi_out_width : 16; 321 RK_U32 scale_down_roi_out_height : 16; 322 } reg035; 323 324 } Vdpu382RegCommon; 325 326 /* base: OFFSET_COMMON_ADDR_REGS */ 327 typedef struct Vdpu382RegCommonAddr_t { 328 /* offset 128 */ 329 RK_U32 reg128_rlc_base; 330 331 RK_U32 reg129_rlcwrite_base; 332 333 RK_U32 reg130_decout_base; 334 335 RK_U32 reg131_colmv_cur_base; 336 337 RK_U32 reg132_error_ref_base; 338 339 RK_U32 reg133_rcb_intra_base; 340 341 RK_U32 reg134_rcb_transd_row_base; 342 343 RK_U32 reg135_rcb_transd_col_base; 344 345 RK_U32 reg136_rcb_streamd_row_base; 346 347 RK_U32 reg137_rcb_inter_row_base; 348 349 RK_U32 reg138_rcb_inter_col_base; 350 351 RK_U32 reg139_rcb_dblk_base; 352 353 RK_U32 reg140_rcb_sao_base; 354 355 RK_U32 reg141_rcb_fbc_base; 356 357 RK_U32 reg142_rcb_filter_col_base; 358 359 RK_U32 reg143_rcb_base; 360 } Vdpu382RegCommonAddr; 361 362 /* base: OFFSET_COMMON_ADDR_REGS */ 363 typedef struct Vdpu382RegIrqStatus_t { 364 struct SWREG224_STA_INT { 365 RK_U32 dec_irq : 1; 366 RK_U32 dec_irq_raw : 1; 367 368 RK_U32 dec_rdy_sta : 1; 369 RK_U32 dec_bus_sta : 1; 370 RK_U32 dec_error_sta : 1; 371 RK_U32 dec_timeout_sta : 1; 372 RK_U32 buf_empty_sta : 1; 373 RK_U32 colmv_ref_error_sta : 1; 374 RK_U32 cabu_end_sta : 1; 375 376 RK_U32 softreset_rdy : 1; 377 378 RK_U32 dec_line_irq : 1; 379 RK_U32 dec_line_irq_raw : 1; 380 RK_U32 ltb_pause_sta : 1; 381 RK_U32 mmureset_rdy : 1; 382 RK_U32 ltb_end_sta : 1; 383 384 RK_U32 reserve : 17; 385 } reg224; 386 387 struct SWREG225_STA_SLICE_BYTE_OFFSET { 388 RK_U32 strmd_slice_byte_offset : 32; 389 } reg225; 390 391 struct SWREG226_STA_CABAC_ERROR_STATUS { 392 RK_U32 all_frame_error_flag : 1; 393 RK_U32 strmd_detect_error_flag : 3; 394 RK_U32 strmd_error_status : 28; 395 } reg226; 396 397 struct SWREG227_STA_COLMV_ERROR_REF_PICIDX { 398 RK_U32 colmv_error_ref_picidx : 4; 399 RK_U32 reserve : 28; 400 } reg227; 401 402 struct SWREG228_STA_CABAC_ERROR_CTU_OFFSET { 403 RK_U32 cabac_error_ctu_offset_x : 12; 404 RK_U32 : 4; 405 RK_U32 cabac_error_ctu_offset_y : 12; 406 RK_U32 : 4; 407 } reg228; 408 409 struct SWREG229_STA_AXI_WCH_FINISH_FLAG { 410 RK_U32 axi_wch_finish_flag : 17; 411 RK_U32 reserved : 15; 412 } reg229; 413 414 struct SWREG230_STA_SLICE_DEC_NUM { 415 RK_U32 slicedec_num : 25; 416 RK_U32 reserve : 7; 417 } reg230; 418 419 struct SWREG231_STA_FRAME_ERROR_CTU_NUM { 420 RK_U32 frame_ctu_err_num : 32; 421 } reg231; 422 423 struct SWREG232_STA_ERROR_PACKET_NUM { 424 RK_U32 packet_err_num : 16; 425 RK_U32 reserve : 16; 426 } reg232; 427 428 struct SWREG233_STA_ERR_CTU_NUM_IN_RO { 429 RK_U32 error_ctu_num_in_roi : 24; 430 RK_U32 reserve : 8; 431 } reg233; 432 433 struct SWREG234_BUF_EMPTY_OFFSET { 434 RK_U32 coord_report_offset_x : 16; 435 RK_U32 coord_report_offset_y : 16; 436 } reg234; 437 438 struct SWREG235_COORD_REPORT_OUTBUF_HEIGHT { 439 RK_U32 coord_report_output_height : 16; 440 RK_U32 reserve : 16; 441 } reg235; 442 443 RK_U32 reserve_reg236_237[2]; 444 } Vdpu382RegIrqStatus; 445 446 typedef struct Vdpu382RegStatistic_t { 447 struct SWREG256_DEBUG_PERF_LATENCY_CTRL0 { 448 RK_U32 axi_perf_work_e : 1; 449 RK_U32 axi_perf_clr_e : 1; 450 RK_U32 reserve0 : 1; 451 RK_U32 axi_cnt_type : 1; 452 RK_U32 rd_latency_id : 4; 453 RK_U32 rd_latency_thr : 12; 454 RK_U32 reserve1 : 12; 455 } reg256; 456 457 struct SWREG257_DEBUG_PERF_LATENCY_CTRL1 { 458 RK_U32 addr_align_type : 2; 459 RK_U32 ar_cnt_id_type : 1; 460 RK_U32 aw_cnt_id_type : 1; 461 RK_U32 ar_count_id : 4; 462 RK_U32 aw_count_id : 4; 463 RK_U32 rd_band_width_mode : 1; 464 RK_U32 reserve : 19; 465 } reg257; 466 467 struct SWREG258_DEBUG_PERF_RD_MAX_LATENCY_NUM { 468 RK_U32 rd_max_latency_num : 16; 469 RK_U32 reserve : 16; 470 } reg258; 471 472 RK_U32 reg259_rd_latency_thr_num_ch0; 473 RK_U32 reg260_rd_latency_acc_sum; 474 RK_U32 reg261_perf_rd_axi_total_byte; 475 RK_U32 reg262_perf_wr_axi_total_byte; 476 RK_U32 reg263_perf_working_cnt; 477 478 struct SWREG264_DEBUG_BUS_STATE { 479 RK_U32 bus_state_flag : 25; 480 RK_U32 reserve : 7; 481 } reg264; 482 483 union { 484 struct { 485 RK_U32 perf_cnt0_sel : 6; 486 RK_U32 reserve0 : 2; 487 RK_U32 perf_cnt1_sel : 6; 488 RK_U32 reserve1 : 2; 489 RK_U32 perf_cnt2_sel : 6; 490 RK_U32 reserve2 : 10; 491 }; 492 493 RK_U32 link_perf_cnt0; 494 } reg265; 495 496 RK_U32 reg266_perf_cnt0; 497 RK_U32 reg267_perf_cnt1; 498 RK_U32 reg268_perf_cnt2; 499 500 RK_U32 reserve_reg269; 501 502 struct SWREG270_DEBUG_QOS_CTRL { 503 RK_U32 bus2mc_buffer_qos_level : 8; 504 RK_U32 reserve0 : 8; 505 RK_U32 axi_wr_hurry_level : 3; 506 RK_U32 reserve1 : 1; 507 RK_U32 axi_wr_qos : 3; 508 RK_U32 reserve2 : 1; 509 RK_U32 axi_rd_hurry_level : 3; 510 RK_U32 reserve3 : 1; 511 RK_U32 axi_rd_qos : 3; 512 RK_U32 reserve4 : 1; 513 } reg270; 514 515 RK_U32 reg271_wr_wait_cycle_qos; 516 517 struct SWREG272_DEBUG_INT { 518 RK_U32 busidle_flag : 1; 519 RK_U32 reserved : 4; 520 RK_U32 mmu_busidle_flag : 1; 521 RK_U32 wr_tansfer_cnt : 8; 522 RK_U32 reserved1 : 2; 523 RK_U32 Sw_streamfifo_space2full : 7; 524 RK_U32 reserved2 : 1; 525 RK_U32 mmu_wr_transer_cnt : 8; 526 } reg272; 527 528 struct SWREG273 { 529 RK_U32 bus_status_flag : 25; 530 RK_U32 reserve0 : 6; 531 RK_U32 pps_no_ref_bframe_dec_r : 1; 532 } reg273; 533 534 RK_U16 reg274_y_min_value; 535 RK_U16 reg274_y_max_value; 536 RK_U16 reg275_u_min_value; 537 RK_U16 reg275_u_max_value; 538 RK_U16 reg276_v_min_value; 539 RK_U16 reg276_v_max_value; 540 541 struct SWREG277_ERROR_SPREAD_NUM { 542 RK_U32 err_spread_cnt_sum : 24; 543 RK_U32 : 8; 544 } reg277; 545 546 // RK_U32 reg277_err_spread_num; 547 // struct SWREG278_DEC_LINE_OFFSET_Y { 548 // RK_U32 dec_line_offset_y : 16; 549 // RK_U32 reserve : 16; 550 // } reg278; 551 552 } Vdpu382RegStatistic; 553 554 typedef struct vdpu382_rcb_info_t { 555 RK_S32 reg; 556 RK_S32 size; 557 RK_S32 offset; 558 } Vdpu382RcbInfo; 559 560 #ifdef __cplusplus 561 extern "C" { 562 #endif 563 564 RK_S32 vdpu382_get_rcb_buf_size(Vdpu382RcbInfo *info, RK_S32 width, RK_S32 height); 565 void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu382RcbInfo *info); 566 RK_S32 vdpu382_compare_rcb_size(const void *a, const void *b); 567 RK_S32 vdpu382_set_rcbinfo(MppDev dev, Vdpu382RcbInfo *rcb_info); 568 void vdpu382_setup_statistic(Vdpu382RegCommon *com, Vdpu382RegStatistic *sta); 569 void vdpu382_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand); 570 void vdpu382_setup_down_scale(MppFrame frame, MppDev dev, Vdpu382RegCommon *com); 571 RK_U32 vdpu382_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size, 572 RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress); 573 574 #ifdef __cplusplus 575 } 576 #endif 577 578 #endif /* __VDPU382_COM_H__ */ 579