1 /*
2 * Copyright (C) 2011-2014, 2016-2017 ARM Limited. All rights reserved.
3 *
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
6 *
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
9 */
10
11 #ifndef __MALI_GP_H__
12 #define __MALI_GP_H__
13
14 #include "mali_osk.h"
15 #include "mali_gp_job.h"
16 #include "mali_hw_core.h"
17 #include "regs/mali_gp_regs.h"
18
19 struct mali_group;
20
21 /**
22 * Definition of the GP core struct
23 * Used to track a GP core in the system.
24 */
25 struct mali_gp_core {
26 struct mali_hw_core hw_core; /**< Common for all HW cores */
27 _mali_osk_irq_t *irq; /**< IRQ handler */
28 };
29
30 _mali_osk_errcode_t mali_gp_initialize(void);
31 void mali_gp_terminate(void);
32
33 struct mali_gp_core *mali_gp_create(const _mali_osk_resource_t *resource, struct mali_group *group);
34 void mali_gp_delete(struct mali_gp_core *core);
35
36 void mali_gp_stop_bus(struct mali_gp_core *core);
37 _mali_osk_errcode_t mali_gp_stop_bus_wait(struct mali_gp_core *core);
38 void mali_gp_reset_async(struct mali_gp_core *core);
39 _mali_osk_errcode_t mali_gp_reset_wait(struct mali_gp_core *core);
40 void mali_gp_hard_reset(struct mali_gp_core *core);
41 _mali_osk_errcode_t mali_gp_reset(struct mali_gp_core *core);
42
43 void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job);
44 void mali_gp_resume_with_new_heap(struct mali_gp_core *core, u32 start_addr, u32 end_addr);
45
46 u32 mali_gp_core_get_version(struct mali_gp_core *core);
47
48 struct mali_gp_core *mali_gp_get_global_gp_core(void);
49
50 #if MALI_STATE_TRACKING
51 u32 mali_gp_dump_state(struct mali_gp_core *core, char *buf, u32 size);
52 #endif
53
54 void mali_gp_update_performance_counters(struct mali_gp_core *core, struct mali_gp_job *job);
55
mali_gp_core_description(struct mali_gp_core * core)56 MALI_STATIC_INLINE const char *mali_gp_core_description(struct mali_gp_core *core)
57 {
58 return core->hw_core.description;
59 }
60
mali_gp_get_interrupt_result(struct mali_gp_core * core)61 MALI_STATIC_INLINE enum mali_interrupt_result mali_gp_get_interrupt_result(struct mali_gp_core *core)
62 {
63 u32 stat_used = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_STAT) &
64 MALIGP2_REG_VAL_IRQ_MASK_USED;
65
66 if (0 == stat_used) {
67 return MALI_INTERRUPT_RESULT_NONE;
68 } else if ((MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST |
69 MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST) == stat_used) {
70 return MALI_INTERRUPT_RESULT_SUCCESS;
71 } else if (MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST == stat_used) {
72 return MALI_INTERRUPT_RESULT_SUCCESS_VS;
73 } else if (MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST == stat_used) {
74 return MALI_INTERRUPT_RESULT_SUCCESS_PLBU;
75 } else if (MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM & stat_used) {
76 return MALI_INTERRUPT_RESULT_OOM;
77 }
78
79 return MALI_INTERRUPT_RESULT_ERROR;
80 }
81
mali_gp_get_rawstat(struct mali_gp_core * core)82 MALI_STATIC_INLINE u32 mali_gp_get_rawstat(struct mali_gp_core *core)
83 {
84 MALI_DEBUG_ASSERT_POINTER(core);
85 return mali_hw_core_register_read(&core->hw_core,
86 MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT);
87 }
88
mali_gp_is_active(struct mali_gp_core * core)89 MALI_STATIC_INLINE u32 mali_gp_is_active(struct mali_gp_core *core)
90 {
91 u32 status = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS);
92 return (status & MALIGP2_REG_VAL_STATUS_MASK_ACTIVE) ? MALI_TRUE : MALI_FALSE;
93 }
94
mali_gp_mask_all_interrupts(struct mali_gp_core * core)95 MALI_STATIC_INLINE void mali_gp_mask_all_interrupts(struct mali_gp_core *core)
96 {
97 mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_NONE);
98 }
99
mali_gp_enable_interrupts(struct mali_gp_core * core,enum mali_interrupt_result exceptions)100 MALI_STATIC_INLINE void mali_gp_enable_interrupts(struct mali_gp_core *core, enum mali_interrupt_result exceptions)
101 {
102 /* Enable all interrupts, except those specified in exceptions */
103 u32 value;
104
105 if (MALI_INTERRUPT_RESULT_SUCCESS_VS == exceptions) {
106 /* Enable all used except VS complete */
107 value = MALIGP2_REG_VAL_IRQ_MASK_USED &
108 ~MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST;
109 } else {
110 MALI_DEBUG_ASSERT(MALI_INTERRUPT_RESULT_SUCCESS_PLBU ==
111 exceptions);
112 /* Enable all used except PLBU complete */
113 value = MALIGP2_REG_VAL_IRQ_MASK_USED &
114 ~MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST;
115 }
116
117 mali_hw_core_register_write(&core->hw_core,
118 MALIGP2_REG_ADDR_MGMT_INT_MASK,
119 value);
120 }
121
mali_gp_read_plbu_alloc_start_addr(struct mali_gp_core * core)122 MALI_STATIC_INLINE u32 mali_gp_read_plbu_alloc_start_addr(struct mali_gp_core *core)
123 {
124 return mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR);
125 }
126
127 #endif /* __MALI_GP_H__ */
128