1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Include file private to the SOC Interconnect support files. 4 * 5 * Copyright (C) 1999-2017, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: siutils_priv.h 625739 2016-03-17 12:28:03Z $ 29 */ 30 31 #ifndef _siutils_priv_h_ 32 #define _siutils_priv_h_ 33 34 #if defined(SI_ERROR_ENFORCE) 35 #define SI_ERROR(args) printf args 36 #else 37 #define SI_ERROR(args) printf args 38 #endif 39 40 #if defined(ENABLE_CORECAPTURE) 41 42 #define SI_PRINT(args) osl_wificc_logDebug args 43 44 #else 45 46 #define SI_PRINT(args) printf args 47 48 #endif /* ENABLE_CORECAPTURE */ 49 50 51 #define SI_MSG(args) 52 53 #ifdef BCMDBG_SI 54 #define SI_VMSG(args) printf args 55 #else 56 #define SI_VMSG(args) 57 #endif 58 59 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 60 61 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 62 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 63 typedef bool (*si_intrsenabled_t)(void *intr_arg); 64 65 66 #define SI_GPIO_MAX 16 67 68 typedef struct gci_gpio_item { 69 void *arg; 70 uint8 gci_gpio; 71 uint8 status; 72 gci_gpio_handler_t handler; 73 struct gci_gpio_item *next; 74 } gci_gpio_item_t; 75 76 #define AI_SLAVE_WRAPPER 0 77 #define AI_MASTER_WRAPPER 1 78 79 typedef struct axi_wrapper { 80 uint32 mfg; 81 uint32 cid; 82 uint32 rev; 83 uint32 wrapper_type; 84 uint32 wrapper_addr; 85 uint32 wrapper_size; 86 } axi_wrapper_t; 87 88 #define SI_MAX_AXI_WRAPPERS 32 89 #define AI_REG_READ_TIMEOUT 300 /* in msec */ 90 91 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */ 92 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */ 93 #define BT_CC_SPROM_BADREG_LO 0x18000190 94 #define BT_CC_SPROM_BADREG_HI 0 95 #define BCM4350_BT_AXI_ID 6 96 #define BCM4345_BT_AXI_ID 6 97 98 typedef struct si_cores_info { 99 volatile void *regs[SI_MAXCORES]; /* other regs va */ 100 101 uint coreid[SI_MAXCORES]; /**< id of each core */ 102 uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */ 103 void *regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */ 104 uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set (usbh20) */ 105 uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */ 106 uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */ 107 108 void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */ 109 uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */ 110 111 void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */ 112 uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */ 113 114 uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */ 115 uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */ 116 } si_cores_info_t; 117 118 /** misc si info needed by some of the routines */ 119 typedef struct si_info { 120 struct si_pub pub; /**< back plane public state (must be first field) */ 121 122 void *osh; /**< osl os handle */ 123 void *sdh; /**< bcmsdh handle */ 124 125 uint dev_coreid; /**< the core provides driver functions */ 126 void *intr_arg; /**< interrupt callback function arg */ 127 si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */ 128 si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */ 129 si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */ 130 131 void *pch; /**< PCI/E core handle */ 132 133 bool memseg; /**< flag to toggle MEM_SEG register */ 134 135 char *vars; 136 uint varsz; 137 138 volatile void *curmap; /* current regs va */ 139 140 uint curidx; /**< current core index */ 141 uint numcores; /**< # discovered cores */ 142 143 void *curwrap; /**< current wrapper va */ 144 145 uint32 oob_router; /**< oob router registers for axi */ 146 147 si_cores_info_t *cores_info; 148 gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */ 149 uint chipnew; /**< new chip number */ 150 uint second_bar0win; /**< Backplane region */ 151 uint num_br; /**< # discovered bridges */ 152 uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */ 153 uint32 xtalfreq; 154 uint32 macclk_mul_fact; /* Multiplication factor necessary to adjust MAC Clock 155 * during ULB Mode operation. One instance where this is used is configuring TSF L-frac 156 * register 157 */ 158 bool device_removed; 159 uint axi_num_wrappers; 160 axi_wrapper_t * axi_wrapper; 161 } si_info_t; 162 163 164 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) 165 166 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 167 ISALIGNED((x), SI_CORE_SIZE)) 168 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 169 #define BADCOREADDR 0 170 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 171 #define NOREV -1 /**< Invalid rev */ 172 173 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 174 ((si)->pub.buscoretype == PCI_CORE_ID)) 175 176 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 177 ((si)->pub.buscoretype == PCIE_CORE_ID)) 178 179 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 180 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 181 182 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 183 184 #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 185 186 /** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */ 187 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 188 189 #define CCREGS_FAST(si) \ 190 (((si)->curmap == NULL) ? NULL : \ 191 ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 192 #define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 193 194 /* 195 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 196 * after core switching to avoid invalid register accesss inside ISR. 197 */ 198 #define INTR_OFF(si, intr_val) \ 199 if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 200 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 201 #define INTR_RESTORE(si, intr_val) \ 202 if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 203 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 204 205 /* dynamic clock control defines */ 206 #define LPOMINFREQ 25000 /**< low power oscillator min */ 207 #define LPOMAXFREQ 43000 /**< low power oscillator max */ 208 #define XTALMINFREQ 19800000 /**< 20 MHz - 1% */ 209 #define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */ 210 #define PCIMINFREQ 25000000 /**< 25 MHz */ 211 #define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */ 212 213 #define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */ 214 #define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */ 215 216 /* GPIO Based LED powersave defines */ 217 #define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */ 218 #define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */ 219 220 #ifndef DEFAULT_GPIOTIMERVAL 221 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 222 #endif 223 224 /* Silicon Backplane externs */ 225 extern void sb_scan(si_t *sih, volatile void *regs, uint devid); 226 extern uint sb_coreid(si_t *sih); 227 extern uint sb_intflag(si_t *sih); 228 extern uint sb_flag(si_t *sih); 229 extern void sb_setint(si_t *sih, int siflag); 230 extern uint sb_corevendor(si_t *sih); 231 extern uint sb_corerev(si_t *sih); 232 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 233 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff); 234 extern bool sb_iscoreup(si_t *sih); 235 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx); 236 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 237 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 238 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 239 extern void sb_commit(si_t *sih); 240 extern uint32 sb_base(uint32 admatch); 241 extern uint32 sb_size(uint32 admatch); 242 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 243 extern void sb_core_disable(si_t *sih, uint32 bits); 244 extern uint32 sb_addrspace(si_t *sih, uint asidx); 245 extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 246 extern int sb_numaddrspaces(si_t *sih); 247 248 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 249 250 extern bool sb_taclear(si_t *sih, bool details); 251 252 #if defined(BCMDBG_PHYDUMP) 253 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 254 #endif 255 256 /* Wake-on-wireless-LAN (WOWL) */ 257 extern bool sb_pci_pmecap(si_t *sih); 258 struct osl_info; 259 extern bool sb_pci_fastpmecap(struct osl_info *osh); 260 extern bool sb_pci_pmeclr(si_t *sih); 261 extern void sb_pci_pmeen(si_t *sih); 262 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 263 264 /* AMBA Interconnect exported externs */ 265 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 266 void *sdh, char **vars, uint *varsz); 267 extern si_t *ai_kattach(osl_t *osh); 268 extern void ai_scan(si_t *sih, void *regs, uint devid); 269 270 extern uint ai_flag(si_t *sih); 271 extern uint ai_flag_alt(si_t *sih); 272 extern void ai_setint(si_t *sih, int siflag); 273 extern uint ai_coreidx(si_t *sih); 274 extern uint ai_corevendor(si_t *sih); 275 extern uint ai_corerev(si_t *sih); 276 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff); 277 extern bool ai_iscoreup(si_t *sih); 278 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx); 279 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx); 280 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 281 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 282 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 283 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 284 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 285 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits, 286 uint32 resetbits, void *p, void *s); 287 extern void ai_core_disable(si_t *sih, uint32 bits); 288 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits, 289 aidmp_t *pmacai, aidmp_t *smacai); 290 extern int ai_numaddrspaces(si_t *sih); 291 extern uint32 ai_addrspace(si_t *sih, uint asidx); 292 extern uint32 ai_addrspacesize(si_t *sih, uint asidx); 293 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 294 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 295 extern void ai_enable_backplane_timeouts(si_t *sih); 296 extern uint32 ai_clear_backplane_to(si_t *sih); 297 extern uint ai_num_slaveports(si_t *sih, uint coreidx); 298 299 #ifdef BCM_BACKPLANE_TIMEOUT 300 uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr); 301 #endif /* BCM_BACKPLANE_TIMEOUT */ 302 303 #if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT) 304 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap); 305 #endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */ 306 307 #if defined(BCMDBG_PHYDUMP) 308 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 309 #endif 310 311 extern uint32 ai_wrapper_dump_buf_size(si_t *sih); 312 extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p); 313 314 #define ub_scan(a, b, c) do {} while (0) 315 #define ub_flag(a) (0) 316 #define ub_setint(a, b) do {} while (0) 317 #define ub_coreidx(a) (0) 318 #define ub_corevendor(a) (0) 319 #define ub_corerev(a) (0) 320 #define ub_iscoreup(a) (0) 321 #define ub_setcoreidx(a, b) (0) 322 #define ub_core_cflags(a, b, c) (0) 323 #define ub_core_cflags_wo(a, b, c) do {} while (0) 324 #define ub_core_sflags(a, b, c) (0) 325 #define ub_corereg(a, b, c, d, e) (0) 326 #define ub_core_reset(a, b, c) do {} while (0) 327 #define ub_core_disable(a, b) do {} while (0) 328 #define ub_numaddrspaces(a) (0) 329 #define ub_addrspace(a, b) (0) 330 #define ub_addrspacesize(a, b) (0) 331 #define ub_view(a, b) do {} while (0) 332 #define ub_dumpregs(a, b) do {} while (0) 333 334 #endif /* _siutils_priv_h_ */ 335