1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/pcs/pcs-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 /* Synopsys Core versions */ 30 #define DWMAC_CORE_3_40 0x34 31 #define DWMAC_CORE_3_50 0x35 32 #define DWMAC_CORE_4_00 0x40 33 #define DWMAC_CORE_4_10 0x41 34 #define DWMAC_CORE_5_00 0x50 35 #define DWMAC_CORE_5_10 0x51 36 #define DWXGMAC_CORE_2_10 0x21 37 #define DWXLGMAC_CORE_2_00 0x20 38 39 /* Device ID */ 40 #define DWXGMAC_ID 0x76 41 #define DWXLGMAC_ID 0x27 42 43 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 44 45 /* TX and RX Descriptor Length, these need to be power of two. 46 * TX descriptor length less than 64 may cause transmit queue timed out error. 47 * RX descriptor length less than 64 may cause inconsistent Rx chain error. 48 */ 49 #define DMA_MIN_TX_SIZE 64 50 #define DMA_MAX_TX_SIZE 1024 51 #if IS_ENABLED(CONFIG_STMMAC_UIO) 52 #define DMA_DEFAULT_TX_SIZE 1024 53 #else 54 #define DMA_DEFAULT_TX_SIZE 512 55 #endif 56 #define DMA_MIN_RX_SIZE 64 57 #define DMA_MAX_RX_SIZE 1024 58 #if IS_ENABLED(CONFIG_STMMAC_UIO) 59 #define DMA_DEFAULT_RX_SIZE 1024 60 #else 61 #define DMA_DEFAULT_RX_SIZE 512 62 #endif 63 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 64 65 #undef FRAME_FILTER_DEBUG 66 /* #define FRAME_FILTER_DEBUG */ 67 68 /* Extra statistic and debug information exposed by ethtool */ 69 struct stmmac_extra_stats { 70 /* Transmit errors */ 71 unsigned long tx_underflow ____cacheline_aligned; 72 unsigned long tx_carrier; 73 unsigned long tx_losscarrier; 74 unsigned long vlan_tag; 75 unsigned long tx_deferred; 76 unsigned long tx_vlan; 77 unsigned long tx_jabber; 78 unsigned long tx_frame_flushed; 79 unsigned long tx_payload_error; 80 unsigned long tx_ip_header_error; 81 /* Receive errors */ 82 unsigned long rx_desc; 83 unsigned long sa_filter_fail; 84 unsigned long overflow_error; 85 unsigned long ipc_csum_error; 86 unsigned long rx_collision; 87 unsigned long rx_crc_errors; 88 unsigned long dribbling_bit; 89 unsigned long rx_length; 90 unsigned long rx_mii; 91 unsigned long rx_multicast; 92 unsigned long rx_gmac_overflow; 93 unsigned long rx_watchdog; 94 unsigned long da_rx_filter_fail; 95 unsigned long sa_rx_filter_fail; 96 unsigned long rx_missed_cntr; 97 unsigned long rx_overflow_cntr; 98 unsigned long rx_vlan; 99 unsigned long rx_split_hdr_pkt_n; 100 /* Tx/Rx IRQ error info */ 101 unsigned long tx_undeflow_irq; 102 unsigned long tx_process_stopped_irq; 103 unsigned long tx_jabber_irq; 104 unsigned long rx_overflow_irq; 105 unsigned long rx_buf_unav_irq; 106 unsigned long rx_process_stopped_irq; 107 unsigned long rx_watchdog_irq; 108 unsigned long tx_early_irq; 109 unsigned long fatal_bus_error_irq; 110 /* Tx/Rx IRQ Events */ 111 unsigned long rx_early_irq; 112 unsigned long threshold; 113 unsigned long tx_pkt_n; 114 unsigned long rx_pkt_n; 115 unsigned long normal_irq_n; 116 unsigned long rx_normal_irq_n; 117 unsigned long napi_poll; 118 unsigned long tx_normal_irq_n; 119 unsigned long tx_clean; 120 unsigned long tx_set_ic_bit; 121 unsigned long irq_receive_pmt_irq_n; 122 /* MMC info */ 123 unsigned long mmc_tx_irq_n; 124 unsigned long mmc_rx_irq_n; 125 unsigned long mmc_rx_csum_offload_irq_n; 126 /* EEE */ 127 unsigned long irq_tx_path_in_lpi_mode_n; 128 unsigned long irq_tx_path_exit_lpi_mode_n; 129 unsigned long irq_rx_path_in_lpi_mode_n; 130 unsigned long irq_rx_path_exit_lpi_mode_n; 131 unsigned long phy_eee_wakeup_error_n; 132 /* Extended RDES status */ 133 unsigned long ip_hdr_err; 134 unsigned long ip_payload_err; 135 unsigned long ip_csum_bypassed; 136 unsigned long ipv4_pkt_rcvd; 137 unsigned long ipv6_pkt_rcvd; 138 unsigned long no_ptp_rx_msg_type_ext; 139 unsigned long ptp_rx_msg_type_sync; 140 unsigned long ptp_rx_msg_type_follow_up; 141 unsigned long ptp_rx_msg_type_delay_req; 142 unsigned long ptp_rx_msg_type_delay_resp; 143 unsigned long ptp_rx_msg_type_pdelay_req; 144 unsigned long ptp_rx_msg_type_pdelay_resp; 145 unsigned long ptp_rx_msg_type_pdelay_follow_up; 146 unsigned long ptp_rx_msg_type_announce; 147 unsigned long ptp_rx_msg_type_management; 148 unsigned long ptp_rx_msg_pkt_reserved_type; 149 unsigned long ptp_frame_type; 150 unsigned long ptp_ver; 151 unsigned long timestamp_dropped; 152 unsigned long av_pkt_rcvd; 153 unsigned long av_tagged_pkt_rcvd; 154 unsigned long vlan_tag_priority_val; 155 unsigned long l3_filter_match; 156 unsigned long l4_filter_match; 157 unsigned long l3_l4_filter_no_match; 158 /* PCS */ 159 unsigned long irq_pcs_ane_n; 160 unsigned long irq_pcs_link_n; 161 unsigned long irq_rgmii_n; 162 unsigned long pcs_link; 163 unsigned long pcs_duplex; 164 unsigned long pcs_speed; 165 /* debug register */ 166 unsigned long mtl_tx_status_fifo_full; 167 unsigned long mtl_tx_fifo_not_empty; 168 unsigned long mmtl_fifo_ctrl; 169 unsigned long mtl_tx_fifo_read_ctrl_write; 170 unsigned long mtl_tx_fifo_read_ctrl_wait; 171 unsigned long mtl_tx_fifo_read_ctrl_read; 172 unsigned long mtl_tx_fifo_read_ctrl_idle; 173 unsigned long mac_tx_in_pause; 174 unsigned long mac_tx_frame_ctrl_xfer; 175 unsigned long mac_tx_frame_ctrl_idle; 176 unsigned long mac_tx_frame_ctrl_wait; 177 unsigned long mac_tx_frame_ctrl_pause; 178 unsigned long mac_gmii_tx_proto_engine; 179 unsigned long mtl_rx_fifo_fill_level_full; 180 unsigned long mtl_rx_fifo_fill_above_thresh; 181 unsigned long mtl_rx_fifo_fill_below_thresh; 182 unsigned long mtl_rx_fifo_fill_level_empty; 183 unsigned long mtl_rx_fifo_read_ctrl_flush; 184 unsigned long mtl_rx_fifo_read_ctrl_read_data; 185 unsigned long mtl_rx_fifo_read_ctrl_status; 186 unsigned long mtl_rx_fifo_read_ctrl_idle; 187 unsigned long mtl_rx_fifo_ctrl_active; 188 unsigned long mac_rx_frame_ctrl_fifo; 189 unsigned long mac_gmii_rx_proto_engine; 190 /* TSO */ 191 unsigned long tx_tso_frames; 192 unsigned long tx_tso_nfrags; 193 }; 194 195 /* Safety Feature statistics exposed by ethtool */ 196 struct stmmac_safety_stats { 197 unsigned long mac_errors[32]; 198 unsigned long mtl_errors[32]; 199 unsigned long dma_errors[32]; 200 }; 201 202 /* Number of fields in Safety Stats */ 203 #define STMMAC_SAFETY_FEAT_SIZE \ 204 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 205 206 /* CSR Frequency Access Defines*/ 207 #define CSR_F_35M 35000000 208 #define CSR_F_60M 60000000 209 #define CSR_F_100M 100000000 210 #define CSR_F_150M 150000000 211 #define CSR_F_250M 250000000 212 #define CSR_F_300M 300000000 213 214 #define MAC_CSR_H_FRQ_MASK 0x20 215 216 #define HASH_TABLE_SIZE 64 217 #define PAUSE_TIME 0xffff 218 219 /* Flow Control defines */ 220 #define FLOW_OFF 0 221 #define FLOW_RX 1 222 #define FLOW_TX 2 223 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 224 225 /* PCS defines */ 226 #define STMMAC_PCS_RGMII (1 << 0) 227 #define STMMAC_PCS_SGMII (1 << 1) 228 #define STMMAC_PCS_TBI (1 << 2) 229 #define STMMAC_PCS_RTBI (1 << 3) 230 231 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 232 233 /* DAM HW feature register fields */ 234 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 235 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 236 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 237 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 238 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 239 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 240 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 241 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 242 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 243 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 244 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 245 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 246 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 247 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 248 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 249 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 250 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 251 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 252 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 253 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 254 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 255 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 256 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 257 /* Timestamping with Internal System Time */ 258 #define DMA_HW_FEAT_INTTSEN 0x02000000 259 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 260 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 261 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 262 #define DEFAULT_DMA_PBL 8 263 264 /* PCS status and mask defines */ 265 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 266 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 267 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 268 269 /* Max/Min RI Watchdog Timer count value */ 270 #define MAX_DMA_RIWT 0xff 271 #define MIN_DMA_RIWT 0x10 272 #define DEF_DMA_RIWT 0xa0 273 /* Tx coalesce parameters */ 274 #define STMMAC_COAL_TX_TIMER 1000 275 #define STMMAC_MAX_COAL_TX_TICK 100000 276 #define STMMAC_TX_MAX_FRAMES 256 277 #define STMMAC_TX_FRAMES 25 278 #define STMMAC_RX_FRAMES 0 279 280 /* Packets types */ 281 enum packets_types { 282 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 283 PACKET_PTPQ = 0x2, /* PTP Packets */ 284 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 285 PACKET_UPQ = 0x4, /* Untagged Packets */ 286 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 287 }; 288 289 /* Rx IPC status */ 290 enum rx_frame_status { 291 good_frame = 0x0, 292 discard_frame = 0x1, 293 csum_none = 0x2, 294 llc_snap = 0x4, 295 dma_own = 0x8, 296 rx_not_ls = 0x10, 297 }; 298 299 /* Tx status */ 300 enum tx_frame_status { 301 tx_done = 0x0, 302 tx_not_ls = 0x1, 303 tx_err = 0x2, 304 tx_dma_own = 0x4, 305 }; 306 307 enum dma_irq_status { 308 tx_hard_error = 0x1, 309 tx_hard_error_bump_tc = 0x2, 310 handle_rx = 0x4, 311 handle_tx = 0x8, 312 }; 313 314 /* EEE and LPI defines */ 315 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 316 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 317 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 318 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 319 320 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 321 322 /* Physical Coding Sublayer */ 323 struct rgmii_adv { 324 unsigned int pause; 325 unsigned int duplex; 326 unsigned int lp_pause; 327 unsigned int lp_duplex; 328 }; 329 330 #define STMMAC_PCS_PAUSE 1 331 #define STMMAC_PCS_ASYM_PAUSE 2 332 333 /* DMA HW capabilities */ 334 struct dma_features { 335 unsigned int mbps_10_100; 336 unsigned int mbps_1000; 337 unsigned int half_duplex; 338 unsigned int hash_filter; 339 unsigned int multi_addr; 340 unsigned int pcs; 341 unsigned int sma_mdio; 342 unsigned int pmt_remote_wake_up; 343 unsigned int pmt_magic_frame; 344 unsigned int rmon; 345 /* IEEE 1588-2002 */ 346 unsigned int time_stamp; 347 /* IEEE 1588-2008 */ 348 unsigned int atime_stamp; 349 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 350 unsigned int eee; 351 unsigned int av; 352 unsigned int hash_tb_sz; 353 unsigned int tsoen; 354 /* TX and RX csum */ 355 unsigned int tx_coe; 356 unsigned int rx_coe; 357 unsigned int rx_coe_type1; 358 unsigned int rx_coe_type2; 359 unsigned int rxfifo_over_2048; 360 /* TX and RX number of channels */ 361 unsigned int number_rx_channel; 362 unsigned int number_tx_channel; 363 /* TX and RX number of queues */ 364 unsigned int number_rx_queues; 365 unsigned int number_tx_queues; 366 /* PPS output */ 367 unsigned int pps_out_num; 368 /* Alternate (enhanced) DESC mode */ 369 unsigned int enh_desc; 370 /* TX and RX FIFO sizes */ 371 unsigned int tx_fifo_size; 372 unsigned int rx_fifo_size; 373 /* Automotive Safety Package */ 374 unsigned int asp; 375 /* RX Parser */ 376 unsigned int frpsel; 377 unsigned int frpbs; 378 unsigned int frpes; 379 unsigned int addr64; 380 unsigned int rssen; 381 unsigned int vlhash; 382 unsigned int sphen; 383 unsigned int vlins; 384 unsigned int dvlan; 385 unsigned int l3l4fnum; 386 unsigned int arpoffsel; 387 /* TSN Features */ 388 unsigned int estwid; 389 unsigned int estdep; 390 unsigned int estsel; 391 unsigned int fpesel; 392 unsigned int tbssel; 393 }; 394 395 /* RX Buffer size must be multiple of 4/8/16 bytes */ 396 #define BUF_SIZE_16KiB 16368 397 #define BUF_SIZE_8KiB 8188 398 #define BUF_SIZE_4KiB 4096 399 #define BUF_SIZE_2KiB 2048 400 401 /* Power Down and WOL */ 402 #define PMT_NOT_SUPPORTED 0 403 #define PMT_SUPPORTED 1 404 405 /* Common MAC defines */ 406 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 407 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 408 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 409 410 /* Default LPI timers */ 411 #define STMMAC_DEFAULT_LIT_LS 0x3E8 412 #define STMMAC_DEFAULT_TWT_LS 0x1E 413 414 #define STMMAC_CHAIN_MODE 0x1 415 #define STMMAC_RING_MODE 0x2 416 417 #define JUMBO_LEN 9000 418 419 /* Receive Side Scaling */ 420 #define STMMAC_RSS_HASH_KEY_SIZE 40 421 #define STMMAC_RSS_MAX_TABLE_SIZE 256 422 423 /* VLAN */ 424 #define STMMAC_VLAN_NONE 0x0 425 #define STMMAC_VLAN_REMOVE 0x1 426 #define STMMAC_VLAN_INSERT 0x2 427 #define STMMAC_VLAN_REPLACE 0x3 428 429 extern const struct stmmac_desc_ops enh_desc_ops; 430 extern const struct stmmac_desc_ops ndesc_ops; 431 432 struct mac_device_info; 433 434 extern const struct stmmac_hwtimestamp stmmac_ptp; 435 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 436 437 struct mac_link { 438 u32 speed_mask; 439 u32 speed10; 440 u32 speed100; 441 u32 speed1000; 442 u32 speed2500; 443 u32 duplex; 444 struct { 445 u32 speed2500; 446 u32 speed5000; 447 u32 speed10000; 448 } xgmii; 449 struct { 450 u32 speed25000; 451 u32 speed40000; 452 u32 speed50000; 453 u32 speed100000; 454 } xlgmii; 455 }; 456 457 struct mii_regs { 458 unsigned int addr; /* MII Address */ 459 unsigned int data; /* MII Data */ 460 unsigned int addr_shift; /* MII address shift */ 461 unsigned int reg_shift; /* MII reg shift */ 462 unsigned int addr_mask; /* MII address mask */ 463 unsigned int reg_mask; /* MII reg mask */ 464 unsigned int clk_csr_shift; 465 unsigned int clk_csr_mask; 466 }; 467 468 struct mac_device_info { 469 const struct stmmac_ops *mac; 470 const struct stmmac_desc_ops *desc; 471 const struct stmmac_dma_ops *dma; 472 const struct stmmac_mode_ops *mode; 473 const struct stmmac_hwtimestamp *ptp; 474 const struct stmmac_tc_ops *tc; 475 const struct stmmac_mmc_ops *mmc; 476 const struct mdio_xpcs_ops *xpcs; 477 struct mdio_xpcs_args xpcs_args; 478 struct mii_regs mii; /* MII register Addresses */ 479 struct mac_link link; 480 void __iomem *pcsr; /* vpointer to device CSRs */ 481 unsigned int multicast_filter_bins; 482 unsigned int unicast_filter_entries; 483 unsigned int mcast_bits_log2; 484 unsigned int rx_csum; 485 unsigned int pcs; 486 unsigned int pmt; 487 unsigned int ps; 488 unsigned int xlgmac; 489 unsigned int num_vlan; 490 u32 vlan_filter[32]; 491 unsigned int promisc; 492 bool vlan_fail_q_en; 493 u8 vlan_fail_q; 494 }; 495 496 struct stmmac_rx_routing { 497 u32 reg_mask; 498 u32 reg_shift; 499 }; 500 501 int dwmac100_setup(struct stmmac_priv *priv); 502 int dwmac1000_setup(struct stmmac_priv *priv); 503 int dwmac4_setup(struct stmmac_priv *priv); 504 int dwxgmac2_setup(struct stmmac_priv *priv); 505 int dwxlgmac2_setup(struct stmmac_priv *priv); 506 507 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 508 unsigned int high, unsigned int low); 509 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 510 unsigned int high, unsigned int low); 511 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 512 513 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 514 unsigned int high, unsigned int low); 515 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 516 unsigned int high, unsigned int low); 517 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 518 519 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 520 521 extern const struct stmmac_mode_ops ring_mode_ops; 522 extern const struct stmmac_mode_ops chain_mode_ops; 523 extern const struct stmmac_desc_ops dwmac4_desc_ops; 524 525 #endif /* __COMMON_H__ */ 526